Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	116624	1			T1	8		T2	29		T3	2
all_values[1]	116624	1			T1	8		T2	29		T3	2
all_values[2]	116624	1			T1	8		T2	29		T3	2
all_values[3]	116624	1			T1	8		T2	29		T3	2
all_values[4]	116624	1			T1	8		T2	29		T3	2
all_values[5]	116624	1			T1	8		T2	29		T3	2
all_values[6]	116624	1			T1	8		T2	29		T3	2
all_values[7]	116624	1			T1	8		T2	29		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

480815

1

T1

49

T2

105

T3

16

auto[1]

452177

1

T1

15

T2

127

T4

129

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

872751

1

T1

45

T2

222

T3

13

auto[1]

60241

1

T1

19

T2

10

T3

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	36199	1			T4	4		T5	1		T7	134
all_values[0]	auto[0]	auto[1]	25111	1			T1	5		T2	4		T3	2
all_values[0]	auto[1]	auto[0]	32324	1			T2	23		T4	7		T6	10
all_values[0]	auto[1]	auto[1]	22990	1			T1	3		T2	2		T4	16
all_values[1]	auto[0]	auto[0]	58761	1			T1	3		T2	14		T3	2
all_values[1]	auto[0]	auto[1]	1615	1			T1	3		T5	1		T6	4
all_values[1]	auto[1]	auto[0]	54405	1			T1	2		T2	15		T4	25
all_values[1]	auto[1]	auto[1]	1843	1			T5	3		T7	4		T9	1
all_values[2]	auto[0]	auto[0]	54748	1			T1	2		T2	12		T3	1
all_values[2]	auto[0]	auto[1]	2968	1			T1	1		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	56391	1			T1	2		T2	13		T4	17
all_values[2]	auto[1]	auto[1]	2517	1			T1	3		T2	2		T4	2
all_values[3]	auto[0]	auto[0]	60020	1			T1	4		T2	15		T3	2
all_values[3]	auto[0]	auto[1]	320	1			T1	4		T5	1		T7	2
all_values[3]	auto[1]	auto[0]	55972	1			T2	14		T4	10		T5	15
all_values[3]	auto[1]	auto[1]	312	1			T7	10		T11	1		T20	1
all_values[4]	auto[0]	auto[0]	62660	1			T1	3		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	500	1			T7	2		T11	5		T20	3
all_values[4]	auto[1]	auto[0]	53008	1			T1	5		T2	25		T4	17
all_values[4]	auto[1]	auto[1]	456	1			T7	7		T12	1		T20	1
all_values[5]	auto[0]	auto[0]	58235	1			T1	8		T2	25		T3	2
all_values[5]	auto[0]	auto[1]	203	1			T7	3		T11	2		T20	1
all_values[5]	auto[1]	auto[0]	58001	1			T2	4		T4	6		T5	2
all_values[5]	auto[1]	auto[1]	185	1			T7	2		T11	1		T12	2
all_values[6]	auto[0]	auto[0]	61211	1			T1	8		T2	23		T3	2
all_values[6]	auto[0]	auto[1]	200	1			T7	1		T11	3		T12	3
all_values[6]	auto[1]	auto[0]	55000	1			T2	6		T4	2		T5	18
all_values[6]	auto[1]	auto[1]	213	1			T7	3		T13	1		T30	3
all_values[7]	auto[0]	auto[0]	57625	1			T1	8		T2	6		T3	2
all_values[7]	auto[0]	auto[1]	439	1			T7	1		T11	3		T34	1
all_values[7]	auto[1]	auto[0]	58191	1			T2	23		T4	26		T5	15
all_values[7]	auto[1]	auto[1]	369	1			T4	1		T7	6		T11	1