Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2617

1

T1

1

T2

1

T3

1

auto[UartRx]

2617

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4622	1			T1	2		T2	2		T3	2
values[1]	44	1			T7	2		T21	1		T12	2
values[2]	54	1			T7	2		T8	2		T21	2
values[3]	63	1			T22	1		T30	1		T110	2
values[4]	59	1			T11	1		T22	1		T29	1
values[5]	60	1			T7	2		T8	1		T21	1
values[6]	58	1			T7	3		T22	1		T12	1
values[7]	51	1			T7	2		T22	1		T12	2
values[8]	58	1			T7	2		T21	1		T11	1
values[9]	69	1			T7	1		T21	1		T29	1
values[10]	63	1			T11	4		T13	1		T41	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2394	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	15	1			T30	1		T97	1		T100	1
auto[UartTx]	values[2]	20	1			T7	1		T8	2		T21	1
auto[UartTx]	values[3]	21	1			T22	1		T111	1		T49	1
auto[UartTx]	values[4]	25	1			T13	1		T41	1		T111	2
auto[UartTx]	values[5]	20	1			T29	1		T31	1		T41	2
auto[UartTx]	values[6]	18	1			T7	1		T29	1		T110	1
auto[UartTx]	values[7]	26	1			T7	2		T22	1		T12	2
auto[UartTx]	values[8]	22	1			T7	1		T100	1		T129	1
auto[UartTx]	values[9]	24	1			T7	1		T21	1		T30	1
auto[UartTx]	values[10]	19	1			T11	1		T13	1		T314	1
auto[UartRx]	values[0]	2228	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	29	1			T7	2		T21	1		T12	2
auto[UartRx]	values[2]	34	1			T7	1		T21	1		T22	1
auto[UartRx]	values[3]	42	1			T30	1		T110	2		T97	1
auto[UartRx]	values[4]	34	1			T11	1		T22	1		T29	1
auto[UartRx]	values[5]	40	1			T7	2		T8	1		T21	1
auto[UartRx]	values[6]	40	1			T7	2		T22	1		T12	1
auto[UartRx]	values[7]	25	1			T31	1		T314	1		T175	1
auto[UartRx]	values[8]	36	1			T7	1		T21	1		T11	1
auto[UartRx]	values[9]	45	1			T29	1		T30	1		T31	1
auto[UartRx]	values[10]	44	1			T11	3		T41	1		T110	1