Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2422	1			T6	1		T7	9		T21	4
auto[BaudRate115200]	2117	1			T1	1		T5	2		T6	1
auto[BaudRate230400]	2009	1			T1	1		T2	5		T4	3
auto[BaudRate128Kbps]	2110	1			T1	1		T2	1		T3	1
auto[BaudRate256Kbps]	2285	1			T3	1		T4	1		T6	1
auto[BaudRate1Mbps]	1873	1			T4	2		T5	2		T7	10
auto[BaudRate1p5Mbps]	1369	1			T1	2		T2	1		T5	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1753	1			T7	55		T11	51		T15	12
freqs[25]	1342	1			T3	2		T19	6		T284	2
freqs[48]	661	1			T264	7		T93	2		T185	10
freqs[50]	489	1			T4	7		T285	2		T36	8
freqs[100]	984	1			T10	7		T22	18		T300	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	283	1			T7	9		T11	9		T15	12
auto[BaudRate9600]	freqs[25]	220	1			T19	3		T118	2		T174	1
auto[BaudRate9600]	freqs[48]	107	1			T185	4		T315	2		T175	10
auto[BaudRate9600]	freqs[50]	59	1			T36	3		T268	2		T316	1
auto[BaudRate9600]	freqs[100]	167	1			T22	2		T119	1		T125	2
auto[BaudRate115200]	freqs[24]	278	1			T7	12		T11	8		T178	1
auto[BaudRate115200]	freqs[25]	209	1			T19	3		T284	1		T37	1
auto[BaudRate115200]	freqs[48]	108	1			T264	1		T93	1		T315	1
auto[BaudRate115200]	freqs[50]	64	1			T101	1		T104	3		T301	2
auto[BaudRate115200]	freqs[100]	139	1			T22	2		T119	1		T125	1
auto[BaudRate230400]	freqs[24]	213	1			T7	4		T11	8		T178	2
auto[BaudRate230400]	freqs[25]	186	1			T270	1		T118	2		T174	1
auto[BaudRate230400]	freqs[48]	82	1			T264	1		T185	1		T247	1
auto[BaudRate230400]	freqs[50]	63	1			T4	3		T285	1		T104	1
auto[BaudRate230400]	freqs[100]	114	1			T22	3		T125	3		T40	1
auto[BaudRate128Kbps]	freqs[24]	258	1			T7	4		T11	8		T178	1
auto[BaudRate128Kbps]	freqs[25]	179	1			T3	1		T37	3		T118	1
auto[BaudRate128Kbps]	freqs[48]	95	1			T264	1		T185	3		T247	2
auto[BaudRate128Kbps]	freqs[50]	69	1			T4	1		T36	1		T263	1
auto[BaudRate128Kbps]	freqs[100]	129	1			T22	2		T119	2		T125	1
auto[BaudRate256Kbps]	freqs[24]	307	1			T7	8		T11	9		T178	1
auto[BaudRate256Kbps]	freqs[25]	200	1			T3	1		T37	1		T248	3
auto[BaudRate256Kbps]	freqs[48]	94	1			T185	1		T315	2		T175	10
auto[BaudRate256Kbps]	freqs[50]	78	1			T4	1		T285	1		T36	1
auto[BaudRate256Kbps]	freqs[100]	161	1			T10	4		T22	2		T125	2
auto[BaudRate1Mbps]	freqs[24]	271	1			T7	10		T11	9		T13	16
auto[BaudRate1Mbps]	freqs[25]	225	1			T37	3		T118	2		T174	1
auto[BaudRate1Mbps]	freqs[48]	93	1			T264	2		T185	1		T315	3
auto[BaudRate1Mbps]	freqs[50]	70	1			T4	2		T36	1		T101	2
auto[BaudRate1Mbps]	freqs[100]	137	1			T10	1		T22	5		T119	1
auto[BaudRate1p5Mbps]	freqs[25]	123	1			T284	1		T37	2		T270	1
auto[BaudRate1p5Mbps]	freqs[48]	82	1			T264	2		T93	1		T315	3
auto[BaudRate1p5Mbps]	freqs[50]	86	1			T36	2		T101	2		T39	3
auto[BaudRate1p5Mbps]	freqs[100]	137	1			T10	2		T22	2		T300	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded