Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	33212095	1			T1	14		T2	14		T4	28
all_levels[1]	210863	1			T2	5		T5	5		T6	4
all_levels[2]	2707	1			T5	9		T6	2		T7	11
all_levels[3]	1148	1			T5	8		T6	1		T7	10
all_levels[4]	704	1			T4	1		T5	7		T6	2
all_levels[5]	590	1			T2	1		T5	6		T6	6
all_levels[6]	422	1			T5	2		T6	1		T7	1
all_levels[7]	363	1			T2	2		T5	1		T6	1
all_levels[8]	319	1			T4	1		T5	2		T6	2
all_levels[9]	253	1			T5	2		T6	1		T8	3
all_levels[10]	214	1			T6	1		T7	1		T8	3
all_levels[11]	184	1			T6	1		T8	2		T34	2
all_levels[12]	189	1			T5	1		T6	1		T7	1
all_levels[13]	139	1			T5	1		T11	1		T12	1
all_levels[14]	156	1			T5	2		T7	1		T8	1
all_levels[15]	107	1			T8	3		T11	1		T20	1
all_levels[16]	95	1			T7	1		T8	1		T113	1
all_levels[17]	102	1			T4	1		T8	1		T20	1
all_levels[18]	106	1			T20	1		T35	1		T13	2
all_levels[19]	80	1			T8	1		T35	1		T114	1
all_levels[20]	57	1			T12	1		T115	1		T116	1
all_levels[21]	61	1			T4	1		T20	1		T35	1
all_levels[22]	78	1			T8	2		T20	1		T117	1
all_levels[23]	50	1			T8	3		T117	1		T118	1
all_levels[24]	42	1			T20	1		T117	2		T13	1
all_levels[25]	43	1			T12	1		T20	2		T119	1
all_levels[26]	43	1			T12	1		T20	1		T120	1
all_levels[27]	56	1			T13	1		T121	1		T122	1
all_levels[28]	46	1			T7	1		T8	1		T20	1
all_levels[29]	35	1			T8	1		T20	1		T123	2
all_levels[30]	33	1			T124	1		T125	4		T95	1
all_levels[31]	44	1			T4	1		T8	1		T31	1
all_levels[32]	41	1			T101	1		T126	2		T127	1
all_levels[33]	17	1			T115	1		T128	1		T129	1
all_levels[34]	20	1			T101	1		T130	1		T131	1
all_levels[35]	36	1			T8	1		T115	1		T41	1
all_levels[36]	24	1			T5	2		T94	1		T95	1
all_levels[37]	30	1			T90	1		T132	1		T133	1
all_levels[38]	16	1			T1	1		T134	1		T135	1
all_levels[39]	25	1			T7	1		T20	1		T136	1
all_levels[40]	18	1			T117	1		T13	1		T137	1
all_levels[41]	24	1			T20	1		T30	1		T126	1
all_levels[42]	17	1			T94	1		T121	1		T138	1
all_levels[43]	20	1			T4	1		T117	2		T120	1
all_levels[44]	13	1			T115	1		T139	1		T140	1
all_levels[45]	15	1			T141	1		T142	2		T143	1
all_levels[46]	17	1			T144	2		T145	2		T146	1
all_levels[47]	10	1			T147	1		T148	1		T149	1
all_levels[48]	12	1			T30	1		T144	2		T150	1
all_levels[49]	10	1			T20	1		T132	1		T151	1
all_levels[50]	14	1			T13	1		T100	1		T152	1
all_levels[51]	17	1			T117	1		T110	1		T153	2
all_levels[52]	14	1			T154	1		T155	1		T156	1
all_levels[53]	5	1			T157	1		T158	1		T159	1
all_levels[54]	17	1			T11	1		T41	1		T46	4
all_levels[55]	4	1			T41	1		T160	1		T161	1
all_levels[56]	5	1			T162	1		T163	1		T161	1
all_levels[57]	23	1			T164	1		T165	1		T151	1
all_levels[58]	9	1			T115	1		T166	1		T50	1
all_levels[59]	7	1			T167	1		T168	3		T169	1
all_levels[60]	12	1			T20	1		T37	1		T170	1
all_levels[61]	6	1			T171	2		T172	1		T173	3
all_levels[62]	10	1			T174	3		T175	1		T162	1
all_levels[63]	16	1			T118	1		T13	1		T115	1
all_levels[64]	131	1			T1	1		T7	2		T35	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33427300

1

T1

14

T2

15

T4

34

auto[1]

4779

1

T1

2

T2

7

T5

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	33207826	1			T1	12		T2	11		T4	28
all_levels[0]	auto[1]	4269	1			T1	2		T2	3		T5	6
all_levels[1]	auto[0]	210784	1			T2	2		T5	5		T6	4
all_levels[1]	auto[1]	79	1			T2	3		T176	1		T113	2
all_levels[2]	auto[0]	2664	1			T5	9		T6	2		T7	11
all_levels[2]	auto[1]	43	1			T123	2		T177	1		T153	1
all_levels[3]	auto[0]	1118	1			T5	8		T6	1		T7	10
all_levels[3]	auto[1]	30	1			T114	3		T178	1		T179	1
all_levels[4]	auto[0]	682	1			T4	1		T5	6		T6	2
all_levels[4]	auto[1]	22	1			T5	1		T180	1		T125	1
all_levels[5]	auto[0]	564	1			T2	1		T5	6		T6	5
all_levels[5]	auto[1]	26	1			T6	1		T181	2		T182	1
all_levels[6]	auto[0]	400	1			T5	2		T6	1		T7	1
all_levels[6]	auto[1]	22	1			T183	3		T184	2		T185	1
all_levels[7]	auto[0]	344	1			T2	1		T5	1		T6	1
all_levels[7]	auto[1]	19	1			T2	1		T186	2		T152	6
all_levels[8]	auto[0]	300	1			T4	1		T5	2		T6	2
all_levels[8]	auto[1]	19	1			T179	1		T174	1		T89	1
all_levels[9]	auto[0]	245	1			T5	2		T6	1		T8	3
all_levels[9]	auto[1]	8	1			T102	2		T152	1		T187	1
all_levels[10]	auto[0]	197	1			T6	1		T7	1		T8	3
all_levels[10]	auto[1]	17	1			T188	1		T120	2		T137	2
all_levels[11]	auto[0]	166	1			T6	1		T8	2		T34	2
all_levels[11]	auto[1]	18	1			T46	2		T189	2		T190	2
all_levels[12]	auto[0]	170	1			T5	1		T6	1		T7	1
all_levels[12]	auto[1]	19	1			T186	1		T191	1		T192	2
all_levels[13]	auto[0]	123	1			T5	1		T11	1		T12	1
all_levels[13]	auto[1]	16	1			T193	1		T89	1		T185	1
all_levels[14]	auto[0]	144	1			T5	2		T7	1		T8	1
all_levels[14]	auto[1]	12	1			T194	2		T195	2		T196	3
all_levels[15]	auto[0]	103	1			T8	3		T11	1		T20	1
all_levels[15]	auto[1]	4	1			T89	1		T197	1		T198	1
all_levels[16]	auto[0]	81	1			T7	1		T8	1		T113	1
all_levels[16]	auto[1]	14	1			T180	2		T89	1		T199	1
all_levels[17]	auto[0]	95	1			T4	1		T8	1		T20	1
all_levels[17]	auto[1]	7	1			T200	1		T201	1		T148	1
all_levels[18]	auto[0]	98	1			T20	1		T35	1		T13	2
all_levels[18]	auto[1]	8	1			T153	1		T202	1		T203	1
all_levels[19]	auto[0]	79	1			T8	1		T35	1		T114	1
all_levels[19]	auto[1]	1	1			T204	1		-	-		-	-
all_levels[20]	auto[0]	56	1			T12	1		T115	1		T116	1
all_levels[20]	auto[1]	1	1			T205	1		-	-		-	-
all_levels[21]	auto[0]	56	1			T4	1		T20	1		T35	1
all_levels[21]	auto[1]	5	1			T206	3		T207	2		-	-
all_levels[22]	auto[0]	65	1			T8	2		T20	1		T117	1
all_levels[22]	auto[1]	13	1			T13	4		T208	1		T209	2
all_levels[23]	auto[0]	48	1			T8	1		T117	1		T118	1
all_levels[23]	auto[1]	2	1			T8	2		-	-		-	-
all_levels[24]	auto[0]	39	1			T20	1		T117	2		T13	1
all_levels[24]	auto[1]	3	1			T100	1		T194	1		T210	1
all_levels[25]	auto[0]	42	1			T12	1		T20	2		T119	1
all_levels[25]	auto[1]	1	1			T211	1		-	-		-	-
all_levels[26]	auto[0]	36	1			T12	1		T20	1		T120	1
all_levels[26]	auto[1]	7	1			T212	2		T213	2		T214	2
all_levels[27]	auto[0]	56	1			T13	1		T121	1		T122	1
all_levels[28]	auto[0]	38	1			T7	1		T8	1		T20	1
all_levels[28]	auto[1]	8	1			T122	2		T158	1		T149	1
all_levels[29]	auto[0]	32	1			T8	1		T20	1		T123	1
all_levels[29]	auto[1]	3	1			T123	1		T215	1		T216	1
all_levels[30]	auto[0]	27	1			T124	1		T125	1		T95	1
all_levels[30]	auto[1]	6	1			T125	3		T217	2		T218	1
all_levels[31]	auto[0]	41	1			T4	1		T8	1		T31	1
all_levels[31]	auto[1]	3	1			T219	1		T220	2		-	-
all_levels[32]	auto[0]	39	1			T101	1		T126	1		T127	1
all_levels[32]	auto[1]	2	1			T126	1		T168	1		-	-
all_levels[33]	auto[0]	14	1			T115	1		T128	1		T129	1
all_levels[33]	auto[1]	3	1			T221	3		-	-		-	-
all_levels[34]	auto[0]	19	1			T101	1		T130	1		T131	1
all_levels[34]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[35]	auto[0]	34	1			T8	1		T115	1		T41	1
all_levels[35]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[36]	auto[0]	23	1			T5	1		T94	1		T95	1
all_levels[36]	auto[1]	1	1			T5	1		-	-		-	-
all_levels[37]	auto[0]	26	1			T90	1		T132	1		T133	1
all_levels[37]	auto[1]	4	1			T225	3		T222	1		-	-
all_levels[38]	auto[0]	16	1			T1	1		T134	1		T135	1
all_levels[39]	auto[0]	22	1			T7	1		T20	1		T136	1
all_levels[39]	auto[1]	3	1			T226	1		T227	1		T228	1
all_levels[40]	auto[0]	17	1			T117	1		T13	1		T137	1
all_levels[40]	auto[1]	1	1			T148	1		-	-		-	-
all_levels[41]	auto[0]	23	1			T20	1		T30	1		T126	1
all_levels[41]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[42]	auto[0]	15	1			T94	1		T121	1		T138	1
all_levels[42]	auto[1]	2	1			T230	2		-	-		-	-
all_levels[43]	auto[0]	20	1			T4	1		T117	2		T120	1
all_levels[44]	auto[0]	12	1			T115	1		T139	1		T140	1
all_levels[44]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[45]	auto[0]	11	1			T141	1		T142	1		T143	1
all_levels[45]	auto[1]	4	1			T142	1		T232	1		T233	2
all_levels[46]	auto[0]	14	1			T144	1		T145	1		T146	1
all_levels[46]	auto[1]	3	1			T144	1		T145	1		T234	1
all_levels[47]	auto[0]	10	1			T147	1		T148	1		T149	1
all_levels[48]	auto[0]	11	1			T30	1		T144	1		T150	1
all_levels[48]	auto[1]	1	1			T144	1		-	-		-	-
all_levels[49]	auto[0]	9	1			T20	1		T132	1		T151	1
all_levels[49]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[50]	auto[0]	14	1			T13	1		T100	1		T152	1
all_levels[51]	auto[0]	15	1			T117	1		T110	1		T153	1
all_levels[51]	auto[1]	2	1			T153	1		T236	1		-	-
all_levels[52]	auto[0]	11	1			T154	1		T155	1		T156	1
all_levels[52]	auto[1]	3	1			T237	1		T238	2		-	-
all_levels[53]	auto[0]	5	1			T157	1		T158	1		T159	1
all_levels[54]	auto[0]	13	1			T11	1		T41	1		T46	1
all_levels[54]	auto[1]	4	1			T46	3		T127	1		-	-
all_levels[55]	auto[0]	4	1			T41	1		T160	1		T161	1
all_levels[56]	auto[0]	5	1			T162	1		T163	1		T161	1
all_levels[57]	auto[0]	17	1			T164	1		T165	1		T151	1
all_levels[57]	auto[1]	6	1			T171	1		T239	1		T240	4
all_levels[58]	auto[0]	9	1			T115	1		T166	1		T50	1
all_levels[59]	auto[0]	4	1			T167	1		T168	1		T169	1
all_levels[59]	auto[1]	3	1			T168	2		T241	1		-	-
all_levels[60]	auto[0]	12	1			T20	1		T37	1		T170	1
all_levels[61]	auto[0]	3	1			T171	1		T172	1		T173	1
all_levels[61]	auto[1]	3	1			T171	1		T173	2		-	-
all_levels[62]	auto[0]	7	1			T174	1		T175	1		T162	1
all_levels[62]	auto[1]	3	1			T174	2		T242	1		-	-
all_levels[63]	auto[0]	15	1			T118	1		T13	1		T115	1
all_levels[63]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[64]	auto[0]	112	1			T1	1		T7	2		T35	1
all_levels[64]	auto[1]	19	1			T244	2		T245	1		T158	1