Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	116624	1			T1	8		T2	29		T3	2
all_pins[1]	116624	1			T1	8		T2	29		T3	2
all_pins[2]	116624	1			T1	8		T2	29		T3	2
all_pins[3]	116624	1			T1	8		T2	29		T3	2
all_pins[4]	116624	1			T1	8		T2	29		T3	2
all_pins[5]	116624	1			T1	8		T2	29		T3	2
all_pins[6]	116624	1			T1	8		T2	29		T3	2
all_pins[7]	116624	1			T1	8		T2	29		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	903222	1			T1	58		T2	228		T3	16
values[0x1]	29770	1			T1	6		T2	4		T4	20
transitions[0x0=>0x1]	28517	1			T1	6		T2	4		T4	19
transitions[0x1=>0x0]	28066	1			T1	6		T2	3		T4	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93575	1			T1	5		T2	27		T3	2
all_pins[0]	values[0x1]	23049	1			T1	3		T2	2		T4	16
all_pins[0]	transitions[0x0=>0x1]	22396	1			T1	3		T2	2		T4	16
all_pins[0]	transitions[0x1=>0x0]	1186	1			T5	3		T7	2		T11	2
all_pins[1]	values[0x0]	114785	1			T1	8		T2	29		T3	2
all_pins[1]	values[0x1]	1839	1			T5	3		T7	4		T9	1
all_pins[1]	transitions[0x0=>0x1]	1736	1			T5	2		T7	2		T9	1
all_pins[1]	transitions[0x1=>0x0]	2465	1			T1	3		T2	2		T4	2
all_pins[2]	values[0x0]	114056	1			T1	5		T2	27		T3	2
all_pins[2]	values[0x1]	2568	1			T1	3		T2	2		T4	2
all_pins[2]	transitions[0x0=>0x1]	2498	1			T1	3		T2	2		T4	2
all_pins[2]	transitions[0x1=>0x0]	242	1			T7	6		T11	1		T104	1
all_pins[3]	values[0x0]	116312	1			T1	8		T2	29		T3	2
all_pins[3]	values[0x1]	312	1			T7	10		T11	1		T20	1
all_pins[3]	transitions[0x0=>0x1]	243	1			T7	4		T11	1		T20	1
all_pins[3]	transitions[0x1=>0x0]	387	1			T7	1		T12	1		T20	1
all_pins[4]	values[0x0]	116168	1			T1	8		T2	29		T3	2
all_pins[4]	values[0x1]	456	1			T7	7		T12	1		T20	1
all_pins[4]	transitions[0x0=>0x1]	376	1			T7	7		T12	1		T13	10
all_pins[4]	transitions[0x1=>0x0]	152	1			T7	2		T11	2		T12	2
all_pins[5]	values[0x0]	116392	1			T1	8		T2	29		T3	2
all_pins[5]	values[0x1]	232	1			T7	2		T11	2		T12	2
all_pins[5]	transitions[0x0=>0x1]	185	1			T7	2		T11	2		T12	2
all_pins[5]	transitions[0x1=>0x0]	898	1			T4	1		T5	2		T7	4
all_pins[6]	values[0x0]	115679	1			T1	8		T2	29		T3	2
all_pins[6]	values[0x1]	945	1			T4	1		T5	2		T7	4
all_pins[6]	transitions[0x0=>0x1]	872	1			T5	2		T11	6		T22	1
all_pins[6]	transitions[0x1=>0x0]	296	1			T7	2		T11	1		T34	4
all_pins[7]	values[0x0]	116255	1			T1	8		T2	29		T3	2
all_pins[7]	values[0x1]	369	1			T4	1		T7	6		T11	1
all_pins[7]	transitions[0x0=>0x1]	211	1			T4	1		T7	3		T11	1
all_pins[7]	transitions[0x1=>0x0]	22440	1			T1	3		T2	1		T4	15