Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8073753	1			T1	12		T2	9		T4	3
all_levels[1]	1613282	1			T2	5		T5	42		T6	7
all_levels[2]	427842	1			T4	2		T5	3		T6	1
all_levels[3]	252905	1			T5	5		T6	3		T7	534
all_levels[4]	658814	1			T6	1		T7	3076		T8	2
all_levels[5]	272987	1			T2	6		T5	2		T7	787
all_levels[6]	501696	1			T4	1		T6	3		T7	808
all_levels[7]	582906	1			T6	4		T7	839		T8	2
all_levels[8]	264506	1			T2	2		T6	3		T7	676
all_levels[9]	225229	1			T7	698		T9	64		T10	204
all_levels[10]	245753	1			T5	1		T7	808		T8	2
all_levels[11]	360363	1			T6	2		T7	789		T8	4
all_levels[12]	347504	1			T4	2		T5	1		T6	2
all_levels[13]	235464	1			T5	2		T7	547		T9	43
all_levels[14]	273276	1			T4	1		T5	2		T6	1
all_levels[15]	207369	1			T4	2		T5	1		T6	6
all_levels[16]	466650	1			T4	2		T5	2		T6	1
all_levels[17]	464442	1			T5	2		T7	1744		T9	47
all_levels[18]	264730	1			T4	1		T5	2		T6	2
all_levels[19]	197258	1			T4	1		T6	1		T7	1667
all_levels[20]	527390	1			T4	1		T5	1		T7	1327
all_levels[21]	214288	1			T7	1623		T9	49		T10	211
all_levels[22]	456622	1			T7	1937		T9	67		T10	217
all_levels[23]	201221	1			T4	1		T5	2		T6	1
all_levels[24]	374491	1			T4	1		T7	2632		T8	2
all_levels[25]	246566	1			T7	1959		T8	2		T9	49
all_levels[26]	247359	1			T4	1		T7	1927		T8	2
all_levels[27]	203058	1			T4	1		T7	1753		T8	1
all_levels[28]	224127	1			T4	2		T7	1213		T8	2
all_levels[29]	492293	1			T6	2		T7	1268		T8	3
all_levels[30]	200973	1			T7	1645		T9	53		T10	205
all_levels[31]	730095	1			T7	2395		T8	1		T9	1005
all_levels[32]	13376364	1			T1	5		T4	13		T5	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33427300

1

T1

14

T2

15

T4

34

auto[1]

4276

1

T1

3

T2

7

T4

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8071407	1			T1	10		T2	5		T4	3
all_levels[0]	auto[1]	2346	1			T1	2		T2	4		T5	4
all_levels[1]	auto[0]	1612930	1			T2	4		T5	40		T6	5
all_levels[1]	auto[1]	352	1			T2	1		T5	2		T6	2
all_levels[2]	auto[0]	427816	1			T4	2		T5	3		T6	1
all_levels[2]	auto[1]	26	1			T123	2		T187	2		T128	1
all_levels[3]	auto[0]	252761	1			T5	5		T6	3		T7	534
all_levels[3]	auto[1]	144	1			T116	1		T98	1		T318	2
all_levels[4]	auto[0]	658791	1			T6	1		T7	3076		T8	2
all_levels[4]	auto[1]	23	1			T36	1		T274	1		T146	1
all_levels[5]	auto[0]	272947	1			T2	4		T5	2		T7	787
all_levels[5]	auto[1]	40	1			T2	2		T35	1		T188	1
all_levels[6]	auto[0]	501672	1			T4	1		T6	3		T7	808
all_levels[6]	auto[1]	24	1			T180	2		T179	1		T46	2
all_levels[7]	auto[0]	582705	1			T6	4		T7	839		T8	2
all_levels[7]	auto[1]	201	1			T257	1		T178	1		T14	29
all_levels[8]	auto[0]	264470	1			T2	2		T6	2		T7	676
all_levels[8]	auto[1]	36	1			T6	1		T265	1		T319	2
all_levels[9]	auto[0]	225217	1			T7	698		T9	64		T10	204
all_levels[9]	auto[1]	12	1			T177	1		T274	1		T320	1
all_levels[10]	auto[0]	245720	1			T5	1		T7	808		T8	2
all_levels[10]	auto[1]	33	1			T37	1		T179	1		T252	1
all_levels[11]	auto[0]	360345	1			T6	2		T7	789		T8	4
all_levels[11]	auto[1]	18	1			T321	1		T275	1		T122	1
all_levels[12]	auto[0]	347485	1			T4	2		T5	1		T6	2
all_levels[12]	auto[1]	19	1			T180	2		T252	2		T193	2
all_levels[13]	auto[0]	235440	1			T5	1		T7	547		T9	43
all_levels[13]	auto[1]	24	1			T5	1		T321	1		T322	2
all_levels[14]	auto[0]	273256	1			T4	1		T5	2		T6	1
all_levels[14]	auto[1]	20	1			T144	1		T187	3		T323	1
all_levels[15]	auto[0]	207219	1			T4	2		T5	1		T6	4
all_levels[15]	auto[1]	150	1			T6	2		T183	1		T14	4
all_levels[16]	auto[0]	466625	1			T4	2		T5	2		T6	1
all_levels[16]	auto[1]	25	1			T8	1		T183	1		T97	2
all_levels[17]	auto[0]	464421	1			T5	2		T7	1744		T9	47
all_levels[17]	auto[1]	21	1			T186	2		T128	2		T324	1
all_levels[18]	auto[0]	264706	1			T4	1		T5	2		T6	2
all_levels[18]	auto[1]	24	1			T257	2		T110	1		T297	1
all_levels[19]	auto[0]	197232	1			T4	1		T6	1		T7	1667
all_levels[19]	auto[1]	26	1			T316	3		T325	1		T326	1
all_levels[20]	auto[0]	527372	1			T4	1		T5	1		T7	1327
all_levels[20]	auto[1]	18	1			T33	1		T117	1		T125	1
all_levels[21]	auto[0]	214280	1			T7	1623		T9	49		T10	211
all_levels[21]	auto[1]	8	1			T30	1		T40	1		T95	1
all_levels[22]	auto[0]	456607	1			T7	1937		T9	67		T10	217
all_levels[22]	auto[1]	15	1			T37	3		T187	1		T189	1
all_levels[23]	auto[0]	201194	1			T4	1		T5	2		T6	1
all_levels[23]	auto[1]	27	1			T188	1		T13	1		T46	4
all_levels[24]	auto[0]	374472	1			T4	1		T7	2632		T8	2
all_levels[24]	auto[1]	19	1			T179	2		T126	1		T153	1
all_levels[25]	auto[0]	246545	1			T7	1959		T8	2		T9	49
all_levels[25]	auto[1]	21	1			T102	1		T268	1		T100	1
all_levels[26]	auto[0]	247347	1			T4	1		T7	1927		T8	2
all_levels[26]	auto[1]	12	1			T327	1		T328	1		T329	1
all_levels[27]	auto[0]	203040	1			T4	1		T7	1753		T8	1
all_levels[27]	auto[1]	18	1			T313	1		T202	1		T330	1
all_levels[28]	auto[0]	224110	1			T4	2		T7	1213		T8	2
all_levels[28]	auto[1]	17	1			T188	1		T244	4		T331	1
all_levels[29]	auto[0]	492283	1			T6	2		T7	1268		T8	3
all_levels[29]	auto[1]	10	1			T321	1		T153	1		T150	1
all_levels[30]	auto[0]	200960	1			T7	1645		T9	53		T10	205
all_levels[30]	auto[1]	13	1			T35	1		T100	1		T332	1
all_levels[31]	auto[0]	730078	1			T7	2395		T8	1		T9	1005
all_levels[31]	auto[1]	17	1			T125	2		T42	1		T122	2
all_levels[32]	auto[0]	13375847	1			T1	4		T4	12		T5	1
all_levels[32]	auto[1]	517	1			T1	1		T4	1		T6	1