Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	802	1			T7	12		T11	7		T12	4
all_values[1]	802	1			T7	12		T11	7		T12	4
all_values[2]	802	1			T7	12		T11	7		T12	4
all_values[3]	802	1			T7	12		T11	7		T12	4
all_values[4]	802	1			T7	12		T11	7		T12	4
all_values[5]	802	1			T7	12		T11	7		T12	4
all_values[6]	802	1			T7	12		T11	7		T12	4
all_values[7]	802	1			T7	12		T11	7		T12	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3484

1

T7

44

T11

30

T12

16

auto[1]

2932

1

T7

52

T11

26

T12

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2304

1

T7

30

T11

28

T12

15

auto[1]

4112

1

T7

66

T11

28

T12

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3783

1

T7

57

T11

35

T12

21

auto[1]

2633

1

T7

39

T11

21

T12

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	278	1			T7	7		T20	1		T13	4
all_values[0]	auto[0]	auto[1]	auto[1]	221	1			T7	2		T11	2		T12	3
all_values[0]	auto[1]	auto[0]	auto[1]	169	1			T7	1		T11	1		T12	1
all_values[0]	auto[1]	auto[1]	auto[1]	134	1			T7	2		T11	4		T30	2
all_values[1]	auto[0]	auto[0]	auto[0]	236	1			T7	3		T12	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	225	1			T7	3		T11	3		T12	1
all_values[1]	auto[1]	auto[0]	auto[1]	175	1			T7	2		T11	1		T12	1
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T7	4		T11	3		T20	1
all_values[2]	auto[0]	auto[0]	auto[0]	191	1			T7	3		T11	5		T12	1
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T20	1		T13	1		T30	1
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T7	2		T12	3		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	79	1			T7	3		T30	1		T110	3
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T7	1		T11	2		T20	2
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T7	3		T13	1		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	177	1			T7	1		T11	3		T13	1
all_values[3]	auto[0]	auto[0]	auto[1]	75	1			T7	1		T20	2		T13	2
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T11	1		T12	2		T13	2
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T7	4		T11	1		T30	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T7	1		T11	1		T12	2
all_values[3]	auto[1]	auto[1]	auto[1]	139	1			T7	5		T11	1		T20	1
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T7	1		T11	2		T13	2
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T7	1		T20	1		T13	1
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T7	2		T11	5		T12	3
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T7	3		T110	1		T111	2
all_values[4]	auto[1]	auto[0]	auto[1]	199	1			T7	1		T20	3		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T7	4		T12	1		T13	2
all_values[5]	auto[0]	auto[0]	auto[0]	161	1			T7	3		T11	2		T12	2
all_values[5]	auto[0]	auto[0]	auto[1]	88	1			T7	2		T11	1		T20	2
all_values[5]	auto[0]	auto[1]	auto[0]	134	1			T7	2		T11	1		T13	1
all_values[5]	auto[0]	auto[1]	auto[1]	76	1			T11	1		T12	1		T13	1
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T7	1		T11	1		T20	1
all_values[5]	auto[1]	auto[1]	auto[1]	173	1			T7	4		T11	1		T12	1
all_values[6]	auto[0]	auto[0]	auto[0]	153	1			T7	6		T20	2		T13	2
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T11	1		T12	1		T30	1
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T11	2		T20	1		T13	1
all_values[6]	auto[0]	auto[1]	auto[1]	110	1			T7	2		T13	1		T112	1
all_values[6]	auto[1]	auto[0]	auto[1]	193	1			T7	2		T11	4		T12	2
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T7	2		T12	1		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T7	4		T11	3		T12	1
all_values[7]	auto[0]	auto[0]	auto[1]	94	1			T11	1		T12	1		T112	1
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T11	1		T20	1		T30	2
all_values[7]	auto[0]	auto[1]	auto[1]	70	1			T7	2		T112	2		T110	3
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T7	3		T11	2		T12	2
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T7	3		T20	2		T13	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal