Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98546	1			T1	31		T2	1		T3	235
all_values[1]	98546	1			T1	31		T2	1		T3	235
all_values[2]	98546	1			T1	31		T2	1		T3	235
all_values[3]	98546	1			T1	31		T2	1		T3	235
all_values[4]	98546	1			T1	31		T2	1		T3	235
all_values[5]	98546	1			T1	31		T2	1		T3	235
all_values[6]	98546	1			T1	31		T2	1		T3	235
all_values[7]	98546	1			T1	31		T2	1		T3	235

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

407866

1

T1

177

T2

2

T3

851

auto[1]

380502

1

T1

71

T2

6

T3

1029

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

734659

1

T1

238

T2

7

T3

1619

auto[1]

53709

1

T1

10

T2

1

T3

261

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30954	1			T1	21		T3	42		T5	42
all_values[0]	auto[0]	auto[1]	24155	1			T1	1		T3	67		T4	2
all_values[0]	auto[1]	auto[0]	25701	1			T1	5		T3	28		T5	4
all_values[0]	auto[1]	auto[1]	17736	1			T1	4		T2	1		T3	98
all_values[1]	auto[0]	auto[0]	47982	1			T1	25		T2	1		T3	85
all_values[1]	auto[0]	auto[1]	1766	1			T3	13		T13	1		T152	2
all_values[1]	auto[1]	auto[0]	47346	1			T1	6		T3	124		T5	49
all_values[1]	auto[1]	auto[1]	1452	1			T3	13		T7	2		T15	3
all_values[2]	auto[0]	auto[0]	47960	1			T3	65		T4	1		T5	65
all_values[2]	auto[0]	auto[1]	2936	1			T3	13		T4	1		T5	4
all_values[2]	auto[1]	auto[0]	45153	1			T1	26		T2	1		T3	152
all_values[2]	auto[1]	auto[1]	2497	1			T1	5		T3	5		T5	1
all_values[3]	auto[0]	auto[0]	47489	1			T1	31		T3	63		T4	2
all_values[3]	auto[0]	auto[1]	325	1			T3	6		T11	4		T13	5
all_values[3]	auto[1]	auto[0]	50408	1			T2	1		T3	164		T5	42
all_values[3]	auto[1]	auto[1]	324	1			T3	2		T11	1		T13	1
all_values[4]	auto[0]	auto[0]	49385	1			T1	31		T3	129		T4	2
all_values[4]	auto[0]	auto[1]	554	1			T3	3		T11	6		T13	2
all_values[4]	auto[1]	auto[0]	48147	1			T2	1		T3	91		T5	47
all_values[4]	auto[1]	auto[1]	460	1			T3	12		T11	2		T13	2
all_values[5]	auto[0]	auto[0]	49195	1			T1	31		T3	92		T4	2
all_values[5]	auto[0]	auto[1]	201	1			T3	5		T13	1		T12	1
all_values[5]	auto[1]	auto[0]	48964	1			T2	1		T3	138		T5	9
all_values[5]	auto[1]	auto[1]	186	1			T13	3		T12	3		T64	1
all_values[6]	auto[0]	auto[0]	53037	1			T1	12		T3	111		T4	2
all_values[6]	auto[0]	auto[1]	177	1			T3	2		T13	1		T64	5
all_values[6]	auto[1]	auto[0]	45154	1			T1	19		T2	1		T3	117
all_values[6]	auto[1]	auto[1]	178	1			T3	5		T12	1		T82	4
all_values[7]	auto[0]	auto[0]	51407	1			T1	25		T2	1		T3	152
all_values[7]	auto[0]	auto[1]	343	1			T3	3		T14	4		T11	1
all_values[7]	auto[1]	auto[0]	46377	1			T1	6		T3	66		T5	58
all_values[7]	auto[1]	auto[1]	419	1			T3	14		T14	2		T13	2