Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2642

1

T1

1

T2

1

T3

11

auto[UartRx]

2642

1

T1

1

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4667	1			T1	2		T2	2		T3	13
values[1]	43	1			T3	1		T30	2		T31	2
values[2]	42	1			T25	1		T26	1		T27	1
values[3]	58	1			T3	2		T12	1		T26	2
values[4]	68	1			T3	1		T17	1		T12	1
values[5]	49	1			T3	1		T25	1		T26	1
values[6]	68	1			T3	2		T17	1		T26	1
values[7]	60	1			T17	1		T12	2		T25	1
values[8]	67	1			T3	1		T12	1		T26	1
values[9]	58	1			T3	1		T17	3		T12	1
values[10]	74	1			T25	1		T26	1		T27	3

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2435	1			T1	1		T2	1		T3	8
auto[UartTx]	values[1]	7	1			T30	1		T315	1		T316	1
auto[UartTx]	values[2]	15	1			T25	1		T26	1		T27	1
auto[UartTx]	values[3]	17	1			T312	1		T40	1		T153	1
auto[UartTx]	values[4]	22	1			T3	1		T17	1		T26	1
auto[UartTx]	values[5]	19	1			T27	1		T30	1		T317	2
auto[UartTx]	values[6]	22	1			T3	1		T26	1		T83	1
auto[UartTx]	values[7]	15	1			T17	1		T27	1		T106	1
auto[UartTx]	values[8]	33	1			T3	1		T26	1		T302	1
auto[UartTx]	values[9]	23	1			T17	2		T27	1		T28	1
auto[UartTx]	values[10]	23	1			T25	1		T27	1		T29	1
auto[UartRx]	values[0]	2232	1			T1	1		T2	1		T3	5
auto[UartRx]	values[1]	36	1			T3	1		T30	1		T31	2
auto[UartRx]	values[2]	27	1			T28	1		T30	1		T99	2
auto[UartRx]	values[3]	41	1			T3	2		T12	1		T26	2
auto[UartRx]	values[4]	46	1			T12	1		T99	1		T82	1
auto[UartRx]	values[5]	30	1			T3	1		T25	1		T26	1
auto[UartRx]	values[6]	46	1			T3	1		T17	1		T27	1
auto[UartRx]	values[7]	45	1			T12	2		T25	1		T26	1
auto[UartRx]	values[8]	34	1			T12	1		T27	1		T28	1
auto[UartRx]	values[9]	35	1			T3	1		T17	1		T12	1
auto[UartRx]	values[10]	51	1			T26	1		T27	2		T29	1