Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2314	1			T3	16		T5	2		T6	2
auto[BaudRate115200]	2049	1			T1	1		T2	9		T3	27
auto[BaudRate230400]	2002	1			T2	3		T3	14		T4	1
auto[BaudRate128Kbps]	1929	1			T1	2		T2	3		T3	10
auto[BaudRate256Kbps]	2163	1			T1	4		T2	9		T3	27
auto[BaudRate1Mbps]	1827	1			T1	1		T2	3		T3	30
auto[BaudRate1p5Mbps]	1349	1			T2	6		T3	5		T32	4

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1504	1			T3	129		T282	2		T291	2
freqs[25]	1233	1			T1	8		T4	2		T9	6
freqs[48]	571	1			T5	10		T248	19		T173	7
freqs[50]	529	1			T6	9		T15	27		T35	10
freqs[100]	1060	1			T14	6		T286	1		T285	4

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	217	1			T3	16		T291	1		T95	1
auto[BaudRate9600]	freqs[25]	225	1			T9	1		T289	1		T318	1
auto[BaudRate9600]	freqs[48]	121	1			T5	2		T248	3		T173	4
auto[BaudRate9600]	freqs[50]	86	1			T6	2		T15	2		T113	1
auto[BaudRate9600]	freqs[100]	178	1			T285	2		T92	1		T93	1
auto[BaudRate115200]	freqs[24]	228	1			T3	27		T152	2		T253	9
auto[BaudRate115200]	freqs[25]	179	1			T1	1		T289	1		T314	1
auto[BaudRate115200]	freqs[48]	78	1			T5	1		T248	1		T306	2
auto[BaudRate115200]	freqs[50]	84	1			T15	4		T113	1		T256	1
auto[BaudRate115200]	freqs[100]	164	1			T14	1		T286	1		T285	1
auto[BaudRate230400]	freqs[24]	239	1			T3	14		T282	1		T291	1
auto[BaudRate230400]	freqs[25]	193	1			T4	1		T116	4		T118	2
auto[BaudRate230400]	freqs[48]	83	1			T5	2		T248	3		T173	1
auto[BaudRate230400]	freqs[50]	81	1			T6	2		T15	4		T113	1
auto[BaudRate230400]	freqs[100]	133	1			T14	1		T88	3		T92	2
auto[BaudRate128Kbps]	freqs[24]	214	1			T3	10		T282	1		T95	1
auto[BaudRate128Kbps]	freqs[25]	167	1			T1	2		T9	1		T115	2
auto[BaudRate128Kbps]	freqs[48]	57	1			T5	2		T248	2		T173	1
auto[BaudRate128Kbps]	freqs[50]	59	1			T6	1		T15	5		T113	2
auto[BaudRate128Kbps]	freqs[100]	148	1			T14	1		T28	1		T194	4
auto[BaudRate256Kbps]	freqs[24]	271	1			T3	27		T95	1		T152	1
auto[BaudRate256Kbps]	freqs[25]	193	1			T1	4		T9	3		T319	2
auto[BaudRate256Kbps]	freqs[48]	78	1			T5	3		T248	4		T301	1
auto[BaudRate256Kbps]	freqs[50]	73	1			T6	2		T15	2		T35	3
auto[BaudRate256Kbps]	freqs[100]	141	1			T14	1		T92	1		T93	1
auto[BaudRate1Mbps]	freqs[24]	232	1			T3	30		T152	3		T253	1
auto[BaudRate1Mbps]	freqs[25]	170	1			T1	1		T4	1		T9	1
auto[BaudRate1Mbps]	freqs[48]	80	1			T248	4		T173	1		T301	1
auto[BaudRate1Mbps]	freqs[50]	65	1			T6	2		T15	5		T35	1
auto[BaudRate1Mbps]	freqs[100]	148	1			T14	1		T285	1		T88	1
auto[BaudRate1p5Mbps]	freqs[25]	106	1			T116	1		T118	2		T319	1
auto[BaudRate1p5Mbps]	freqs[48]	74	1			T248	2		T301	1		T306	1
auto[BaudRate1p5Mbps]	freqs[50]	81	1			T15	5		T35	6		T320	2
auto[BaudRate1p5Mbps]	freqs[100]	148	1			T14	1		T92	1		T93	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded