Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26022815	1			T1	15		T2	1		T3	40465
all_levels[1]	201918	1			T1	1		T3	251		T5	1
all_levels[2]	2448	1			T3	9		T6	5		T8	25
all_levels[3]	1107	1			T3	5		T5	2		T6	1
all_levels[4]	695	1			T3	3		T14	2		T96	4
all_levels[5]	519	1			T3	1		T5	1		T107	1
all_levels[6]	461	1			T3	2		T32	1		T14	2
all_levels[7]	394	1			T1	2		T3	3		T32	2
all_levels[8]	315	1			T3	2		T13	1		T17	2
all_levels[9]	293	1			T1	3		T3	3		T7	1
all_levels[10]	213	1			T14	1		T107	3		T108	1
all_levels[11]	184	1			T109	1		T110	1		T25	1
all_levels[12]	172	1			T15	1		T111	1		T112	1
all_levels[13]	171	1			T3	1		T107	2		T17	2
all_levels[14]	133	1			T3	3		T15	1		T97	1
all_levels[15]	118	1			T3	1		T14	1		T113	1
all_levels[16]	105	1			T14	1		T96	1		T12	1
all_levels[17]	102	1			T3	1		T96	2		T17	1
all_levels[18]	86	1			T3	1		T113	1		T114	1
all_levels[19]	81	1			T14	1		T33	1		T12	1
all_levels[20]	77	1			T113	2		T26	2		T92	1
all_levels[21]	65	1			T14	1		T33	2		T34	1
all_levels[22]	62	1			T112	1		T26	1		T115	1
all_levels[23]	63	1			T14	1		T111	1		T112	1
all_levels[24]	63	1			T25	1		T92	1		T116	1
all_levels[25]	50	1			T111	1		T117	1		T118	1
all_levels[26]	58	1			T3	1		T119	1		T120	3
all_levels[27]	48	1			T119	1		T121	1		T122	1
all_levels[28]	53	1			T123	1		T124	2		T125	1
all_levels[29]	42	1			T110	3		T17	1		T100	1
all_levels[30]	44	1			T3	1		T112	1		T98	2
all_levels[31]	41	1			T117	1		T126	1		T127	1
all_levels[32]	28	1			T100	1		T112	1		T123	1
all_levels[33]	30	1			T5	1		T92	1		T128	1
all_levels[34]	32	1			T25	1		T115	1		T117	1
all_levels[35]	21	1			T6	1		T117	1		T129	1
all_levels[36]	18	1			T130	1		T131	1		T132	1
all_levels[37]	16	1			T98	1		T133	1		T131	1
all_levels[38]	20	1			T123	1		T134	2		T135	1
all_levels[39]	19	1			T6	2		T115	1		T136	1
all_levels[40]	19	1			T137	2		T138	1		T139	3
all_levels[41]	24	1			T118	1		T140	1		T141	1
all_levels[42]	15	1			T113	1		T106	1		T142	1
all_levels[43]	11	1			T143	1		T144	1		T145	1
all_levels[44]	20	1			T17	1		T146	1		T147	1
all_levels[45]	19	1			T113	1		T106	1		T141	1
all_levels[46]	13	1			T17	1		T143	1		T141	1
all_levels[47]	12	1			T148	2		T131	1		T149	1
all_levels[48]	14	1			T150	1		T138	1		T131	1
all_levels[49]	20	1			T17	1		T112	2		T151	2
all_levels[50]	9	1			T152	1		T136	1		T153	1
all_levels[51]	10	1			T154	1		T143	1		T155	2
all_levels[52]	12	1			T151	1		T142	1		T156	1
all_levels[53]	12	1			T25	1		T157	1		T131	1
all_levels[54]	11	1			T152	1		T100	1		T106	1
all_levels[55]	9	1			T158	1		T159	2		T160	1
all_levels[56]	7	1			T161	1		T135	1		T162	1
all_levels[57]	7	1			T163	1		T31	1		T135	1
all_levels[58]	14	1			T106	2		T150	1		T164	1
all_levels[59]	6	1			T163	1		T165	1		T135	1
all_levels[60]	15	1			T5	1		T151	1		T166	5
all_levels[61]	7	1			T99	1		T138	1		T167	1
all_levels[62]	7	1			T150	1		T168	2		T169	1
all_levels[63]	13	1			T170	1		T171	1		T148	1
all_levels[64]	81	1			T3	3		T100	1		T172	4

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26228819

1

T1

14

T3

40726

T5

149

auto[1]

4748

1

T1

7

T2

1

T3

30

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57]]	[auto[1]]	--	--	2
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26018499	1			T1	11		T3	40435		T5	143
all_levels[0]	auto[1]	4316	1			T1	4		T2	1		T3	30
all_levels[1]	auto[0]	201840	1			T1	1		T3	251		T5	1
all_levels[1]	auto[1]	78	1			T96	2		T152	1		T12	1
all_levels[2]	auto[0]	2414	1			T3	9		T6	5		T8	25
all_levels[2]	auto[1]	34	1			T92	1		T98	1		T114	1
all_levels[3]	auto[0]	1088	1			T3	5		T5	2		T6	1
all_levels[3]	auto[1]	19	1			T173	2		T174	2		T85	3
all_levels[4]	auto[0]	683	1			T3	3		T14	2		T96	4
all_levels[4]	auto[1]	12	1			T92	1		T175	1		T176	2
all_levels[5]	auto[0]	511	1			T3	1		T5	1		T107	1
all_levels[5]	auto[1]	8	1			T134	1		T177	3		T178	2
all_levels[6]	auto[0]	438	1			T3	2		T32	1		T14	2
all_levels[6]	auto[1]	23	1			T179	1		T180	2		T181	2
all_levels[7]	auto[0]	379	1			T1	1		T3	3		T32	2
all_levels[7]	auto[1]	15	1			T1	1		T93	1		T140	1
all_levels[8]	auto[0]	302	1			T3	2		T13	1		T17	2
all_levels[8]	auto[1]	13	1			T122	2		T182	1		T139	1
all_levels[9]	auto[0]	271	1			T1	1		T3	3		T7	1
all_levels[9]	auto[1]	22	1			T1	2		T108	3		T134	1
all_levels[10]	auto[0]	190	1			T14	1		T107	2		T108	1
all_levels[10]	auto[1]	23	1			T107	1		T114	2		T183	1
all_levels[11]	auto[0]	176	1			T109	1		T110	1		T25	1
all_levels[11]	auto[1]	8	1			T184	2		T185	2		T186	1
all_levels[12]	auto[0]	167	1			T15	1		T111	1		T112	1
all_levels[12]	auto[1]	5	1			T148	1		T187	1		T188	1
all_levels[13]	auto[0]	156	1			T3	1		T107	2		T17	2
all_levels[13]	auto[1]	15	1			T108	1		T189	4		T190	1
all_levels[14]	auto[0]	126	1			T3	3		T15	1		T97	1
all_levels[14]	auto[1]	7	1			T191	4		T192	1		T193	1
all_levels[15]	auto[0]	109	1			T3	1		T14	1		T113	1
all_levels[15]	auto[1]	9	1			T194	1		T125	1		T155	2
all_levels[16]	auto[0]	99	1			T14	1		T96	1		T12	1
all_levels[16]	auto[1]	6	1			T195	1		T196	1		T185	1
all_levels[17]	auto[0]	97	1			T3	1		T96	2		T17	1
all_levels[17]	auto[1]	5	1			T161	1		T197	2		T198	2
all_levels[18]	auto[0]	81	1			T3	1		T113	1		T114	1
all_levels[18]	auto[1]	5	1			T199	1		T200	1		T201	1
all_levels[19]	auto[0]	75	1			T14	1		T33	1		T12	1
all_levels[19]	auto[1]	6	1			T202	2		T203	1		T204	1
all_levels[20]	auto[0]	70	1			T113	2		T26	2		T92	1
all_levels[20]	auto[1]	7	1			T205	1		T144	3		T206	1
all_levels[21]	auto[0]	55	1			T14	1		T33	2		T34	1
all_levels[21]	auto[1]	10	1			T120	1		T207	3		T208	3
all_levels[22]	auto[0]	58	1			T112	1		T26	1		T115	1
all_levels[22]	auto[1]	4	1			T85	1		T209	1		T210	1
all_levels[23]	auto[0]	59	1			T14	1		T111	1		T112	1
all_levels[23]	auto[1]	4	1			T207	1		T211	1		T212	2
all_levels[24]	auto[0]	61	1			T25	1		T92	1		T116	1
all_levels[24]	auto[1]	2	1			T213	1		T214	1		-	-
all_levels[25]	auto[0]	48	1			T111	1		T117	1		T118	1
all_levels[25]	auto[1]	2	1			T215	2		-	-		-	-
all_levels[26]	auto[0]	52	1			T3	1		T119	1		T120	1
all_levels[26]	auto[1]	6	1			T120	2		T216	2		T217	1
all_levels[27]	auto[0]	44	1			T119	1		T121	1		T122	1
all_levels[27]	auto[1]	4	1			T218	1		T219	1		T209	1
all_levels[28]	auto[0]	51	1			T123	1		T124	1		T125	1
all_levels[28]	auto[1]	2	1			T124	1		T182	1		-	-
all_levels[29]	auto[0]	35	1			T110	1		T17	1		T100	1
all_levels[29]	auto[1]	7	1			T110	2		T220	1		T142	1
all_levels[30]	auto[0]	37	1			T3	1		T112	1		T98	2
all_levels[30]	auto[1]	7	1			T161	1		T221	3		T222	1
all_levels[31]	auto[0]	32	1			T117	1		T126	1		T127	1
all_levels[31]	auto[1]	9	1			T223	4		T224	3		T225	2
all_levels[32]	auto[0]	27	1			T100	1		T112	1		T123	1
all_levels[32]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[33]	auto[0]	27	1			T5	1		T92	1		T128	1
all_levels[33]	auto[1]	3	1			T227	1		T228	2		-	-
all_levels[34]	auto[0]	27	1			T25	1		T115	1		T117	1
all_levels[34]	auto[1]	5	1			T182	1		T209	2		T200	2
all_levels[35]	auto[0]	21	1			T6	1		T117	1		T129	1
all_levels[36]	auto[0]	15	1			T130	1		T131	1		T132	1
all_levels[36]	auto[1]	3	1			T229	2		T230	1		-	-
all_levels[37]	auto[0]	13	1			T98	1		T133	1		T131	1
all_levels[37]	auto[1]	3	1			T231	3		-	-		-	-
all_levels[38]	auto[0]	19	1			T123	1		T134	1		T135	1
all_levels[38]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[39]	auto[0]	19	1			T6	2		T115	1		T136	1
all_levels[40]	auto[0]	16	1			T137	1		T138	1		T139	1
all_levels[40]	auto[1]	3	1			T137	1		T139	2		-	-
all_levels[41]	auto[0]	22	1			T118	1		T140	1		T141	1
all_levels[41]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[42]	auto[0]	14	1			T113	1		T106	1		T142	1
all_levels[42]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[43]	auto[0]	10	1			T143	1		T144	1		T145	1
all_levels[43]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[44]	auto[0]	19	1			T17	1		T146	1		T147	1
all_levels[44]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[45]	auto[0]	16	1			T113	1		T106	1		T141	1
all_levels[45]	auto[1]	3	1			T186	1		T236	2		-	-
all_levels[46]	auto[0]	13	1			T17	1		T143	1		T141	1
all_levels[47]	auto[0]	11	1			T148	1		T131	1		T149	1
all_levels[47]	auto[1]	1	1			T148	1		-	-		-	-
all_levels[48]	auto[0]	12	1			T150	1		T138	1		T131	1
all_levels[48]	auto[1]	2	1			T212	2		-	-		-	-
all_levels[49]	auto[0]	15	1			T17	1		T112	1		T151	1
all_levels[49]	auto[1]	5	1			T112	1		T151	1		T182	2
all_levels[50]	auto[0]	9	1			T152	1		T136	1		T153	1
all_levels[51]	auto[0]	8	1			T154	1		T143	1		T155	1
all_levels[51]	auto[1]	2	1			T155	1		T237	1		-	-
all_levels[52]	auto[0]	11	1			T151	1		T142	1		T156	1
all_levels[52]	auto[1]	1	1			T209	1		-	-		-	-
all_levels[53]	auto[0]	8	1			T25	1		T157	1		T131	1
all_levels[53]	auto[1]	4	1			T238	4		-	-		-	-
all_levels[54]	auto[0]	11	1			T152	1		T100	1		T106	1
all_levels[55]	auto[0]	6	1			T158	1		T159	2		T160	1
all_levels[55]	auto[1]	3	1			T239	3		-	-		-	-
all_levels[56]	auto[0]	7	1			T161	1		T135	1		T162	1
all_levels[57]	auto[0]	7	1			T163	1		T31	1		T135	1
all_levels[58]	auto[0]	13	1			T106	2		T150	1		T164	1
all_levels[58]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[59]	auto[0]	6	1			T163	1		T165	1		T135	1
all_levels[60]	auto[0]	11	1			T5	1		T151	1		T166	1
all_levels[60]	auto[1]	4	1			T166	4		-	-		-	-
all_levels[61]	auto[0]	7	1			T99	1		T138	1		T167	1
all_levels[62]	auto[0]	6	1			T150	1		T168	1		T169	1
all_levels[62]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[63]	auto[0]	13	1			T170	1		T171	1		T148	1
all_levels[64]	auto[0]	77	1			T3	3		T100	1		T172	2
all_levels[64]	auto[1]	4	1			T172	2		T216	1		T241	1