Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98546	1			T1	31		T2	1		T3	235
all_pins[1]	98546	1			T1	31		T2	1		T3	235
all_pins[2]	98546	1			T1	31		T2	1		T3	235
all_pins[3]	98546	1			T1	31		T2	1		T3	235
all_pins[4]	98546	1			T1	31		T2	1		T3	235
all_pins[5]	98546	1			T1	31		T2	1		T3	235
all_pins[6]	98546	1			T1	31		T2	1		T3	235
all_pins[7]	98546	1			T1	31		T2	1		T3	235

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	764134	1			T1	239		T2	7		T3	1719
values[0x1]	24234	1			T1	9		T2	1		T3	161
transitions[0x0=>0x1]	23229	1			T1	9		T2	1		T3	146
transitions[0x1=>0x0]	22798	1			T1	8		T3	146		T5	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80730	1			T1	27		T3	137		T4	2
all_pins[0]	values[0x1]	17816	1			T1	4		T2	1		T3	98
all_pins[0]	transitions[0x0=>0x1]	17383	1			T1	4		T2	1		T3	86
all_pins[0]	transitions[0x1=>0x0]	1015	1			T3	1		T15	3		T14	3
all_pins[1]	values[0x0]	97098	1			T1	31		T2	1		T3	222
all_pins[1]	values[0x1]	1448	1			T3	13		T7	2		T15	3
all_pins[1]	transitions[0x0=>0x1]	1344	1			T3	12		T7	2		T15	3
all_pins[1]	transitions[0x1=>0x0]	2453	1			T1	5		T3	4		T5	1
all_pins[2]	values[0x0]	95989	1			T1	26		T2	1		T3	230
all_pins[2]	values[0x1]	2557	1			T1	5		T3	5		T5	1
all_pins[2]	transitions[0x0=>0x1]	2493	1			T1	5		T3	5		T5	1
all_pins[2]	transitions[0x1=>0x0]	260	1			T3	2		T11	1		T12	5
all_pins[3]	values[0x0]	98222	1			T1	31		T2	1		T3	233
all_pins[3]	values[0x1]	324	1			T3	2		T11	1		T13	1
all_pins[3]	transitions[0x0=>0x1]	284	1			T3	2		T11	1		T13	1
all_pins[3]	transitions[0x1=>0x0]	420	1			T3	12		T11	2		T13	2
all_pins[4]	values[0x0]	98086	1			T1	31		T2	1		T3	223
all_pins[4]	values[0x1]	460	1			T3	12		T11	2		T13	2
all_pins[4]	transitions[0x0=>0x1]	392	1			T3	10		T11	2		T13	2
all_pins[4]	transitions[0x1=>0x0]	177	1			T11	1		T13	3		T12	1
all_pins[5]	values[0x0]	98301	1			T1	31		T2	1		T3	233
all_pins[5]	values[0x1]	245	1			T3	2		T11	1		T13	3
all_pins[5]	transitions[0x0=>0x1]	199	1			T3	2		T11	1		T13	3
all_pins[5]	transitions[0x1=>0x0]	919	1			T3	15		T7	2		T8	3
all_pins[6]	values[0x0]	97581	1			T1	31		T2	1		T3	220
all_pins[6]	values[0x1]	965	1			T3	15		T7	2		T8	3
all_pins[6]	transitions[0x0=>0x1]	904	1			T3	15		T7	2		T8	3
all_pins[6]	transitions[0x1=>0x0]	358	1			T3	14		T14	2		T13	2
all_pins[7]	values[0x0]	98127	1			T1	31		T2	1		T3	221
all_pins[7]	values[0x1]	419	1			T3	14		T14	2		T13	2
all_pins[7]	transitions[0x0=>0x1]	230	1			T3	14		T14	2		T13	2
all_pins[7]	transitions[0x1=>0x0]	17196	1			T1	3		T3	98		T5	1