Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6567648	1			T1	2		T3	8520		T5	40
all_levels[1]	1292965	1			T3	186		T5	2		T6	2
all_levels[2]	293431	1			T3	191		T5	6		T6	3
all_levels[3]	206550	1			T3	3588		T5	2		T6	12
all_levels[4]	269413	1			T3	13967		T5	1		T6	2
all_levels[5]	200986	1			T1	3		T3	34		T5	2
all_levels[6]	202249	1			T3	46		T5	4		T8	20
all_levels[7]	186177	1			T3	21		T5	3		T7	1
all_levels[8]	344686	1			T3	22		T8	18		T32	33
all_levels[9]	202480	1			T3	24		T5	1		T8	18
all_levels[10]	213055	1			T3	23		T5	3		T8	21
all_levels[11]	179626	1			T3	20		T8	20		T32	29
all_levels[12]	174675	1			T3	31		T8	21		T32	36
all_levels[13]	175313	1			T3	28		T6	4		T8	20
all_levels[14]	345239	1			T3	23		T8	25		T32	15
all_levels[15]	189272	1			T3	19		T8	18		T32	21
all_levels[16]	211772	1			T3	11679		T8	23		T32	12
all_levels[17]	223587	1			T3	10		T6	2		T7	2
all_levels[18]	161782	1			T1	3		T3	21		T6	20
all_levels[19]	279061	1			T3	26		T6	5		T7	1
all_levels[20]	190063	1			T3	28		T6	2		T7	2
all_levels[21]	203879	1			T3	15		T6	5		T8	17
all_levels[22]	155118	1			T3	19		T6	1		T7	1
all_levels[23]	284941	1			T3	15		T5	11		T6	13
all_levels[24]	226245	1			T1	3		T3	13		T8	17
all_levels[25]	149854	1			T3	18		T5	1		T6	4
all_levels[26]	188538	1			T3	37		T6	3		T8	22
all_levels[27]	167518	1			T3	19		T6	2		T8	23
all_levels[28]	239405	1			T3	25		T5	1		T6	3
all_levels[29]	136866	1			T3	25		T6	1		T8	21
all_levels[30]	129274	1			T3	17		T5	3		T6	3
all_levels[31]	481593	1			T3	180		T6	1		T8	710
all_levels[32]	11759919	1			T1	10		T3	1853		T5	78

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26228819

1

T1

14

T3

40726

T5

149

auto[1]

4361

1

T1

7

T3

17

T5

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6565359	1			T1	1		T3	8505		T5	40
all_levels[0]	auto[1]	2289	1			T1	1		T3	15		T7	2
all_levels[1]	auto[0]	1292626	1			T3	185		T5	2		T6	2
all_levels[1]	auto[1]	339	1			T3	1		T107	1		T110	2
all_levels[2]	auto[0]	293400	1			T3	191		T5	6		T6	3
all_levels[2]	auto[1]	31	1			T120	1		T323	2		T324	1
all_levels[3]	auto[0]	206382	1			T3	3588		T5	2		T6	12
all_levels[3]	auto[1]	168	1			T110	1		T152	1		T305	7
all_levels[4]	auto[0]	269354	1			T3	13967		T5	1		T6	2
all_levels[4]	auto[1]	59	1			T7	1		T260	1		T140	2
all_levels[5]	auto[0]	200955	1			T1	1		T3	34		T5	2
all_levels[5]	auto[1]	31	1			T1	2		T93	2		T151	1
all_levels[6]	auto[0]	202227	1			T3	46		T5	4		T8	20
all_levels[6]	auto[1]	22	1			T114	1		T122	2		T170	1
all_levels[7]	auto[0]	185958	1			T3	21		T5	3		T7	1
all_levels[7]	auto[1]	219	1			T11	8		T134	9		T325	6
all_levels[8]	auto[0]	344657	1			T3	22		T8	18		T32	33
all_levels[8]	auto[1]	29	1			T110	2		T34	2		T255	2
all_levels[9]	auto[0]	202463	1			T3	24		T5	1		T8	18
all_levels[9]	auto[1]	17	1			T15	1		T245	1		T173	1
all_levels[10]	auto[0]	213017	1			T3	23		T5	1		T8	21
all_levels[10]	auto[1]	38	1			T5	2		T38	3		T134	1
all_levels[11]	auto[0]	179610	1			T3	20		T8	20		T32	29
all_levels[11]	auto[1]	16	1			T92	1		T98	1		T99	2
all_levels[12]	auto[0]	174649	1			T3	31		T8	21		T32	36
all_levels[12]	auto[1]	26	1			T246	1		T269	1		T118	1
all_levels[13]	auto[0]	175272	1			T3	28		T6	4		T8	20
all_levels[13]	auto[1]	41	1			T113	1		T64	1		T151	1
all_levels[14]	auto[0]	345215	1			T3	23		T8	25		T32	15
all_levels[14]	auto[1]	24	1			T114	1		T194	1		T227	2
all_levels[15]	auto[0]	189120	1			T3	19		T8	18		T32	21
all_levels[15]	auto[1]	152	1			T152	1		T115	1		T30	11
all_levels[16]	auto[0]	211750	1			T3	11678		T8	23		T32	12
all_levels[16]	auto[1]	22	1			T3	1		T12	1		T85	1
all_levels[17]	auto[0]	223572	1			T3	10		T6	2		T7	2
all_levels[17]	auto[1]	15	1			T264	1		T326	1		T327	1
all_levels[18]	auto[0]	161764	1			T1	1		T3	21		T6	20
all_levels[18]	auto[1]	18	1			T1	2		T274	1		T280	1
all_levels[19]	auto[0]	279041	1			T3	26		T6	5		T7	1
all_levels[19]	auto[1]	20	1			T108	1		T120	1		T181	1
all_levels[20]	auto[0]	190049	1			T3	28		T6	2		T7	2
all_levels[20]	auto[1]	14	1			T220	1		T328	2		T329	1
all_levels[21]	auto[0]	203859	1			T3	15		T6	5		T8	17
all_levels[21]	auto[1]	20	1			T108	1		T98	1		T144	1
all_levels[22]	auto[0]	155093	1			T3	19		T6	1		T7	1
all_levels[22]	auto[1]	25	1			T95	1		T147	2		T330	1
all_levels[23]	auto[0]	284918	1			T3	15		T5	9		T6	13
all_levels[23]	auto[1]	23	1			T5	2		T184	1		T123	1
all_levels[24]	auto[0]	226234	1			T1	2		T3	13		T8	17
all_levels[24]	auto[1]	11	1			T1	1		T140	1		T146	1
all_levels[25]	auto[0]	149831	1			T3	18		T5	1		T6	4
all_levels[25]	auto[1]	23	1			T109	1		T118	1		T258	2
all_levels[26]	auto[0]	188510	1			T3	37		T6	3		T8	22
all_levels[26]	auto[1]	28	1			T172	1		T320	3		T121	1
all_levels[27]	auto[0]	167505	1			T3	19		T6	2		T8	23
all_levels[27]	auto[1]	13	1			T331	2		T332	4		T333	1
all_levels[28]	auto[0]	239389	1			T3	25		T5	1		T6	3
all_levels[28]	auto[1]	16	1			T244	1		T301	1		T147	1
all_levels[29]	auto[0]	136847	1			T3	25		T6	1		T8	21
all_levels[29]	auto[1]	19	1			T96	1		T134	3		T161	1
all_levels[30]	auto[0]	129255	1			T3	17		T5	3		T6	3
all_levels[30]	auto[1]	19	1			T25	1		T334	1		T141	1
all_levels[31]	auto[0]	481569	1			T3	180		T6	1		T8	710
all_levels[31]	auto[1]	24	1			T34	2		T100	3		T278	1
all_levels[32]	auto[0]	11759369	1			T1	9		T3	1853		T5	73
all_levels[32]	auto[1]	550	1			T1	1		T5	5		T7	2