Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	808	1			T3	12		T13	7		T12	4
all_values[1]	808	1			T3	12		T13	7		T12	4
all_values[2]	808	1			T3	12		T13	7		T12	4
all_values[3]	808	1			T3	12		T13	7		T12	4
all_values[4]	808	1			T3	12		T13	7		T12	4
all_values[5]	808	1			T3	12		T13	7		T12	4
all_values[6]	808	1			T3	12		T13	7		T12	4
all_values[7]	808	1			T3	12		T13	7		T12	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3584

1

T3

56

T13

34

T12

17

auto[1]

2880

1

T3

40

T13

22

T12

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T3

38

T13

20

T12

12

auto[1]

4122

1

T3

58

T13

36

T12

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3805

1

T3

58

T13

35

T12

22

auto[1]

2659

1

T3

38

T13

21

T12

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	261	1			T3	4		T13	4		T12	1
all_values[0]	auto[0]	auto[1]	auto[1]	211	1			T3	3		T13	1		T12	2
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T3	2		T13	1		T64	3
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T3	3		T13	1		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	275	1			T3	3		T13	3		T12	1
all_values[1]	auto[0]	auto[1]	auto[0]	211	1			T3	3		T13	1		T64	2
all_values[1]	auto[1]	auto[0]	auto[1]	184	1			T3	2		T12	3		T64	2
all_values[1]	auto[1]	auto[1]	auto[1]	138	1			T3	4		T13	3		T64	2
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T3	2		T13	1		T12	2
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T3	1		T13	1		T28	3
all_values[2]	auto[0]	auto[1]	auto[0]	139	1			T3	5		T13	2		T12	1
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T64	1		T28	1		T104	1
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T3	1		T13	1		T28	1
all_values[2]	auto[1]	auto[1]	auto[1]	144	1			T3	3		T13	2		T12	1
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T3	5		T13	1		T12	4
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T3	3		T13	4		T64	1
all_values[3]	auto[0]	auto[1]	auto[0]	115	1			T3	1		T64	2		T28	3
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T28	2		T104	1		T105	2
all_values[3]	auto[1]	auto[0]	auto[1]	193	1			T3	2		T13	2		T64	1
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T3	1		T28	4		T105	1
all_values[4]	auto[0]	auto[0]	auto[0]	206	1			T3	5		T13	1		T12	1
all_values[4]	auto[0]	auto[0]	auto[1]	68	1			T3	1		T13	1		T82	2
all_values[4]	auto[0]	auto[1]	auto[0]	139	1			T3	2		T64	2		T28	1
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T3	1		T13	1		T12	2
all_values[4]	auto[1]	auto[0]	auto[1]	188	1			T13	2		T28	4		T104	1
all_values[4]	auto[1]	auto[1]	auto[1]	136	1			T3	3		T13	2		T12	1
all_values[5]	auto[0]	auto[0]	auto[0]	176	1			T3	2		T13	2		T28	7
all_values[5]	auto[0]	auto[0]	auto[1]	84	1			T3	2		T12	1		T64	3
all_values[5]	auto[0]	auto[1]	auto[0]	125	1			T3	2		T104	3		T105	1
all_values[5]	auto[0]	auto[1]	auto[1]	74	1			T13	1		T12	1		T28	1
all_values[5]	auto[1]	auto[0]	auto[1]	195	1			T3	4		T13	1		T12	1
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T3	2		T13	3		T12	1
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T3	2		T13	3		T64	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T13	1		T64	2		T105	2
all_values[6]	auto[0]	auto[1]	auto[0]	140	1			T13	2		T12	3		T28	1
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T3	3		T82	1		T106	2
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T3	5		T13	1		T64	4
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T3	2		T12	1		T28	1
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T3	6		T13	3		T64	3
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T3	2		T12	3		T64	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T13	1		T28	3		T105	1
all_values[7]	auto[0]	auto[1]	auto[1]	103	1			T13	1		T64	1		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	170	1			T3	2		T13	1		T64	2
all_values[7]	auto[1]	auto[1]	auto[1]	159	1			T3	2		T13	1		T12	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal