Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	107717	1			T1	1		T2	12		T4	1
all_values[1]	107717	1			T1	1		T2	12		T4	1
all_values[2]	107717	1			T1	1		T2	12		T4	1
all_values[3]	107717	1			T1	1		T2	12		T4	1
all_values[4]	107717	1			T1	1		T2	12		T4	1
all_values[5]	107717	1			T1	1		T2	12		T4	1
all_values[6]	107717	1			T1	1		T2	12		T4	1
all_values[7]	107717	1			T1	1		T2	12		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

427487

1

T1

4

T2

70

T4

4

auto[1]

434249

1

T1

4

T2

26

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

809062

1

T1

7

T2

83

T4

7

auto[1]

52674

1

T1

1

T2

13

T4

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35315	1			T5	11		T7	13		T9	114
all_values[0]	auto[0]	auto[1]	21952	1			T1	1		T2	10		T5	15
all_values[0]	auto[1]	auto[0]	31267	1			T5	8		T7	11		T9	3
all_values[0]	auto[1]	auto[1]	19183	1			T2	2		T4	1		T6	1
all_values[1]	auto[0]	auto[0]	50556	1			T2	10		T5	20		T6	1
all_values[1]	auto[0]	auto[1]	1622	1			T15	10		T17	12		T19	4
all_values[1]	auto[1]	auto[0]	53954	1			T1	1		T2	2		T4	1
all_values[1]	auto[1]	auto[1]	1585	1			T9	2		T94	6		T23	4
all_values[2]	auto[0]	auto[0]	47102	1			T2	10		T4	1		T5	24
all_values[2]	auto[0]	auto[1]	2824	1			T5	4		T7	1		T9	3
all_values[2]	auto[1]	auto[0]	55408	1			T1	1		T2	1		T5	3
all_values[2]	auto[1]	auto[1]	2383	1			T2	1		T5	3		T7	2
all_values[3]	auto[0]	auto[0]	48406	1			T1	1		T6	1		T7	56
all_values[3]	auto[0]	auto[1]	308	1			T15	1		T17	1		T16	6
all_values[3]	auto[1]	auto[0]	58669	1			T2	12		T4	1		T5	34
all_values[3]	auto[1]	auto[1]	334	1			T14	1		T17	3		T16	5
all_values[4]	auto[0]	auto[0]	54174	1			T1	1		T2	10		T4	1
all_values[4]	auto[0]	auto[1]	444	1			T17	4		T16	24		T123	1
all_values[4]	auto[1]	auto[0]	52595	1			T2	2		T5	14		T6	1
all_values[4]	auto[1]	auto[1]	504	1			T15	5		T17	1		T19	2
all_values[5]	auto[0]	auto[0]	53507	1			T1	1		T2	10		T5	20
all_values[5]	auto[0]	auto[1]	215	1			T19	1		T16	5		T129	3
all_values[5]	auto[1]	auto[0]	53804	1			T2	2		T4	1		T5	14
all_values[5]	auto[1]	auto[1]	191	1			T19	2		T16	2		T32	1
all_values[6]	auto[0]	auto[0]	53981	1			T2	10		T4	1		T5	16
all_values[6]	auto[0]	auto[1]	186	1			T17	3		T19	1		T16	2
all_values[6]	auto[1]	auto[0]	53373	1			T1	1		T2	2		T5	18
all_values[6]	auto[1]	auto[1]	177	1			T19	2		T16	5		T32	1
all_values[7]	auto[0]	auto[0]	56540	1			T2	10		T4	1		T5	20
all_values[7]	auto[0]	auto[1]	355	1			T17	3		T19	3		T16	9
all_values[7]	auto[1]	auto[0]	50411	1			T1	1		T2	2		T5	14
all_values[7]	auto[1]	auto[1]	411	1			T17	2		T24	4		T16	5