Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2248	1			T1	6		T2	1		T4	6
auto[BaudRate115200]	2017	1			T1	3		T2	1		T5	3
auto[BaudRate230400]	2006	1			T1	3		T2	1		T5	1
auto[BaudRate128Kbps]	1930	1			T1	3		T2	1		T5	2
auto[BaudRate256Kbps]	2182	1			T1	3		T2	2		T11	2
auto[BaudRate1Mbps]	1805	1			T1	3		T2	2		T6	3
auto[BaudRate1p5Mbps]	1304	1			T1	3		T5	1		T6	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1520	1			T1	24		T7	4		T11	16
freqs[25]	1349	1			T14	6		T39	20		T278	8
freqs[48]	580	1			T45	10		T340	16		T341	2
freqs[50]	589	1			T93	5		T15	26		T44	17
freqs[100]	1205	1			T12	8		T42	7		T38	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	309	1			T1	6		T11	3		T190	2
auto[BaudRate9600]	freqs[25]	200	1			T14	1		T39	1		T278	1
auto[BaudRate9600]	freqs[48]	89	1			T45	2		T340	16		T294	1
auto[BaudRate9600]	freqs[50]	93	1			T93	2		T15	6		T44	3
auto[BaudRate9600]	freqs[100]	200	1			T342	12		T263	3		T151	2
auto[BaudRate115200]	freqs[24]	227	1			T1	3		T11	3		T190	3
auto[BaudRate115200]	freqs[25]	191	1			T39	2		T278	1		T21	4
auto[BaudRate115200]	freqs[48]	77	1			T45	3		T341	1		T294	1
auto[BaudRate115200]	freqs[50]	65	1			T15	1		T44	2		T134	1
auto[BaudRate115200]	freqs[100]	165	1			T12	3		T263	1		T151	3
auto[BaudRate230400]	freqs[24]	195	1			T1	3		T7	2		T265	3
auto[BaudRate230400]	freqs[25]	206	1			T14	3		T39	6		T21	5
auto[BaudRate230400]	freqs[48]	89	1			T45	2		T341	1		T294	2
auto[BaudRate230400]	freqs[50]	87	1			T15	2		T44	2		T322	1
auto[BaudRate230400]	freqs[100]	121	1			T38	1		T263	1		T151	1
auto[BaudRate128Kbps]	freqs[24]	197	1			T1	3		T7	2		T11	4
auto[BaudRate128Kbps]	freqs[25]	172	1			T39	3		T278	2		T21	6
auto[BaudRate128Kbps]	freqs[48]	80	1			T45	1		T294	2		T157	1
auto[BaudRate128Kbps]	freqs[50]	73	1			T93	1		T15	7		T44	3
auto[BaudRate128Kbps]	freqs[100]	146	1			T12	1		T38	1		T343	3
auto[BaudRate256Kbps]	freqs[24]	208	1			T1	3		T11	2		T190	1
auto[BaudRate256Kbps]	freqs[25]	234	1			T14	1		T39	3		T278	2
auto[BaudRate256Kbps]	freqs[48]	83	1			T294	2		T157	1		T292	2
auto[BaudRate256Kbps]	freqs[50]	75	1			T93	1		T15	4		T44	6
auto[BaudRate256Kbps]	freqs[100]	182	1			T12	1		T42	4		T38	1
auto[BaudRate1Mbps]	freqs[24]	268	1			T1	3		T11	4		T297	1
auto[BaudRate1Mbps]	freqs[25]	208	1			T14	1		T39	3		T278	2
auto[BaudRate1Mbps]	freqs[48]	86	1			T45	2		T157	1		T204	3
auto[BaudRate1Mbps]	freqs[50]	95	1			T15	1		T134	1		T301	2
auto[BaudRate1Mbps]	freqs[100]	191	1			T42	1		T38	2		T343	6
auto[BaudRate1p5Mbps]	freqs[25]	138	1			T39	2		T21	1		T121	1
auto[BaudRate1p5Mbps]	freqs[48]	76	1			T294	1		T157	4		T204	1
auto[BaudRate1p5Mbps]	freqs[50]	101	1			T93	1		T15	5		T44	1
auto[BaudRate1p5Mbps]	freqs[100]	200	1			T12	3		T42	2		T38	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded