Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29668016	1			T1	2		T2	12		T4	1
all_levels[1]	183165	1			T2	1		T9	73		T10	1
all_levels[2]	2438	1			T5	3		T9	2		T11	6
all_levels[3]	1124	1			T10	1		T11	2		T12	3
all_levels[4]	768	1			T2	1		T9	1		T10	1
all_levels[5]	572	1			T11	5		T12	3		T13	1
all_levels[6]	447	1			T9	1		T11	2		T12	3
all_levels[7]	359	1			T11	2		T12	1		T13	1
all_levels[8]	316	1			T132	1		T15	1		T133	1
all_levels[9]	261	1			T9	1		T10	1		T15	1
all_levels[10]	239	1			T10	1		T23	1		T15	2
all_levels[11]	178	1			T10	1		T12	2		T132	1
all_levels[12]	174	1			T12	1		T23	1		T133	1
all_levels[13]	154	1			T2	2		T9	2		T12	4
all_levels[14]	136	1			T23	1		T15	2		T134	1
all_levels[15]	120	1			T94	1		T23	1		T15	1
all_levels[16]	97	1			T2	1		T10	2		T94	2
all_levels[17]	81	1			T14	1		T135	1		T40	1
all_levels[18]	90	1			T17	1		T134	1		T136	1
all_levels[19]	99	1			T23	2		T135	1		T16	1
all_levels[20]	77	1			T2	1		T137	1		T135	1
all_levels[21]	88	1			T10	2		T93	1		T135	1
all_levels[22]	69	1			T2	1		T15	1		T36	2
all_levels[23]	44	1			T15	1		T36	2		T24	1
all_levels[24]	70	1			T10	1		T23	1		T17	1
all_levels[25]	64	1			T9	1		T38	5		T138	1
all_levels[26]	44	1			T9	1		T15	1		T139	1
all_levels[27]	69	1			T2	1		T9	2		T23	1
all_levels[28]	37	1			T23	1		T36	1		T140	1
all_levels[29]	52	1			T45	2		T141	1		T142	2
all_levels[30]	46	1			T23	1		T135	1		T141	1
all_levels[31]	41	1			T143	1		T144	1		T141	1
all_levels[32]	31	1			T140	1		T145	3		T108	1
all_levels[33]	26	1			T14	1		T23	1		T15	1
all_levels[34]	29	1			T146	1		T147	1		T148	1
all_levels[35]	25	1			T9	1		T145	1		T142	1
all_levels[36]	28	1			T143	1		T146	1		T149	3
all_levels[37]	21	1			T10	1		T53	1		T150	1
all_levels[38]	20	1			T151	1		T119	1		T152	1
all_levels[39]	24	1			T15	2		T16	1		T121	1
all_levels[40]	28	1			T140	1		T121	2		T141	1
all_levels[41]	19	1			T140	1		T153	1		T154	1
all_levels[42]	22	1			T2	1		T15	1		T121	1
all_levels[43]	12	1			T23	1		T141	1		T155	1
all_levels[44]	17	1			T2	1		T150	1		T156	1
all_levels[45]	16	1			T2	1		T15	1		T157	1
all_levels[46]	13	1			T146	1		T158	3		T159	1
all_levels[47]	20	1			T142	1		T160	1		T161	1
all_levels[48]	11	1			T2	1		T144	1		T162	1
all_levels[49]	14	1			T10	2		T14	1		T163	1
all_levels[50]	23	1			T154	1		T155	3		T164	2
all_levels[51]	20	1			T2	1		T144	1		T142	1
all_levels[52]	8	1			T93	1		T165	1		T78	1
all_levels[53]	18	1			T10	1		T166	1		T167	2
all_levels[54]	20	1			T124	1		T121	1		T55	1
all_levels[55]	13	1			T15	1		T168	1		T169	1
all_levels[56]	9	1			T120	1		T170	1		T171	1
all_levels[57]	12	1			T172	2		T173	1		T174	1
all_levels[58]	8	1			T175	1		T176	1		T177	1
all_levels[59]	15	1			T178	1		T179	1		T180	3
all_levels[60]	5	1			T177	1		T181	1		T182	1
all_levels[61]	16	1			T138	1		T183	2		T184	3
all_levels[62]	5	1			T183	1		T155	1		T116	1
all_levels[63]	4	1			T177	1		T185	1		T186	1
all_levels[64]	107	1			T136	1		T124	2		T157	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29855592

1

T2

19

T5

168

T7

923

auto[1]

4602

1

T1

2

T2

6

T4

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29663864	1			T2	7		T5	165		T7	923
all_levels[0]	auto[1]	4152	1			T1	2		T2	5		T4	1
all_levels[1]	auto[0]	183088	1			T2	1		T9	73		T10	1
all_levels[1]	auto[1]	77	1			T15	5		T37	1		T187	2
all_levels[2]	auto[0]	2404	1			T5	3		T9	2		T11	6
all_levels[2]	auto[1]	34	1			T14	1		T120	1		T144	1
all_levels[3]	auto[0]	1097	1			T10	1		T11	2		T12	3
all_levels[3]	auto[1]	27	1			T144	1		T188	1		T189	1
all_levels[4]	auto[0]	751	1			T2	1		T9	1		T10	1
all_levels[4]	auto[1]	17	1			T190	1		T191	2		T183	1
all_levels[5]	auto[0]	551	1			T11	5		T12	3		T13	1
all_levels[5]	auto[1]	21	1			T192	3		T49	3		T130	2
all_levels[6]	auto[0]	433	1			T9	1		T11	2		T12	3
all_levels[6]	auto[1]	14	1			T93	2		T193	2		T194	1
all_levels[7]	auto[0]	351	1			T11	2		T12	1		T13	1
all_levels[7]	auto[1]	8	1			T195	1		T196	2		T197	1
all_levels[8]	auto[0]	305	1			T132	1		T15	1		T133	1
all_levels[8]	auto[1]	11	1			T198	2		T153	1		T199	1
all_levels[9]	auto[0]	249	1			T9	1		T10	1		T15	1
all_levels[9]	auto[1]	12	1			T200	1		T112	1		T201	1
all_levels[10]	auto[0]	229	1			T10	1		T23	1		T15	2
all_levels[10]	auto[1]	10	1			T190	2		T202	1		T203	1
all_levels[11]	auto[0]	168	1			T10	1		T12	2		T132	1
all_levels[11]	auto[1]	10	1			T204	1		T205	3		T206	3
all_levels[12]	auto[0]	164	1			T12	1		T23	1		T133	1
all_levels[12]	auto[1]	10	1			T193	1		T207	1		T208	1
all_levels[13]	auto[0]	146	1			T2	1		T9	1		T12	4
all_levels[13]	auto[1]	8	1			T2	1		T9	1		T202	1
all_levels[14]	auto[0]	125	1			T23	1		T15	2		T134	1
all_levels[14]	auto[1]	11	1			T183	1		T209	1		T210	2
all_levels[15]	auto[0]	117	1			T94	1		T23	1		T15	1
all_levels[15]	auto[1]	3	1			T124	1		T211	1		T212	1
all_levels[16]	auto[0]	89	1			T2	1		T10	2		T94	1
all_levels[16]	auto[1]	8	1			T94	1		T183	1		T171	1
all_levels[17]	auto[0]	75	1			T14	1		T135	1		T40	1
all_levels[17]	auto[1]	6	1			T213	2		T214	1		T215	1
all_levels[18]	auto[0]	85	1			T17	1		T134	1		T136	1
all_levels[18]	auto[1]	5	1			T216	1		T217	1		T218	1
all_levels[19]	auto[0]	89	1			T23	2		T135	1		T16	1
all_levels[19]	auto[1]	10	1			T170	1		T219	3		T220	1
all_levels[20]	auto[0]	74	1			T2	1		T137	1		T135	1
all_levels[20]	auto[1]	3	1			T221	2		T222	1		-	-
all_levels[21]	auto[0]	78	1			T10	2		T93	1		T135	1
all_levels[21]	auto[1]	10	1			T223	1		T224	3		T225	1
all_levels[22]	auto[0]	62	1			T2	1		T15	1		T36	2
all_levels[22]	auto[1]	7	1			T226	2		T227	1		T228	1
all_levels[23]	auto[0]	39	1			T15	1		T36	1		T24	1
all_levels[23]	auto[1]	5	1			T36	1		T159	4		-	-
all_levels[24]	auto[0]	68	1			T10	1		T23	1		T17	1
all_levels[24]	auto[1]	2	1			T38	1		T213	1		-	-
all_levels[25]	auto[0]	57	1			T9	1		T38	3		T138	1
all_levels[25]	auto[1]	7	1			T38	2		T161	1		T229	1
all_levels[26]	auto[0]	43	1			T9	1		T15	1		T139	1
all_levels[26]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[27]	auto[0]	58	1			T2	1		T9	1		T23	1
all_levels[27]	auto[1]	11	1			T9	1		T231	1		T172	1
all_levels[28]	auto[0]	36	1			T23	1		T36	1		T140	1
all_levels[28]	auto[1]	1	1			T201	1		-	-		-	-
all_levels[29]	auto[0]	44	1			T45	1		T141	1		T142	2
all_levels[29]	auto[1]	8	1			T45	1		T147	1		T193	1
all_levels[30]	auto[0]	40	1			T23	1		T135	1		T141	1
all_levels[30]	auto[1]	6	1			T232	3		T233	2		T234	1
all_levels[31]	auto[0]	37	1			T143	1		T144	1		T141	1
all_levels[31]	auto[1]	4	1			T235	1		T210	1		T236	2
all_levels[32]	auto[0]	27	1			T140	1		T145	1		T108	1
all_levels[32]	auto[1]	4	1			T145	2		T237	2		-	-
all_levels[33]	auto[0]	24	1			T14	1		T23	1		T15	1
all_levels[33]	auto[1]	2	1			T214	1		T238	1		-	-
all_levels[34]	auto[0]	24	1			T146	1		T147	1		T148	1
all_levels[34]	auto[1]	5	1			T231	1		T239	3		T240	1
all_levels[35]	auto[0]	23	1			T9	1		T145	1		T142	1
all_levels[35]	auto[1]	2	1			T241	1		T216	1		-	-
all_levels[36]	auto[0]	25	1			T143	1		T146	1		T149	1
all_levels[36]	auto[1]	3	1			T149	2		T210	1		-	-
all_levels[37]	auto[0]	19	1			T10	1		T53	1		T150	1
all_levels[37]	auto[1]	2	1			T237	1		T242	1		-	-
all_levels[38]	auto[0]	20	1			T151	1		T119	1		T152	1
all_levels[39]	auto[0]	19	1			T15	1		T16	1		T121	1
all_levels[39]	auto[1]	5	1			T15	1		T243	1		T244	2
all_levels[40]	auto[0]	21	1			T140	1		T121	1		T141	1
all_levels[40]	auto[1]	7	1			T121	1		T245	1		T246	2
all_levels[41]	auto[0]	19	1			T140	1		T153	1		T154	1
all_levels[42]	auto[0]	20	1			T2	1		T15	1		T121	1
all_levels[42]	auto[1]	2	1			T179	1		T247	1		-	-
all_levels[43]	auto[0]	9	1			T23	1		T141	1		T155	1
all_levels[43]	auto[1]	3	1			T248	3		-	-		-	-
all_levels[44]	auto[0]	17	1			T2	1		T150	1		T156	1
all_levels[45]	auto[0]	15	1			T2	1		T15	1		T157	1
all_levels[45]	auto[1]	1	1			T249	1		-	-		-	-
all_levels[46]	auto[0]	11	1			T146	1		T158	1		T159	1
all_levels[46]	auto[1]	2	1			T158	2		-	-		-	-
all_levels[47]	auto[0]	16	1			T142	1		T160	1		T161	1
all_levels[47]	auto[1]	4	1			T250	2		T251	1		T252	1
all_levels[48]	auto[0]	11	1			T2	1		T144	1		T162	1
all_levels[49]	auto[0]	14	1			T10	2		T14	1		T163	1
all_levels[50]	auto[0]	19	1			T154	1		T155	3		T164	1
all_levels[50]	auto[1]	4	1			T164	1		T253	3		-	-
all_levels[51]	auto[0]	16	1			T2	1		T144	1		T142	1
all_levels[51]	auto[1]	4	1			T226	1		T221	3		-	-
all_levels[52]	auto[0]	7	1			T93	1		T165	1		T78	1
all_levels[52]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[53]	auto[0]	13	1			T10	1		T166	1		T167	1
all_levels[53]	auto[1]	5	1			T167	1		T255	1		T256	2
all_levels[54]	auto[0]	16	1			T124	1		T121	1		T55	1
all_levels[54]	auto[1]	4	1			T257	3		T252	1		-	-
all_levels[55]	auto[0]	13	1			T15	1		T168	1		T169	1
all_levels[56]	auto[0]	8	1			T120	1		T170	1		T171	1
all_levels[56]	auto[1]	1	1			T258	1		-	-		-	-
all_levels[57]	auto[0]	11	1			T172	1		T173	1		T174	1
all_levels[57]	auto[1]	1	1			T172	1		-	-		-	-
all_levels[58]	auto[0]	8	1			T175	1		T176	1		T177	1
all_levels[59]	auto[0]	9	1			T178	1		T179	1		T180	1
all_levels[59]	auto[1]	6	1			T180	2		T230	1		T259	3
all_levels[60]	auto[0]	5	1			T177	1		T181	1		T182	1
all_levels[61]	auto[0]	13	1			T138	1		T183	1		T184	1
all_levels[61]	auto[1]	3	1			T183	1		T184	2		-	-
all_levels[62]	auto[0]	5	1			T183	1		T155	1		T116	1
all_levels[63]	auto[0]	4	1			T177	1		T185	1		T186	1
all_levels[64]	auto[0]	95	1			T136	1		T124	1		T157	2
all_levels[64]	auto[1]	12	1			T124	1		T160	1		T169	2