Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	107717	1			T1	1		T2	12		T4	1
all_pins[1]	107717	1			T1	1		T2	12		T4	1
all_pins[2]	107717	1			T1	1		T2	12		T4	1
all_pins[3]	107717	1			T1	1		T2	12		T4	1
all_pins[4]	107717	1			T1	1		T2	12		T4	1
all_pins[5]	107717	1			T1	1		T2	12		T4	1
all_pins[6]	107717	1			T1	1		T2	12		T4	1
all_pins[7]	107717	1			T1	1		T2	12		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	836102	1			T1	8		T2	92		T4	7
values[0x1]	25634	1			T2	4		T4	1		T5	3
transitions[0x0=>0x1]	24525	1			T2	4		T4	1		T5	3
transitions[0x1=>0x0]	24089	1			T2	3		T5	3		T7	45

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	88453	1			T1	1		T2	10		T5	34
all_pins[0]	values[0x1]	19264	1			T2	2		T4	1		T6	1
all_pins[0]	transitions[0x0=>0x1]	18706	1			T2	2		T4	1		T6	1
all_pins[0]	transitions[0x1=>0x0]	1021	1			T9	2		T94	6		T23	4
all_pins[1]	values[0x0]	106138	1			T1	1		T2	12		T4	1
all_pins[1]	values[0x1]	1579	1			T9	2		T94	6		T23	4
all_pins[1]	transitions[0x0=>0x1]	1477	1			T9	1		T94	5		T23	4
all_pins[1]	transitions[0x1=>0x0]	2335	1			T2	1		T5	3		T7	2
all_pins[2]	values[0x0]	105280	1			T1	1		T2	11		T4	1
all_pins[2]	values[0x1]	2437	1			T2	1		T5	3		T7	2
all_pins[2]	transitions[0x0=>0x1]	2360	1			T2	1		T5	3		T7	2
all_pins[2]	transitions[0x1=>0x0]	257	1			T14	1		T17	2		T16	5
all_pins[3]	values[0x0]	107383	1			T1	1		T2	12		T4	1
all_pins[3]	values[0x1]	334	1			T14	1		T17	3		T16	5
all_pins[3]	transitions[0x0=>0x1]	295	1			T14	1		T17	3		T16	5
all_pins[3]	transitions[0x1=>0x0]	465	1			T15	5		T17	1		T19	2
all_pins[4]	values[0x0]	107213	1			T1	1		T2	12		T4	1
all_pins[4]	values[0x1]	504	1			T15	5		T17	1		T19	2
all_pins[4]	transitions[0x0=>0x1]	434	1			T15	4		T17	1		T19	1
all_pins[4]	transitions[0x1=>0x0]	175	1			T19	1		T16	3		T32	1
all_pins[5]	values[0x0]	107472	1			T1	1		T2	12		T4	1
all_pins[5]	values[0x1]	245	1			T15	1		T19	2		T16	4
all_pins[5]	transitions[0x0=>0x1]	210	1			T15	1		T19	1		T16	3
all_pins[5]	transitions[0x1=>0x0]	825	1			T2	1		T14	2		T137	1
all_pins[6]	values[0x0]	106857	1			T1	1		T2	11		T4	1
all_pins[6]	values[0x1]	860	1			T2	1		T14	2		T137	1
all_pins[6]	transitions[0x0=>0x1]	810	1			T2	1		T14	2		T137	1
all_pins[6]	transitions[0x1=>0x0]	361	1			T17	2		T24	4		T16	5
all_pins[7]	values[0x0]	107306	1			T1	1		T2	12		T4	1
all_pins[7]	values[0x1]	411	1			T17	2		T24	4		T16	5
all_pins[7]	transitions[0x0=>0x1]	233	1			T17	1		T24	4		T16	4
all_pins[7]	transitions[0x1=>0x0]	18650	1			T2	1		T7	43		T10	2