Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7118534	1			T2	24		T5	14		T7	28
all_levels[1]	1423734	1			T2	1		T5	4		T7	824
all_levels[2]	325558	1			T2	1		T5	5		T9	13
all_levels[3]	541045	1			T5	4		T9	7		T42	97
all_levels[4]	442829	1			T5	1		T9	1		T42	100
all_levels[5]	192356	1			T5	5		T9	3		T42	99
all_levels[6]	195106	1			T5	2		T9	15		T42	93
all_levels[7]	234806	1			T5	2		T7	10		T9	11
all_levels[8]	237634	1			T5	7		T7	93		T9	7
all_levels[9]	258247	1			T5	3		T9	11		T42	103
all_levels[10]	201170	1			T5	6		T9	12		T11	3
all_levels[11]	204000	1			T5	3		T9	12		T42	99
all_levels[12]	175322	1			T5	4		T9	3		T11	1
all_levels[13]	201445	1			T5	2		T9	3		T42	99
all_levels[14]	193210	1			T5	2		T9	4		T42	102
all_levels[15]	320762	1			T5	9		T9	5		T10	1
all_levels[16]	311210	1			T5	5		T9	9		T11	16
all_levels[17]	284442	1			T5	1		T9	9		T42	97
all_levels[18]	316436	1			T5	6		T9	2		T42	96
all_levels[19]	210883	1			T5	6		T9	1		T11	1
all_levels[20]	252259	1			T9	3		T42	93		T266	813
all_levels[21]	704561	1			T9	6		T42	103		T94	2
all_levels[22]	492037	1			T9	12		T42	97		T266	647
all_levels[23]	267500	1			T9	6		T11	2		T42	96
all_levels[24]	233849	1			T9	3		T42	95		T266	653
all_levels[25]	242551	1			T9	8		T42	90		T266	653
all_levels[26]	291087	1			T9	6		T11	29		T42	93
all_levels[27]	185928	1			T9	9		T42	99		T266	653
all_levels[28]	221726	1			T9	5		T42	97		T266	653
all_levels[29]	294891	1			T9	4		T12	1		T42	93
all_levels[30]	241191	1			T9	6		T11	1		T42	99
all_levels[31]	463344	1			T9	2		T42	5120		T266	2180
all_levels[32]	12580141	1			T5	86		T9	16		T11	153

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29855592

1

T2

19

T5

168

T7

923

auto[1]

4202

1

T2

7

T5

9

T7

32

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7116273	1			T2	17		T5	8		T7	5
all_levels[0]	auto[1]	2261	1			T2	7		T5	6		T7	23
all_levels[1]	auto[0]	1423475	1			T2	1		T5	4		T7	824
all_levels[1]	auto[1]	259	1			T93	1		T14	3		T137	2
all_levels[2]	auto[0]	325512	1			T2	1		T5	5		T9	12
all_levels[2]	auto[1]	46	1			T9	1		T11	1		T120	2
all_levels[3]	auto[0]	540828	1			T5	4		T9	7		T42	97
all_levels[3]	auto[1]	217	1			T324	1		T16	24		T46	10
all_levels[4]	auto[0]	442791	1			T5	1		T9	1		T42	100
all_levels[4]	auto[1]	38	1			T15	3		T37	1		T190	3
all_levels[5]	auto[0]	192317	1			T5	5		T9	3		T42	99
all_levels[5]	auto[1]	39	1			T183	1		T261	1		T344	1
all_levels[6]	auto[0]	195070	1			T5	2		T9	15		T42	93
all_levels[6]	auto[1]	36	1			T151	1		T138	4		T200	2
all_levels[7]	auto[0]	234681	1			T5	2		T7	1		T9	11
all_levels[7]	auto[1]	125	1			T7	9		T13	1		T14	1
all_levels[8]	auto[0]	237612	1			T5	7		T7	93		T9	7
all_levels[8]	auto[1]	22	1			T17	1		T198	1		T53	1
all_levels[9]	auto[0]	258220	1			T5	3		T9	11		T42	103
all_levels[9]	auto[1]	27	1			T201	2		T345	1		T334	1
all_levels[10]	auto[0]	201134	1			T5	5		T9	12		T11	3
all_levels[10]	auto[1]	36	1			T5	1		T136	1		T129	1
all_levels[11]	auto[0]	203975	1			T5	3		T9	12		T42	99
all_levels[11]	auto[1]	25	1			T346	2		T347	2		T348	1
all_levels[12]	auto[0]	175308	1			T5	4		T9	3		T11	1
all_levels[12]	auto[1]	14	1			T121	2		T49	1		T150	1
all_levels[13]	auto[0]	201427	1			T5	2		T9	3		T42	99
all_levels[13]	auto[1]	18	1			T36	1		T278	1		T301	2
all_levels[14]	auto[0]	193190	1			T5	2		T9	4		T42	102
all_levels[14]	auto[1]	20	1			T44	1		T45	1		T268	2
all_levels[15]	auto[0]	320576	1			T5	9		T9	5		T10	1
all_levels[15]	auto[1]	186	1			T22	14		T123	2		T289	1
all_levels[16]	auto[0]	311189	1			T5	5		T9	9		T11	16
all_levels[16]	auto[1]	21	1			T37	1		T123	1		T268	1
all_levels[17]	auto[0]	284430	1			T5	1		T9	9		T42	97
all_levels[17]	auto[1]	12	1			T325	1		T349	1		T350	1
all_levels[18]	auto[0]	316420	1			T5	6		T9	2		T42	96
all_levels[18]	auto[1]	16	1			T15	2		T163	1		T54	3
all_levels[19]	auto[0]	210855	1			T5	6		T9	1		T11	1
all_levels[19]	auto[1]	28	1			T36	2		T121	2		T330	1
all_levels[20]	auto[0]	252236	1			T9	3		T42	93		T266	813
all_levels[20]	auto[1]	23	1			T190	1		T153	1		T166	2
all_levels[21]	auto[0]	704539	1			T9	6		T42	103		T94	1
all_levels[21]	auto[1]	22	1			T94	1		T132	1		T15	1
all_levels[22]	auto[0]	492004	1			T9	12		T42	97		T266	647
all_levels[22]	auto[1]	33	1			T37	1		T153	1		T351	2
all_levels[23]	auto[0]	267488	1			T9	6		T11	2		T42	96
all_levels[23]	auto[1]	12	1			T266	1		T135	1		T352	1
all_levels[24]	auto[0]	233839	1			T9	3		T42	95		T266	653
all_levels[24]	auto[1]	10	1			T106	1		T201	1		T309	1
all_levels[25]	auto[0]	242537	1			T9	8		T42	90		T266	653
all_levels[25]	auto[1]	14	1			T353	1		T350	1		T197	1
all_levels[26]	auto[0]	291065	1			T9	6		T11	29		T42	93
all_levels[26]	auto[1]	22	1			T37	1		T189	1		T313	3
all_levels[27]	auto[0]	185901	1			T9	9		T42	99		T266	653
all_levels[27]	auto[1]	27	1			T190	1		T300	1		T147	2
all_levels[28]	auto[0]	221705	1			T9	4		T42	97		T266	653
all_levels[28]	auto[1]	21	1			T9	1		T143	4		T141	1
all_levels[29]	auto[0]	294871	1			T9	4		T12	1		T42	93
all_levels[29]	auto[1]	20	1			T137	1		T354	1		T239	2
all_levels[30]	auto[0]	241181	1			T9	6		T11	1		T42	99
all_levels[30]	auto[1]	10	1			T190	1		T314	1		T355	1
all_levels[31]	auto[0]	463327	1			T9	2		T42	5120		T266	2180
all_levels[31]	auto[1]	17	1			T132	1		T187	1		T120	1
all_levels[32]	auto[0]	12579616	1			T5	84		T9	16		T11	153
all_levels[32]	auto[1]	525	1			T5	2		T12	2		T42	1