Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	814	1			T17	8		T19	7		T16	18
all_values[1]	814	1			T17	8		T19	7		T16	18
all_values[2]	814	1			T17	8		T19	7		T16	18
all_values[3]	814	1			T17	8		T19	7		T16	18
all_values[4]	814	1			T17	8		T19	7		T16	18
all_values[5]	814	1			T17	8		T19	7		T16	18
all_values[6]	814	1			T17	8		T19	7		T16	18
all_values[7]	814	1			T17	8		T19	7		T16	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3519

1

T17

36

T19

31

T16

85

auto[1]

2993

1

T17

28

T19

25

T16

59

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T17

18

T19

22

T16

54

auto[1]

4131

1

T17

46

T19

34

T16

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3806

1

T17

35

T19

32

T16

78

auto[1]

2706

1

T17

29

T19

24

T16

66

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	268	1			T17	3		T19	1		T16	4
all_values[0]	auto[0]	auto[1]	auto[1]	222	1			T17	2		T19	2		T16	7
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T19	1		T16	6		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T17	3		T19	3		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	233	1			T17	1		T19	3		T16	6
all_values[1]	auto[0]	auto[1]	auto[0]	228	1			T17	2		T19	1		T16	6
all_values[1]	auto[1]	auto[0]	auto[1]	199	1			T17	4		T19	1		T16	4
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T17	1		T19	2		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	178	1			T19	2		T32	1		T33	3
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T17	3		T16	2		T32	1
all_values[2]	auto[0]	auto[1]	auto[0]	155	1			T19	2		T16	6		T129	5
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T19	1		T16	1		T33	2
all_values[2]	auto[1]	auto[0]	auto[1]	187	1			T17	4		T19	1		T16	6
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T17	1		T19	1		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	171	1			T19	5		T16	6		T32	1
all_values[3]	auto[0]	auto[0]	auto[1]	81	1			T16	2		T129	1		T130	3
all_values[3]	auto[0]	auto[1]	auto[0]	159	1			T17	1		T16	2		T129	2
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T17	1		T33	2		T122	1
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T17	3		T19	1		T16	6
all_values[3]	auto[1]	auto[1]	auto[1]	137	1			T17	3		T19	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T17	1		T19	3		T16	3
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T17	2		T19	1		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	174	1			T16	5		T33	4		T131	1
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T17	1		T32	1		T131	1
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T19	1		T16	5		T32	2
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T17	4		T19	2		T16	3
all_values[5]	auto[0]	auto[0]	auto[0]	156	1			T17	6		T16	5		T32	2
all_values[5]	auto[0]	auto[0]	auto[1]	94	1			T16	2		T129	1		T122	1
all_values[5]	auto[0]	auto[1]	auto[0]	137	1			T17	2		T19	1		T16	1
all_values[5]	auto[0]	auto[1]	auto[1]	77	1			T19	2		T33	1		T55	1
all_values[5]	auto[1]	auto[0]	auto[1]	203	1			T19	2		T16	6		T33	2
all_values[5]	auto[1]	auto[1]	auto[1]	147	1			T19	2		T16	4		T32	1
all_values[6]	auto[0]	auto[0]	auto[0]	180	1			T19	1		T16	4		T32	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T33	1		T122	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T17	3		T19	2		T16	5
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T16	2		T32	1		T33	3
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T17	2		T19	2		T16	5
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T17	1		T19	2		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	189	1			T17	2		T19	1		T16	2
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T17	2		T19	3		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T19	1		T16	3		T32	1
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T17	1		T16	1		T33	2
all_values[7]	auto[1]	auto[0]	auto[1]	161	1			T17	1		T19	2		T16	8
all_values[7]	auto[1]	auto[1]	auto[1]	174	1			T17	2		T16	3		T32	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal