Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1319
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T101 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3894893531 Apr 02 12:26:43 PM PDT 24 Apr 02 12:26:45 PM PDT 24 88077721 ps
T1256 /workspace/coverage/cover_reg_top/49.uart_intr_test.2484465586 Apr 02 12:26:49 PM PDT 24 Apr 02 12:26:50 PM PDT 24 15583579 ps
T83 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2901128163 Apr 02 12:26:50 PM PDT 24 Apr 02 12:26:51 PM PDT 24 45639639 ps
T1257 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1653794465 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 26050878 ps
T1258 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2171853191 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 33631144 ps
T1259 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3196077990 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 23468180 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1835909650 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:13 PM PDT 24 275357504 ps
T1261 /workspace/coverage/cover_reg_top/10.uart_intr_test.1242119001 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 49886211 ps
T125 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2235195504 Apr 02 12:26:30 PM PDT 24 Apr 02 12:26:31 PM PDT 24 65962803 ps
T1262 /workspace/coverage/cover_reg_top/1.uart_intr_test.3512343341 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:08 PM PDT 24 36277992 ps
T1263 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2456046089 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 13242767 ps
T1264 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1493302779 Apr 02 12:26:59 PM PDT 24 Apr 02 12:27:00 PM PDT 24 27204129 ps
T1265 /workspace/coverage/cover_reg_top/6.uart_intr_test.1522636983 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 11473993 ps
T1266 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3302698115 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:13 PM PDT 24 13614999 ps
T1267 /workspace/coverage/cover_reg_top/8.uart_intr_test.1165442212 Apr 02 12:26:15 PM PDT 24 Apr 02 12:26:21 PM PDT 24 29393199 ps
T1268 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3313182692 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:12 PM PDT 24 24154160 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1831035235 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 14979608 ps
T1270 /workspace/coverage/cover_reg_top/21.uart_intr_test.1099216414 Apr 02 12:26:30 PM PDT 24 Apr 02 12:26:31 PM PDT 24 14456125 ps
T1271 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2632268972 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 24162923 ps
T1272 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.981154289 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:13 PM PDT 24 62199057 ps
T1273 /workspace/coverage/cover_reg_top/11.uart_intr_test.71392808 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 36461615 ps
T1274 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2087288757 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 54350063 ps
T1275 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2228305072 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 21892022 ps
T1276 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1351176179 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:15 PM PDT 24 3366260135 ps
T1277 /workspace/coverage/cover_reg_top/48.uart_intr_test.1246236389 Apr 02 12:26:12 PM PDT 24 Apr 02 12:26:12 PM PDT 24 23670139 ps
T1278 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1523680162 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:08 PM PDT 24 143523004 ps
T1279 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2417112222 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 27742529 ps
T1280 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.256098651 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:07 PM PDT 24 39460951 ps
T128 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.895270291 Apr 02 12:26:01 PM PDT 24 Apr 02 12:26:02 PM PDT 24 243937576 ps
T1281 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4108269415 Apr 02 12:26:36 PM PDT 24 Apr 02 12:26:41 PM PDT 24 28321101 ps
T1282 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2402814363 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:13 PM PDT 24 129567904 ps
T1283 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3510745604 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 45884349 ps
T1284 /workspace/coverage/cover_reg_top/18.uart_intr_test.3724690359 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:11 PM PDT 24 48092445 ps
T1285 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1159690220 Apr 02 12:26:41 PM PDT 24 Apr 02 12:26:42 PM PDT 24 32001254 ps
T1286 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1512217773 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 19009831 ps
T1287 /workspace/coverage/cover_reg_top/43.uart_intr_test.3981539665 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:19 PM PDT 24 11400601 ps
T1288 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2962223167 Apr 02 12:27:06 PM PDT 24 Apr 02 12:27:07 PM PDT 24 83912042 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3264024306 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:10 PM PDT 24 171041659 ps
T1290 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1574551405 Apr 02 12:26:04 PM PDT 24 Apr 02 12:26:06 PM PDT 24 486028100 ps
T1291 /workspace/coverage/cover_reg_top/41.uart_intr_test.310830511 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 13867365 ps
T1292 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3188377773 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 22420061 ps
T1293 /workspace/coverage/cover_reg_top/47.uart_intr_test.1951761507 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 45033327 ps
T1294 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3999585799 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:09 PM PDT 24 14399434 ps
T1295 /workspace/coverage/cover_reg_top/7.uart_intr_test.905762948 Apr 02 12:26:33 PM PDT 24 Apr 02 12:26:34 PM PDT 24 38164626 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2703959494 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:10 PM PDT 24 82366663 ps
T1297 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3961349587 Apr 02 12:26:59 PM PDT 24 Apr 02 12:27:00 PM PDT 24 95413081 ps
T1298 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2780171045 Apr 02 12:26:30 PM PDT 24 Apr 02 12:26:30 PM PDT 24 13650907 ps
T1299 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.898746903 Apr 02 12:27:01 PM PDT 24 Apr 02 12:27:02 PM PDT 24 36547895 ps
T1300 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3335735893 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 95575832 ps
T1301 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3458227882 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:14 PM PDT 24 364184290 ps
T1302 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1219919447 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:12 PM PDT 24 85040305 ps
T1303 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3853183766 Apr 02 12:26:07 PM PDT 24 Apr 02 12:26:08 PM PDT 24 163879848 ps
T1304 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1379822437 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 19239121 ps
T1305 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3680370284 Apr 02 12:27:05 PM PDT 24 Apr 02 12:27:06 PM PDT 24 48420274 ps
T1306 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1888499880 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:08 PM PDT 24 187107322 ps
T1307 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2799753375 Apr 02 12:26:13 PM PDT 24 Apr 02 12:26:14 PM PDT 24 29755800 ps
T1308 /workspace/coverage/cover_reg_top/38.uart_intr_test.3868145141 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:08 PM PDT 24 37334303 ps
T69 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3311697876 Apr 02 12:27:00 PM PDT 24 Apr 02 12:27:01 PM PDT 24 32090010 ps
T1309 /workspace/coverage/cover_reg_top/42.uart_intr_test.1070949326 Apr 02 12:26:10 PM PDT 24 Apr 02 12:26:11 PM PDT 24 35156237 ps
T1310 /workspace/coverage/cover_reg_top/45.uart_intr_test.4215627249 Apr 02 12:26:14 PM PDT 24 Apr 02 12:26:14 PM PDT 24 13553160 ps
T1311 /workspace/coverage/cover_reg_top/32.uart_intr_test.2645246351 Apr 02 12:26:11 PM PDT 24 Apr 02 12:26:12 PM PDT 24 32328293 ps
T1312 /workspace/coverage/cover_reg_top/31.uart_intr_test.1321948951 Apr 02 12:26:15 PM PDT 24 Apr 02 12:26:16 PM PDT 24 12988726 ps
T1313 /workspace/coverage/cover_reg_top/18.uart_tl_errors.715651143 Apr 02 12:26:08 PM PDT 24 Apr 02 12:26:14 PM PDT 24 55898418 ps
T1314 /workspace/coverage/cover_reg_top/14.uart_csr_rw.75126832 Apr 02 12:26:57 PM PDT 24 Apr 02 12:26:58 PM PDT 24 47717446 ps
T1315 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1901514819 Apr 02 12:27:08 PM PDT 24 Apr 02 12:27:11 PM PDT 24 19114915 ps
T1316 /workspace/coverage/cover_reg_top/30.uart_intr_test.2853253156 Apr 02 12:26:14 PM PDT 24 Apr 02 12:26:14 PM PDT 24 71042531 ps
T1317 /workspace/coverage/cover_reg_top/35.uart_intr_test.1559880627 Apr 02 12:26:06 PM PDT 24 Apr 02 12:26:06 PM PDT 24 13717277 ps
T1318 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1781540616 Apr 02 12:26:05 PM PDT 24 Apr 02 12:26:05 PM PDT 24 221771374 ps
T1319 /workspace/coverage/cover_reg_top/17.uart_intr_test.4196134778 Apr 02 12:26:09 PM PDT 24 Apr 02 12:26:09 PM PDT 24 44918948 ps

Test location /workspace/coverage/default/96.uart_fifo_reset.2464865737
Short name T9
Test name
Test status
Simulation time 134228997358 ps
CPU time 230.86 seconds
Started Apr 02 02:23:14 PM PDT 24
Finished Apr 02 02:27:06 PM PDT 24
Peak memory 200400 kb
Host smart-bdd3bff2-652a-4e5d-9dba-07610f5651d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464865737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2464865737
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1088045504
Short name T16
Test name
Test status
Simulation time 318879448784 ps
CPU time 204.61 seconds
Started Apr 02 02:11:33 PM PDT 24
Finished Apr 02 02:14:58 PM PDT 24
Peak memory 210736 kb
Host smart-b21c3687-6005-4ab7-ac4e-a3e01f0e00b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088045504 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1088045504
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.1477742763
Short name T264
Test name
Test status
Simulation time 354453489048 ps
CPU time 2559.88 seconds
Started Apr 02 02:20:14 PM PDT 24
Finished Apr 02 03:02:55 PM PDT 24
Peak memory 200416 kb
Host smart-9420060c-0ed2-469c-8ff2-4d97e5e5d6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477742763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1477742763
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all.1013298622
Short name T23
Test name
Test status
Simulation time 476424008737 ps
CPU time 202.92 seconds
Started Apr 02 02:15:53 PM PDT 24
Finished Apr 02 02:19:16 PM PDT 24
Peak memory 216956 kb
Host smart-18153735-6f84-451f-96c2-f4e17251e84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013298622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1013298622
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2822148222
Short name T57
Test name
Test status
Simulation time 939331746250 ps
CPU time 483.9 seconds
Started Apr 02 02:22:32 PM PDT 24
Finished Apr 02 02:30:36 PM PDT 24
Peak memory 228944 kb
Host smart-98742746-074b-413d-be3f-df5b5427ec44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822148222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2822148222
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4088870037
Short name T17
Test name
Test status
Simulation time 171365207627 ps
CPU time 202.23 seconds
Started Apr 02 02:22:10 PM PDT 24
Finished Apr 02 02:25:32 PM PDT 24
Peak memory 215876 kb
Host smart-18aa97a1-1dfe-49ef-8afb-ceb32a68c913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088870037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4088870037
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3719412677
Short name T27
Test name
Test status
Simulation time 120548475 ps
CPU time 0.72 seconds
Started Apr 02 02:11:46 PM PDT 24
Finished Apr 02 02:11:47 PM PDT 24
Peak memory 218948 kb
Host smart-ece75985-a70a-4199-8bfc-da02881ef5cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719412677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3719412677
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.313393700
Short name T124
Test name
Test status
Simulation time 127178520452 ps
CPU time 108.43 seconds
Started Apr 02 02:16:45 PM PDT 24
Finished Apr 02 02:18:33 PM PDT 24
Peak memory 200388 kb
Host smart-c6ef8862-038f-4e6b-a357-f859e256f800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313393700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.313393700
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3958678198
Short name T155
Test name
Test status
Simulation time 461148326003 ps
CPU time 708.83 seconds
Started Apr 02 02:23:13 PM PDT 24
Finished Apr 02 02:35:02 PM PDT 24
Peak memory 229948 kb
Host smart-73541400-1c77-4dbc-a3b6-cf3902d4b9b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958678198 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3958678198
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.1614447549
Short name T15
Test name
Test status
Simulation time 289974627423 ps
CPU time 383.57 seconds
Started Apr 02 02:14:52 PM PDT 24
Finished Apr 02 02:21:16 PM PDT 24
Peak memory 200460 kb
Host smart-583e57cc-e0e1-4246-9b3a-7ad07427648d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614447549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1614447549
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3625123373
Short name T132
Test name
Test status
Simulation time 79272798403 ps
CPU time 127.18 seconds
Started Apr 02 02:26:13 PM PDT 24
Finished Apr 02 02:28:20 PM PDT 24
Peak memory 200476 kb
Host smart-9cd0a615-e2a9-4393-882c-e2082ace9abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625123373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3625123373
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3852625978
Short name T33
Test name
Test status
Simulation time 146920008599 ps
CPU time 387.82 seconds
Started Apr 02 02:14:34 PM PDT 24
Finished Apr 02 02:21:03 PM PDT 24
Peak memory 217236 kb
Host smart-4fc2ab80-3d9a-4ba4-8184-75879ebb4a1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852625978 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3852625978
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.704480941
Short name T32
Test name
Test status
Simulation time 32022396621 ps
CPU time 718.83 seconds
Started Apr 02 02:23:00 PM PDT 24
Finished Apr 02 02:34:59 PM PDT 24
Peak memory 216868 kb
Host smart-ce90651e-92bd-497e-9c74-2f713d87847e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704480941 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.704480941
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2178362091
Short name T7
Test name
Test status
Simulation time 44300176060 ps
CPU time 23.72 seconds
Started Apr 02 02:19:00 PM PDT 24
Finished Apr 02 02:19:24 PM PDT 24
Peak memory 200468 kb
Host smart-9b23b615-94e3-4f92-abfe-aa9f26e8cc23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178362091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2178362091
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.698041521
Short name T45
Test name
Test status
Simulation time 51160858287 ps
CPU time 60.1 seconds
Started Apr 02 02:23:04 PM PDT 24
Finished Apr 02 02:24:04 PM PDT 24
Peak memory 200488 kb
Host smart-d48690b8-0454-4e04-8ad1-39670016951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698041521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.698041521
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1198668087
Short name T65
Test name
Test status
Simulation time 13858098 ps
CPU time 0.6 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 195204 kb
Host smart-53c23b07-d659-4d95-b4f7-383b4544a8a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198668087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1198668087
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2283606804
Short name T99
Test name
Test status
Simulation time 132111638 ps
CPU time 1.17 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 198940 kb
Host smart-cf74934f-a525-49eb-877f-06902842576a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283606804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2283606804
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2961286713
Short name T157
Test name
Test status
Simulation time 135361131951 ps
CPU time 253.39 seconds
Started Apr 02 02:14:37 PM PDT 24
Finished Apr 02 02:18:51 PM PDT 24
Peak memory 200520 kb
Host smart-48426a61-e244-4063-bd56-740c62f6b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961286713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2961286713
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_alert_test.712105138
Short name T48
Test name
Test status
Simulation time 14684522 ps
CPU time 0.54 seconds
Started Apr 02 02:11:44 PM PDT 24
Finished Apr 02 02:11:45 PM PDT 24
Peak memory 195864 kb
Host smart-f186f59b-0570-44d8-9d0f-5e706dc17bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712105138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.712105138
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2848578649
Short name T153
Test name
Test status
Simulation time 52983525909 ps
CPU time 83.21 seconds
Started Apr 02 02:14:57 PM PDT 24
Finished Apr 02 02:16:20 PM PDT 24
Peak memory 200540 kb
Host smart-ad2d6030-91e2-4ffe-a84d-2c9cae5cac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848578649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2848578649
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1533946591
Short name T144
Test name
Test status
Simulation time 180550414251 ps
CPU time 82.75 seconds
Started Apr 02 02:25:42 PM PDT 24
Finished Apr 02 02:27:05 PM PDT 24
Peak memory 200224 kb
Host smart-ed894029-7deb-4e12-8d43-ebe9467b70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533946591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1533946591
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_perf.152128498
Short name T266
Test name
Test status
Simulation time 12068853907 ps
CPU time 98.49 seconds
Started Apr 02 02:19:45 PM PDT 24
Finished Apr 02 02:21:24 PM PDT 24
Peak memory 200476 kb
Host smart-efb619a9-32ea-43ad-b4a9-ce87ceda0cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152128498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.152128498
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1693286537
Short name T156
Test name
Test status
Simulation time 1086145255475 ps
CPU time 844.81 seconds
Started Apr 02 02:22:02 PM PDT 24
Finished Apr 02 02:36:07 PM PDT 24
Peak memory 225408 kb
Host smart-09ab3d54-5d13-43dc-a581-f674ec34d99d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693286537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1693286537
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_perf.830645110
Short name T279
Test name
Test status
Simulation time 21048366621 ps
CPU time 272.75 seconds
Started Apr 02 02:14:32 PM PDT 24
Finished Apr 02 02:19:05 PM PDT 24
Peak memory 200484 kb
Host smart-3ca404f1-0be6-448f-8df3-2ceeecaa4600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830645110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.830645110
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3006463995
Short name T160
Test name
Test status
Simulation time 297781213154 ps
CPU time 1759.82 seconds
Started Apr 02 02:22:31 PM PDT 24
Finished Apr 02 02:51:51 PM PDT 24
Peak memory 226804 kb
Host smart-ff171d38-c376-47f3-bd2d-7ae0b752194e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006463995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3006463995
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2898346021
Short name T146
Test name
Test status
Simulation time 150967051978 ps
CPU time 137.53 seconds
Started Apr 02 02:15:10 PM PDT 24
Finished Apr 02 02:17:28 PM PDT 24
Peak memory 200484 kb
Host smart-f1199437-f5cf-4ed0-8dc0-56864a596ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898346021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2898346021
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2537022787
Short name T42
Test name
Test status
Simulation time 107554964339 ps
CPU time 763.04 seconds
Started Apr 02 02:17:39 PM PDT 24
Finished Apr 02 02:30:22 PM PDT 24
Peak memory 200436 kb
Host smart-312525cc-0654-488c-b62c-e85a20fca0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537022787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2537022787
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3216769167
Short name T136
Test name
Test status
Simulation time 267106856009 ps
CPU time 103.79 seconds
Started Apr 02 02:11:29 PM PDT 24
Finished Apr 02 02:13:13 PM PDT 24
Peak memory 200456 kb
Host smart-5c308fed-59a4-4ea7-b709-d1b85f3ac9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216769167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3216769167
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1723428205
Short name T142
Test name
Test status
Simulation time 66249900488 ps
CPU time 367.41 seconds
Started Apr 02 02:15:19 PM PDT 24
Finished Apr 02 02:21:27 PM PDT 24
Peak memory 216996 kb
Host smart-8c189f71-01ff-484e-a3ac-948b34cc1907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723428205 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1723428205
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2795595926
Short name T30
Test name
Test status
Simulation time 127902350831 ps
CPU time 543.34 seconds
Started Apr 02 02:17:02 PM PDT 24
Finished Apr 02 02:26:06 PM PDT 24
Peak memory 208788 kb
Host smart-7e1ca83f-1084-4a07-af68-4cb3d901018d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795595926 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2795595926
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4140220030
Short name T183
Test name
Test status
Simulation time 153848251180 ps
CPU time 75.08 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:27:49 PM PDT 24
Peak memory 200380 kb
Host smart-0f67cba8-6a38-4ec7-a83f-8988c6a00011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140220030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4140220030
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2530904418
Short name T177
Test name
Test status
Simulation time 130051126747 ps
CPU time 137.2 seconds
Started Apr 02 02:20:55 PM PDT 24
Finished Apr 02 02:23:12 PM PDT 24
Peak memory 200356 kb
Host smart-5241b070-345c-4f2a-8524-96f41818053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530904418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2530904418
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3335735893
Short name T1300
Test name
Test status
Simulation time 95575832 ps
CPU time 1.34 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 199068 kb
Host smart-0f349255-aedd-4b8a-8078-4c09796a276c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335735893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3335735893
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.717400635
Short name T121
Test name
Test status
Simulation time 124956137268 ps
CPU time 90.35 seconds
Started Apr 02 02:23:00 PM PDT 24
Finished Apr 02 02:24:31 PM PDT 24
Peak memory 200472 kb
Host smart-c5f77dad-8d1e-4b5e-bb4c-7e11255e41ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717400635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.717400635
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3632754386
Short name T151
Test name
Test status
Simulation time 39231863610 ps
CPU time 69.25 seconds
Started Apr 02 02:24:04 PM PDT 24
Finished Apr 02 02:25:13 PM PDT 24
Peak memory 200404 kb
Host smart-7e3c0539-e08c-4ae7-84fc-ef489344ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632754386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3632754386
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.188814729
Short name T309
Test name
Test status
Simulation time 38092481741 ps
CPU time 709.31 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:27:53 PM PDT 24
Peak memory 217240 kb
Host smart-14c00fca-cc90-4440-bc43-9c57467040c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188814729 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.188814729
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1763535094
Short name T10
Test name
Test status
Simulation time 21369745173 ps
CPU time 20.9 seconds
Started Apr 02 02:25:28 PM PDT 24
Finished Apr 02 02:25:49 PM PDT 24
Peak memory 200448 kb
Host smart-c14639c4-6d23-4bba-8da3-0d41cc698ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763535094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1763535094
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.921636279
Short name T197
Test name
Test status
Simulation time 89218175936 ps
CPU time 70.92 seconds
Started Apr 02 02:23:38 PM PDT 24
Finished Apr 02 02:24:49 PM PDT 24
Peak memory 200172 kb
Host smart-802b7d24-7a40-4a5a-a09f-1c70ab28b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921636279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.921636279
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1809484252
Short name T179
Test name
Test status
Simulation time 635973419045 ps
CPU time 837.1 seconds
Started Apr 02 02:14:23 PM PDT 24
Finished Apr 02 02:28:20 PM PDT 24
Peak memory 216932 kb
Host smart-b8199420-2bc1-4ba3-9798-7318008f1d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809484252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1809484252
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1768965718
Short name T190
Test name
Test status
Simulation time 99298072725 ps
CPU time 39.99 seconds
Started Apr 02 02:23:42 PM PDT 24
Finished Apr 02 02:24:23 PM PDT 24
Peak memory 200524 kb
Host smart-25d5905a-f5eb-47ef-b831-f0ab7bce8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768965718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1768965718
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all.624022716
Short name T172
Test name
Test status
Simulation time 441093795364 ps
CPU time 577.12 seconds
Started Apr 02 02:19:48 PM PDT 24
Finished Apr 02 02:29:25 PM PDT 24
Peak memory 200476 kb
Host smart-83402087-2683-4502-9174-30b9a2f6a28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624022716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.624022716
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all.2152764194
Short name T443
Test name
Test status
Simulation time 387580441380 ps
CPU time 80.68 seconds
Started Apr 02 02:13:31 PM PDT 24
Finished Apr 02 02:14:52 PM PDT 24
Peak memory 200468 kb
Host smart-725e138e-051a-425d-9375-21cdd6eb2025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152764194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2152764194
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3904181930
Short name T193
Test name
Test status
Simulation time 16556394373 ps
CPU time 31.02 seconds
Started Apr 02 02:23:24 PM PDT 24
Finished Apr 02 02:23:55 PM PDT 24
Peak memory 200460 kb
Host smart-53775f7d-1d08-4726-a6ff-c97321ac1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904181930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3904181930
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.2407354814
Short name T973
Test name
Test status
Simulation time 127451068921 ps
CPU time 177.54 seconds
Started Apr 02 02:15:24 PM PDT 24
Finished Apr 02 02:18:22 PM PDT 24
Peak memory 200440 kb
Host smart-22ad4c09-788e-467c-9682-d8325c90219b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407354814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2407354814
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3054624638
Short name T226
Test name
Test status
Simulation time 203220153240 ps
CPU time 89.52 seconds
Started Apr 02 02:25:55 PM PDT 24
Finished Apr 02 02:27:25 PM PDT 24
Peak memory 200396 kb
Host smart-53b6119c-4e4d-4c9c-ade1-7e7b784e8d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054624638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3054624638
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.4015249283
Short name T254
Test name
Test status
Simulation time 407868142931 ps
CPU time 132.26 seconds
Started Apr 02 02:12:14 PM PDT 24
Finished Apr 02 02:14:26 PM PDT 24
Peak memory 200472 kb
Host smart-6bbef701-bf69-4a16-91db-9f2337cfa959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015249283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.4015249283
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2270104859
Short name T213
Test name
Test status
Simulation time 21495403602 ps
CPU time 29.3 seconds
Started Apr 02 02:23:32 PM PDT 24
Finished Apr 02 02:24:01 PM PDT 24
Peak memory 200468 kb
Host smart-6b671321-03b6-4625-8970-e3c59186364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270104859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2270104859
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.211656043
Short name T250
Test name
Test status
Simulation time 31959080853 ps
CPU time 29.26 seconds
Started Apr 02 02:23:44 PM PDT 24
Finished Apr 02 02:24:13 PM PDT 24
Peak memory 200448 kb
Host smart-5c4ac13e-ade0-4d5f-9777-fbf0c1d6aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211656043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.211656043
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_noise_filter.293832024
Short name T330
Test name
Test status
Simulation time 92862134470 ps
CPU time 187.59 seconds
Started Apr 02 02:14:27 PM PDT 24
Finished Apr 02 02:17:36 PM PDT 24
Peak memory 199676 kb
Host smart-d30f91ff-cbd1-4a9d-ab3e-27ec83e8bfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293832024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.293832024
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2590453750
Short name T242
Test name
Test status
Simulation time 108982965318 ps
CPU time 47.48 seconds
Started Apr 02 02:24:27 PM PDT 24
Finished Apr 02 02:25:14 PM PDT 24
Peak memory 200288 kb
Host smart-1299ffb0-b0bb-4d89-ad73-83924f1e99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590453750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2590453750
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3603801553
Short name T216
Test name
Test status
Simulation time 59373831821 ps
CPU time 73.93 seconds
Started Apr 02 02:24:38 PM PDT 24
Finished Apr 02 02:25:53 PM PDT 24
Peak memory 200532 kb
Host smart-91209732-feed-433d-841d-1b9f533181d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603801553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3603801553
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2777668140
Short name T239
Test name
Test status
Simulation time 81254604575 ps
CPU time 136.27 seconds
Started Apr 02 02:24:40 PM PDT 24
Finished Apr 02 02:26:56 PM PDT 24
Peak memory 200492 kb
Host smart-7bfdf179-e44e-4ad6-b3f5-c2d71feb648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777668140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2777668140
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.891623988
Short name T563
Test name
Test status
Simulation time 732694113295 ps
CPU time 1266.83 seconds
Started Apr 02 02:16:14 PM PDT 24
Finished Apr 02 02:37:21 PM PDT 24
Peak memory 229360 kb
Host smart-e1dfb206-8d23-4045-a9d5-052891f36423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891623988 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.891623988
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.424131673
Short name T230
Test name
Test status
Simulation time 178000721439 ps
CPU time 88.23 seconds
Started Apr 02 02:26:08 PM PDT 24
Finished Apr 02 02:27:37 PM PDT 24
Peak memory 200452 kb
Host smart-889129bc-4855-441d-aa04-97580f50f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424131673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.424131673
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3164040286
Short name T210
Test name
Test status
Simulation time 120158274846 ps
CPU time 51.12 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:27:26 PM PDT 24
Peak memory 200288 kb
Host smart-887bb9bd-b4c9-4e91-b688-461dad4796bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164040286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3164040286
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_noise_filter.359378933
Short name T318
Test name
Test status
Simulation time 89215367884 ps
CPU time 162.91 seconds
Started Apr 02 02:18:10 PM PDT 24
Finished Apr 02 02:20:54 PM PDT 24
Peak memory 200544 kb
Host smart-90c792b7-0d63-478a-ac09-55f8e76ca668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359378933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.359378933
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2751048388
Short name T211
Test name
Test status
Simulation time 81033662912 ps
CPU time 37.66 seconds
Started Apr 02 02:23:26 PM PDT 24
Finished Apr 02 02:24:04 PM PDT 24
Peak memory 200352 kb
Host smart-95ae92d2-84b1-42ce-803d-c93db282fc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751048388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2751048388
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1372310885
Short name T167
Test name
Test status
Simulation time 91774197169 ps
CPU time 36.16 seconds
Started Apr 02 02:23:24 PM PDT 24
Finished Apr 02 02:24:00 PM PDT 24
Peak memory 200368 kb
Host smart-7feb9198-de04-4b95-9145-b7a422bb20ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372310885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1372310885
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3012715076
Short name T201
Test name
Test status
Simulation time 16711493173 ps
CPU time 28.74 seconds
Started Apr 02 02:14:15 PM PDT 24
Finished Apr 02 02:14:45 PM PDT 24
Peak memory 200528 kb
Host smart-5d494ac3-399a-4c16-9f69-81cc768abf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012715076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3012715076
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1631342089
Short name T138
Test name
Test status
Simulation time 70416139432 ps
CPU time 21.12 seconds
Started Apr 02 02:23:49 PM PDT 24
Finished Apr 02 02:24:10 PM PDT 24
Peak memory 200360 kb
Host smart-952f815b-0719-4add-a266-0d676c148c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631342089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1631342089
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1534752929
Short name T1108
Test name
Test status
Simulation time 43108460087 ps
CPU time 73.86 seconds
Started Apr 02 02:23:53 PM PDT 24
Finished Apr 02 02:25:07 PM PDT 24
Peak memory 200448 kb
Host smart-feff81e9-6f77-4ff7-9bd2-654e60019a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534752929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1534752929
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3349689760
Short name T214
Test name
Test status
Simulation time 31374394020 ps
CPU time 59.33 seconds
Started Apr 02 02:23:54 PM PDT 24
Finished Apr 02 02:24:54 PM PDT 24
Peak memory 200488 kb
Host smart-0a68ccc8-d992-463b-be73-b81e84eb7787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349689760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3349689760
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3927297606
Short name T280
Test name
Test status
Simulation time 31693058622 ps
CPU time 54.06 seconds
Started Apr 02 02:15:17 PM PDT 24
Finished Apr 02 02:16:11 PM PDT 24
Peak memory 200360 kb
Host smart-2e0657cc-e1a4-4254-88c2-7f19c8d55a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927297606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3927297606
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.547016118
Short name T36
Test name
Test status
Simulation time 9617362447 ps
CPU time 16.64 seconds
Started Apr 02 02:15:28 PM PDT 24
Finished Apr 02 02:15:45 PM PDT 24
Peak memory 200508 kb
Host smart-276f5f93-fce3-4846-b452-d6531b459017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547016118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.547016118
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2032212812
Short name T258
Test name
Test status
Simulation time 219542122015 ps
CPU time 23.73 seconds
Started Apr 02 02:25:41 PM PDT 24
Finished Apr 02 02:26:05 PM PDT 24
Peak memory 200212 kb
Host smart-c8a95ce5-864a-451a-848d-a1a360f4b577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032212812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2032212812
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4177529168
Short name T248
Test name
Test status
Simulation time 79674984474 ps
CPU time 25.62 seconds
Started Apr 02 02:25:53 PM PDT 24
Finished Apr 02 02:26:18 PM PDT 24
Peak memory 200432 kb
Host smart-595f117b-a634-40b2-8da8-3a30ee39ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177529168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4177529168
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.667676224
Short name T164
Test name
Test status
Simulation time 36198974502 ps
CPU time 19.29 seconds
Started Apr 02 02:26:16 PM PDT 24
Finished Apr 02 02:26:36 PM PDT 24
Peak memory 200436 kb
Host smart-afcdb983-09a5-456c-928c-8a8541b1c534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667676224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.667676224
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3333364419
Short name T257
Test name
Test status
Simulation time 30310240629 ps
CPU time 11.26 seconds
Started Apr 02 02:26:31 PM PDT 24
Finished Apr 02 02:26:42 PM PDT 24
Peak memory 200440 kb
Host smart-85bde08b-129b-40a8-b501-adc9f72e1c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333364419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3333364419
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3840147609
Short name T249
Test name
Test status
Simulation time 273500993421 ps
CPU time 240.44 seconds
Started Apr 02 02:26:35 PM PDT 24
Finished Apr 02 02:30:36 PM PDT 24
Peak memory 200420 kb
Host smart-08c0cb54-8347-4a9b-84de-6765c085a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840147609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3840147609
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2621371862
Short name T233
Test name
Test status
Simulation time 44527034901 ps
CPU time 46.87 seconds
Started Apr 02 02:19:54 PM PDT 24
Finished Apr 02 02:20:40 PM PDT 24
Peak memory 200396 kb
Host smart-15eb51e0-b842-4cbc-9c56-886c467f8ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621371862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2621371862
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.395112921
Short name T158
Test name
Test status
Simulation time 207466645122 ps
CPU time 31.45 seconds
Started Apr 02 02:22:10 PM PDT 24
Finished Apr 02 02:22:41 PM PDT 24
Peak memory 200392 kb
Host smart-c0e3b6d8-a229-4bcc-8c80-2aa0b7a77beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395112921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.395112921
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.535934849
Short name T222
Test name
Test status
Simulation time 28020777771 ps
CPU time 47.41 seconds
Started Apr 02 02:22:24 PM PDT 24
Finished Apr 02 02:23:12 PM PDT 24
Peak memory 200424 kb
Host smart-6e88cb5e-2bb5-4977-bb4a-fca06372f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535934849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.535934849
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1576827735
Short name T237
Test name
Test status
Simulation time 155445120271 ps
CPU time 124.67 seconds
Started Apr 02 02:22:24 PM PDT 24
Finished Apr 02 02:24:30 PM PDT 24
Peak memory 200436 kb
Host smart-72088202-037e-4c7d-834a-f2576aa85ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576827735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1576827735
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.256098651
Short name T1280
Test name
Test status
Simulation time 39460951 ps
CPU time 0.64 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 195144 kb
Host smart-354630cf-fd1f-47e7-8b4c-994ee5840e12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256098651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.256098651
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3678950643
Short name T1217
Test name
Test status
Simulation time 177549736 ps
CPU time 2.42 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 197436 kb
Host smart-830f07bc-2397-4250-a1f9-fa23bf17acb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678950643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3678950643
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1831035235
Short name T1269
Test name
Test status
Simulation time 14979608 ps
CPU time 0.59 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 195144 kb
Host smart-e0ed6a23-eb81-4d29-8a42-5488d85c3a36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831035235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1831035235
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1379822437
Short name T1304
Test name
Test status
Simulation time 19239121 ps
CPU time 0.65 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 197456 kb
Host smart-e8d95c86-3057-4bf9-98c8-ae87c40c4c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379822437 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1379822437
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3262256371
Short name T1193
Test name
Test status
Simulation time 47179060 ps
CPU time 0.62 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 194092 kb
Host smart-816795e4-4ba6-4815-b17b-de8068fbd07e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262256371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3262256371
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2799753375
Short name T1307
Test name
Test status
Simulation time 29755800 ps
CPU time 0.67 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 195528 kb
Host smart-2b1fd80c-93e6-4e5a-adc1-61b7d8fde0d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799753375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2799753375
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.811931184
Short name T1214
Test name
Test status
Simulation time 108593305 ps
CPU time 1.09 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 199740 kb
Host smart-4c32073a-b3a8-4687-8147-3701e0ba2a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811931184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.811931184
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.716057475
Short name T97
Test name
Test status
Simulation time 58806350 ps
CPU time 0.96 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 198728 kb
Host smart-9d4caabd-37a3-43d5-8c88-581f3dae0e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716057475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.716057475
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3999585799
Short name T1294
Test name
Test status
Simulation time 14399434 ps
CPU time 0.64 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195132 kb
Host smart-4f8d25b5-2767-4826-99ef-a58fc179004a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999585799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3999585799
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2402814363
Short name T1282
Test name
Test status
Simulation time 129567904 ps
CPU time 1.5 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 197624 kb
Host smart-7004a818-fa48-44c5-825b-6168ee8485ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402814363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2402814363
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1370921086
Short name T67
Test name
Test status
Simulation time 13269469 ps
CPU time 0.59 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 195028 kb
Host smart-a90bcd14-8bfc-42aa-9d19-2ea6aaabc885
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370921086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1370921086
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2695987634
Short name T1254
Test name
Test status
Simulation time 58851834 ps
CPU time 0.87 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 199556 kb
Host smart-593b53c2-57e3-472e-aa32-ec4d63062d1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695987634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2695987634
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3510745604
Short name T1283
Test name
Test status
Simulation time 45884349 ps
CPU time 0.59 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195088 kb
Host smart-c2aa7673-b7a1-43b8-8913-bb5ce82eece9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510745604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3510745604
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3512343341
Short name T1262
Test name
Test status
Simulation time 36277992 ps
CPU time 0.63 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 194140 kb
Host smart-2e67cb40-f764-4a10-8ee8-5ec52cb8dcd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512343341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3512343341
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1888499880
Short name T1306
Test name
Test status
Simulation time 187107322 ps
CPU time 0.71 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 197464 kb
Host smart-2b2ea65e-0932-4cc0-8794-e9ead4a6d884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888499880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1888499880
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2134256011
Short name T1210
Test name
Test status
Simulation time 214104961 ps
CPU time 2.04 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 199856 kb
Host smart-750dc06b-77a5-42c2-8d56-550a6e7eb9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134256011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2134256011
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1523680162
Short name T1278
Test name
Test status
Simulation time 143523004 ps
CPU time 1.04 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198796 kb
Host smart-8e9a3b87-6f19-410a-ba86-036dddfcd6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523680162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1523680162
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2962223167
Short name T1288
Test name
Test status
Simulation time 83912042 ps
CPU time 0.75 seconds
Started Apr 02 12:27:06 PM PDT 24
Finished Apr 02 12:27:07 PM PDT 24
Peak memory 198468 kb
Host smart-2e22446e-9034-4c2b-a02a-ef65e9679898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962223167 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2962223167
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2456046089
Short name T1263
Test name
Test status
Simulation time 13242767 ps
CPU time 0.63 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195144 kb
Host smart-7c5d0cdd-686a-4c81-b81c-88423ed6a1ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456046089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2456046089
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1242119001
Short name T1261
Test name
Test status
Simulation time 49886211 ps
CPU time 0.55 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 194148 kb
Host smart-dcd9f74d-b0cf-48f8-a584-680a51e33ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242119001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1242119001
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2478578035
Short name T87
Test name
Test status
Simulation time 55423432 ps
CPU time 0.74 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 196804 kb
Host smart-88c86375-855d-461a-b0ff-71b6749fd065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478578035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2478578035
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3259625696
Short name T1221
Test name
Test status
Simulation time 60494341 ps
CPU time 1.3 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 199820 kb
Host smart-816c6c27-98c5-4219-8d58-82083dd042bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259625696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3259625696
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2321812863
Short name T98
Test name
Test status
Simulation time 91234426 ps
CPU time 1.32 seconds
Started Apr 02 12:26:25 PM PDT 24
Finished Apr 02 12:26:26 PM PDT 24
Peak memory 198948 kb
Host smart-813eff58-19cc-4396-bc4d-efe84b8437ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321812863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2321812863
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1159690220
Short name T1285
Test name
Test status
Simulation time 32001254 ps
CPU time 0.82 seconds
Started Apr 02 12:26:41 PM PDT 24
Finished Apr 02 12:26:42 PM PDT 24
Peak memory 199620 kb
Host smart-ce5e0c5c-6caa-4914-a27e-1e442da2f5fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159690220 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1159690220
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2780171045
Short name T1298
Test name
Test status
Simulation time 13650907 ps
CPU time 0.6 seconds
Started Apr 02 12:26:30 PM PDT 24
Finished Apr 02 12:26:30 PM PDT 24
Peak memory 195136 kb
Host smart-c54f108b-f957-4e75-b9c8-dcead269b95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780171045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2780171045
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.71392808
Short name T1273
Test name
Test status
Simulation time 36461615 ps
CPU time 0.54 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 194056 kb
Host smart-2af8f9b0-ec40-40a6-b950-6f5d6b913201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71392808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.71392808
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3095249374
Short name T89
Test name
Test status
Simulation time 191913853 ps
CPU time 0.74 seconds
Started Apr 02 12:27:07 PM PDT 24
Finished Apr 02 12:27:09 PM PDT 24
Peak memory 196952 kb
Host smart-c3be3797-738b-4cac-8244-5a8b5cb80532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095249374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3095249374
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1219919447
Short name T1302
Test name
Test status
Simulation time 85040305 ps
CPU time 1.57 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 199696 kb
Host smart-633a546e-2e96-4c73-a6dc-85a28b50b95c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219919447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1219919447
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3961349587
Short name T1297
Test name
Test status
Simulation time 95413081 ps
CPU time 1.21 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 199044 kb
Host smart-cfd5c896-fb1c-4b56-928a-6aabad54c0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961349587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3961349587
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1027450582
Short name T1200
Test name
Test status
Simulation time 20131095 ps
CPU time 0.67 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 197768 kb
Host smart-ee564c8c-121d-4af7-a390-15a96c7c1234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027450582 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1027450582
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4019548877
Short name T66
Test name
Test status
Simulation time 28074663 ps
CPU time 0.61 seconds
Started Apr 02 12:26:28 PM PDT 24
Finished Apr 02 12:26:29 PM PDT 24
Peak memory 195112 kb
Host smart-75af4ea1-932f-4c60-b104-e7a50f4d07db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019548877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4019548877
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2629291153
Short name T1196
Test name
Test status
Simulation time 13326617 ps
CPU time 0.58 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 194028 kb
Host smart-73126b4c-f435-4f92-bbd5-6e7810cfba58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629291153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2629291153
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3250041108
Short name T91
Test name
Test status
Simulation time 315238031 ps
CPU time 0.72 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 195484 kb
Host smart-c77ab897-45e6-4721-b6d5-eb777d49a77d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250041108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3250041108
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1931499427
Short name T1212
Test name
Test status
Simulation time 94540325 ps
CPU time 1.89 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 199760 kb
Host smart-87ca080b-1ae2-424f-9990-0d1e7b9dbb86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931499427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1931499427
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1046654120
Short name T1252
Test name
Test status
Simulation time 268574722 ps
CPU time 1.24 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:15 PM PDT 24
Peak memory 198992 kb
Host smart-c19cc1c3-2c0a-4c38-baa4-a412659190ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046654120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1046654120
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2505719578
Short name T1229
Test name
Test status
Simulation time 118891660 ps
CPU time 1.42 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 199812 kb
Host smart-fa105b8b-85ba-4a3b-a9e9-d06f4954774d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505719578 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2505719578
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4259413110
Short name T1240
Test name
Test status
Simulation time 22612858 ps
CPU time 0.57 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 195132 kb
Host smart-30503d23-5b7f-4fa3-870b-0f0b68c15cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259413110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4259413110
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1240719663
Short name T1243
Test name
Test status
Simulation time 13108813 ps
CPU time 0.56 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 194092 kb
Host smart-637070e1-8d0b-4dc6-b282-a2d182d943c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240719663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1240719663
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1493302779
Short name T1264
Test name
Test status
Simulation time 27204129 ps
CPU time 0.72 seconds
Started Apr 02 12:26:59 PM PDT 24
Finished Apr 02 12:27:00 PM PDT 24
Peak memory 197376 kb
Host smart-7691875a-9d1a-4776-bd6d-131fff7a4dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493302779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1493302779
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.432620059
Short name T1235
Test name
Test status
Simulation time 439799228 ps
CPU time 1.24 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 199768 kb
Host smart-c2d2e773-f296-42be-9ac0-2d04f6e5b705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432620059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.432620059
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3894893531
Short name T101
Test name
Test status
Simulation time 88077721 ps
CPU time 1.26 seconds
Started Apr 02 12:26:43 PM PDT 24
Finished Apr 02 12:26:45 PM PDT 24
Peak memory 199108 kb
Host smart-b8dd28b1-5040-403c-84b0-4fbffcf5a3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894893531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3894893531
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.867283466
Short name T1203
Test name
Test status
Simulation time 53394958 ps
CPU time 0.75 seconds
Started Apr 02 12:26:15 PM PDT 24
Finished Apr 02 12:26:16 PM PDT 24
Peak memory 198056 kb
Host smart-bf9a411c-f3f3-4c42-b6a1-2fe75e066f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867283466 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.867283466
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.75126832
Short name T1314
Test name
Test status
Simulation time 47717446 ps
CPU time 0.57 seconds
Started Apr 02 12:26:57 PM PDT 24
Finished Apr 02 12:26:58 PM PDT 24
Peak memory 195112 kb
Host smart-f48f45ee-151a-47ee-a869-51ced5dd9dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75126832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.75126832
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1800197278
Short name T1245
Test name
Test status
Simulation time 14826025 ps
CPU time 0.59 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 194148 kb
Host smart-ed8ff42b-4b67-4882-b7a3-8abbc6850d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800197278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1800197278
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2251611095
Short name T84
Test name
Test status
Simulation time 381913094 ps
CPU time 0.69 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 197212 kb
Host smart-a7394b68-a054-4231-a2d8-7daaa73cb019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251611095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2251611095
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2478255938
Short name T1218
Test name
Test status
Simulation time 104134410 ps
CPU time 1.77 seconds
Started Apr 02 12:26:33 PM PDT 24
Finished Apr 02 12:26:35 PM PDT 24
Peak memory 199660 kb
Host smart-c85a47ec-50aa-4fba-b7c3-dcc8f2c02515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478255938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2478255938
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3882281891
Short name T100
Test name
Test status
Simulation time 66492353 ps
CPU time 0.93 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198728 kb
Host smart-9c395bcd-fe39-4d64-a305-467262f9b9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882281891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3882281891
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2848921324
Short name T1216
Test name
Test status
Simulation time 21332986 ps
CPU time 0.7 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 197716 kb
Host smart-fab29a06-abd2-46da-ad8a-0ca4262ed4f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848921324 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2848921324
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.222684835
Short name T81
Test name
Test status
Simulation time 28711147 ps
CPU time 0.64 seconds
Started Apr 02 12:26:42 PM PDT 24
Finished Apr 02 12:26:43 PM PDT 24
Peak memory 195276 kb
Host smart-25c46768-9d04-450e-98d6-1d450eb54d44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222684835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.222684835
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1292464497
Short name T1199
Test name
Test status
Simulation time 18257987 ps
CPU time 0.63 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 194172 kb
Host smart-c233b287-efe8-4ef6-958b-9ea93c1be492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292464497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1292464497
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4233255729
Short name T85
Test name
Test status
Simulation time 33973898 ps
CPU time 0.8 seconds
Started Apr 02 12:26:49 PM PDT 24
Finished Apr 02 12:26:49 PM PDT 24
Peak memory 197380 kb
Host smart-c107a66b-eba6-482b-8544-9610382ab0f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233255729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4233255729
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3853183766
Short name T1303
Test name
Test status
Simulation time 163879848 ps
CPU time 0.97 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 199536 kb
Host smart-63c81f53-a465-4172-918d-09fd539c1e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853183766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3853183766
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1569510373
Short name T127
Test name
Test status
Simulation time 72674179 ps
CPU time 1.28 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:16 PM PDT 24
Peak memory 199012 kb
Host smart-3eff50ff-ae0c-47bc-b54d-9d9269811978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569510373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1569510373
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2703959494
Short name T1296
Test name
Test status
Simulation time 82366663 ps
CPU time 0.76 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 198876 kb
Host smart-e80d480e-4ed4-4181-a414-0718a9efd4f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703959494 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2703959494
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2954375570
Short name T86
Test name
Test status
Simulation time 15068905 ps
CPU time 0.61 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 195340 kb
Host smart-e91ae10a-cc4c-41a6-81c6-f456b9546770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954375570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2954375570
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2191252177
Short name T1192
Test name
Test status
Simulation time 106622789 ps
CPU time 0.56 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 194096 kb
Host smart-fa5d37b2-cb56-46a3-8c37-a285782de408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191252177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2191252177
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1506986631
Short name T1255
Test name
Test status
Simulation time 83093945 ps
CPU time 0.71 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 197324 kb
Host smart-7b8217a2-eca1-4ffc-bdfa-687b680bd04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506986631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1506986631
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3699454837
Short name T1209
Test name
Test status
Simulation time 33544603 ps
CPU time 1.46 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 199748 kb
Host smart-10bdfba2-b8e7-4fb0-9bcb-4e27afd6b837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699454837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3699454837
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4108269415
Short name T1281
Test name
Test status
Simulation time 28321101 ps
CPU time 1.26 seconds
Started Apr 02 12:26:36 PM PDT 24
Finished Apr 02 12:26:41 PM PDT 24
Peak memory 199740 kb
Host smart-7c9d4f3e-6a7f-4961-a671-eb2ef53ee857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108269415 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4108269415
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.4141160294
Short name T82
Test name
Test status
Simulation time 39133191 ps
CPU time 0.63 seconds
Started Apr 02 12:26:21 PM PDT 24
Finished Apr 02 12:26:22 PM PDT 24
Peak memory 195448 kb
Host smart-c8fddb21-ff08-4c51-9c5e-0fa24b6017a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141160294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.4141160294
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4196134778
Short name T1319
Test name
Test status
Simulation time 44918948 ps
CPU time 0.56 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 194140 kb
Host smart-3434117a-951d-409b-b1bb-f7a55b8afd20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196134778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4196134778
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.519138191
Short name T1224
Test name
Test status
Simulation time 41166374 ps
CPU time 0.63 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 195308 kb
Host smart-317b85e8-67b1-4f35-9515-0b7546066407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519138191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.519138191
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.125022265
Short name T1202
Test name
Test status
Simulation time 36520850 ps
CPU time 1.71 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 199680 kb
Host smart-3a9a870b-3c5c-430d-8227-515ed788bb34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125022265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.125022265
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1889225303
Short name T1236
Test name
Test status
Simulation time 45107204 ps
CPU time 1.02 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198832 kb
Host smart-fa0327cb-ea5c-45b0-b046-57d0f03ab8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889225303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1889225303
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2632268972
Short name T1271
Test name
Test status
Simulation time 24162923 ps
CPU time 0.72 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 198020 kb
Host smart-29b2bec8-d663-48f4-852f-44d24c037f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632268972 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2632268972
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1031051569
Short name T90
Test name
Test status
Simulation time 18295774 ps
CPU time 0.61 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 195372 kb
Host smart-bf533cef-7749-4825-b699-478163572244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031051569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1031051569
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3724690359
Short name T1284
Test name
Test status
Simulation time 48092445 ps
CPU time 0.55 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194044 kb
Host smart-3a11d65c-02be-4696-bc98-ba970c449f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724690359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3724690359
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3196077990
Short name T1259
Test name
Test status
Simulation time 23468180 ps
CPU time 0.66 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 196456 kb
Host smart-cfe66521-a865-40a7-ac26-a069e94962d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196077990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3196077990
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.715651143
Short name T1313
Test name
Test status
Simulation time 55898418 ps
CPU time 1.49 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 199792 kb
Host smart-c84ff9ab-acd8-45ea-a939-83f675a480a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715651143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.715651143
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2235195504
Short name T125
Test name
Test status
Simulation time 65962803 ps
CPU time 0.96 seconds
Started Apr 02 12:26:30 PM PDT 24
Finished Apr 02 12:26:31 PM PDT 24
Peak memory 198416 kb
Host smart-d5679e0b-8b6b-4eea-b710-487fed8abe1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235195504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2235195504
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3774374998
Short name T1207
Test name
Test status
Simulation time 41527745 ps
CPU time 0.73 seconds
Started Apr 02 12:26:24 PM PDT 24
Finished Apr 02 12:26:25 PM PDT 24
Peak memory 199604 kb
Host smart-ee4d8ca7-0dd9-4f41-9b8d-8a3549e60326
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774374998 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3774374998
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1376843950
Short name T1213
Test name
Test status
Simulation time 20611007 ps
CPU time 0.56 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195112 kb
Host smart-89388954-4f73-4c1f-8917-05ea0a680207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376843950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1376843950
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.322541504
Short name T1223
Test name
Test status
Simulation time 17327730 ps
CPU time 0.6 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 194132 kb
Host smart-d76db91f-78d5-4bbb-8c03-48c528d3d2dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322541504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.322541504
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3313182692
Short name T1268
Test name
Test status
Simulation time 24154160 ps
CPU time 0.79 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 195900 kb
Host smart-1dc266b7-c918-4135-b2c6-566448bd848c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313182692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3313182692
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.374352868
Short name T1211
Test name
Test status
Simulation time 48975372 ps
CPU time 1.25 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 199808 kb
Host smart-ac42d8bf-c79c-4c74-9f22-ee897b399025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374352868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.374352868
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.470562541
Short name T126
Test name
Test status
Simulation time 359521606 ps
CPU time 1.26 seconds
Started Apr 02 12:26:34 PM PDT 24
Finished Apr 02 12:26:36 PM PDT 24
Peak memory 199152 kb
Host smart-ba041ba3-3592-45d6-b0d1-7a73365ef1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470562541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.470562541
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3108278485
Short name T68
Test name
Test status
Simulation time 17449043 ps
CPU time 0.72 seconds
Started Apr 02 12:25:59 PM PDT 24
Finished Apr 02 12:26:00 PM PDT 24
Peak memory 196112 kb
Host smart-97c2620e-fcd9-4531-91a8-857977d2e2e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108278485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3108278485
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1880538101
Short name T1185
Test name
Test status
Simulation time 1017322812 ps
CPU time 2.23 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 197264 kb
Host smart-a0b5692c-a3bb-4f66-ac76-316b19d7157a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880538101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1880538101
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2417112222
Short name T1279
Test name
Test status
Simulation time 27742529 ps
CPU time 0.56 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195080 kb
Host smart-372700f5-6238-49d5-89be-681a4d0c2b32
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417112222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2417112222
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1735448262
Short name T1242
Test name
Test status
Simulation time 41660319 ps
CPU time 0.77 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 198780 kb
Host smart-ea48e9ac-0cc4-469e-b397-e17c24e24622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735448262 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1735448262
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2466730259
Short name T92
Test name
Test status
Simulation time 27728654 ps
CPU time 0.59 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 195168 kb
Host smart-66da79b6-ccc7-4cff-a6f5-06775ea3d1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466730259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2466730259
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.746455804
Short name T1189
Test name
Test status
Simulation time 28350207 ps
CPU time 0.57 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 193960 kb
Host smart-9d15efc7-2ee0-4cb5-acd4-ce6b315ca44b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746455804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.746455804
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1781540616
Short name T1318
Test name
Test status
Simulation time 221771374 ps
CPU time 0.71 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 197224 kb
Host smart-f679d77f-be99-497c-902c-839b31c0bc35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781540616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1781540616
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3646561683
Short name T1188
Test name
Test status
Simulation time 251083067 ps
CPU time 1.33 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 199728 kb
Host smart-de6056bc-74ac-45d6-be39-ccfd12165678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646561683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3646561683
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.895270291
Short name T128
Test name
Test status
Simulation time 243937576 ps
CPU time 1.32 seconds
Started Apr 02 12:26:01 PM PDT 24
Finished Apr 02 12:26:02 PM PDT 24
Peak memory 199244 kb
Host smart-85857de3-1696-4812-8815-b7077ad54ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895270291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.895270291
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3901995567
Short name T1205
Test name
Test status
Simulation time 26367817 ps
CPU time 0.62 seconds
Started Apr 02 12:26:52 PM PDT 24
Finished Apr 02 12:26:53 PM PDT 24
Peak memory 194204 kb
Host smart-9894fd1f-f800-412d-a8db-efb56aa3cb66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901995567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3901995567
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1099216414
Short name T1270
Test name
Test status
Simulation time 14456125 ps
CPU time 0.57 seconds
Started Apr 02 12:26:30 PM PDT 24
Finished Apr 02 12:26:31 PM PDT 24
Peak memory 194220 kb
Host smart-4f5bb878-1110-4a3b-9544-9cdb540901d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099216414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1099216414
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2094928330
Short name T1195
Test name
Test status
Simulation time 47789713 ps
CPU time 0.57 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194112 kb
Host smart-0509b791-067a-4001-907b-b2a98a423371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094928330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2094928330
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4243538026
Short name T1237
Test name
Test status
Simulation time 16352955 ps
CPU time 0.57 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 194076 kb
Host smart-6ea73bf3-b54e-4e58-abaa-48cf6722350c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243538026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4243538026
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2876957034
Short name T1249
Test name
Test status
Simulation time 16940054 ps
CPU time 0.58 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194072 kb
Host smart-c4c1c092-516e-4e5c-9f50-16d64146eb5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876957034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2876957034
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4278524453
Short name T1204
Test name
Test status
Simulation time 50435586 ps
CPU time 0.57 seconds
Started Apr 02 12:26:47 PM PDT 24
Finished Apr 02 12:26:48 PM PDT 24
Peak memory 194096 kb
Host smart-82987c34-1590-4dcc-ae24-2761d4079315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278524453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4278524453
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1135971801
Short name T1220
Test name
Test status
Simulation time 45123999 ps
CPU time 0.54 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 194048 kb
Host smart-0c471b36-ac03-4373-a8d7-4f28622eee77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135971801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1135971801
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3882391128
Short name T1241
Test name
Test status
Simulation time 14767122 ps
CPU time 0.54 seconds
Started Apr 02 12:26:30 PM PDT 24
Finished Apr 02 12:26:31 PM PDT 24
Peak memory 194076 kb
Host smart-40009373-64e4-4fa5-958d-a91242555c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882391128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3882391128
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2480774364
Short name T1239
Test name
Test status
Simulation time 24944045 ps
CPU time 0.57 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 194072 kb
Host smart-aa755e15-e41c-4b5d-a0c3-29daa7461466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480774364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2480774364
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2707355067
Short name T1184
Test name
Test status
Simulation time 12300727 ps
CPU time 0.57 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 194132 kb
Host smart-de0c3aed-1059-4f21-b2f9-3a7d6a4183c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707355067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2707355067
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2171853191
Short name T1258
Test name
Test status
Simulation time 33631144 ps
CPU time 0.76 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 195904 kb
Host smart-c2553f35-ba75-4fe1-a18b-68232d6274e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171853191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2171853191
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1351176179
Short name T1276
Test name
Test status
Simulation time 3366260135 ps
CPU time 2.36 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:15 PM PDT 24
Peak memory 197268 kb
Host smart-d06da49e-c30a-4180-a936-ea44b955a387
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351176179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1351176179
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1646353841
Short name T1208
Test name
Test status
Simulation time 12729522 ps
CPU time 0.57 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 195068 kb
Host smart-3f08d450-55f6-446f-bc19-f9915e9e92d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646353841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1646353841
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1126749186
Short name T1226
Test name
Test status
Simulation time 16743760 ps
CPU time 0.64 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 196976 kb
Host smart-c8cb9f61-b52b-47e1-a4eb-57d5131535a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126749186 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1126749186
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2087288757
Short name T1274
Test name
Test status
Simulation time 54350063 ps
CPU time 0.57 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 195140 kb
Host smart-6a625d87-04ea-4e22-a814-9f65ad694316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087288757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2087288757
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3489930876
Short name T1244
Test name
Test status
Simulation time 22602184 ps
CPU time 0.6 seconds
Started Apr 02 12:26:02 PM PDT 24
Finished Apr 02 12:26:03 PM PDT 24
Peak memory 194192 kb
Host smart-2d01b7ec-3357-48b1-8629-0f66c420d3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489930876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3489930876
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1512217773
Short name T1286
Test name
Test status
Simulation time 19009831 ps
CPU time 0.68 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 195184 kb
Host smart-df05d134-5987-474d-9d98-7b071f5ce865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512217773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1512217773
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1680282113
Short name T1190
Test name
Test status
Simulation time 62136404 ps
CPU time 1.54 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 199784 kb
Host smart-049a2d92-3fb4-499b-b019-4d631edd3dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680282113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1680282113
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1574551405
Short name T1290
Test name
Test status
Simulation time 486028100 ps
CPU time 1.31 seconds
Started Apr 02 12:26:04 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 198996 kb
Host smart-400761db-e729-4c88-bb34-d36514fcfac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574551405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1574551405
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2853253156
Short name T1316
Test name
Test status
Simulation time 71042531 ps
CPU time 0.54 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 194072 kb
Host smart-bb8b1f51-6e8f-4509-9608-2af05b895985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853253156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2853253156
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1321948951
Short name T1312
Test name
Test status
Simulation time 12988726 ps
CPU time 0.58 seconds
Started Apr 02 12:26:15 PM PDT 24
Finished Apr 02 12:26:16 PM PDT 24
Peak memory 194168 kb
Host smart-f009d222-712f-44f6-964b-c320774b082c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321948951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1321948951
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2645246351
Short name T1311
Test name
Test status
Simulation time 32328293 ps
CPU time 0.61 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 194180 kb
Host smart-1ca86969-36d7-4d79-85de-85a4b7a60dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645246351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2645246351
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1334496853
Short name T1228
Test name
Test status
Simulation time 21924276 ps
CPU time 0.58 seconds
Started Apr 02 12:26:45 PM PDT 24
Finished Apr 02 12:26:45 PM PDT 24
Peak memory 194200 kb
Host smart-638579bf-e6c1-4a4f-aa40-cc1b5776ed8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334496853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1334496853
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1150382591
Short name T1232
Test name
Test status
Simulation time 12499422 ps
CPU time 0.56 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 194060 kb
Host smart-46dfe15b-78e5-4395-8660-31073fcc19ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150382591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1150382591
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1559880627
Short name T1317
Test name
Test status
Simulation time 13717277 ps
CPU time 0.61 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:06 PM PDT 24
Peak memory 194228 kb
Host smart-e7b9257c-9bf2-4a46-aded-57c717e11be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559880627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1559880627
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.277178865
Short name T1186
Test name
Test status
Simulation time 18012956 ps
CPU time 0.58 seconds
Started Apr 02 12:26:47 PM PDT 24
Finished Apr 02 12:26:48 PM PDT 24
Peak memory 194128 kb
Host smart-d8d4bb26-80fb-4e2a-8713-0bcadb1e8345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277178865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.277178865
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2967819607
Short name T1233
Test name
Test status
Simulation time 17384454 ps
CPU time 0.55 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194104 kb
Host smart-59215e72-45c6-44c7-8e23-6d3cc510b3ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967819607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2967819607
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3868145141
Short name T1308
Test name
Test status
Simulation time 37334303 ps
CPU time 0.55 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 194028 kb
Host smart-b897a648-6e71-4af7-9f2b-81dbb635fe71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868145141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3868145141
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4040612990
Short name T1187
Test name
Test status
Simulation time 35963229 ps
CPU time 0.59 seconds
Started Apr 02 12:26:41 PM PDT 24
Finished Apr 02 12:26:42 PM PDT 24
Peak memory 194144 kb
Host smart-ac3780e7-1847-43cb-9bcf-90f756251b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040612990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4040612990
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2901128163
Short name T83
Test name
Test status
Simulation time 45639639 ps
CPU time 0.66 seconds
Started Apr 02 12:26:50 PM PDT 24
Finished Apr 02 12:26:51 PM PDT 24
Peak memory 194692 kb
Host smart-1ee3336f-14f8-4062-bfc2-aff5ae4ffc8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901128163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2901128163
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4265709090
Short name T1206
Test name
Test status
Simulation time 176586092 ps
CPU time 2.33 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 197624 kb
Host smart-388022b2-eda9-4512-abf4-3adae3c68845
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265709090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4265709090
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1653794465
Short name T1257
Test name
Test status
Simulation time 26050878 ps
CPU time 0.63 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 195112 kb
Host smart-1f40e2f3-85c5-425d-8f04-9051a781976d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653794465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1653794465
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.898746903
Short name T1299
Test name
Test status
Simulation time 36547895 ps
CPU time 0.88 seconds
Started Apr 02 12:27:01 PM PDT 24
Finished Apr 02 12:27:02 PM PDT 24
Peak memory 199624 kb
Host smart-51af60d4-8bde-4cca-bb8e-8044960037ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898746903 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.898746903
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2617783610
Short name T88
Test name
Test status
Simulation time 37523549 ps
CPU time 0.56 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 195120 kb
Host smart-ecaf7d3d-691c-4419-b5f8-4be139e5c0e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617783610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2617783610
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.141598174
Short name T1247
Test name
Test status
Simulation time 27052187 ps
CPU time 0.58 seconds
Started Apr 02 12:26:52 PM PDT 24
Finished Apr 02 12:26:54 PM PDT 24
Peak memory 194032 kb
Host smart-c4c490bf-4c9e-48d2-a2fa-b88f0cb628cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141598174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.141598174
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.981154289
Short name T1272
Test name
Test status
Simulation time 62199057 ps
CPU time 0.63 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 195404 kb
Host smart-4ce64bda-cfc8-4a7d-a020-8e199bc076f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981154289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.981154289
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1267639469
Short name T1215
Test name
Test status
Simulation time 766171356 ps
CPU time 1.96 seconds
Started Apr 02 12:26:30 PM PDT 24
Finished Apr 02 12:26:32 PM PDT 24
Peak memory 199776 kb
Host smart-6dcdf934-767e-49f7-97d7-ef77ed586b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267639469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1267639469
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1296277913
Short name T95
Test name
Test status
Simulation time 1313381872 ps
CPU time 1.28 seconds
Started Apr 02 12:26:11 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 199056 kb
Host smart-2ea7b0ef-5335-44db-82b8-bde60732369f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296277913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1296277913
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.591719766
Short name T1191
Test name
Test status
Simulation time 42284101 ps
CPU time 0.56 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194052 kb
Host smart-c9f6b90f-8540-4367-84c5-606885287365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591719766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.591719766
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.310830511
Short name T1291
Test name
Test status
Simulation time 13867365 ps
CPU time 0.56 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194040 kb
Host smart-509557e3-6dfc-4527-99c8-389433478dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310830511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.310830511
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1070949326
Short name T1309
Test name
Test status
Simulation time 35156237 ps
CPU time 0.62 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194012 kb
Host smart-bc4483bb-dff2-4480-a158-db04fd8d49ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070949326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1070949326
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3981539665
Short name T1287
Test name
Test status
Simulation time 11400601 ps
CPU time 0.58 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:19 PM PDT 24
Peak memory 194132 kb
Host smart-b4d47434-0b48-49e3-a2ea-c6839a8c014d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981539665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3981539665
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3726050120
Short name T1230
Test name
Test status
Simulation time 26419146 ps
CPU time 0.55 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 194064 kb
Host smart-37bd3883-d4c7-43da-a364-8781a4a94258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726050120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3726050120
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4215627249
Short name T1310
Test name
Test status
Simulation time 13553160 ps
CPU time 0.54 seconds
Started Apr 02 12:26:14 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 194072 kb
Host smart-3a6c5449-2236-4892-9a72-eb730dd166a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215627249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4215627249
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1349851043
Short name T1183
Test name
Test status
Simulation time 14506113 ps
CPU time 0.59 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194108 kb
Host smart-431d6420-0659-43b1-9493-b80c30b60794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349851043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1349851043
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1951761507
Short name T1293
Test name
Test status
Simulation time 45033327 ps
CPU time 0.57 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 194016 kb
Host smart-3bbbb60a-454e-43e0-b8ed-5dda2f4c9dea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951761507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1951761507
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1246236389
Short name T1277
Test name
Test status
Simulation time 23670139 ps
CPU time 0.54 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:12 PM PDT 24
Peak memory 194036 kb
Host smart-f1d26d1c-7675-4ce3-b921-0b0c4e6c638e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246236389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1246236389
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2484465586
Short name T1256
Test name
Test status
Simulation time 15583579 ps
CPU time 0.58 seconds
Started Apr 02 12:26:49 PM PDT 24
Finished Apr 02 12:26:50 PM PDT 24
Peak memory 194112 kb
Host smart-676d1ccc-6705-4236-8882-22f1469c6191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484465586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2484465586
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2228305072
Short name T1275
Test name
Test status
Simulation time 21892022 ps
CPU time 0.73 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 198708 kb
Host smart-a34805ea-cdaa-4d89-9f9f-ff3c86d2962b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228305072 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2228305072
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2213949739
Short name T1253
Test name
Test status
Simulation time 87384755 ps
CPU time 0.59 seconds
Started Apr 02 12:26:41 PM PDT 24
Finished Apr 02 12:26:42 PM PDT 24
Peak memory 195108 kb
Host smart-1ac6f6bc-b6e9-4b0e-819b-08251c8f2f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213949739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2213949739
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3234603761
Short name T1201
Test name
Test status
Simulation time 43196780 ps
CPU time 0.53 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 194132 kb
Host smart-8296b325-153b-4913-b66a-916f4fc0976d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234603761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3234603761
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.393580049
Short name T1231
Test name
Test status
Simulation time 20741724 ps
CPU time 0.65 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:05 PM PDT 24
Peak memory 195256 kb
Host smart-5a79bd70-e8cc-4640-8828-d19f2c0c8dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393580049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.393580049
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1972687302
Short name T1225
Test name
Test status
Simulation time 143159203 ps
CPU time 1.84 seconds
Started Apr 02 12:26:05 PM PDT 24
Finished Apr 02 12:26:07 PM PDT 24
Peak memory 199720 kb
Host smart-cff9f0f8-ef6d-4745-bdde-33cfd6e02527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972687302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1972687302
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4028759547
Short name T1227
Test name
Test status
Simulation time 41725476 ps
CPU time 0.97 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198664 kb
Host smart-bee0b3ad-e4c1-4e92-828a-4904a6d3220c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028759547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4028759547
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3612115435
Short name T1238
Test name
Test status
Simulation time 58802771 ps
CPU time 1.35 seconds
Started Apr 02 12:27:02 PM PDT 24
Finished Apr 02 12:27:04 PM PDT 24
Peak memory 199752 kb
Host smart-1dd2cf79-3541-422e-bbc8-c107291b5583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612115435 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3612115435
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4063958370
Short name T1251
Test name
Test status
Simulation time 44892987 ps
CPU time 0.63 seconds
Started Apr 02 12:26:29 PM PDT 24
Finished Apr 02 12:26:29 PM PDT 24
Peak memory 195204 kb
Host smart-af7d3051-4ea9-4f65-9742-59ea0a68df0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063958370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4063958370
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1522636983
Short name T1265
Test name
Test status
Simulation time 11473993 ps
CPU time 0.55 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 194136 kb
Host smart-b28857ad-2ebc-4aca-8c6e-fe4b95414994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522636983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1522636983
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3302698115
Short name T1266
Test name
Test status
Simulation time 13614999 ps
CPU time 0.67 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 196428 kb
Host smart-631b26f1-e551-4111-a55b-02b8edaaca86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302698115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3302698115
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1835909650
Short name T1260
Test name
Test status
Simulation time 275357504 ps
CPU time 1.43 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 199772 kb
Host smart-d80a7b41-74e8-4416-8cc9-ba0f82e4b0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835909650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1835909650
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1462182096
Short name T1194
Test name
Test status
Simulation time 115205832 ps
CPU time 0.77 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:16 PM PDT 24
Peak memory 198980 kb
Host smart-e3a95fa7-15b3-4f12-b35c-c2a774df9f21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462182096 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1462182096
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3188377773
Short name T1292
Test name
Test status
Simulation time 22420061 ps
CPU time 0.56 seconds
Started Apr 02 12:26:09 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 195112 kb
Host smart-a3b3b719-e42a-4681-877d-db7a9386b9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188377773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3188377773
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.905762948
Short name T1295
Test name
Test status
Simulation time 38164626 ps
CPU time 0.59 seconds
Started Apr 02 12:26:33 PM PDT 24
Finished Apr 02 12:26:34 PM PDT 24
Peak memory 194012 kb
Host smart-ec3d80be-5d14-428c-8862-c663c232d3b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905762948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.905762948
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1173486948
Short name T1246
Test name
Test status
Simulation time 18917841 ps
CPU time 0.65 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 196296 kb
Host smart-83245f2a-d836-4bd2-9622-0287d25b4460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173486948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1173486948
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1933416895
Short name T1234
Test name
Test status
Simulation time 545847887 ps
CPU time 1.94 seconds
Started Apr 02 12:26:06 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 199768 kb
Host smart-01551a1f-2018-4b32-a6e7-728c8eadadea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933416895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1933416895
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2694035022
Short name T96
Test name
Test status
Simulation time 55167668 ps
CPU time 0.96 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:18 PM PDT 24
Peak memory 198676 kb
Host smart-f4d44bba-9784-47f1-b5ca-e930c4f914ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694035022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2694035022
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4105251394
Short name T1222
Test name
Test status
Simulation time 24330716 ps
CPU time 1.02 seconds
Started Apr 02 12:26:15 PM PDT 24
Finished Apr 02 12:26:17 PM PDT 24
Peak memory 199564 kb
Host smart-3c766ed6-48e1-4ec1-9225-1530110e3f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105251394 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4105251394
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3311697876
Short name T69
Test name
Test status
Simulation time 32090010 ps
CPU time 0.6 seconds
Started Apr 02 12:27:00 PM PDT 24
Finished Apr 02 12:27:01 PM PDT 24
Peak memory 195232 kb
Host smart-739772eb-a93e-4775-a052-1e6b06839ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311697876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3311697876
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1165442212
Short name T1267
Test name
Test status
Simulation time 29393199 ps
CPU time 0.55 seconds
Started Apr 02 12:26:15 PM PDT 24
Finished Apr 02 12:26:21 PM PDT 24
Peak memory 194164 kb
Host smart-da72790f-4e13-496f-a374-49037288ff3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165442212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1165442212
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3680370284
Short name T1305
Test name
Test status
Simulation time 48420274 ps
CPU time 0.62 seconds
Started Apr 02 12:27:05 PM PDT 24
Finished Apr 02 12:27:06 PM PDT 24
Peak memory 195472 kb
Host smart-243670f2-d807-4c02-905f-d182e68086e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680370284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3680370284
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3458227882
Short name T1301
Test name
Test status
Simulation time 364184290 ps
CPU time 1.4 seconds
Started Apr 02 12:26:13 PM PDT 24
Finished Apr 02 12:26:14 PM PDT 24
Peak memory 199788 kb
Host smart-ba1aea59-ea5d-4b18-be77-cd289d1ba49b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458227882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3458227882
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3264024306
Short name T1289
Test name
Test status
Simulation time 171041659 ps
CPU time 1.29 seconds
Started Apr 02 12:26:08 PM PDT 24
Finished Apr 02 12:26:10 PM PDT 24
Peak memory 198948 kb
Host smart-0f194d49-dab7-4f5d-9946-5124448623c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264024306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3264024306
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1901514819
Short name T1315
Test name
Test status
Simulation time 19114915 ps
CPU time 0.85 seconds
Started Apr 02 12:27:08 PM PDT 24
Finished Apr 02 12:27:11 PM PDT 24
Peak memory 199600 kb
Host smart-06752542-6064-4c73-994c-1ca31b4fb597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901514819 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1901514819
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2500256082
Short name T1197
Test name
Test status
Simulation time 17775943 ps
CPU time 0.6 seconds
Started Apr 02 12:26:10 PM PDT 24
Finished Apr 02 12:26:11 PM PDT 24
Peak memory 195000 kb
Host smart-a02fcc3e-4416-4887-9f0b-cc936d14e532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500256082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2500256082
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.382412892
Short name T1248
Test name
Test status
Simulation time 62725178 ps
CPU time 0.58 seconds
Started Apr 02 12:26:49 PM PDT 24
Finished Apr 02 12:26:50 PM PDT 24
Peak memory 194072 kb
Host smart-572ccf1b-2d74-461c-a1cf-76c67dcf437f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382412892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.382412892
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4130503641
Short name T1250
Test name
Test status
Simulation time 28246155 ps
CPU time 0.72 seconds
Started Apr 02 12:26:12 PM PDT 24
Finished Apr 02 12:26:13 PM PDT 24
Peak memory 196780 kb
Host smart-461e588d-299d-40c8-9999-533589f31589
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130503641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4130503641
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.217463218
Short name T1219
Test name
Test status
Simulation time 40149795 ps
CPU time 1.98 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:09 PM PDT 24
Peak memory 199764 kb
Host smart-eb3c2fe5-8cb9-42ec-b97f-483921995507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217463218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.217463218
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3882997269
Short name T1198
Test name
Test status
Simulation time 37170150 ps
CPU time 0.92 seconds
Started Apr 02 12:26:07 PM PDT 24
Finished Apr 02 12:26:08 PM PDT 24
Peak memory 198800 kb
Host smart-e2a04577-8a5a-4c69-81ff-7cc8f593fbfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882997269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3882997269
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.615623954
Short name T740
Test name
Test status
Simulation time 15392422 ps
CPU time 0.54 seconds
Started Apr 02 02:11:37 PM PDT 24
Finished Apr 02 02:11:38 PM PDT 24
Peak memory 195848 kb
Host smart-1eed61df-0501-4fc2-8acd-4ea81111ba32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615623954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.615623954
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2486774508
Short name T1119
Test name
Test status
Simulation time 32691347303 ps
CPU time 56.97 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:12:24 PM PDT 24
Peak memory 200432 kb
Host smart-f1a0ea4f-c983-4f84-9adb-762b943acbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486774508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2486774508
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.311600618
Short name T903
Test name
Test status
Simulation time 261054957509 ps
CPU time 277.44 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:16:04 PM PDT 24
Peak memory 200408 kb
Host smart-7bfcb6c1-e29b-4adf-965c-0889f89cc000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311600618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.311600618
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1136503751
Short name T440
Test name
Test status
Simulation time 169786931659 ps
CPU time 52.2 seconds
Started Apr 02 02:11:30 PM PDT 24
Finished Apr 02 02:12:23 PM PDT 24
Peak memory 200496 kb
Host smart-6926be26-ec1c-408a-be9d-c355adecdf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136503751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1136503751
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.954622788
Short name T1000
Test name
Test status
Simulation time 48585606045 ps
CPU time 39.42 seconds
Started Apr 02 02:11:27 PM PDT 24
Finished Apr 02 02:12:06 PM PDT 24
Peak memory 200412 kb
Host smart-e0ef3c78-c813-4aed-9b65-4c425000d9f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954622788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.954622788
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2968418112
Short name T619
Test name
Test status
Simulation time 116164598195 ps
CPU time 289.76 seconds
Started Apr 02 02:11:32 PM PDT 24
Finished Apr 02 02:16:22 PM PDT 24
Peak memory 200524 kb
Host smart-f01b6b9f-e589-452f-8bf0-db35ce4d4469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968418112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2968418112
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1317533362
Short name T1012
Test name
Test status
Simulation time 3193071653 ps
CPU time 6 seconds
Started Apr 02 02:11:32 PM PDT 24
Finished Apr 02 02:11:38 PM PDT 24
Peak memory 199704 kb
Host smart-5bbd9701-259a-406e-8c83-dc3d555038b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317533362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1317533362
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1642155630
Short name T383
Test name
Test status
Simulation time 39109716727 ps
CPU time 31.02 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:11:57 PM PDT 24
Peak memory 199140 kb
Host smart-b0d88556-335b-47f7-98ee-e7d59a1e52e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642155630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1642155630
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2889174052
Short name T592
Test name
Test status
Simulation time 5407721713 ps
CPU time 141.65 seconds
Started Apr 02 02:11:33 PM PDT 24
Finished Apr 02 02:13:55 PM PDT 24
Peak memory 200516 kb
Host smart-39b7090c-b57c-40ab-a9cf-1867612eeb3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889174052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2889174052
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1620207259
Short name T358
Test name
Test status
Simulation time 7474057071 ps
CPU time 15.78 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:11:42 PM PDT 24
Peak memory 199676 kb
Host smart-0f4bb740-1437-45a2-9921-d7998fc3736b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620207259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1620207259
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1926570599
Short name T565
Test name
Test status
Simulation time 628925970 ps
CPU time 1.68 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:11:27 PM PDT 24
Peak memory 196096 kb
Host smart-2615a872-45b2-43a8-aa79-e15ae5e324ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926570599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1926570599
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3626893989
Short name T29
Test name
Test status
Simulation time 64119229 ps
CPU time 0.85 seconds
Started Apr 02 02:11:34 PM PDT 24
Finished Apr 02 02:11:35 PM PDT 24
Peak memory 218976 kb
Host smart-75edaa30-a24b-49af-bae0-657593d4c217
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626893989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3626893989
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.4276329293
Short name T374
Test name
Test status
Simulation time 125953144 ps
CPU time 0.72 seconds
Started Apr 02 02:11:29 PM PDT 24
Finished Apr 02 02:11:30 PM PDT 24
Peak memory 197460 kb
Host smart-2a86a5db-b137-4368-afaa-9653e33eb753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276329293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4276329293
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2231901901
Short name T710
Test name
Test status
Simulation time 32061869324 ps
CPU time 458.11 seconds
Started Apr 02 02:11:35 PM PDT 24
Finished Apr 02 02:19:13 PM PDT 24
Peak memory 200456 kb
Host smart-cf3aa5da-8b9d-4000-8330-e1821dbb4d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231901901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2231901901
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.531312956
Short name T361
Test name
Test status
Simulation time 6414937518 ps
CPU time 32.54 seconds
Started Apr 02 02:11:28 PM PDT 24
Finished Apr 02 02:12:01 PM PDT 24
Peak memory 200496 kb
Host smart-d9a5dd45-75f8-4e7e-85a9-838e3e583f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531312956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.531312956
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2377324129
Short name T772
Test name
Test status
Simulation time 16076737986 ps
CPU time 30.21 seconds
Started Apr 02 02:11:26 PM PDT 24
Finished Apr 02 02:11:56 PM PDT 24
Peak memory 200480 kb
Host smart-d317a0d7-cd68-48ce-9a03-cc057601e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377324129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2377324129
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2209744323
Short name T1015
Test name
Test status
Simulation time 189161944838 ps
CPU time 17.01 seconds
Started Apr 02 02:11:38 PM PDT 24
Finished Apr 02 02:11:55 PM PDT 24
Peak memory 200492 kb
Host smart-9ab655a6-ad96-4d16-9324-ac23d03f71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209744323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2209744323
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.355798765
Short name T78
Test name
Test status
Simulation time 115477065243 ps
CPU time 96.97 seconds
Started Apr 02 02:11:37 PM PDT 24
Finished Apr 02 02:13:14 PM PDT 24
Peak memory 200488 kb
Host smart-fb1fee85-389a-4e48-9084-6a36970bf96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355798765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.355798765
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1794271887
Short name T971
Test name
Test status
Simulation time 8894024925 ps
CPU time 28.82 seconds
Started Apr 02 02:11:37 PM PDT 24
Finished Apr 02 02:12:06 PM PDT 24
Peak memory 200420 kb
Host smart-6f6f7b7a-a043-4246-91fd-90bf81003440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794271887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1794271887
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1884377348
Short name T307
Test name
Test status
Simulation time 393919113257 ps
CPU time 177.81 seconds
Started Apr 02 02:11:44 PM PDT 24
Finished Apr 02 02:14:42 PM PDT 24
Peak memory 200372 kb
Host smart-436f3f50-e19b-4a35-a1a0-4f86263ddcbf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884377348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1884377348
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3906919486
Short name T987
Test name
Test status
Simulation time 65631685789 ps
CPU time 106.79 seconds
Started Apr 02 02:11:46 PM PDT 24
Finished Apr 02 02:13:33 PM PDT 24
Peak memory 200460 kb
Host smart-6202c9e3-e14a-45a0-9f55-3edd702c7728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906919486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3906919486
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.145463266
Short name T407
Test name
Test status
Simulation time 6278067967 ps
CPU time 6.13 seconds
Started Apr 02 02:11:47 PM PDT 24
Finished Apr 02 02:11:53 PM PDT 24
Peak memory 200432 kb
Host smart-8ec32a99-a5e2-4d7f-bead-90bf31827ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145463266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.145463266
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1097783256
Short name T838
Test name
Test status
Simulation time 94841343606 ps
CPU time 48.03 seconds
Started Apr 02 02:11:41 PM PDT 24
Finished Apr 02 02:12:29 PM PDT 24
Peak memory 199412 kb
Host smart-9f141925-9f5e-4b53-aacb-566ed260d6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097783256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1097783256
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1760538330
Short name T271
Test name
Test status
Simulation time 15647356133 ps
CPU time 731.45 seconds
Started Apr 02 02:11:45 PM PDT 24
Finished Apr 02 02:23:57 PM PDT 24
Peak memory 200536 kb
Host smart-d876d199-ad03-4fc7-b058-3f2bfef20938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760538330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1760538330
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.25109265
Short name T357
Test name
Test status
Simulation time 6304543257 ps
CPU time 16.46 seconds
Started Apr 02 02:11:44 PM PDT 24
Finished Apr 02 02:12:01 PM PDT 24
Peak memory 198608 kb
Host smart-0fb82e40-d23e-4c76-85e2-ad10945db1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25109265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.25109265
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2511283304
Short name T370
Test name
Test status
Simulation time 20645224345 ps
CPU time 16.92 seconds
Started Apr 02 02:11:46 PM PDT 24
Finished Apr 02 02:12:03 PM PDT 24
Peak memory 200392 kb
Host smart-15b7eae8-30b3-4b07-8e74-23d91cea5273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511283304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2511283304
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.556940661
Short name T632
Test name
Test status
Simulation time 3361936863 ps
CPU time 1.43 seconds
Started Apr 02 02:11:40 PM PDT 24
Finished Apr 02 02:11:42 PM PDT 24
Peak memory 196760 kb
Host smart-cfe15b05-54a5-41df-8f84-0ff46be968e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556940661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.556940661
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.1763959731
Short name T828
Test name
Test status
Simulation time 267227875 ps
CPU time 1.39 seconds
Started Apr 02 02:11:37 PM PDT 24
Finished Apr 02 02:11:38 PM PDT 24
Peak memory 198876 kb
Host smart-b6ffea56-3cac-4542-a6a3-e5bbdd4c1e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763959731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1763959731
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3615485221
Short name T131
Test name
Test status
Simulation time 64860477764 ps
CPU time 94.32 seconds
Started Apr 02 02:11:45 PM PDT 24
Finished Apr 02 02:13:19 PM PDT 24
Peak memory 200484 kb
Host smart-1d92714a-ff01-4b52-b412-9caf300f26e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615485221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3615485221
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2430521090
Short name T118
Test name
Test status
Simulation time 69581840044 ps
CPU time 228.58 seconds
Started Apr 02 02:11:46 PM PDT 24
Finished Apr 02 02:15:34 PM PDT 24
Peak memory 208752 kb
Host smart-bef853b7-3bd5-48ab-8d11-18cdcd6fbc39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430521090 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2430521090
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2564628714
Short name T431
Test name
Test status
Simulation time 871502913 ps
CPU time 2.01 seconds
Started Apr 02 02:11:46 PM PDT 24
Finished Apr 02 02:11:48 PM PDT 24
Peak memory 199320 kb
Host smart-5014931b-2fd3-47b7-b446-9e129e39e97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564628714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2564628714
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4256821505
Short name T663
Test name
Test status
Simulation time 161818669200 ps
CPU time 225 seconds
Started Apr 02 02:11:37 PM PDT 24
Finished Apr 02 02:15:22 PM PDT 24
Peak memory 200532 kb
Host smart-e919adc3-d0f1-43c8-89ed-6ca881a171ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256821505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4256821505
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3409498587
Short name T478
Test name
Test status
Simulation time 47932636 ps
CPU time 0.53 seconds
Started Apr 02 02:14:01 PM PDT 24
Finished Apr 02 02:14:01 PM PDT 24
Peak memory 195876 kb
Host smart-4b23f499-4c47-45f5-b64d-b2f323c23ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409498587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3409498587
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1278393255
Short name T294
Test name
Test status
Simulation time 121269027535 ps
CPU time 201.99 seconds
Started Apr 02 02:13:47 PM PDT 24
Finished Apr 02 02:17:09 PM PDT 24
Peak memory 200420 kb
Host smart-ec9f0f02-8d71-4127-bf20-47742bebebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278393255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1278393255
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.553657784
Short name T333
Test name
Test status
Simulation time 51392369910 ps
CPU time 41.34 seconds
Started Apr 02 02:13:46 PM PDT 24
Finished Apr 02 02:14:27 PM PDT 24
Peak memory 200440 kb
Host smart-70fa31ed-0ac7-4110-a45e-f2ce86a9efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553657784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.553657784
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2272570670
Short name T281
Test name
Test status
Simulation time 8618332714 ps
CPU time 13.62 seconds
Started Apr 02 02:13:48 PM PDT 24
Finished Apr 02 02:14:02 PM PDT 24
Peak memory 200432 kb
Host smart-f79e4d71-bfda-4105-b0d6-0994877807d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272570670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2272570670
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.943384528
Short name T1103
Test name
Test status
Simulation time 7588195592 ps
CPU time 2.55 seconds
Started Apr 02 02:13:48 PM PDT 24
Finished Apr 02 02:13:51 PM PDT 24
Peak memory 197248 kb
Host smart-c59d5df1-4eda-4958-b9aa-36cd137ffd58
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943384528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.943384528
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.581417365
Short name T658
Test name
Test status
Simulation time 166126064557 ps
CPU time 189.2 seconds
Started Apr 02 02:13:53 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 200444 kb
Host smart-db219719-49a6-4541-b33d-e5558a5e76f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581417365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.581417365
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1309877621
Short name T717
Test name
Test status
Simulation time 6903824069 ps
CPU time 4.72 seconds
Started Apr 02 02:13:55 PM PDT 24
Finished Apr 02 02:14:00 PM PDT 24
Peak memory 199444 kb
Host smart-a29500c2-27ec-4445-9ca2-99993d85992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309877621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1309877621
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1650313775
Short name T1168
Test name
Test status
Simulation time 56624854588 ps
CPU time 73.06 seconds
Started Apr 02 02:13:50 PM PDT 24
Finished Apr 02 02:15:03 PM PDT 24
Peak memory 216300 kb
Host smart-1fa7160b-28f1-4de1-83dc-09b21c4374f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650313775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1650313775
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1026123050
Short name T1149
Test name
Test status
Simulation time 11864934027 ps
CPU time 664.56 seconds
Started Apr 02 02:13:57 PM PDT 24
Finished Apr 02 02:25:02 PM PDT 24
Peak memory 200488 kb
Host smart-afa53112-badf-4bb5-a263-675bfe97cc9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026123050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1026123050
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1559997651
Short name T816
Test name
Test status
Simulation time 3470216530 ps
CPU time 6.31 seconds
Started Apr 02 02:13:49 PM PDT 24
Finished Apr 02 02:13:56 PM PDT 24
Peak memory 199500 kb
Host smart-c137b71d-3607-437d-aa6a-6b7e061becfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559997651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1559997651
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.113747927
Short name T425
Test name
Test status
Simulation time 133748755436 ps
CPU time 54.14 seconds
Started Apr 02 02:13:51 PM PDT 24
Finished Apr 02 02:14:45 PM PDT 24
Peak memory 199028 kb
Host smart-cc27fc92-f8d6-4736-810b-647de02f0b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113747927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.113747927
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2028198372
Short name T328
Test name
Test status
Simulation time 26404889374 ps
CPU time 9.92 seconds
Started Apr 02 02:13:52 PM PDT 24
Finished Apr 02 02:14:02 PM PDT 24
Peak memory 196408 kb
Host smart-e7f89342-5027-4d1d-99ed-239de70a319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028198372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2028198372
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2212657145
Short name T305
Test name
Test status
Simulation time 5746496558 ps
CPU time 11.14 seconds
Started Apr 02 02:13:46 PM PDT 24
Finished Apr 02 02:13:57 PM PDT 24
Peak memory 199628 kb
Host smart-264e468d-6156-4608-97d3-e3a4ceea1995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212657145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2212657145
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2560249901
Short name T401
Test name
Test status
Simulation time 29564678026 ps
CPU time 17.05 seconds
Started Apr 02 02:14:00 PM PDT 24
Finished Apr 02 02:14:18 PM PDT 24
Peak memory 200416 kb
Host smart-a440aaf1-f2d6-4f89-b797-49dce6cdb02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560249901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2560249901
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.730861505
Short name T162
Test name
Test status
Simulation time 48953675608 ps
CPU time 323.28 seconds
Started Apr 02 02:13:57 PM PDT 24
Finished Apr 02 02:19:21 PM PDT 24
Peak memory 217228 kb
Host smart-39d588bf-5288-4193-b02b-8b88ea636880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730861505 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.730861505
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4131579660
Short name T876
Test name
Test status
Simulation time 2342779979 ps
CPU time 1.87 seconds
Started Apr 02 02:13:53 PM PDT 24
Finished Apr 02 02:13:55 PM PDT 24
Peak memory 199276 kb
Host smart-9cca0f47-312e-4096-8eaa-f3c1e3c03560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131579660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4131579660
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3915328360
Short name T521
Test name
Test status
Simulation time 39576197782 ps
CPU time 71.55 seconds
Started Apr 02 02:13:47 PM PDT 24
Finished Apr 02 02:14:59 PM PDT 24
Peak memory 200388 kb
Host smart-09fc2239-40a6-413b-84fc-973c18ff3ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915328360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3915328360
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3502567234
Short name T375
Test name
Test status
Simulation time 77152672141 ps
CPU time 54.11 seconds
Started Apr 02 02:23:16 PM PDT 24
Finished Apr 02 02:24:11 PM PDT 24
Peak memory 200432 kb
Host smart-bd61b39d-d53f-4d25-b1d7-b073d574f53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502567234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3502567234
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1468371080
Short name T564
Test name
Test status
Simulation time 70361499746 ps
CPU time 30.52 seconds
Started Apr 02 02:23:25 PM PDT 24
Finished Apr 02 02:23:56 PM PDT 24
Peak memory 200384 kb
Host smart-3a32a053-7a1c-4140-b3e4-6b411183f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468371080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1468371080
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2503777313
Short name T617
Test name
Test status
Simulation time 121483724804 ps
CPU time 205.94 seconds
Started Apr 02 02:23:20 PM PDT 24
Finished Apr 02 02:26:46 PM PDT 24
Peak memory 200512 kb
Host smart-ac679754-d06d-4166-9aff-18593a402179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503777313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2503777313
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2212905840
Short name T958
Test name
Test status
Simulation time 30999630448 ps
CPU time 16.76 seconds
Started Apr 02 02:23:25 PM PDT 24
Finished Apr 02 02:23:42 PM PDT 24
Peak memory 200344 kb
Host smart-bcb7bbe9-aa6f-4294-b0d3-8ca3a4f88248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212905840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2212905840
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1403440860
Short name T643
Test name
Test status
Simulation time 29872050403 ps
CPU time 13.02 seconds
Started Apr 02 02:23:24 PM PDT 24
Finished Apr 02 02:23:37 PM PDT 24
Peak memory 200500 kb
Host smart-cb9f646a-b033-4373-9262-24ef63ab9b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403440860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1403440860
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2245603327
Short name T215
Test name
Test status
Simulation time 64741122008 ps
CPU time 120.28 seconds
Started Apr 02 02:23:27 PM PDT 24
Finished Apr 02 02:25:28 PM PDT 24
Peak memory 200512 kb
Host smart-2ab66cc6-c6d3-4768-8a61-b0f8aedf299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245603327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2245603327
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4106929805
Short name T672
Test name
Test status
Simulation time 16527371556 ps
CPU time 7.75 seconds
Started Apr 02 02:23:31 PM PDT 24
Finished Apr 02 02:23:39 PM PDT 24
Peak memory 200476 kb
Host smart-2ebe2807-3cd5-4ec3-97e8-dd69dcbed0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106929805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4106929805
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4023740443
Short name T993
Test name
Test status
Simulation time 13105265 ps
CPU time 0.55 seconds
Started Apr 02 02:14:10 PM PDT 24
Finished Apr 02 02:14:11 PM PDT 24
Peak memory 195852 kb
Host smart-6f76a156-ecc7-4d16-9a1d-675656e616aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023740443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4023740443
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2650371712
Short name T486
Test name
Test status
Simulation time 87563920456 ps
CPU time 23.31 seconds
Started Apr 02 02:14:02 PM PDT 24
Finished Apr 02 02:14:25 PM PDT 24
Peak memory 200212 kb
Host smart-4e9b5615-3149-412c-a407-d28279379f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650371712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2650371712
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.673211816
Short name T986
Test name
Test status
Simulation time 155450795830 ps
CPU time 54.99 seconds
Started Apr 02 02:14:03 PM PDT 24
Finished Apr 02 02:14:58 PM PDT 24
Peak memory 200356 kb
Host smart-160a5da9-f149-42d9-8ef1-6228f4b63bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673211816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.673211816
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3298655707
Short name T577
Test name
Test status
Simulation time 24248037757 ps
CPU time 25.87 seconds
Started Apr 02 02:14:00 PM PDT 24
Finished Apr 02 02:14:26 PM PDT 24
Peak memory 200468 kb
Host smart-076524ab-8bc2-4bd6-a4b4-c4769d4b1e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298655707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3298655707
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1263835259
Short name T337
Test name
Test status
Simulation time 24879728180 ps
CPU time 43.9 seconds
Started Apr 02 02:14:05 PM PDT 24
Finished Apr 02 02:14:49 PM PDT 24
Peak memory 200500 kb
Host smart-188182fa-b04d-465b-8770-7d8df981d3fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263835259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1263835259
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3323143837
Short name T1001
Test name
Test status
Simulation time 87929766764 ps
CPU time 402.52 seconds
Started Apr 02 02:14:05 PM PDT 24
Finished Apr 02 02:20:48 PM PDT 24
Peak memory 200420 kb
Host smart-9b902b92-2973-4fc1-b339-9391cf92e223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323143837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3323143837
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.934957160
Short name T460
Test name
Test status
Simulation time 9045393202 ps
CPU time 8.67 seconds
Started Apr 02 02:14:08 PM PDT 24
Finished Apr 02 02:14:17 PM PDT 24
Peak memory 200488 kb
Host smart-cd95a6dc-4541-4a04-a147-cad10e81af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934957160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.934957160
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.279991966
Short name T743
Test name
Test status
Simulation time 78539244146 ps
CPU time 71.19 seconds
Started Apr 02 02:14:06 PM PDT 24
Finished Apr 02 02:15:17 PM PDT 24
Peak memory 200592 kb
Host smart-df2c8d1c-65d9-4a5a-bc99-458e8705fe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279991966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.279991966
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2375227490
Short name T878
Test name
Test status
Simulation time 19258322732 ps
CPU time 1062.14 seconds
Started Apr 02 02:14:06 PM PDT 24
Finished Apr 02 02:31:49 PM PDT 24
Peak memory 200468 kb
Host smart-bd0ba959-97f9-4e3d-b89b-aad9434b9899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375227490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2375227490
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2979190421
Short name T1160
Test name
Test status
Simulation time 3795099323 ps
CPU time 31.86 seconds
Started Apr 02 02:14:05 PM PDT 24
Finished Apr 02 02:14:36 PM PDT 24
Peak memory 199516 kb
Host smart-920dacf2-cd80-4433-9658-72853ead9012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979190421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2979190421
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2396357371
Short name T935
Test name
Test status
Simulation time 281885246991 ps
CPU time 47.93 seconds
Started Apr 02 02:14:06 PM PDT 24
Finished Apr 02 02:14:54 PM PDT 24
Peak memory 200360 kb
Host smart-0feee92a-583f-40d3-bc62-d58c3f13a559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396357371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2396357371
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4079878499
Short name T297
Test name
Test status
Simulation time 3238202235 ps
CPU time 1.84 seconds
Started Apr 02 02:14:08 PM PDT 24
Finished Apr 02 02:14:09 PM PDT 24
Peak memory 196344 kb
Host smart-3ecc5738-0296-4a61-b553-22677339c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079878499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4079878499
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2958841010
Short name T626
Test name
Test status
Simulation time 668593758 ps
CPU time 2.6 seconds
Started Apr 02 02:13:57 PM PDT 24
Finished Apr 02 02:14:00 PM PDT 24
Peak memory 198860 kb
Host smart-bfe092d6-3b73-48c8-a6a4-b2c3a1152898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958841010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2958841010
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3558650755
Short name T1114
Test name
Test status
Simulation time 326257800234 ps
CPU time 148.74 seconds
Started Apr 02 02:14:09 PM PDT 24
Finished Apr 02 02:16:38 PM PDT 24
Peak memory 200408 kb
Host smart-15e060df-50b9-494b-94b0-dd9e635222fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558650755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3558650755
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.999988109
Short name T560
Test name
Test status
Simulation time 802719156269 ps
CPU time 834.91 seconds
Started Apr 02 02:14:08 PM PDT 24
Finished Apr 02 02:28:03 PM PDT 24
Peak memory 215972 kb
Host smart-78f009fe-8219-41db-8fbd-0a2706681f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999988109 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.999988109
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.475857690
Short name T675
Test name
Test status
Simulation time 332086603 ps
CPU time 1.35 seconds
Started Apr 02 02:14:06 PM PDT 24
Finished Apr 02 02:14:07 PM PDT 24
Peak memory 198796 kb
Host smart-8b5f794e-d5a1-4d2a-a515-7fb2794c62c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475857690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.475857690
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2158419445
Short name T914
Test name
Test status
Simulation time 4344862871 ps
CPU time 3.64 seconds
Started Apr 02 02:14:02 PM PDT 24
Finished Apr 02 02:14:06 PM PDT 24
Peak memory 198864 kb
Host smart-d0059828-cb4e-4c13-b671-e9f4dc3fcf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158419445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2158419445
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2522134068
Short name T864
Test name
Test status
Simulation time 126800426907 ps
CPU time 225.99 seconds
Started Apr 02 02:23:34 PM PDT 24
Finished Apr 02 02:27:21 PM PDT 24
Peak memory 200432 kb
Host smart-4e9c0a31-2936-40ce-9fa2-c3229984680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522134068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2522134068
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.532199257
Short name T194
Test name
Test status
Simulation time 116051686998 ps
CPU time 204.18 seconds
Started Apr 02 02:23:34 PM PDT 24
Finished Apr 02 02:26:59 PM PDT 24
Peak memory 200476 kb
Host smart-13894fd2-7b78-4129-a64f-7b4412a22da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532199257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.532199257
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1640003564
Short name T150
Test name
Test status
Simulation time 67723539826 ps
CPU time 27.97 seconds
Started Apr 02 02:23:35 PM PDT 24
Finished Apr 02 02:24:03 PM PDT 24
Peak memory 200548 kb
Host smart-e442883a-6256-4e48-a366-34193bf17d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640003564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1640003564
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1957293863
Short name T1021
Test name
Test status
Simulation time 219486944640 ps
CPU time 53.49 seconds
Started Apr 02 02:23:35 PM PDT 24
Finished Apr 02 02:24:29 PM PDT 24
Peak memory 200492 kb
Host smart-552b0b1d-ec3c-4b51-b4e5-c54403e3e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957293863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1957293863
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3302718348
Short name T981
Test name
Test status
Simulation time 10602914950 ps
CPU time 19.35 seconds
Started Apr 02 02:23:35 PM PDT 24
Finished Apr 02 02:23:54 PM PDT 24
Peak memory 200392 kb
Host smart-d7951c73-2635-4d95-8efa-9c3b1f374f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302718348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3302718348
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3448737708
Short name T108
Test name
Test status
Simulation time 73126186180 ps
CPU time 14.15 seconds
Started Apr 02 02:23:36 PM PDT 24
Finished Apr 02 02:23:50 PM PDT 24
Peak memory 200432 kb
Host smart-5ceac967-2b7b-405a-b9cf-a227982b688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448737708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3448737708
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3893076822
Short name T1174
Test name
Test status
Simulation time 11760717615 ps
CPU time 20.17 seconds
Started Apr 02 02:23:39 PM PDT 24
Finished Apr 02 02:23:59 PM PDT 24
Peak memory 200348 kb
Host smart-4cf6793b-1036-4618-8005-e3c0078a09fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893076822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3893076822
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.67768544
Short name T967
Test name
Test status
Simulation time 229776570792 ps
CPU time 555.91 seconds
Started Apr 02 02:23:38 PM PDT 24
Finished Apr 02 02:32:54 PM PDT 24
Peak memory 200416 kb
Host smart-ea310901-eddb-4382-8247-23491339713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67768544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.67768544
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4100090066
Short name T586
Test name
Test status
Simulation time 23768891 ps
CPU time 0.55 seconds
Started Apr 02 02:14:20 PM PDT 24
Finished Apr 02 02:14:21 PM PDT 24
Peak memory 195892 kb
Host smart-03044d61-1256-4fc1-862f-3b45a5772d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100090066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4100090066
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1942562586
Short name T637
Test name
Test status
Simulation time 58739673040 ps
CPU time 26.66 seconds
Started Apr 02 02:14:14 PM PDT 24
Finished Apr 02 02:14:41 PM PDT 24
Peak memory 200584 kb
Host smart-20e36bff-c40b-44ac-869d-defc8405a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942562586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1942562586
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2160390016
Short name T722
Test name
Test status
Simulation time 19360830556 ps
CPU time 31.2 seconds
Started Apr 02 02:14:14 PM PDT 24
Finished Apr 02 02:14:46 PM PDT 24
Peak memory 200268 kb
Host smart-da785b16-f534-4a7c-b128-cde3251aab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160390016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2160390016
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.195188507
Short name T1125
Test name
Test status
Simulation time 71367010257 ps
CPU time 12.17 seconds
Started Apr 02 02:14:16 PM PDT 24
Finished Apr 02 02:14:28 PM PDT 24
Peak memory 199892 kb
Host smart-94132194-950f-49ae-9fde-8fa8c8b4a57e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195188507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.195188507
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.855552459
Short name T845
Test name
Test status
Simulation time 76891296250 ps
CPU time 308.76 seconds
Started Apr 02 02:14:23 PM PDT 24
Finished Apr 02 02:19:32 PM PDT 24
Peak memory 200488 kb
Host smart-03fe47cc-2f25-416a-847e-058f49ea5056
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855552459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.855552459
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1092669904
Short name T639
Test name
Test status
Simulation time 12026362974 ps
CPU time 5.43 seconds
Started Apr 02 02:14:18 PM PDT 24
Finished Apr 02 02:14:23 PM PDT 24
Peak memory 200320 kb
Host smart-c4a36723-988f-411b-aea5-5864da65c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092669904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1092669904
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.948738249
Short name T1102
Test name
Test status
Simulation time 152734628597 ps
CPU time 67.58 seconds
Started Apr 02 02:14:16 PM PDT 24
Finished Apr 02 02:15:25 PM PDT 24
Peak memory 200660 kb
Host smart-e8eb48b8-aee6-40c2-8d78-e935da88d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948738249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.948738249
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2613456604
Short name T915
Test name
Test status
Simulation time 12218077729 ps
CPU time 408.29 seconds
Started Apr 02 02:14:18 PM PDT 24
Finished Apr 02 02:21:07 PM PDT 24
Peak memory 200392 kb
Host smart-faa3fff9-5858-4a53-92a8-366133a4519f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613456604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2613456604
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.104276564
Short name T1050
Test name
Test status
Simulation time 2016983726 ps
CPU time 6.84 seconds
Started Apr 02 02:14:16 PM PDT 24
Finished Apr 02 02:14:24 PM PDT 24
Peak memory 198652 kb
Host smart-cfa6cf10-1ff4-4f1d-a5ba-46b272c384b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104276564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.104276564
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2696537450
Short name T817
Test name
Test status
Simulation time 54382819680 ps
CPU time 99.85 seconds
Started Apr 02 02:14:17 PM PDT 24
Finished Apr 02 02:15:58 PM PDT 24
Peak memory 200280 kb
Host smart-41c5e8e0-10cc-4ae7-a935-0b370c2758d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696537450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2696537450
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.157128006
Short name T490
Test name
Test status
Simulation time 6439811227 ps
CPU time 1.91 seconds
Started Apr 02 02:14:15 PM PDT 24
Finished Apr 02 02:14:17 PM PDT 24
Peak memory 196512 kb
Host smart-151387ac-559f-4618-b56c-6a59a6b87658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157128006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.157128006
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.698037351
Short name T74
Test name
Test status
Simulation time 673713742 ps
CPU time 4.28 seconds
Started Apr 02 02:14:15 PM PDT 24
Finished Apr 02 02:14:19 PM PDT 24
Peak memory 199308 kb
Host smart-98b81578-a24d-4a4a-a2a8-626d5c5730bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698037351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.698037351
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.808268757
Short name T738
Test name
Test status
Simulation time 35310087645 ps
CPU time 72.82 seconds
Started Apr 02 02:14:22 PM PDT 24
Finished Apr 02 02:15:36 PM PDT 24
Peak memory 200480 kb
Host smart-edbf0585-c870-4163-89a4-222f23c6af66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808268757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.808268757
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1756310381
Short name T1164
Test name
Test status
Simulation time 1140672632 ps
CPU time 3.08 seconds
Started Apr 02 02:14:15 PM PDT 24
Finished Apr 02 02:14:18 PM PDT 24
Peak memory 198692 kb
Host smart-c5f585e7-b087-4191-adfc-8a16799bbf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756310381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1756310381
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4144050687
Short name T531
Test name
Test status
Simulation time 95169911810 ps
CPU time 24.12 seconds
Started Apr 02 02:14:12 PM PDT 24
Finished Apr 02 02:14:37 PM PDT 24
Peak memory 200432 kb
Host smart-29508c86-e743-4c20-9400-e65e63854437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144050687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4144050687
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.272288520
Short name T589
Test name
Test status
Simulation time 101058454219 ps
CPU time 49.48 seconds
Started Apr 02 02:23:44 PM PDT 24
Finished Apr 02 02:24:34 PM PDT 24
Peak memory 200412 kb
Host smart-adb0b290-2a82-4cd1-88ac-562af1df7218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272288520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.272288520
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.884906310
Short name T520
Test name
Test status
Simulation time 7830764533 ps
CPU time 21.77 seconds
Started Apr 02 02:23:42 PM PDT 24
Finished Apr 02 02:24:04 PM PDT 24
Peak memory 200436 kb
Host smart-9dee99c3-3f1d-48bc-b758-88aa337e27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884906310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.884906310
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.914852468
Short name T94
Test name
Test status
Simulation time 16042124855 ps
CPU time 25.84 seconds
Started Apr 02 02:23:44 PM PDT 24
Finished Apr 02 02:24:11 PM PDT 24
Peak memory 200448 kb
Host smart-08e1b443-2639-4b87-9196-9c8da0c3cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914852468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.914852468
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1787274231
Short name T671
Test name
Test status
Simulation time 75390498382 ps
CPU time 109.72 seconds
Started Apr 02 02:23:42 PM PDT 24
Finished Apr 02 02:25:32 PM PDT 24
Peak memory 200444 kb
Host smart-12e86592-a27b-476b-be57-73510b97a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787274231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1787274231
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1352444880
Short name T191
Test name
Test status
Simulation time 31653067030 ps
CPU time 52.95 seconds
Started Apr 02 02:23:50 PM PDT 24
Finished Apr 02 02:24:44 PM PDT 24
Peak memory 200404 kb
Host smart-4250600c-1b11-49ca-8f2e-303ad9312f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352444880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1352444880
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.798290732
Short name T806
Test name
Test status
Simulation time 73127432248 ps
CPU time 34.37 seconds
Started Apr 02 02:23:51 PM PDT 24
Finished Apr 02 02:24:26 PM PDT 24
Peak memory 200500 kb
Host smart-c384f4ac-21a1-4ed5-ae8f-9300ec13f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798290732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.798290732
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1367856530
Short name T966
Test name
Test status
Simulation time 53357107043 ps
CPU time 13.65 seconds
Started Apr 02 02:23:50 PM PDT 24
Finished Apr 02 02:24:04 PM PDT 24
Peak memory 200488 kb
Host smart-e3819d6e-e7c0-41ac-9122-2bfae31c1ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367856530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1367856530
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3949086684
Short name T716
Test name
Test status
Simulation time 136049890 ps
CPU time 0.53 seconds
Started Apr 02 02:14:34 PM PDT 24
Finished Apr 02 02:14:36 PM PDT 24
Peak memory 195364 kb
Host smart-1ae94756-0f89-4f86-971b-8b3532bde669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949086684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3949086684
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.769068771
Short name T1075
Test name
Test status
Simulation time 110627713776 ps
CPU time 40.03 seconds
Started Apr 02 02:14:27 PM PDT 24
Finished Apr 02 02:15:09 PM PDT 24
Peak memory 200452 kb
Host smart-d3231530-c5d3-456a-947a-d60cc2d6416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769068771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.769068771
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.901144652
Short name T286
Test name
Test status
Simulation time 277302639154 ps
CPU time 106.68 seconds
Started Apr 02 02:14:24 PM PDT 24
Finished Apr 02 02:16:11 PM PDT 24
Peak memory 200536 kb
Host smart-e8d669c2-e823-46cf-8768-943bf28af4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901144652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.901144652
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2619572623
Short name T753
Test name
Test status
Simulation time 68658990769 ps
CPU time 54.23 seconds
Started Apr 02 02:14:31 PM PDT 24
Finished Apr 02 02:15:26 PM PDT 24
Peak memory 200276 kb
Host smart-cf4dabd3-22c7-4cc2-8619-11d56636e13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619572623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2619572623
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.307617594
Short name T1043
Test name
Test status
Simulation time 47948066344 ps
CPU time 77.88 seconds
Started Apr 02 02:14:27 PM PDT 24
Finished Apr 02 02:15:46 PM PDT 24
Peak memory 200384 kb
Host smart-f7896b4f-028b-454e-b44c-020ae7cde3e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307617594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.307617594
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1398993134
Short name T881
Test name
Test status
Simulation time 143695335030 ps
CPU time 336.23 seconds
Started Apr 02 02:14:37 PM PDT 24
Finished Apr 02 02:20:13 PM PDT 24
Peak memory 200484 kb
Host smart-bb979429-2fe0-41fe-9671-7fdc6b33580f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398993134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1398993134
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2846537256
Short name T468
Test name
Test status
Simulation time 2967794482 ps
CPU time 11.99 seconds
Started Apr 02 02:14:32 PM PDT 24
Finished Apr 02 02:14:44 PM PDT 24
Peak memory 199068 kb
Host smart-320ee42c-79e3-46ff-a619-589679fe9838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846537256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2846537256
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1315021219
Short name T1020
Test name
Test status
Simulation time 3427724185 ps
CPU time 7.83 seconds
Started Apr 02 02:14:27 PM PDT 24
Finished Apr 02 02:14:36 PM PDT 24
Peak memory 199452 kb
Host smart-3338f7d6-ac55-4a06-9d5b-e487d7a26db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315021219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1315021219
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.524815104
Short name T168
Test name
Test status
Simulation time 13251947455 ps
CPU time 20.28 seconds
Started Apr 02 02:14:34 PM PDT 24
Finished Apr 02 02:14:56 PM PDT 24
Peak memory 200432 kb
Host smart-bb4cf3fd-ddaf-4670-913c-cb21867f9ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524815104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.524815104
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3353508249
Short name T857
Test name
Test status
Simulation time 2950741516 ps
CPU time 5.43 seconds
Started Apr 02 02:14:27 PM PDT 24
Finished Apr 02 02:14:34 PM PDT 24
Peak memory 196444 kb
Host smart-b4325eb4-0bb4-46d8-bd9a-c9a4c7f06103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353508249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3353508249
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.239110993
Short name T649
Test name
Test status
Simulation time 447558605 ps
CPU time 1.97 seconds
Started Apr 02 02:14:25 PM PDT 24
Finished Apr 02 02:14:28 PM PDT 24
Peak memory 199888 kb
Host smart-fdc8a659-b580-42f2-9250-ced5551b8b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239110993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.239110993
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.821786744
Short name T1179
Test name
Test status
Simulation time 337483924047 ps
CPU time 388.31 seconds
Started Apr 02 02:14:33 PM PDT 24
Finished Apr 02 02:21:04 PM PDT 24
Peak memory 209020 kb
Host smart-59d0128a-2e08-4346-9d7c-7160acd923da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821786744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.821786744
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.748820471
Short name T359
Test name
Test status
Simulation time 459970314 ps
CPU time 2.03 seconds
Started Apr 02 02:14:32 PM PDT 24
Finished Apr 02 02:14:34 PM PDT 24
Peak memory 200372 kb
Host smart-4f17a50f-352d-4fa0-858f-ffee4dccd260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748820471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.748820471
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.649358309
Short name T278
Test name
Test status
Simulation time 60587260342 ps
CPU time 24.47 seconds
Started Apr 02 02:14:26 PM PDT 24
Finished Apr 02 02:14:51 PM PDT 24
Peak memory 200476 kb
Host smart-386934a5-3a98-485d-94ff-d6b2cc24d815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649358309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.649358309
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2983905002
Short name T685
Test name
Test status
Simulation time 108930549281 ps
CPU time 61.15 seconds
Started Apr 02 02:23:54 PM PDT 24
Finished Apr 02 02:24:55 PM PDT 24
Peak memory 200484 kb
Host smart-bc0c50b2-4458-42ef-9411-f3ae21c3a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983905002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2983905002
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1390081708
Short name T504
Test name
Test status
Simulation time 16719500518 ps
CPU time 30.71 seconds
Started Apr 02 02:23:53 PM PDT 24
Finished Apr 02 02:24:24 PM PDT 24
Peak memory 200524 kb
Host smart-85d07f26-7b91-4dbd-83ae-64bee3e4218a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390081708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1390081708
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1722007095
Short name T1158
Test name
Test status
Simulation time 30700067779 ps
CPU time 25.3 seconds
Started Apr 02 02:23:53 PM PDT 24
Finished Apr 02 02:24:18 PM PDT 24
Peak memory 200432 kb
Host smart-264b0601-7150-495a-924c-39a7da3f6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722007095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1722007095
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2831658109
Short name T506
Test name
Test status
Simulation time 24441132373 ps
CPU time 27.85 seconds
Started Apr 02 02:23:56 PM PDT 24
Finished Apr 02 02:24:24 PM PDT 24
Peak memory 200532 kb
Host smart-33e53bbf-cd48-427f-ac84-ec4345744cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831658109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2831658109
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1107608202
Short name T945
Test name
Test status
Simulation time 21125130570 ps
CPU time 9.59 seconds
Started Apr 02 02:24:04 PM PDT 24
Finished Apr 02 02:24:14 PM PDT 24
Peak memory 200496 kb
Host smart-f181539d-dfde-44cf-8703-2778a326b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107608202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1107608202
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1866978600
Short name T905
Test name
Test status
Simulation time 87909739918 ps
CPU time 126.52 seconds
Started Apr 02 02:24:03 PM PDT 24
Finished Apr 02 02:26:09 PM PDT 24
Peak memory 200364 kb
Host smart-ab398914-bcb9-4272-bb52-6226226dc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866978600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1866978600
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2720382907
Short name T999
Test name
Test status
Simulation time 32740148706 ps
CPU time 35.25 seconds
Started Apr 02 02:24:01 PM PDT 24
Finished Apr 02 02:24:37 PM PDT 24
Peak memory 200496 kb
Host smart-9db68f01-0632-49c3-8caa-f74e585573fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720382907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2720382907
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2755780576
Short name T255
Test name
Test status
Simulation time 38578345571 ps
CPU time 14.81 seconds
Started Apr 02 02:24:04 PM PDT 24
Finished Apr 02 02:24:19 PM PDT 24
Peak memory 200528 kb
Host smart-3ea58cac-c982-4842-86ec-977ff44f2bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755780576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2755780576
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1088580845
Short name T583
Test name
Test status
Simulation time 11153959 ps
CPU time 0.55 seconds
Started Apr 02 02:14:53 PM PDT 24
Finished Apr 02 02:14:54 PM PDT 24
Peak memory 195784 kb
Host smart-11514cde-a7e5-4214-b014-9f9d5a4d0828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088580845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1088580845
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1137828775
Short name T711
Test name
Test status
Simulation time 232460451106 ps
CPU time 54.85 seconds
Started Apr 02 02:14:34 PM PDT 24
Finished Apr 02 02:15:30 PM PDT 24
Peak memory 200480 kb
Host smart-b5b5cdb6-c829-4046-8a0e-085c87d66d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137828775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1137828775
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4050633786
Short name T308
Test name
Test status
Simulation time 182022804739 ps
CPU time 155.62 seconds
Started Apr 02 02:14:40 PM PDT 24
Finished Apr 02 02:17:15 PM PDT 24
Peak memory 200472 kb
Host smart-031a9b38-efc9-40d6-a138-b858c4530a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050633786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4050633786
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1780516510
Short name T524
Test name
Test status
Simulation time 7295911374 ps
CPU time 7.01 seconds
Started Apr 02 02:14:39 PM PDT 24
Finished Apr 02 02:14:46 PM PDT 24
Peak memory 200400 kb
Host smart-409b636c-dd1b-420c-81d5-017a866244d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780516510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1780516510
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.626063109
Short name T515
Test name
Test status
Simulation time 65911243934 ps
CPU time 669.62 seconds
Started Apr 02 02:14:52 PM PDT 24
Finished Apr 02 02:26:02 PM PDT 24
Peak memory 200444 kb
Host smart-15c16f63-43d9-40cf-b064-fb8f3d079f58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626063109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.626063109
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.621486643
Short name T701
Test name
Test status
Simulation time 135160896 ps
CPU time 0.84 seconds
Started Apr 02 02:14:52 PM PDT 24
Finished Apr 02 02:14:53 PM PDT 24
Peak memory 196540 kb
Host smart-2159fd71-dd7f-43da-9ec2-9c7a3d2d1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621486643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.621486643
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3799166384
Short name T289
Test name
Test status
Simulation time 112197600919 ps
CPU time 50.15 seconds
Started Apr 02 02:14:41 PM PDT 24
Finished Apr 02 02:15:32 PM PDT 24
Peak memory 208844 kb
Host smart-2b92b23e-2b58-4df6-8dd6-44a70eccc149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799166384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3799166384
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.114495713
Short name T544
Test name
Test status
Simulation time 17703490698 ps
CPU time 271.1 seconds
Started Apr 02 02:14:48 PM PDT 24
Finished Apr 02 02:19:20 PM PDT 24
Peak memory 200496 kb
Host smart-5cf643f1-dfff-484c-a7b9-322140468db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114495713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.114495713
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1943081696
Short name T798
Test name
Test status
Simulation time 3688251717 ps
CPU time 6.56 seconds
Started Apr 02 02:14:39 PM PDT 24
Finished Apr 02 02:14:46 PM PDT 24
Peak memory 199368 kb
Host smart-5c389563-5c1e-4da7-a155-a34f8699508c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943081696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1943081696
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1605989740
Short name T381
Test name
Test status
Simulation time 20660992252 ps
CPU time 17.94 seconds
Started Apr 02 02:14:50 PM PDT 24
Finished Apr 02 02:15:08 PM PDT 24
Peak memory 199872 kb
Host smart-051cce6c-d099-4436-b8e3-08574f482400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605989740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1605989740
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2254958119
Short name T380
Test name
Test status
Simulation time 1491611873 ps
CPU time 3.11 seconds
Started Apr 02 02:14:43 PM PDT 24
Finished Apr 02 02:14:46 PM PDT 24
Peak memory 195824 kb
Host smart-bc74c941-679a-4931-8acb-0260d4824cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254958119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2254958119
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.123547979
Short name T1170
Test name
Test status
Simulation time 958898699 ps
CPU time 1.97 seconds
Started Apr 02 02:14:32 PM PDT 24
Finished Apr 02 02:14:34 PM PDT 24
Peak memory 199236 kb
Host smart-8e40dbfc-c7bd-4b0c-ba36-f9db13ceaeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123547979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.123547979
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3680983429
Short name T686
Test name
Test status
Simulation time 10474963141 ps
CPU time 99.46 seconds
Started Apr 02 02:14:53 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 200600 kb
Host smart-869ce5b7-5987-4ff9-8022-1eeaf36ebdad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680983429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3680983429
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1906135540
Short name T692
Test name
Test status
Simulation time 8299116153 ps
CPU time 11.11 seconds
Started Apr 02 02:14:50 PM PDT 24
Finished Apr 02 02:15:01 PM PDT 24
Peak memory 200416 kb
Host smart-ba6b70a4-a55f-4bb4-a29c-cfe1b210533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906135540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1906135540
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3701937772
Short name T444
Test name
Test status
Simulation time 11957207799 ps
CPU time 6.42 seconds
Started Apr 02 02:14:37 PM PDT 24
Finished Apr 02 02:14:44 PM PDT 24
Peak memory 200504 kb
Host smart-38a12c04-17ee-48c6-be14-296ae966ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701937772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3701937772
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1357230273
Short name T1116
Test name
Test status
Simulation time 8627526233 ps
CPU time 14.06 seconds
Started Apr 02 02:24:06 PM PDT 24
Finished Apr 02 02:24:20 PM PDT 24
Peak memory 200448 kb
Host smart-0626235a-a11b-4024-ae32-50db885fd798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357230273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1357230273
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1203161983
Short name T1172
Test name
Test status
Simulation time 257618196311 ps
CPU time 24.9 seconds
Started Apr 02 02:24:10 PM PDT 24
Finished Apr 02 02:24:35 PM PDT 24
Peak memory 200436 kb
Host smart-2f004fc3-de2d-40de-8af4-f068835609e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203161983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1203161983
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.714430467
Short name T949
Test name
Test status
Simulation time 103029801487 ps
CPU time 150.27 seconds
Started Apr 02 02:24:09 PM PDT 24
Finished Apr 02 02:26:39 PM PDT 24
Peak memory 200512 kb
Host smart-2f626eb4-7d8b-4af4-ab1c-2a181d1fd136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714430467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.714430467
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.111499287
Short name T532
Test name
Test status
Simulation time 33686718503 ps
CPU time 26.2 seconds
Started Apr 02 02:24:09 PM PDT 24
Finished Apr 02 02:24:35 PM PDT 24
Peak memory 200396 kb
Host smart-eaf23574-d25c-42fb-acdc-457c7f5ee36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111499287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.111499287
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2374861146
Short name T830
Test name
Test status
Simulation time 33941386359 ps
CPU time 25.78 seconds
Started Apr 02 02:24:09 PM PDT 24
Finished Apr 02 02:24:35 PM PDT 24
Peak memory 200472 kb
Host smart-e2a9bd98-48f1-43af-a1ac-47d8f5e3783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374861146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2374861146
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.673189037
Short name T256
Test name
Test status
Simulation time 71270085176 ps
CPU time 33 seconds
Started Apr 02 02:24:14 PM PDT 24
Finished Apr 02 02:24:47 PM PDT 24
Peak memory 200472 kb
Host smart-6938dfc3-c829-4932-930f-6d5f9f346bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673189037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.673189037
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1988589778
Short name T1054
Test name
Test status
Simulation time 107995053169 ps
CPU time 162.93 seconds
Started Apr 02 02:24:15 PM PDT 24
Finished Apr 02 02:26:58 PM PDT 24
Peak memory 200352 kb
Host smart-bbab62b4-5faa-4a14-8d4c-f9fc4e5b1da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988589778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1988589778
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2088919255
Short name T169
Test name
Test status
Simulation time 47676376800 ps
CPU time 25.8 seconds
Started Apr 02 02:24:15 PM PDT 24
Finished Apr 02 02:24:41 PM PDT 24
Peak memory 200420 kb
Host smart-af45c37a-f94b-42ee-a2a7-e3bc5658e809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088919255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2088919255
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1319266085
Short name T199
Test name
Test status
Simulation time 42351696752 ps
CPU time 45.07 seconds
Started Apr 02 02:24:13 PM PDT 24
Finished Apr 02 02:24:58 PM PDT 24
Peak memory 200436 kb
Host smart-ad740828-72a4-4e3d-a0cd-3182d383c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319266085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1319266085
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.600434238
Short name T25
Test name
Test status
Simulation time 101875474 ps
CPU time 0.52 seconds
Started Apr 02 02:15:06 PM PDT 24
Finished Apr 02 02:15:07 PM PDT 24
Peak memory 195876 kb
Host smart-2538e4b2-c568-42e1-a405-5d2bb939049f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600434238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.600434238
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1343671509
Short name T580
Test name
Test status
Simulation time 197468204531 ps
CPU time 45.23 seconds
Started Apr 02 02:14:56 PM PDT 24
Finished Apr 02 02:15:41 PM PDT 24
Peak memory 200420 kb
Host smart-ad65b185-ce97-4162-9e68-fcec88ebbbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343671509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1343671509
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3443165974
Short name T1088
Test name
Test status
Simulation time 66520548320 ps
CPU time 24.71 seconds
Started Apr 02 02:14:55 PM PDT 24
Finished Apr 02 02:15:20 PM PDT 24
Peak memory 200148 kb
Host smart-0e70dc02-c8e7-42c1-be82-6f116e4476f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443165974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3443165974
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.215739459
Short name T606
Test name
Test status
Simulation time 20251303073 ps
CPU time 18.18 seconds
Started Apr 02 02:15:06 PM PDT 24
Finished Apr 02 02:15:24 PM PDT 24
Peak memory 199936 kb
Host smart-6f6deb8e-ebcc-4c9f-96d5-f9a9cc687634
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215739459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.215739459
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2281692531
Short name T939
Test name
Test status
Simulation time 49376260827 ps
CPU time 150.33 seconds
Started Apr 02 02:15:05 PM PDT 24
Finished Apr 02 02:17:36 PM PDT 24
Peak memory 200348 kb
Host smart-3032a582-c419-40c9-86fb-adfc3ebd00f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281692531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2281692531
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3961651498
Short name T420
Test name
Test status
Simulation time 11698762319 ps
CPU time 16.87 seconds
Started Apr 02 02:15:02 PM PDT 24
Finished Apr 02 02:15:19 PM PDT 24
Peak memory 200488 kb
Host smart-002cacec-1d38-479a-87ef-95ba015071e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961651498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3961651498
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1445603007
Short name T957
Test name
Test status
Simulation time 93969397109 ps
CPU time 43.18 seconds
Started Apr 02 02:14:59 PM PDT 24
Finished Apr 02 02:15:42 PM PDT 24
Peak memory 200692 kb
Host smart-5b9b852e-b558-42f6-b48e-cf8a7bef8463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445603007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1445603007
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3349806363
Short name T327
Test name
Test status
Simulation time 4159473501 ps
CPU time 207.9 seconds
Started Apr 02 02:15:03 PM PDT 24
Finished Apr 02 02:18:31 PM PDT 24
Peak memory 200460 kb
Host smart-18327251-a26e-492c-91c2-116a61a0955a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349806363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3349806363
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1401511378
Short name T832
Test name
Test status
Simulation time 3702684100 ps
CPU time 30.51 seconds
Started Apr 02 02:14:59 PM PDT 24
Finished Apr 02 02:15:30 PM PDT 24
Peak memory 198928 kb
Host smart-5dc36b0b-8332-4e96-8095-218edeb3d81e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401511378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1401511378
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2255898333
Short name T867
Test name
Test status
Simulation time 59649392837 ps
CPU time 92.4 seconds
Started Apr 02 02:15:02 PM PDT 24
Finished Apr 02 02:16:35 PM PDT 24
Peak memory 200448 kb
Host smart-5ce9cacb-4c36-46e3-a365-9f5cd6990711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255898333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2255898333
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2928037485
Short name T1017
Test name
Test status
Simulation time 2851876522 ps
CPU time 1.76 seconds
Started Apr 02 02:15:03 PM PDT 24
Finished Apr 02 02:15:05 PM PDT 24
Peak memory 196196 kb
Host smart-43168024-5194-4bb0-9f46-3d890c3b5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928037485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2928037485
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3691515615
Short name T839
Test name
Test status
Simulation time 6281669082 ps
CPU time 15.76 seconds
Started Apr 02 02:14:53 PM PDT 24
Finished Apr 02 02:15:09 PM PDT 24
Peak memory 200460 kb
Host smart-316be020-5b45-468c-b9c3-bec22a839854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691515615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3691515615
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3428058619
Short name T875
Test name
Test status
Simulation time 242134855847 ps
CPU time 115.66 seconds
Started Apr 02 02:15:07 PM PDT 24
Finished Apr 02 02:17:03 PM PDT 24
Peak memory 216984 kb
Host smart-47310d70-385d-4053-9a7c-671054d02f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428058619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3428058619
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.555312758
Short name T1011
Test name
Test status
Simulation time 155058727099 ps
CPU time 429.75 seconds
Started Apr 02 02:15:07 PM PDT 24
Finished Apr 02 02:22:18 PM PDT 24
Peak memory 225348 kb
Host smart-f194d960-a26e-480c-9e41-e8781805226b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555312758 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.555312758
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2989823879
Short name T646
Test name
Test status
Simulation time 1215484541 ps
CPU time 2.11 seconds
Started Apr 02 02:15:02 PM PDT 24
Finished Apr 02 02:15:05 PM PDT 24
Peak memory 198848 kb
Host smart-948c2d14-e8a1-4a87-9ae8-9cac7096d23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989823879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2989823879
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3219209774
Short name T559
Test name
Test status
Simulation time 262892603009 ps
CPU time 53.06 seconds
Started Apr 02 02:14:53 PM PDT 24
Finished Apr 02 02:15:46 PM PDT 24
Peak memory 200352 kb
Host smart-7805922a-d789-41ab-9b8a-846859298dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219209774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3219209774
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4136509710
Short name T54
Test name
Test status
Simulation time 14036278327 ps
CPU time 23.61 seconds
Started Apr 02 02:24:20 PM PDT 24
Finished Apr 02 02:24:43 PM PDT 24
Peak memory 200456 kb
Host smart-6bd05ad5-6c34-4628-b731-cdb99d862944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136509710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4136509710
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3540784636
Short name T223
Test name
Test status
Simulation time 26882301533 ps
CPU time 45.31 seconds
Started Apr 02 02:24:20 PM PDT 24
Finished Apr 02 02:25:05 PM PDT 24
Peak memory 200432 kb
Host smart-79375075-e7a5-45b7-9094-7d5949ce5a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540784636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3540784636
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3158010912
Short name T883
Test name
Test status
Simulation time 20453090319 ps
CPU time 47.34 seconds
Started Apr 02 02:24:22 PM PDT 24
Finished Apr 02 02:25:09 PM PDT 24
Peak memory 200420 kb
Host smart-6b36e3db-bd3f-4f38-ba7d-d639da5b5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158010912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3158010912
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1375905096
Short name T106
Test name
Test status
Simulation time 142689889951 ps
CPU time 57.77 seconds
Started Apr 02 02:24:18 PM PDT 24
Finished Apr 02 02:25:16 PM PDT 24
Peak memory 200452 kb
Host smart-6317ce1e-ee8b-4543-94da-7743ad57e69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375905096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1375905096
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1296796972
Short name T147
Test name
Test status
Simulation time 45309112751 ps
CPU time 20.63 seconds
Started Apr 02 02:24:23 PM PDT 24
Finished Apr 02 02:24:44 PM PDT 24
Peak memory 200476 kb
Host smart-a7cc0063-b74a-406c-b5fb-c5867dfa33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296796972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1296796972
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3085062646
Short name T207
Test name
Test status
Simulation time 50333157652 ps
CPU time 72.67 seconds
Started Apr 02 02:24:26 PM PDT 24
Finished Apr 02 02:25:38 PM PDT 24
Peak memory 200428 kb
Host smart-aedf880a-7708-4871-a5f0-0ae48cc9c872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085062646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3085062646
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.80816940
Short name T998
Test name
Test status
Simulation time 77539383214 ps
CPU time 73.07 seconds
Started Apr 02 02:24:29 PM PDT 24
Finished Apr 02 02:25:42 PM PDT 24
Peak memory 200500 kb
Host smart-34d5a74a-0f27-4199-8806-3c8fd88b52ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80816940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.80816940
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2290355373
Short name T1058
Test name
Test status
Simulation time 96721212509 ps
CPU time 79.1 seconds
Started Apr 02 02:24:29 PM PDT 24
Finished Apr 02 02:25:48 PM PDT 24
Peak memory 200468 kb
Host smart-c2c4cdf6-0174-4495-9913-34030bc871e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290355373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2290355373
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3130323022
Short name T899
Test name
Test status
Simulation time 76582992037 ps
CPU time 124.6 seconds
Started Apr 02 02:24:26 PM PDT 24
Finished Apr 02 02:26:30 PM PDT 24
Peak memory 200500 kb
Host smart-4045c97d-7b39-426a-95ba-0ec93da3d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130323022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3130323022
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1109969133
Short name T728
Test name
Test status
Simulation time 133328572262 ps
CPU time 43.84 seconds
Started Apr 02 02:24:26 PM PDT 24
Finished Apr 02 02:25:09 PM PDT 24
Peak memory 200520 kb
Host smart-1b3fdeef-df87-466a-bab9-f06f4972dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109969133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1109969133
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2726523403
Short name T848
Test name
Test status
Simulation time 20640830 ps
CPU time 0.53 seconds
Started Apr 02 02:15:18 PM PDT 24
Finished Apr 02 02:15:19 PM PDT 24
Peak memory 195920 kb
Host smart-96c6b870-8023-40b3-b081-c427e7b85ee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726523403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2726523403
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3110618991
Short name T176
Test name
Test status
Simulation time 47665250032 ps
CPU time 73.6 seconds
Started Apr 02 02:15:06 PM PDT 24
Finished Apr 02 02:16:20 PM PDT 24
Peak memory 200448 kb
Host smart-70c50ef8-b439-4c4f-b1c6-37009d1348fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110618991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3110618991
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3066470658
Short name T1084
Test name
Test status
Simulation time 98235438424 ps
CPU time 44.77 seconds
Started Apr 02 02:15:11 PM PDT 24
Finished Apr 02 02:15:55 PM PDT 24
Peak memory 200500 kb
Host smart-653db429-f570-4495-9d3f-a40fe3ebdc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066470658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3066470658
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.833805995
Short name T480
Test name
Test status
Simulation time 30587098786 ps
CPU time 14.63 seconds
Started Apr 02 02:15:13 PM PDT 24
Finished Apr 02 02:15:28 PM PDT 24
Peak memory 199696 kb
Host smart-15ef675f-1cd1-4f6e-b02a-dec8818687d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833805995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.833805995
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1043942730
Short name T269
Test name
Test status
Simulation time 84728233327 ps
CPU time 606.1 seconds
Started Apr 02 02:15:17 PM PDT 24
Finished Apr 02 02:25:23 PM PDT 24
Peak memory 200452 kb
Host smart-bf71750b-58c9-430d-8518-a81efaf1bca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1043942730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1043942730
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.75262140
Short name T682
Test name
Test status
Simulation time 1317041771 ps
CPU time 2.79 seconds
Started Apr 02 02:15:13 PM PDT 24
Finished Apr 02 02:15:16 PM PDT 24
Peak memory 198964 kb
Host smart-dea09ef0-f23c-4f59-b430-cde3b530c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75262140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.75262140
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1201110971
Short name T1028
Test name
Test status
Simulation time 135908992964 ps
CPU time 67.65 seconds
Started Apr 02 02:15:13 PM PDT 24
Finished Apr 02 02:16:20 PM PDT 24
Peak memory 208724 kb
Host smart-ef1fb34b-5346-4a40-aefa-a08d70c25b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201110971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1201110971
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2426630311
Short name T782
Test name
Test status
Simulation time 8343046753 ps
CPU time 96.92 seconds
Started Apr 02 02:15:14 PM PDT 24
Finished Apr 02 02:16:51 PM PDT 24
Peak memory 200516 kb
Host smart-1e1d7471-d9dd-451b-aa05-26423944f79c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426630311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2426630311
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.218904623
Short name T1048
Test name
Test status
Simulation time 5775311265 ps
CPU time 12.66 seconds
Started Apr 02 02:15:10 PM PDT 24
Finished Apr 02 02:15:23 PM PDT 24
Peak memory 199336 kb
Host smart-ba9ab82b-d72c-4eff-803d-071b2787b7d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218904623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.218904623
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3325663535
Short name T321
Test name
Test status
Simulation time 10257454664 ps
CPU time 19.38 seconds
Started Apr 02 02:15:14 PM PDT 24
Finished Apr 02 02:15:33 PM PDT 24
Peak memory 200528 kb
Host smart-258064d3-0f13-4aeb-9f41-d3ffd602bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325663535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3325663535
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1463158366
Short name T377
Test name
Test status
Simulation time 2841379126 ps
CPU time 2.74 seconds
Started Apr 02 02:15:14 PM PDT 24
Finished Apr 02 02:15:16 PM PDT 24
Peak memory 196112 kb
Host smart-32277bce-34d3-435e-9a93-468b4b1d892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463158366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1463158366
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2393641883
Short name T614
Test name
Test status
Simulation time 1005904373 ps
CPU time 2.15 seconds
Started Apr 02 02:15:06 PM PDT 24
Finished Apr 02 02:15:09 PM PDT 24
Peak memory 200028 kb
Host smart-a8097484-e6ee-4e8c-b06b-6a037da3dab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393641883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2393641883
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2126973749
Short name T424
Test name
Test status
Simulation time 310287102008 ps
CPU time 723.93 seconds
Started Apr 02 02:15:15 PM PDT 24
Finished Apr 02 02:27:19 PM PDT 24
Peak memory 200492 kb
Host smart-559634e6-a184-4819-ae60-3940754c8a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126973749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2126973749
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.55191108
Short name T1145
Test name
Test status
Simulation time 7544307506 ps
CPU time 15.24 seconds
Started Apr 02 02:15:16 PM PDT 24
Finished Apr 02 02:15:31 PM PDT 24
Peak memory 199780 kb
Host smart-adfbfc76-5c49-4789-ba90-895b93054d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55191108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.55191108
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2392458523
Short name T495
Test name
Test status
Simulation time 148015467191 ps
CPU time 49.64 seconds
Started Apr 02 02:15:05 PM PDT 24
Finished Apr 02 02:15:55 PM PDT 24
Peak memory 200440 kb
Host smart-e89cf0a4-d3b8-43fa-b2b9-2ad0d7e448e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392458523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2392458523
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3327506561
Short name T757
Test name
Test status
Simulation time 92510050189 ps
CPU time 34.37 seconds
Started Apr 02 02:24:31 PM PDT 24
Finished Apr 02 02:25:06 PM PDT 24
Peak memory 198908 kb
Host smart-65a77705-56e2-4f78-afaf-95d7b95f5817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327506561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3327506561
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1800088582
Short name T346
Test name
Test status
Simulation time 163967916101 ps
CPU time 242.5 seconds
Started Apr 02 02:24:32 PM PDT 24
Finished Apr 02 02:28:34 PM PDT 24
Peak memory 200128 kb
Host smart-4c3cba0b-7129-4cee-be8d-4830248ba4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800088582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1800088582
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2318374333
Short name T673
Test name
Test status
Simulation time 86157674968 ps
CPU time 19.98 seconds
Started Apr 02 02:24:28 PM PDT 24
Finished Apr 02 02:24:49 PM PDT 24
Peak memory 200404 kb
Host smart-71fc0f4e-21e1-48db-8536-95dcbfcb89e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318374333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2318374333
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1370135997
Short name T229
Test name
Test status
Simulation time 28798325470 ps
CPU time 50.36 seconds
Started Apr 02 02:24:30 PM PDT 24
Finished Apr 02 02:25:21 PM PDT 24
Peak memory 200512 kb
Host smart-a9f29a16-0943-4705-8e66-4dc7525edb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370135997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1370135997
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2462024453
Short name T385
Test name
Test status
Simulation time 10288391244 ps
CPU time 18.07 seconds
Started Apr 02 02:24:36 PM PDT 24
Finished Apr 02 02:24:54 PM PDT 24
Peak memory 199020 kb
Host smart-defad64f-b4ff-40cf-9087-6d54db108dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462024453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2462024453
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2786162310
Short name T574
Test name
Test status
Simulation time 113955522297 ps
CPU time 32.96 seconds
Started Apr 02 02:24:36 PM PDT 24
Finished Apr 02 02:25:09 PM PDT 24
Peak memory 200436 kb
Host smart-3d127a2c-9cbd-45d9-8412-2bfd28a3fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786162310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2786162310
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2208348501
Short name T198
Test name
Test status
Simulation time 23365652142 ps
CPU time 33.59 seconds
Started Apr 02 02:24:34 PM PDT 24
Finished Apr 02 02:25:07 PM PDT 24
Peak memory 200344 kb
Host smart-1c6a0840-7594-4bd7-9005-f32a782e922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208348501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2208348501
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2353012748
Short name T426
Test name
Test status
Simulation time 351516857122 ps
CPU time 39.48 seconds
Started Apr 02 02:24:35 PM PDT 24
Finished Apr 02 02:25:15 PM PDT 24
Peak memory 200504 kb
Host smart-3ab63783-1f58-4440-8f66-d0122ccab16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353012748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2353012748
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4229573508
Short name T809
Test name
Test status
Simulation time 18925623931 ps
CPU time 32.42 seconds
Started Apr 02 02:24:34 PM PDT 24
Finished Apr 02 02:25:06 PM PDT 24
Peak memory 200456 kb
Host smart-14bf5f3e-d1a7-47a4-a096-caac45f52914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229573508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4229573508
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1081149627
Short name T705
Test name
Test status
Simulation time 88895517 ps
CPU time 0.52 seconds
Started Apr 02 02:15:25 PM PDT 24
Finished Apr 02 02:15:26 PM PDT 24
Peak memory 195864 kb
Host smart-56bf3f0f-0e25-44a4-8127-92874ea70d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081149627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1081149627
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1960326076
Short name T1176
Test name
Test status
Simulation time 120294383933 ps
CPU time 12.36 seconds
Started Apr 02 02:15:21 PM PDT 24
Finished Apr 02 02:15:34 PM PDT 24
Peak memory 200240 kb
Host smart-b06245f3-27a5-46ba-bfad-124298fe0a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960326076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1960326076
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1497027470
Short name T111
Test name
Test status
Simulation time 128850297672 ps
CPU time 58.05 seconds
Started Apr 02 02:15:22 PM PDT 24
Finished Apr 02 02:16:20 PM PDT 24
Peak memory 200512 kb
Host smart-e7443eba-6c39-4aac-891b-3876bda08123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497027470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1497027470
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.359663517
Short name T754
Test name
Test status
Simulation time 18549440000 ps
CPU time 36.64 seconds
Started Apr 02 02:15:23 PM PDT 24
Finished Apr 02 02:16:00 PM PDT 24
Peak memory 200428 kb
Host smart-2b706587-3a29-48c0-b95e-701fb1087385
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359663517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.359663517
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2821468900
Short name T464
Test name
Test status
Simulation time 229601768034 ps
CPU time 342.95 seconds
Started Apr 02 02:15:24 PM PDT 24
Finished Apr 02 02:21:07 PM PDT 24
Peak memory 200424 kb
Host smart-1c2cfea6-31db-49df-90fd-31d8c3d292c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821468900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2821468900
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2335541859
Short name T50
Test name
Test status
Simulation time 5550901605 ps
CPU time 3.38 seconds
Started Apr 02 02:15:26 PM PDT 24
Finished Apr 02 02:15:29 PM PDT 24
Peak memory 199620 kb
Host smart-6ea394e8-4ca5-4a3f-a7c7-f28a5ef97a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335541859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2335541859
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1875446062
Short name T1163
Test name
Test status
Simulation time 191399750626 ps
CPU time 80.56 seconds
Started Apr 02 02:15:24 PM PDT 24
Finished Apr 02 02:16:44 PM PDT 24
Peak memory 216148 kb
Host smart-921f362f-559f-4045-932b-512186471db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875446062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1875446062
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.4046115313
Short name T868
Test name
Test status
Simulation time 23969143060 ps
CPU time 1180.86 seconds
Started Apr 02 02:15:26 PM PDT 24
Finished Apr 02 02:35:07 PM PDT 24
Peak memory 200512 kb
Host smart-961a639f-02cc-4db4-83ec-e5de7d548a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046115313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4046115313
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.577409265
Short name T851
Test name
Test status
Simulation time 3049373967 ps
CPU time 7.65 seconds
Started Apr 02 02:15:22 PM PDT 24
Finished Apr 02 02:15:30 PM PDT 24
Peak memory 198552 kb
Host smart-c12a4b3b-aa89-441c-86fb-c0732c8ba45b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577409265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.577409265
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.350204916
Short name T768
Test name
Test status
Simulation time 21627918158 ps
CPU time 36.11 seconds
Started Apr 02 02:15:30 PM PDT 24
Finished Apr 02 02:16:06 PM PDT 24
Peak memory 200376 kb
Host smart-1d876052-03e5-49f0-a870-784ed343268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350204916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.350204916
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3736130129
Short name T669
Test name
Test status
Simulation time 4432019559 ps
CPU time 1.49 seconds
Started Apr 02 02:15:26 PM PDT 24
Finished Apr 02 02:15:28 PM PDT 24
Peak memory 196512 kb
Host smart-306ffc9c-0746-44cf-9d0a-ecf3612e7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736130129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3736130129
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3160246023
Short name T929
Test name
Test status
Simulation time 725793141 ps
CPU time 2.22 seconds
Started Apr 02 02:15:19 PM PDT 24
Finished Apr 02 02:15:21 PM PDT 24
Peak memory 200400 kb
Host smart-0188374e-0204-4256-b476-2df6ebfc7ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160246023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3160246023
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3650632012
Short name T724
Test name
Test status
Simulation time 89458379898 ps
CPU time 672.04 seconds
Started Apr 02 02:15:24 PM PDT 24
Finished Apr 02 02:26:36 PM PDT 24
Peak memory 228248 kb
Host smart-77fd0a72-8c03-48a3-97cd-b210a107063a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650632012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3650632012
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2037241264
Short name T760
Test name
Test status
Simulation time 10547577454 ps
CPU time 7.8 seconds
Started Apr 02 02:15:26 PM PDT 24
Finished Apr 02 02:15:34 PM PDT 24
Peak memory 199840 kb
Host smart-1c55af3e-563c-4507-89d6-6d62d4f149db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037241264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2037241264
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2985795136
Short name T526
Test name
Test status
Simulation time 33574847906 ps
CPU time 12.83 seconds
Started Apr 02 02:15:15 PM PDT 24
Finished Apr 02 02:15:28 PM PDT 24
Peak memory 200416 kb
Host smart-4ef62f85-fc60-48e5-9f8e-36429b772b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985795136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2985795136
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.465297914
Short name T860
Test name
Test status
Simulation time 20814786466 ps
CPU time 18.86 seconds
Started Apr 02 02:24:35 PM PDT 24
Finished Apr 02 02:24:54 PM PDT 24
Peak memory 200464 kb
Host smart-81282b2a-29e4-40de-a4af-0bf0a7690f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465297914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.465297914
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.263013476
Short name T37
Test name
Test status
Simulation time 75716804274 ps
CPU time 133.97 seconds
Started Apr 02 02:24:34 PM PDT 24
Finished Apr 02 02:26:48 PM PDT 24
Peak memory 200372 kb
Host smart-38c4337b-9786-4d55-b66c-80a9e94b5b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263013476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.263013476
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3925352505
Short name T996
Test name
Test status
Simulation time 63112980121 ps
CPU time 40.03 seconds
Started Apr 02 02:24:38 PM PDT 24
Finished Apr 02 02:25:19 PM PDT 24
Peak memory 200436 kb
Host smart-de7af38e-a656-4532-9867-1d956e7a2654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925352505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3925352505
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3180020404
Short name T907
Test name
Test status
Simulation time 31966755634 ps
CPU time 68.44 seconds
Started Apr 02 02:24:41 PM PDT 24
Finished Apr 02 02:25:50 PM PDT 24
Peak memory 200444 kb
Host smart-a2a4a236-dbae-4a26-a476-5224439ed8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180020404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3180020404
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3675994235
Short name T180
Test name
Test status
Simulation time 103091586552 ps
CPU time 180.47 seconds
Started Apr 02 02:24:39 PM PDT 24
Finished Apr 02 02:27:40 PM PDT 24
Peak memory 200408 kb
Host smart-c99717a6-1d9a-4387-bf9e-1e56f9c11291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675994235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3675994235
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3483930565
Short name T720
Test name
Test status
Simulation time 23968318388 ps
CPU time 18.78 seconds
Started Apr 02 02:24:41 PM PDT 24
Finished Apr 02 02:25:00 PM PDT 24
Peak memory 199476 kb
Host smart-118be156-0ada-44c9-a236-90069c9bc52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483930565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3483930565
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1045014983
Short name T913
Test name
Test status
Simulation time 71247740975 ps
CPU time 45.95 seconds
Started Apr 02 02:24:44 PM PDT 24
Finished Apr 02 02:25:30 PM PDT 24
Peak memory 200512 kb
Host smart-44117f79-4895-479c-ac8e-135911d01881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045014983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1045014983
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1261214428
Short name T641
Test name
Test status
Simulation time 112699844356 ps
CPU time 27.66 seconds
Started Apr 02 02:24:44 PM PDT 24
Finished Apr 02 02:25:12 PM PDT 24
Peak memory 200512 kb
Host smart-02f500ac-8b28-4fc1-a6e6-7bf48aa1e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261214428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1261214428
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3959414956
Short name T416
Test name
Test status
Simulation time 20662280 ps
CPU time 0.55 seconds
Started Apr 02 02:15:38 PM PDT 24
Finished Apr 02 02:15:39 PM PDT 24
Peak memory 194868 kb
Host smart-824c9c31-8563-4077-929c-8a052c8e6a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959414956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3959414956
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2231271016
Short name T387
Test name
Test status
Simulation time 22066574213 ps
CPU time 23.47 seconds
Started Apr 02 02:15:27 PM PDT 24
Finished Apr 02 02:15:51 PM PDT 24
Peak memory 200476 kb
Host smart-0ad4bad8-f517-4b84-8b59-61548f21858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231271016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2231271016
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.4017072167
Short name T698
Test name
Test status
Simulation time 112026367535 ps
CPU time 94.39 seconds
Started Apr 02 02:15:28 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 200380 kb
Host smart-0c9ed02a-4c1b-48a6-8d08-f4c2aa22f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017072167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4017072167
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.1687227704
Short name T1072
Test name
Test status
Simulation time 25016215774 ps
CPU time 42.78 seconds
Started Apr 02 02:15:29 PM PDT 24
Finished Apr 02 02:16:12 PM PDT 24
Peak memory 200444 kb
Host smart-9aed31a6-7a5d-407c-b326-26d0b4c4be3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687227704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1687227704
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1475001604
Short name T529
Test name
Test status
Simulation time 37007854167 ps
CPU time 285.92 seconds
Started Apr 02 02:15:34 PM PDT 24
Finished Apr 02 02:20:20 PM PDT 24
Peak memory 200448 kb
Host smart-6986cbff-aa1e-4cb2-8fe4-56aabf7d4521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475001604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1475001604
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2395521253
Short name T693
Test name
Test status
Simulation time 510419193 ps
CPU time 0.67 seconds
Started Apr 02 02:15:32 PM PDT 24
Finished Apr 02 02:15:33 PM PDT 24
Peak memory 196128 kb
Host smart-e16a6c97-7137-4722-988c-c9f77c4c8820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395521253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2395521253
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.942368653
Short name T616
Test name
Test status
Simulation time 166199326905 ps
CPU time 198.81 seconds
Started Apr 02 02:15:30 PM PDT 24
Finished Apr 02 02:18:49 PM PDT 24
Peak memory 216100 kb
Host smart-ebec5b4e-2bc4-44d2-9ab8-6142646a0e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942368653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.942368653
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.4256969892
Short name T629
Test name
Test status
Simulation time 11293755664 ps
CPU time 174.09 seconds
Started Apr 02 02:15:35 PM PDT 24
Finished Apr 02 02:18:29 PM PDT 24
Peak memory 200436 kb
Host smart-6ca42c82-df94-4fdc-bf5c-45b0f69eef63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256969892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4256969892
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2177087808
Short name T667
Test name
Test status
Simulation time 4940427368 ps
CPU time 10.48 seconds
Started Apr 02 02:15:30 PM PDT 24
Finished Apr 02 02:15:40 PM PDT 24
Peak memory 199608 kb
Host smart-f124b481-b6d8-43f2-99ab-c501bb1ea0a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177087808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2177087808
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2943831921
Short name T764
Test name
Test status
Simulation time 90148485926 ps
CPU time 14.71 seconds
Started Apr 02 02:15:31 PM PDT 24
Finished Apr 02 02:15:46 PM PDT 24
Peak memory 200348 kb
Host smart-58bf4168-6192-4480-a848-49dc0aa50490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943831921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2943831921
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2507157296
Short name T51
Test name
Test status
Simulation time 36805742459 ps
CPU time 16.64 seconds
Started Apr 02 02:15:34 PM PDT 24
Finished Apr 02 02:15:51 PM PDT 24
Peak memory 196384 kb
Host smart-36535e30-7a3e-4fcb-8bf3-727541a255ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507157296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2507157296
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3688538433
Short name T1031
Test name
Test status
Simulation time 701472923 ps
CPU time 2.26 seconds
Started Apr 02 02:15:29 PM PDT 24
Finished Apr 02 02:15:31 PM PDT 24
Peak memory 200052 kb
Host smart-f5af2665-a277-45af-b6c0-8bf12bd042c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688538433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3688538433
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2959609158
Short name T708
Test name
Test status
Simulation time 144973076910 ps
CPU time 234.07 seconds
Started Apr 02 02:15:38 PM PDT 24
Finished Apr 02 02:19:32 PM PDT 24
Peak memory 200720 kb
Host smart-b9cc3a0d-cde8-4e90-901e-6f4f8914ea1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959609158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2959609158
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2939779316
Short name T70
Test name
Test status
Simulation time 127094778742 ps
CPU time 432.32 seconds
Started Apr 02 02:15:34 PM PDT 24
Finished Apr 02 02:22:47 PM PDT 24
Peak memory 216624 kb
Host smart-2f77c3b1-9e9a-4ecf-abf6-df8846d79746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939779316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2939779316
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.513588064
Short name T656
Test name
Test status
Simulation time 6839456749 ps
CPU time 9.99 seconds
Started Apr 02 02:15:33 PM PDT 24
Finished Apr 02 02:15:43 PM PDT 24
Peak memory 200328 kb
Host smart-2c74b939-9513-4f02-b0be-bd804ba07e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513588064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.513588064
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.45036396
Short name T1089
Test name
Test status
Simulation time 76321117832 ps
CPU time 107 seconds
Started Apr 02 02:15:30 PM PDT 24
Finished Apr 02 02:17:17 PM PDT 24
Peak memory 200400 kb
Host smart-ba4b66fb-368b-47a4-8357-a3a1606a65f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45036396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.45036396
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1711559532
Short name T163
Test name
Test status
Simulation time 239457144878 ps
CPU time 20.05 seconds
Started Apr 02 02:24:46 PM PDT 24
Finished Apr 02 02:25:06 PM PDT 24
Peak memory 200452 kb
Host smart-75f86ca0-9ff5-4405-bd76-170144298ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711559532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1711559532
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.680748071
Short name T438
Test name
Test status
Simulation time 35860031043 ps
CPU time 62.13 seconds
Started Apr 02 02:24:44 PM PDT 24
Finished Apr 02 02:25:47 PM PDT 24
Peak memory 200044 kb
Host smart-3665a2cf-cb5e-4399-b7ee-628eb35e4cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680748071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.680748071
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1525460856
Short name T877
Test name
Test status
Simulation time 10941099078 ps
CPU time 15.66 seconds
Started Apr 02 02:24:49 PM PDT 24
Finished Apr 02 02:25:05 PM PDT 24
Peak memory 200436 kb
Host smart-2a865147-65dd-441d-b4ec-de4b8203b16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525460856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1525460856
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3851582016
Short name T737
Test name
Test status
Simulation time 10087995170 ps
CPU time 17.89 seconds
Started Apr 02 02:25:16 PM PDT 24
Finished Apr 02 02:25:34 PM PDT 24
Peak memory 200504 kb
Host smart-faeff63e-b108-402c-a8b5-485d8358eed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851582016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3851582016
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1555091891
Short name T241
Test name
Test status
Simulation time 22291944215 ps
CPU time 31.16 seconds
Started Apr 02 02:24:51 PM PDT 24
Finished Apr 02 02:25:22 PM PDT 24
Peak memory 200388 kb
Host smart-7e156ba5-0328-4b2c-990d-9a8197d2fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555091891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1555091891
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1729419493
Short name T261
Test name
Test status
Simulation time 106903193779 ps
CPU time 410.31 seconds
Started Apr 02 02:24:50 PM PDT 24
Finished Apr 02 02:31:41 PM PDT 24
Peak memory 200452 kb
Host smart-3e5d0dab-d2b7-46de-a889-2ad7beb1c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729419493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1729419493
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2650048240
Short name T1156
Test name
Test status
Simulation time 198794395453 ps
CPU time 67.87 seconds
Started Apr 02 02:24:51 PM PDT 24
Finished Apr 02 02:25:59 PM PDT 24
Peak memory 200440 kb
Host smart-34788fbd-ed86-4708-ad17-e072204e1dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650048240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2650048240
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.724703312
Short name T238
Test name
Test status
Simulation time 39975777152 ps
CPU time 33.6 seconds
Started Apr 02 02:24:55 PM PDT 24
Finished Apr 02 02:25:29 PM PDT 24
Peak memory 200256 kb
Host smart-944ba979-c7a7-4d51-9cb7-85c0746108d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724703312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.724703312
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.671730742
Short name T245
Test name
Test status
Simulation time 162027550442 ps
CPU time 124.17 seconds
Started Apr 02 02:24:55 PM PDT 24
Finished Apr 02 02:26:59 PM PDT 24
Peak memory 200384 kb
Host smart-8941dd10-30f9-4af1-a6e1-d1b69bdbafb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671730742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.671730742
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3113711664
Short name T1085
Test name
Test status
Simulation time 67412847656 ps
CPU time 45.5 seconds
Started Apr 02 02:24:55 PM PDT 24
Finished Apr 02 02:25:41 PM PDT 24
Peak memory 200472 kb
Host smart-31460607-b0c5-4c81-800d-f9b31fcef567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113711664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3113711664
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2109492743
Short name T892
Test name
Test status
Simulation time 108420840 ps
CPU time 0.52 seconds
Started Apr 02 02:15:53 PM PDT 24
Finished Apr 02 02:15:54 PM PDT 24
Peak memory 194788 kb
Host smart-ee2fbd7a-9175-4b3a-8fb4-a81df3528790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109492743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2109492743
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1132769478
Short name T989
Test name
Test status
Simulation time 319247244255 ps
CPU time 296.25 seconds
Started Apr 02 02:15:41 PM PDT 24
Finished Apr 02 02:20:37 PM PDT 24
Peak memory 200452 kb
Host smart-2a5203d0-4ac1-41fb-a749-9e4e32a19236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132769478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1132769478
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1496352562
Short name T40
Test name
Test status
Simulation time 33341216790 ps
CPU time 54.18 seconds
Started Apr 02 02:15:39 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 200412 kb
Host smart-0d3d3f85-4277-42ed-add6-ef6454f2db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496352562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1496352562
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.4043416512
Short name T546
Test name
Test status
Simulation time 54562101810 ps
CPU time 22.1 seconds
Started Apr 02 02:15:42 PM PDT 24
Finished Apr 02 02:16:04 PM PDT 24
Peak memory 200476 kb
Host smart-62647a1f-e989-42b9-9764-9c2157aa7ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043416512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4043416512
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2974065594
Short name T712
Test name
Test status
Simulation time 176245819267 ps
CPU time 191.69 seconds
Started Apr 02 02:15:47 PM PDT 24
Finished Apr 02 02:19:00 PM PDT 24
Peak memory 200480 kb
Host smart-37bfeea1-85dd-4269-abc0-2ecb1237c495
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974065594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2974065594
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3864012001
Short name T1137
Test name
Test status
Simulation time 64959348459 ps
CPU time 141.38 seconds
Started Apr 02 02:15:50 PM PDT 24
Finished Apr 02 02:18:11 PM PDT 24
Peak memory 200428 kb
Host smart-3e9d3680-082f-4982-9f1e-33f081a24a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864012001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3864012001
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4123092699
Short name T456
Test name
Test status
Simulation time 8326006106 ps
CPU time 15.11 seconds
Started Apr 02 02:15:52 PM PDT 24
Finished Apr 02 02:16:07 PM PDT 24
Peak memory 200436 kb
Host smart-d3771af1-c609-48c6-a303-9c38d579d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123092699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4123092699
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3400513105
Short name T414
Test name
Test status
Simulation time 63881199509 ps
CPU time 53.06 seconds
Started Apr 02 02:15:46 PM PDT 24
Finished Apr 02 02:16:39 PM PDT 24
Peak memory 200016 kb
Host smart-a5cdc68c-78d6-44f3-9492-d075e928d28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400513105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3400513105
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.2026776642
Short name T1140
Test name
Test status
Simulation time 4887591466 ps
CPU time 294.44 seconds
Started Apr 02 02:15:50 PM PDT 24
Finished Apr 02 02:20:45 PM PDT 24
Peak memory 200484 kb
Host smart-560d1771-7009-4040-add1-2023bdbbdb73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026776642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2026776642
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1628364904
Short name T538
Test name
Test status
Simulation time 4551204812 ps
CPU time 10.45 seconds
Started Apr 02 02:15:42 PM PDT 24
Finished Apr 02 02:15:53 PM PDT 24
Peak memory 199116 kb
Host smart-2cd9bade-0cbe-4454-8d65-b0773203ae10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628364904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1628364904
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1128984264
Short name T970
Test name
Test status
Simulation time 8656924011 ps
CPU time 18.1 seconds
Started Apr 02 02:15:51 PM PDT 24
Finished Apr 02 02:16:10 PM PDT 24
Peak memory 200420 kb
Host smart-2be49bdf-30c8-46a8-a48b-0dd1639638a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128984264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1128984264
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3412325518
Short name T441
Test name
Test status
Simulation time 1974142690 ps
CPU time 2.08 seconds
Started Apr 02 02:15:46 PM PDT 24
Finished Apr 02 02:15:49 PM PDT 24
Peak memory 195824 kb
Host smart-c9530c01-abd2-47f1-bc3f-c3db8b5220d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412325518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3412325518
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.4264386446
Short name T980
Test name
Test status
Simulation time 11111339155 ps
CPU time 54.03 seconds
Started Apr 02 02:15:38 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 200424 kb
Host smart-57eb9de2-60f6-4d08-8e9b-2c0134fd58de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264386446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4264386446
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1873580190
Short name T62
Test name
Test status
Simulation time 108875177594 ps
CPU time 369.23 seconds
Started Apr 02 02:15:50 PM PDT 24
Finished Apr 02 02:21:59 PM PDT 24
Peak memory 216524 kb
Host smart-33343e0d-075f-4a43-bf6a-e4b91ad3b385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873580190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1873580190
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1923581196
Short name T445
Test name
Test status
Simulation time 7913293433 ps
CPU time 9.13 seconds
Started Apr 02 02:15:51 PM PDT 24
Finished Apr 02 02:16:01 PM PDT 24
Peak memory 200472 kb
Host smart-5cff458d-9093-4102-9fa2-54f523773ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923581196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1923581196
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2726581734
Short name T634
Test name
Test status
Simulation time 62520783690 ps
CPU time 16.79 seconds
Started Apr 02 02:15:38 PM PDT 24
Finished Apr 02 02:15:56 PM PDT 24
Peak memory 200448 kb
Host smart-338c6e9e-62cf-4971-a313-53e768b33dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726581734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2726581734
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2549685367
Short name T642
Test name
Test status
Simulation time 27554306080 ps
CPU time 34.31 seconds
Started Apr 02 02:24:58 PM PDT 24
Finished Apr 02 02:25:32 PM PDT 24
Peak memory 200496 kb
Host smart-21e34ced-a283-468f-8c42-df717a9753cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549685367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2549685367
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.423365591
Short name T836
Test name
Test status
Simulation time 32630909555 ps
CPU time 62.64 seconds
Started Apr 02 02:24:56 PM PDT 24
Finished Apr 02 02:25:58 PM PDT 24
Peak memory 200500 kb
Host smart-43613281-705c-482a-9c9b-c8375e8de363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423365591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.423365591
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1913242918
Short name T573
Test name
Test status
Simulation time 103541792401 ps
CPU time 82.48 seconds
Started Apr 02 02:24:59 PM PDT 24
Finished Apr 02 02:26:22 PM PDT 24
Peak memory 200512 kb
Host smart-b1b1b85b-7047-4983-9653-278099e51467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913242918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1913242918
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2168489555
Short name T802
Test name
Test status
Simulation time 65326575258 ps
CPU time 20.51 seconds
Started Apr 02 02:24:58 PM PDT 24
Finished Apr 02 02:25:19 PM PDT 24
Peak memory 200484 kb
Host smart-ac730037-8b78-4342-b9e2-48d04cc16cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168489555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2168489555
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1214027203
Short name T244
Test name
Test status
Simulation time 83969716752 ps
CPU time 139.13 seconds
Started Apr 02 02:25:03 PM PDT 24
Finished Apr 02 02:27:23 PM PDT 24
Peak memory 200524 kb
Host smart-6f21400f-b668-4e2e-818c-074edf82de39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214027203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1214027203
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.190654408
Short name T630
Test name
Test status
Simulation time 46640108901 ps
CPU time 22.84 seconds
Started Apr 02 02:25:03 PM PDT 24
Finished Apr 02 02:25:27 PM PDT 24
Peak memory 200416 kb
Host smart-e4a98eaa-7040-44de-9a88-24fb71f297ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190654408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.190654408
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1306195212
Short name T274
Test name
Test status
Simulation time 20198662056 ps
CPU time 34.43 seconds
Started Apr 02 02:25:09 PM PDT 24
Finished Apr 02 02:25:44 PM PDT 24
Peak memory 200384 kb
Host smart-7eba7b98-697f-4b95-8e71-f294daac06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306195212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1306195212
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3788930983
Short name T235
Test name
Test status
Simulation time 73234355517 ps
CPU time 25.78 seconds
Started Apr 02 02:25:05 PM PDT 24
Finished Apr 02 02:25:31 PM PDT 24
Peak memory 200452 kb
Host smart-98e346d0-7ff9-476d-b5bd-1a35ba9d1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788930983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3788930983
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.884219423
Short name T514
Test name
Test status
Simulation time 90162336090 ps
CPU time 129.61 seconds
Started Apr 02 02:25:09 PM PDT 24
Finished Apr 02 02:27:19 PM PDT 24
Peak memory 200444 kb
Host smart-a2fee2e3-637f-419c-9ea3-6ee192936611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884219423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.884219423
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2118001445
Short name T1118
Test name
Test status
Simulation time 287823973312 ps
CPU time 124.2 seconds
Started Apr 02 02:25:05 PM PDT 24
Finished Apr 02 02:27:10 PM PDT 24
Peak memory 200536 kb
Host smart-d5407cc8-10a8-4bd0-aae7-6ae32498e418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118001445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2118001445
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1618515146
Short name T811
Test name
Test status
Simulation time 12449224 ps
CPU time 0.56 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:11:58 PM PDT 24
Peak memory 195876 kb
Host smart-96ac5546-d09c-4968-a1f5-49c048a9bac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618515146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1618515146
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1053293494
Short name T994
Test name
Test status
Simulation time 72280795602 ps
CPU time 112.64 seconds
Started Apr 02 02:11:47 PM PDT 24
Finished Apr 02 02:13:40 PM PDT 24
Peak memory 200448 kb
Host smart-ed3c4329-b573-44bf-b297-5e3e73d9477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053293494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1053293494
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1037805030
Short name T683
Test name
Test status
Simulation time 95923731333 ps
CPU time 16.94 seconds
Started Apr 02 02:11:48 PM PDT 24
Finished Apr 02 02:12:05 PM PDT 24
Peak memory 200376 kb
Host smart-14d4aa95-8a31-4c66-a32a-6dc1ea6624e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037805030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1037805030
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2380301210
Short name T984
Test name
Test status
Simulation time 89651178031 ps
CPU time 46.35 seconds
Started Apr 02 02:11:48 PM PDT 24
Finished Apr 02 02:12:35 PM PDT 24
Peak memory 200388 kb
Host smart-855c756c-bb87-4ea4-994c-139ae746d717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380301210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2380301210
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1177480329
Short name T107
Test name
Test status
Simulation time 23128626321 ps
CPU time 37.59 seconds
Started Apr 02 02:11:49 PM PDT 24
Finished Apr 02 02:12:27 PM PDT 24
Peak memory 198228 kb
Host smart-dd87f011-820a-46bc-8160-705a31bf5b33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177480329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1177480329
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.374313328
Short name T41
Test name
Test status
Simulation time 112506425406 ps
CPU time 914.86 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:27:12 PM PDT 24
Peak memory 200424 kb
Host smart-e09cd8aa-b5dd-4558-a532-0f43d9c8b982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374313328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.374313328
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.8954848
Short name T1026
Test name
Test status
Simulation time 6781845793 ps
CPU time 8.27 seconds
Started Apr 02 02:11:55 PM PDT 24
Finished Apr 02 02:12:03 PM PDT 24
Peak memory 199652 kb
Host smart-d48e0665-6cba-4d06-b02e-ebe07e089a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8954848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.8954848
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1812171278
Short name T808
Test name
Test status
Simulation time 23329357274 ps
CPU time 36 seconds
Started Apr 02 02:11:52 PM PDT 24
Finished Apr 02 02:12:28 PM PDT 24
Peak memory 200784 kb
Host smart-782aab48-9cbb-4a93-830c-67007c2d9c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812171278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1812171278
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.690413190
Short name T436
Test name
Test status
Simulation time 20812532015 ps
CPU time 870.59 seconds
Started Apr 02 02:11:56 PM PDT 24
Finished Apr 02 02:26:27 PM PDT 24
Peak memory 200452 kb
Host smart-e8fe8e75-6c0c-4c05-95ec-77f625b0f941
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=690413190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.690413190
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2354223977
Short name T1087
Test name
Test status
Simulation time 4456443788 ps
CPU time 38.45 seconds
Started Apr 02 02:11:48 PM PDT 24
Finished Apr 02 02:12:27 PM PDT 24
Peak memory 198664 kb
Host smart-a6a1a870-da08-4118-9754-0b17042e1734
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354223977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2354223977
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3699346714
Short name T933
Test name
Test status
Simulation time 77634675162 ps
CPU time 31.57 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:12:29 PM PDT 24
Peak memory 200452 kb
Host smart-51612585-5812-40c0-92b1-83a451d6071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699346714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3699346714
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.190332466
Short name T681
Test name
Test status
Simulation time 1982124008 ps
CPU time 2.29 seconds
Started Apr 02 02:11:53 PM PDT 24
Finished Apr 02 02:11:55 PM PDT 24
Peak memory 195804 kb
Host smart-6b7e35ab-cde4-4183-8119-57b34ba5bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190332466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.190332466
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2085326672
Short name T103
Test name
Test status
Simulation time 130640187 ps
CPU time 0.86 seconds
Started Apr 02 02:11:59 PM PDT 24
Finished Apr 02 02:12:00 PM PDT 24
Peak memory 218788 kb
Host smart-ea104d70-bef2-402f-979d-a481e1e0ba23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085326672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2085326672
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1312188142
Short name T719
Test name
Test status
Simulation time 804646841 ps
CPU time 3.31 seconds
Started Apr 02 02:11:48 PM PDT 24
Finished Apr 02 02:11:51 PM PDT 24
Peak memory 199820 kb
Host smart-7d9baa91-a7b7-4d01-ba71-e2aced3c42eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312188142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1312188142
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4049384917
Short name T1167
Test name
Test status
Simulation time 107206175621 ps
CPU time 172.99 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:14:50 PM PDT 24
Peak memory 200504 kb
Host smart-b76df400-6c4d-493d-a55f-3ab694dd2428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049384917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4049384917
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2186105418
Short name T56
Test name
Test status
Simulation time 55956199570 ps
CPU time 247.77 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:16:05 PM PDT 24
Peak memory 217184 kb
Host smart-f28a7f3a-92f8-4ef8-a6ae-0b75d26bd0e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186105418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2186105418
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2227743776
Short name T1100
Test name
Test status
Simulation time 1240576447 ps
CPU time 2.96 seconds
Started Apr 02 02:11:55 PM PDT 24
Finished Apr 02 02:11:58 PM PDT 24
Peak memory 200080 kb
Host smart-16741ee7-d7b5-4a67-adcd-628bcbc6d6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227743776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2227743776
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2009705611
Short name T462
Test name
Test status
Simulation time 89323251527 ps
CPU time 68.58 seconds
Started Apr 02 02:11:47 PM PDT 24
Finished Apr 02 02:12:55 PM PDT 24
Peak memory 200472 kb
Host smart-56cafe75-e9d7-4128-902a-3e3f517b06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009705611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2009705611
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.336215091
Short name T725
Test name
Test status
Simulation time 41347520 ps
CPU time 0.61 seconds
Started Apr 02 02:16:04 PM PDT 24
Finished Apr 02 02:16:04 PM PDT 24
Peak memory 195892 kb
Host smart-f0ac48ed-1bde-46f9-89ec-e98fe823e977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336215091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.336215091
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1999535850
Short name T569
Test name
Test status
Simulation time 214134794755 ps
CPU time 767.81 seconds
Started Apr 02 02:15:59 PM PDT 24
Finished Apr 02 02:28:47 PM PDT 24
Peak memory 200428 kb
Host smart-32bce31f-81b8-40f7-b9ef-262756f38fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999535850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1999535850
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1895359695
Short name T1038
Test name
Test status
Simulation time 13110942375 ps
CPU time 44.21 seconds
Started Apr 02 02:15:59 PM PDT 24
Finished Apr 02 02:16:43 PM PDT 24
Peak memory 200480 kb
Host smart-622b3b3c-e843-49b6-a63f-6a05f861cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895359695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1895359695
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2374447771
Short name T733
Test name
Test status
Simulation time 92065393287 ps
CPU time 12.48 seconds
Started Apr 02 02:15:59 PM PDT 24
Finished Apr 02 02:16:12 PM PDT 24
Peak memory 200516 kb
Host smart-01d21c05-37c2-4867-8e33-d3f0f77a10ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374447771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2374447771
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2666560930
Short name T492
Test name
Test status
Simulation time 272646766423 ps
CPU time 74.8 seconds
Started Apr 02 02:15:59 PM PDT 24
Finished Apr 02 02:17:14 PM PDT 24
Peak memory 200496 kb
Host smart-ed6f40f4-8964-4b27-9b02-88df11a43d60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666560930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2666560930
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3136802852
Short name T1049
Test name
Test status
Simulation time 63292849666 ps
CPU time 155.95 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:18:40 PM PDT 24
Peak memory 200436 kb
Host smart-146e7cc9-69be-4585-8609-8a1cbd2109ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136802852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3136802852
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.63799632
Short name T894
Test name
Test status
Simulation time 6744789289 ps
CPU time 7.74 seconds
Started Apr 02 02:16:04 PM PDT 24
Finished Apr 02 02:16:12 PM PDT 24
Peak memory 199324 kb
Host smart-f0a27199-0e72-403d-83f2-be31839467cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63799632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.63799632
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3764300472
Short name T921
Test name
Test status
Simulation time 33455277786 ps
CPU time 51.41 seconds
Started Apr 02 02:16:00 PM PDT 24
Finished Apr 02 02:16:51 PM PDT 24
Peak memory 200812 kb
Host smart-1dbba097-83b6-49c0-b31a-e2f7c754ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764300472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3764300472
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.455471690
Short name T581
Test name
Test status
Simulation time 4117193908 ps
CPU time 217.3 seconds
Started Apr 02 02:16:08 PM PDT 24
Finished Apr 02 02:19:45 PM PDT 24
Peak memory 200500 kb
Host smart-014063e3-2cc4-4c97-bffe-708d4b16a2aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455471690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.455471690
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.416499087
Short name T511
Test name
Test status
Simulation time 6970481206 ps
CPU time 60.23 seconds
Started Apr 02 02:16:00 PM PDT 24
Finished Apr 02 02:17:00 PM PDT 24
Peak memory 199068 kb
Host smart-cb5f0783-8e1e-4230-9cf0-4e6aa505f09a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416499087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.416499087
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3102754989
Short name T779
Test name
Test status
Simulation time 32663787441 ps
CPU time 25.42 seconds
Started Apr 02 02:16:02 PM PDT 24
Finished Apr 02 02:16:27 PM PDT 24
Peak memory 200476 kb
Host smart-95aae9a2-101b-4b73-b884-cea6a4d31c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102754989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3102754989
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1174954263
Short name T1090
Test name
Test status
Simulation time 47732681281 ps
CPU time 5.56 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:16:09 PM PDT 24
Peak memory 196504 kb
Host smart-d0ac6a54-b188-4c53-a91d-d4a153038385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174954263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1174954263
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3442350262
Short name T597
Test name
Test status
Simulation time 434113844 ps
CPU time 1.58 seconds
Started Apr 02 02:15:56 PM PDT 24
Finished Apr 02 02:15:58 PM PDT 24
Peak memory 199720 kb
Host smart-ea73c253-2129-4c7e-9368-04f470bff039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442350262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3442350262
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.129720828
Short name T129
Test name
Test status
Simulation time 78279200146 ps
CPU time 151.23 seconds
Started Apr 02 02:16:04 PM PDT 24
Finished Apr 02 02:18:35 PM PDT 24
Peak memory 200804 kb
Host smart-71f30ffe-167b-4085-b886-e7009d5600cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129720828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.129720828
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.310109491
Short name T576
Test name
Test status
Simulation time 6300461588 ps
CPU time 42.93 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:16:47 PM PDT 24
Peak memory 200488 kb
Host smart-0b671db4-83c6-4042-a0aa-81035fe72a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310109491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.310109491
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3677060990
Short name T293
Test name
Test status
Simulation time 26543352060 ps
CPU time 13.75 seconds
Started Apr 02 02:15:53 PM PDT 24
Finished Apr 02 02:16:07 PM PDT 24
Peak memory 200324 kb
Host smart-325d0bb2-a054-431d-b282-dfccd9da9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677060990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3677060990
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.966089334
Short name T472
Test name
Test status
Simulation time 11827496849 ps
CPU time 9.75 seconds
Started Apr 02 02:25:09 PM PDT 24
Finished Apr 02 02:25:19 PM PDT 24
Peak memory 200468 kb
Host smart-c33f5820-04a8-4ae8-9236-3730197669a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966089334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.966089334
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1130868735
Short name T1173
Test name
Test status
Simulation time 131144842974 ps
CPU time 98.47 seconds
Started Apr 02 02:25:11 PM PDT 24
Finished Apr 02 02:26:51 PM PDT 24
Peak memory 200412 kb
Host smart-1ac39686-c058-40f5-952b-143af21d779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130868735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1130868735
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.4004779873
Short name T435
Test name
Test status
Simulation time 20710697532 ps
CPU time 26.84 seconds
Started Apr 02 02:25:13 PM PDT 24
Finished Apr 02 02:25:41 PM PDT 24
Peak memory 200496 kb
Host smart-a2c93fcc-b99f-47bb-b941-f5570f1a309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004779873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.4004779873
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1937393672
Short name T217
Test name
Test status
Simulation time 34540379920 ps
CPU time 27.63 seconds
Started Apr 02 02:25:12 PM PDT 24
Finished Apr 02 02:25:40 PM PDT 24
Peak memory 200436 kb
Host smart-a4c5c2bd-5efb-4ef3-beb9-6e44ed6a04c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937393672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1937393672
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.391961559
Short name T823
Test name
Test status
Simulation time 37621741526 ps
CPU time 36.79 seconds
Started Apr 02 02:25:12 PM PDT 24
Finished Apr 02 02:25:49 PM PDT 24
Peak memory 200452 kb
Host smart-8176744e-b102-41c4-b866-51e92da795ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391961559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.391961559
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3482094057
Short name T306
Test name
Test status
Simulation time 9636626142 ps
CPU time 48.1 seconds
Started Apr 02 02:25:16 PM PDT 24
Finished Apr 02 02:26:04 PM PDT 24
Peak memory 200468 kb
Host smart-f579c501-06e7-4d42-b558-12d3af3b7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482094057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3482094057
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2314953409
Short name T1121
Test name
Test status
Simulation time 78261318884 ps
CPU time 111.85 seconds
Started Apr 02 02:25:16 PM PDT 24
Finished Apr 02 02:27:08 PM PDT 24
Peak memory 200444 kb
Host smart-58285908-e109-45ef-b27b-8f2ab906e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314953409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2314953409
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4124272099
Short name T613
Test name
Test status
Simulation time 11315147065 ps
CPU time 24.46 seconds
Started Apr 02 02:25:20 PM PDT 24
Finished Apr 02 02:25:44 PM PDT 24
Peak memory 200492 kb
Host smart-7e349271-cdd5-43b7-b063-5cb0c560b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124272099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4124272099
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2187839806
Short name T1024
Test name
Test status
Simulation time 119741758328 ps
CPU time 168.02 seconds
Started Apr 02 02:25:19 PM PDT 24
Finished Apr 02 02:28:08 PM PDT 24
Peak memory 200552 kb
Host smart-e1cc95aa-89fa-4500-a267-d6425cc2f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187839806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2187839806
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3931504504
Short name T602
Test name
Test status
Simulation time 10756803722 ps
CPU time 16.33 seconds
Started Apr 02 02:25:18 PM PDT 24
Finished Apr 02 02:25:35 PM PDT 24
Peak memory 200444 kb
Host smart-3bbbcf11-e496-483c-b818-e3c1935a7cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931504504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3931504504
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2357418639
Short name T454
Test name
Test status
Simulation time 47876263 ps
CPU time 0.53 seconds
Started Apr 02 02:16:23 PM PDT 24
Finished Apr 02 02:16:23 PM PDT 24
Peak memory 195892 kb
Host smart-1d809073-9ce0-42f5-8756-067d6fec05c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357418639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2357418639
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3592028546
Short name T651
Test name
Test status
Simulation time 117708271225 ps
CPU time 25.61 seconds
Started Apr 02 02:16:06 PM PDT 24
Finished Apr 02 02:16:32 PM PDT 24
Peak memory 200504 kb
Host smart-035d2b3a-f87b-45a5-92d7-676ec794ed5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592028546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3592028546
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1010611989
Short name T1130
Test name
Test status
Simulation time 79643965610 ps
CPU time 54.23 seconds
Started Apr 02 02:16:08 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 200440 kb
Host smart-e9ce7b9d-433c-4d97-a28f-26a849b2ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010611989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1010611989
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3851695752
Short name T553
Test name
Test status
Simulation time 47654426043 ps
CPU time 15.03 seconds
Started Apr 02 02:16:08 PM PDT 24
Finished Apr 02 02:16:23 PM PDT 24
Peak memory 200504 kb
Host smart-3754619b-d09e-450b-b89d-f89f2997f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851695752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3851695752
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.4058219161
Short name T471
Test name
Test status
Simulation time 60086420857 ps
CPU time 26.41 seconds
Started Apr 02 02:16:07 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 200444 kb
Host smart-daceb88e-1a99-4393-9b37-72e3dc635946
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058219161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.4058219161
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3838388884
Short name T865
Test name
Test status
Simulation time 89661891579 ps
CPU time 672.36 seconds
Started Apr 02 02:16:14 PM PDT 24
Finished Apr 02 02:27:27 PM PDT 24
Peak memory 200408 kb
Host smart-0cfa78dd-a7b9-4079-b023-f4229a948346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838388884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3838388884
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2146445533
Short name T110
Test name
Test status
Simulation time 2983485507 ps
CPU time 5.61 seconds
Started Apr 02 02:16:11 PM PDT 24
Finished Apr 02 02:16:17 PM PDT 24
Peak memory 199468 kb
Host smart-08dba604-8b79-41b1-8e71-4612e6d030f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146445533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2146445533
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3401570729
Short name T1109
Test name
Test status
Simulation time 52082312234 ps
CPU time 57.73 seconds
Started Apr 02 02:16:07 PM PDT 24
Finished Apr 02 02:17:05 PM PDT 24
Peak memory 200664 kb
Host smart-226f2f2f-97bb-4971-851a-033d53e113be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401570729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3401570729
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1359050046
Short name T77
Test name
Test status
Simulation time 26510466769 ps
CPU time 355.81 seconds
Started Apr 02 02:16:10 PM PDT 24
Finished Apr 02 02:22:06 PM PDT 24
Peak memory 200516 kb
Host smart-206a0764-3361-47b0-b6f0-de2d546a8665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359050046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1359050046
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.4104371274
Short name T588
Test name
Test status
Simulation time 1690433172 ps
CPU time 6.33 seconds
Started Apr 02 02:16:07 PM PDT 24
Finished Apr 02 02:16:13 PM PDT 24
Peak memory 198988 kb
Host smart-752c454a-711f-4f4f-91eb-00e379033c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104371274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.4104371274
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.622483983
Short name T178
Test name
Test status
Simulation time 236096382912 ps
CPU time 79.63 seconds
Started Apr 02 02:16:08 PM PDT 24
Finished Apr 02 02:17:27 PM PDT 24
Peak memory 200488 kb
Host smart-717946b7-53c1-43aa-8bde-b8e980739f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622483983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.622483983
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4147491967
Short name T1106
Test name
Test status
Simulation time 5428028449 ps
CPU time 7.86 seconds
Started Apr 02 02:16:08 PM PDT 24
Finished Apr 02 02:16:16 PM PDT 24
Peak memory 196768 kb
Host smart-ba0f74f0-55eb-45e0-aeb6-fe2f4e2d3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147491967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4147491967
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1219469425
Short name T756
Test name
Test status
Simulation time 302239007 ps
CPU time 1.05 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:16:05 PM PDT 24
Peak memory 198616 kb
Host smart-1df634ee-3191-4265-8fa1-f5de05905c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219469425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1219469425
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1813586521
Short name T459
Test name
Test status
Simulation time 118967314787 ps
CPU time 445.76 seconds
Started Apr 02 02:16:16 PM PDT 24
Finished Apr 02 02:23:42 PM PDT 24
Peak memory 200480 kb
Host smart-cdf925c0-5a74-4844-809f-60d2c32d531e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813586521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1813586521
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2337744330
Short name T311
Test name
Test status
Simulation time 6638940679 ps
CPU time 18.33 seconds
Started Apr 02 02:16:11 PM PDT 24
Finished Apr 02 02:16:30 PM PDT 24
Peak memory 200400 kb
Host smart-b3976724-9643-4aca-b424-5e7a8baa2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337744330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2337744330
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1567901165
Short name T354
Test name
Test status
Simulation time 12224312604 ps
CPU time 28.87 seconds
Started Apr 02 02:16:03 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 200352 kb
Host smart-e3256724-d5f8-41cd-9bbf-37e6874196ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567901165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1567901165
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1929161658
Short name T869
Test name
Test status
Simulation time 177056901008 ps
CPU time 90.63 seconds
Started Apr 02 02:25:18 PM PDT 24
Finished Apr 02 02:26:49 PM PDT 24
Peak memory 200384 kb
Host smart-ab46ce91-5653-46d5-8834-1f6031bb0009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929161658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1929161658
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3663152856
Short name T188
Test name
Test status
Simulation time 14835225614 ps
CPU time 25.42 seconds
Started Apr 02 02:25:24 PM PDT 24
Finished Apr 02 02:25:49 PM PDT 24
Peak memory 200424 kb
Host smart-f5f6c36a-eb15-45e1-bd3c-8c26f814b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663152856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3663152856
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4242665907
Short name T704
Test name
Test status
Simulation time 101273049587 ps
CPU time 40.93 seconds
Started Apr 02 02:25:24 PM PDT 24
Finished Apr 02 02:26:05 PM PDT 24
Peak memory 200440 kb
Host smart-271a1944-5367-4d87-b156-df82f09df326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242665907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4242665907
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2675040433
Short name T767
Test name
Test status
Simulation time 63404755310 ps
CPU time 46.92 seconds
Started Apr 02 02:25:27 PM PDT 24
Finished Apr 02 02:26:14 PM PDT 24
Peak memory 200484 kb
Host smart-e795f986-7cc1-4118-8823-f1dfcaeb8f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675040433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2675040433
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3399642782
Short name T12
Test name
Test status
Simulation time 25120881400 ps
CPU time 42.9 seconds
Started Apr 02 02:25:27 PM PDT 24
Finished Apr 02 02:26:10 PM PDT 24
Peak memory 200492 kb
Host smart-9077c05c-376e-4e8d-81aa-13d6b6684f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399642782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3399642782
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.150865177
Short name T873
Test name
Test status
Simulation time 30022781314 ps
CPU time 31.94 seconds
Started Apr 02 02:25:28 PM PDT 24
Finished Apr 02 02:26:00 PM PDT 24
Peak memory 200384 kb
Host smart-c1f72560-9fb4-4bdb-97e8-1f4dcbea3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150865177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.150865177
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2351246594
Short name T171
Test name
Test status
Simulation time 33874954861 ps
CPU time 14.1 seconds
Started Apr 02 02:25:32 PM PDT 24
Finished Apr 02 02:25:47 PM PDT 24
Peak memory 200464 kb
Host smart-1f319706-8228-4244-a225-ce3d003b3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351246594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2351246594
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2308957088
Short name T662
Test name
Test status
Simulation time 95277127166 ps
CPU time 38.04 seconds
Started Apr 02 02:25:32 PM PDT 24
Finished Apr 02 02:26:10 PM PDT 24
Peak memory 200304 kb
Host smart-51ad4332-d19e-4f86-874f-3e83b1b55e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308957088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2308957088
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.899029163
Short name T457
Test name
Test status
Simulation time 121701707354 ps
CPU time 53.07 seconds
Started Apr 02 02:25:32 PM PDT 24
Finished Apr 02 02:26:25 PM PDT 24
Peak memory 200480 kb
Host smart-a5d463dc-2614-4dc5-93bf-4c108c2890b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899029163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.899029163
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3174910425
Short name T946
Test name
Test status
Simulation time 15969651 ps
CPU time 0.55 seconds
Started Apr 02 02:16:28 PM PDT 24
Finished Apr 02 02:16:29 PM PDT 24
Peak memory 195864 kb
Host smart-2c13b745-18f5-4c80-9e70-30dbefae87e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174910425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3174910425
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4047434446
Short name T502
Test name
Test status
Simulation time 32581967847 ps
CPU time 51.88 seconds
Started Apr 02 02:16:16 PM PDT 24
Finished Apr 02 02:17:08 PM PDT 24
Peak memory 200432 kb
Host smart-a30baf1a-c0ea-4da4-be1c-25eda13e33cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047434446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4047434446
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.296729702
Short name T535
Test name
Test status
Simulation time 16136259530 ps
CPU time 17.97 seconds
Started Apr 02 02:16:20 PM PDT 24
Finished Apr 02 02:16:39 PM PDT 24
Peak memory 200428 kb
Host smart-91e78948-476c-4404-bb52-c5cc158a900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296729702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.296729702
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.438594625
Short name T962
Test name
Test status
Simulation time 208846221610 ps
CPU time 74.28 seconds
Started Apr 02 02:16:22 PM PDT 24
Finished Apr 02 02:17:37 PM PDT 24
Peak memory 200372 kb
Host smart-f9fe9595-f711-49f5-98fc-5aa84e74ce22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438594625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.438594625
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1422260616
Short name T270
Test name
Test status
Simulation time 74401018501 ps
CPU time 149.16 seconds
Started Apr 02 02:16:22 PM PDT 24
Finished Apr 02 02:18:52 PM PDT 24
Peak memory 200512 kb
Host smart-6612d341-c832-41a5-b79c-0c762ee4bcf8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422260616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1422260616
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2112999441
Short name T1105
Test name
Test status
Simulation time 152709793154 ps
CPU time 588.54 seconds
Started Apr 02 02:16:27 PM PDT 24
Finished Apr 02 02:26:16 PM PDT 24
Peak memory 200448 kb
Host smart-373fdad7-4cfe-4299-84cb-37c84535f946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112999441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2112999441
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2043044490
Short name T1142
Test name
Test status
Simulation time 3187702850 ps
CPU time 8.83 seconds
Started Apr 02 02:16:25 PM PDT 24
Finished Apr 02 02:16:34 PM PDT 24
Peak memory 200236 kb
Host smart-14edf5bd-1156-4459-bba3-5b508e2b4006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043044490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2043044490
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1736864919
Short name T1046
Test name
Test status
Simulation time 35495033587 ps
CPU time 17.08 seconds
Started Apr 02 02:16:20 PM PDT 24
Finished Apr 02 02:16:38 PM PDT 24
Peak memory 199716 kb
Host smart-64f8324c-1967-4fce-b599-1cccd39c066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736864919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1736864919
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.24431148
Short name T316
Test name
Test status
Simulation time 8201388554 ps
CPU time 463.23 seconds
Started Apr 02 02:16:25 PM PDT 24
Finished Apr 02 02:24:09 PM PDT 24
Peak memory 200408 kb
Host smart-ca9f7080-86d9-42b5-933b-e475ae983da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24431148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.24431148
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3007656604
Short name T655
Test name
Test status
Simulation time 5664527495 ps
CPU time 23.13 seconds
Started Apr 02 02:16:20 PM PDT 24
Finished Apr 02 02:16:44 PM PDT 24
Peak memory 200324 kb
Host smart-ff620956-ba2c-4e19-b5ad-49b5a194e267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007656604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3007656604
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.986446146
Short name T413
Test name
Test status
Simulation time 40251699715 ps
CPU time 15.79 seconds
Started Apr 02 02:16:25 PM PDT 24
Finished Apr 02 02:16:41 PM PDT 24
Peak memory 200324 kb
Host smart-b4855431-284a-44b3-92e4-d7d819fc559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986446146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.986446146
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2338963247
Short name T329
Test name
Test status
Simulation time 3235846282 ps
CPU time 3.18 seconds
Started Apr 02 02:16:22 PM PDT 24
Finished Apr 02 02:16:26 PM PDT 24
Peak memory 196484 kb
Host smart-7c705eed-cb14-4512-9b36-af459e682a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338963247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2338963247
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.381471317
Short name T977
Test name
Test status
Simulation time 696045066 ps
CPU time 2.14 seconds
Started Apr 02 02:16:16 PM PDT 24
Finished Apr 02 02:16:19 PM PDT 24
Peak memory 199256 kb
Host smart-60fd0e60-5883-42ef-9dcd-41d0d51da08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381471317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.381471317
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2499608296
Short name T243
Test name
Test status
Simulation time 511331902093 ps
CPU time 362.81 seconds
Started Apr 02 02:16:26 PM PDT 24
Finished Apr 02 02:22:29 PM PDT 24
Peak memory 211140 kb
Host smart-b2ae3a3b-8b03-4ffc-b1d4-afbb3bfeb0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499608296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2499608296
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3814693140
Short name T713
Test name
Test status
Simulation time 32313880173 ps
CPU time 113.8 seconds
Started Apr 02 02:16:27 PM PDT 24
Finished Apr 02 02:18:21 PM PDT 24
Peak memory 217144 kb
Host smart-6947cbc2-f558-46f6-8aa8-3fc4b09d5bc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814693140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3814693140
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3259725319
Short name T1086
Test name
Test status
Simulation time 3988136830 ps
CPU time 1.42 seconds
Started Apr 02 02:16:25 PM PDT 24
Finished Apr 02 02:16:27 PM PDT 24
Peak memory 200212 kb
Host smart-caa043ec-ee75-4bde-ab79-080200e557b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259725319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3259725319
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.4196242043
Short name T263
Test name
Test status
Simulation time 48190711423 ps
CPU time 93.25 seconds
Started Apr 02 02:16:16 PM PDT 24
Finished Apr 02 02:17:50 PM PDT 24
Peak memory 200452 kb
Host smart-5ae43dbd-96e8-4342-ae4e-d3ba463faef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196242043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.4196242043
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4178242579
Short name T170
Test name
Test status
Simulation time 117312459966 ps
CPU time 99.45 seconds
Started Apr 02 02:25:35 PM PDT 24
Finished Apr 02 02:27:14 PM PDT 24
Peak memory 200464 kb
Host smart-8ee04ff5-2321-404b-aeda-c2611ea69007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178242579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4178242579
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2696570340
Short name T884
Test name
Test status
Simulation time 7459892456 ps
CPU time 13.67 seconds
Started Apr 02 02:25:34 PM PDT 24
Finished Apr 02 02:25:48 PM PDT 24
Peak memory 200512 kb
Host smart-9ee84424-55f8-4f53-8785-af48a53bfe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696570340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2696570340
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4030723514
Short name T208
Test name
Test status
Simulation time 137683575428 ps
CPU time 52.23 seconds
Started Apr 02 02:25:34 PM PDT 24
Finished Apr 02 02:26:26 PM PDT 24
Peak memory 200328 kb
Host smart-ac9ed6ee-5fb3-4666-b619-759320a9f6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030723514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4030723514
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2731389081
Short name T469
Test name
Test status
Simulation time 35578671100 ps
CPU time 24.9 seconds
Started Apr 02 02:25:34 PM PDT 24
Finished Apr 02 02:25:59 PM PDT 24
Peak memory 200512 kb
Host smart-a866f0a3-fa95-42a8-9f93-31d2f4442a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731389081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2731389081
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2512167864
Short name T93
Test name
Test status
Simulation time 108638593243 ps
CPU time 245.98 seconds
Started Apr 02 02:25:37 PM PDT 24
Finished Apr 02 02:29:43 PM PDT 24
Peak memory 200520 kb
Host smart-eec0a0c8-d343-4e1c-8e74-d8b2ebd229a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512167864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2512167864
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3970996611
Short name T910
Test name
Test status
Simulation time 24136223922 ps
CPU time 17.75 seconds
Started Apr 02 02:25:36 PM PDT 24
Finished Apr 02 02:25:54 PM PDT 24
Peak memory 200512 kb
Host smart-d6734e6b-a5fa-4969-b4b4-8bf169ee4708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970996611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3970996611
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.520898216
Short name T1003
Test name
Test status
Simulation time 19132582102 ps
CPU time 8.43 seconds
Started Apr 02 02:25:40 PM PDT 24
Finished Apr 02 02:25:49 PM PDT 24
Peak memory 200432 kb
Host smart-a995f488-a4f7-4e6d-84e3-b743bc42459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520898216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.520898216
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2211336545
Short name T739
Test name
Test status
Simulation time 205922922856 ps
CPU time 99.82 seconds
Started Apr 02 02:25:41 PM PDT 24
Finished Apr 02 02:27:21 PM PDT 24
Peak memory 200472 kb
Host smart-32dc8719-cd62-4f32-bc96-902b82f97aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211336545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2211336545
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3294683531
Short name T891
Test name
Test status
Simulation time 90073374550 ps
CPU time 37.22 seconds
Started Apr 02 02:25:38 PM PDT 24
Finished Apr 02 02:26:15 PM PDT 24
Peak memory 200176 kb
Host smart-80f0e553-011b-4c19-a345-f661f7c02922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294683531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3294683531
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.572968196
Short name T1096
Test name
Test status
Simulation time 18127639166 ps
CPU time 28.02 seconds
Started Apr 02 02:25:37 PM PDT 24
Finished Apr 02 02:26:05 PM PDT 24
Peak memory 200476 kb
Host smart-7fbdb474-e203-47b1-a407-3d2dce53fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572968196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.572968196
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1694170521
Short name T360
Test name
Test status
Simulation time 75036311 ps
CPU time 0.56 seconds
Started Apr 02 02:16:43 PM PDT 24
Finished Apr 02 02:16:43 PM PDT 24
Peak memory 195904 kb
Host smart-ab606629-ce05-4c1a-b6ad-4327ebb51eec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694170521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1694170521
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2301100470
Short name T135
Test name
Test status
Simulation time 33477907019 ps
CPU time 30.14 seconds
Started Apr 02 02:16:30 PM PDT 24
Finished Apr 02 02:17:00 PM PDT 24
Peak memory 200484 kb
Host smart-4fa40db4-e9f8-43bd-aeb2-d34a08f890af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301100470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2301100470
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1328781242
Short name T807
Test name
Test status
Simulation time 30523192828 ps
CPU time 44.85 seconds
Started Apr 02 02:16:35 PM PDT 24
Finished Apr 02 02:17:20 PM PDT 24
Peak memory 200212 kb
Host smart-9f06fbd0-ff57-4bb0-97d6-e06286d742ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328781242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1328781242
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3304213080
Short name T924
Test name
Test status
Simulation time 188905825980 ps
CPU time 79 seconds
Started Apr 02 02:16:36 PM PDT 24
Finished Apr 02 02:17:55 PM PDT 24
Peak memory 200496 kb
Host smart-bb85b1e2-bc5d-4880-b433-4051a5364140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304213080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3304213080
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.326737325
Short name T819
Test name
Test status
Simulation time 40313442969 ps
CPU time 15.8 seconds
Started Apr 02 02:16:34 PM PDT 24
Finished Apr 02 02:16:50 PM PDT 24
Peak memory 200448 kb
Host smart-70b1c57d-859b-4646-94b8-5fca27d123fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326737325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.326737325
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.228330465
Short name T371
Test name
Test status
Simulation time 46349402280 ps
CPU time 88.42 seconds
Started Apr 02 02:16:38 PM PDT 24
Finished Apr 02 02:18:06 PM PDT 24
Peak memory 200468 kb
Host smart-4cc56f9a-c1ee-4fd3-8991-198e096ce275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228330465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.228330465
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2162680713
Short name T853
Test name
Test status
Simulation time 6215314150 ps
CPU time 13 seconds
Started Apr 02 02:16:49 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 200488 kb
Host smart-635ef3b4-7fc5-4149-b518-6f27a0d1c92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162680713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2162680713
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1397337324
Short name T1039
Test name
Test status
Simulation time 5867979836 ps
CPU time 9.78 seconds
Started Apr 02 02:16:34 PM PDT 24
Finished Apr 02 02:16:44 PM PDT 24
Peak memory 195148 kb
Host smart-041a4791-b56d-4da7-a0e9-ce601e6275c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397337324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1397337324
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1172866055
Short name T512
Test name
Test status
Simulation time 9858079439 ps
CPU time 147.23 seconds
Started Apr 02 02:16:39 PM PDT 24
Finished Apr 02 02:19:07 PM PDT 24
Peak memory 200432 kb
Host smart-13426ed4-cdcb-43a1-a619-a73f71cf8df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172866055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1172866055
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1417694373
Short name T342
Test name
Test status
Simulation time 5010431431 ps
CPU time 45.39 seconds
Started Apr 02 02:16:38 PM PDT 24
Finished Apr 02 02:17:23 PM PDT 24
Peak memory 198620 kb
Host smart-c5e08f29-27a9-41ae-9d2b-59b8426e26f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1417694373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1417694373
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1541828924
Short name T282
Test name
Test status
Simulation time 163128956534 ps
CPU time 53.93 seconds
Started Apr 02 02:16:39 PM PDT 24
Finished Apr 02 02:17:33 PM PDT 24
Peak memory 200464 kb
Host smart-43096639-aa64-4f32-b65b-fe1c73487723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541828924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1541828924
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.577477240
Short name T551
Test name
Test status
Simulation time 633936591 ps
CPU time 1.75 seconds
Started Apr 02 02:16:40 PM PDT 24
Finished Apr 02 02:16:42 PM PDT 24
Peak memory 195776 kb
Host smart-5b22c09d-8f55-4c5b-a25c-d298f075e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577477240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.577477240
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1734671505
Short name T386
Test name
Test status
Simulation time 840576852 ps
CPU time 4.96 seconds
Started Apr 02 02:16:27 PM PDT 24
Finished Apr 02 02:16:32 PM PDT 24
Peak memory 200004 kb
Host smart-7dee3474-49b7-44f1-bc9d-7868f770335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734671505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1734671505
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1638045788
Short name T900
Test name
Test status
Simulation time 250013422775 ps
CPU time 632.06 seconds
Started Apr 02 02:16:40 PM PDT 24
Finished Apr 02 02:27:12 PM PDT 24
Peak memory 200400 kb
Host smart-e5b21c16-c565-404a-8060-42c3d1e8c7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638045788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1638045788
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.674155479
Short name T1060
Test name
Test status
Simulation time 286644403915 ps
CPU time 1118.29 seconds
Started Apr 02 02:16:44 PM PDT 24
Finished Apr 02 02:35:22 PM PDT 24
Peak memory 227052 kb
Host smart-108c8234-a6c4-4032-b7c3-648c6d932b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674155479 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.674155479
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.910651922
Short name T795
Test name
Test status
Simulation time 2858945887 ps
CPU time 2.11 seconds
Started Apr 02 02:16:41 PM PDT 24
Finished Apr 02 02:16:43 PM PDT 24
Peak memory 200460 kb
Host smart-3a0192b2-37ed-43e7-93f5-b81c883c71c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910651922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.910651922
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.412649595
Short name T517
Test name
Test status
Simulation time 67103926754 ps
CPU time 37.85 seconds
Started Apr 02 02:16:31 PM PDT 24
Finished Apr 02 02:17:10 PM PDT 24
Peak memory 200416 kb
Host smart-128f5818-36c1-4374-99aa-a3018bf473cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412649595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.412649595
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2527740080
Short name T351
Test name
Test status
Simulation time 70515808726 ps
CPU time 25.97 seconds
Started Apr 02 02:25:38 PM PDT 24
Finished Apr 02 02:26:04 PM PDT 24
Peak memory 200392 kb
Host smart-c674fbbb-9178-45fd-97e2-130d70e4dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527740080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2527740080
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3566027038
Short name T5
Test name
Test status
Simulation time 70990572814 ps
CPU time 131.99 seconds
Started Apr 02 02:25:41 PM PDT 24
Finished Apr 02 02:27:53 PM PDT 24
Peak memory 200508 kb
Host smart-dcc1b2a4-dc07-4714-899a-459535c11799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566027038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3566027038
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1510644139
Short name T334
Test name
Test status
Simulation time 109460271879 ps
CPU time 166.62 seconds
Started Apr 02 02:25:43 PM PDT 24
Finished Apr 02 02:28:30 PM PDT 24
Peak memory 200436 kb
Host smart-b99c53a2-b88d-4790-83e0-d5d5d83a4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510644139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1510644139
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.4006600621
Short name T1018
Test name
Test status
Simulation time 28247263570 ps
CPU time 13.85 seconds
Started Apr 02 02:25:44 PM PDT 24
Finished Apr 02 02:25:58 PM PDT 24
Peak memory 200388 kb
Host smart-9980632a-6a25-4c19-840b-b9f5b454f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006600621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.4006600621
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2015032755
Short name T825
Test name
Test status
Simulation time 99751891787 ps
CPU time 29.54 seconds
Started Apr 02 02:25:45 PM PDT 24
Finished Apr 02 02:26:15 PM PDT 24
Peak memory 200416 kb
Host smart-a3a7e311-2192-4210-b189-b5601b2a3f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015032755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2015032755
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1592487383
Short name T746
Test name
Test status
Simulation time 39086403308 ps
CPU time 53.72 seconds
Started Apr 02 02:25:44 PM PDT 24
Finished Apr 02 02:26:38 PM PDT 24
Peak memory 200508 kb
Host smart-a4f6c687-fe9e-41c6-afdf-9020d3fdc067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592487383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1592487383
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3758715909
Short name T880
Test name
Test status
Simulation time 41818958062 ps
CPU time 16.82 seconds
Started Apr 02 02:25:47 PM PDT 24
Finished Apr 02 02:26:04 PM PDT 24
Peak memory 200500 kb
Host smart-8cdee938-4d44-4e56-ad57-f3c730f7c4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758715909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3758715909
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.194062011
Short name T562
Test name
Test status
Simulation time 40786725 ps
CPU time 0.54 seconds
Started Apr 02 02:16:54 PM PDT 24
Finished Apr 02 02:16:54 PM PDT 24
Peak memory 195848 kb
Host smart-ee4bb278-df51-478e-95f8-786dcd652ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194062011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.194062011
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2708840685
Short name T1052
Test name
Test status
Simulation time 32082911763 ps
CPU time 13.57 seconds
Started Apr 02 02:16:41 PM PDT 24
Finished Apr 02 02:16:55 PM PDT 24
Peak memory 200388 kb
Host smart-afc1c246-f0ed-4715-8212-ec8193a138c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708840685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2708840685
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2040413692
Short name T703
Test name
Test status
Simulation time 116434060567 ps
CPU time 55.33 seconds
Started Apr 02 02:16:43 PM PDT 24
Finished Apr 02 02:17:38 PM PDT 24
Peak memory 200440 kb
Host smart-d09bad07-3928-4b97-b853-729a1c5fd509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040413692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2040413692
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.2704937394
Short name T338
Test name
Test status
Simulation time 339409813352 ps
CPU time 242.23 seconds
Started Apr 02 02:16:41 PM PDT 24
Finished Apr 02 02:20:43 PM PDT 24
Peak memory 198812 kb
Host smart-e00c2aff-6e1f-4717-93f2-e87108d16954
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704937394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2704937394
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.810524958
Short name T678
Test name
Test status
Simulation time 186275456573 ps
CPU time 128.61 seconds
Started Apr 02 02:16:51 PM PDT 24
Finished Apr 02 02:19:00 PM PDT 24
Peak memory 200404 kb
Host smart-bf23efea-d63d-47ac-b21f-37e21a84561f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810524958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.810524958
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.518251624
Short name T963
Test name
Test status
Simulation time 3491904812 ps
CPU time 6.93 seconds
Started Apr 02 02:16:53 PM PDT 24
Finished Apr 02 02:17:00 PM PDT 24
Peak memory 199072 kb
Host smart-333a1647-da13-45d3-b260-df95ba8c074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518251624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.518251624
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.4285893563
Short name T954
Test name
Test status
Simulation time 28034328880 ps
CPU time 48.55 seconds
Started Apr 02 02:16:44 PM PDT 24
Finished Apr 02 02:17:33 PM PDT 24
Peak memory 199336 kb
Host smart-89e0d30e-44d9-49f5-a400-b6753e9b1f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285893563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4285893563
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.231335530
Short name T267
Test name
Test status
Simulation time 14875296609 ps
CPU time 729.79 seconds
Started Apr 02 02:16:55 PM PDT 24
Finished Apr 02 02:29:05 PM PDT 24
Peak memory 200408 kb
Host smart-b5c5e136-4275-4c9c-9b51-f64cccbc9746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231335530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.231335530
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2063908945
Short name T109
Test name
Test status
Simulation time 5329144193 ps
CPU time 46 seconds
Started Apr 02 02:16:43 PM PDT 24
Finished Apr 02 02:17:29 PM PDT 24
Peak memory 199752 kb
Host smart-a9418613-b226-4e4c-b3f1-b3d18aebc5b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063908945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2063908945
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2201211647
Short name T139
Test name
Test status
Simulation time 35494017921 ps
CPU time 52.11 seconds
Started Apr 02 02:16:51 PM PDT 24
Finished Apr 02 02:17:44 PM PDT 24
Peak memory 200488 kb
Host smart-7363b5eb-da73-41a6-b33c-c4e1de18284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201211647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2201211647
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.483780309
Short name T341
Test name
Test status
Simulation time 5822117814 ps
CPU time 5.04 seconds
Started Apr 02 02:16:46 PM PDT 24
Finished Apr 02 02:16:51 PM PDT 24
Peak memory 196504 kb
Host smart-7458b3d2-8b43-4b98-a038-92f611054bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483780309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.483780309
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3202131850
Short name T1181
Test name
Test status
Simulation time 6285808635 ps
CPU time 28.12 seconds
Started Apr 02 02:16:41 PM PDT 24
Finished Apr 02 02:17:09 PM PDT 24
Peak memory 200364 kb
Host smart-1e8f4513-47f5-42b5-a026-c75833b1b633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202131850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3202131850
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3622697534
Short name T697
Test name
Test status
Simulation time 112514483320 ps
CPU time 655.57 seconds
Started Apr 02 02:16:52 PM PDT 24
Finished Apr 02 02:27:48 PM PDT 24
Peak memory 217172 kb
Host smart-17f837a4-948a-4a96-99a4-31a12c67ded1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622697534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3622697534
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3861469859
Short name T611
Test name
Test status
Simulation time 111683292168 ps
CPU time 1384.27 seconds
Started Apr 02 02:16:54 PM PDT 24
Finished Apr 02 02:39:58 PM PDT 24
Peak memory 214656 kb
Host smart-572147cb-d4a5-417f-8fe7-5c3516859c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861469859 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3861469859
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1426455815
Short name T392
Test name
Test status
Simulation time 884464582 ps
CPU time 1.7 seconds
Started Apr 02 02:16:50 PM PDT 24
Finished Apr 02 02:16:52 PM PDT 24
Peak memory 198924 kb
Host smart-6ab96b0c-7814-4102-b6da-1c7c150f51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426455815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1426455815
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.92331624
Short name T292
Test name
Test status
Simulation time 141787752540 ps
CPU time 271.11 seconds
Started Apr 02 02:16:42 PM PDT 24
Finished Apr 02 02:21:13 PM PDT 24
Peak memory 200496 kb
Host smart-699b6672-f273-44cc-8bc8-51c06aaca1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92331624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.92331624
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1939040874
Short name T259
Test name
Test status
Simulation time 22414304832 ps
CPU time 13.13 seconds
Started Apr 02 02:25:53 PM PDT 24
Finished Apr 02 02:26:06 PM PDT 24
Peak memory 200432 kb
Host smart-38155a78-2c76-446c-82b6-8449723b98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939040874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1939040874
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.4212197824
Short name T590
Test name
Test status
Simulation time 9201141421 ps
CPU time 18.05 seconds
Started Apr 02 02:25:50 PM PDT 24
Finished Apr 02 02:26:09 PM PDT 24
Peak memory 200512 kb
Host smart-84c4de17-b88b-451f-8ac4-c664c359c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212197824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4212197824
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2665139841
Short name T363
Test name
Test status
Simulation time 85694520887 ps
CPU time 12.18 seconds
Started Apr 02 02:25:48 PM PDT 24
Finished Apr 02 02:26:00 PM PDT 24
Peak memory 200408 kb
Host smart-494558bc-863e-4ec6-9f0f-1bb22b19afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665139841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2665139841
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3759836308
Short name T985
Test name
Test status
Simulation time 19145261762 ps
CPU time 42.67 seconds
Started Apr 02 02:25:55 PM PDT 24
Finished Apr 02 02:26:38 PM PDT 24
Peak memory 200416 kb
Host smart-5bd2a04b-2515-487e-a6d3-3824c3a1ede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759836308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3759836308
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2448434014
Short name T236
Test name
Test status
Simulation time 17462609674 ps
CPU time 38.44 seconds
Started Apr 02 02:25:54 PM PDT 24
Finished Apr 02 02:26:32 PM PDT 24
Peak memory 200476 kb
Host smart-f0ceb4e1-6618-4d73-b133-e4f85f1d2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448434014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2448434014
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1644238193
Short name T203
Test name
Test status
Simulation time 76751960121 ps
CPU time 33.36 seconds
Started Apr 02 02:25:53 PM PDT 24
Finished Apr 02 02:26:26 PM PDT 24
Peak memory 200496 kb
Host smart-8d5cd9d0-3be3-42d5-b519-e3a73d68b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644238193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1644238193
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.493061886
Short name T1162
Test name
Test status
Simulation time 16540594860 ps
CPU time 31.84 seconds
Started Apr 02 02:25:54 PM PDT 24
Finished Apr 02 02:26:26 PM PDT 24
Peak memory 200472 kb
Host smart-11287c78-747c-4002-802a-4838a1e1f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493061886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.493061886
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4199367453
Short name T1115
Test name
Test status
Simulation time 138237291172 ps
CPU time 176.78 seconds
Started Apr 02 02:25:54 PM PDT 24
Finished Apr 02 02:28:50 PM PDT 24
Peak memory 200488 kb
Host smart-3ad12cf7-f95e-4b06-a073-b8fe2d83fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199367453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4199367453
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3055069114
Short name T209
Test name
Test status
Simulation time 72115693908 ps
CPU time 258.08 seconds
Started Apr 02 02:25:58 PM PDT 24
Finished Apr 02 02:30:17 PM PDT 24
Peak memory 200472 kb
Host smart-dac349e2-514a-4830-beec-974d6e8e4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055069114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3055069114
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1177333188
Short name T778
Test name
Test status
Simulation time 40812692 ps
CPU time 0.54 seconds
Started Apr 02 02:17:04 PM PDT 24
Finished Apr 02 02:17:04 PM PDT 24
Peak memory 195808 kb
Host smart-50d70d64-3833-46f0-8227-a62dfbf1f3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177333188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1177333188
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2777301807
Short name T793
Test name
Test status
Simulation time 19733153076 ps
CPU time 11.84 seconds
Started Apr 02 02:16:56 PM PDT 24
Finished Apr 02 02:17:08 PM PDT 24
Peak memory 200308 kb
Host smart-83a61c23-7a54-449e-843a-40d6b9be4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777301807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2777301807
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.29256573
Short name T1099
Test name
Test status
Simulation time 153611453142 ps
CPU time 70.2 seconds
Started Apr 02 02:17:03 PM PDT 24
Finished Apr 02 02:18:13 PM PDT 24
Peak memory 200500 kb
Host smart-9dc8a585-da77-4fe3-97b9-7276aad5f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29256573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.29256573
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.680806341
Short name T600
Test name
Test status
Simulation time 51074111499 ps
CPU time 37.33 seconds
Started Apr 02 02:16:59 PM PDT 24
Finished Apr 02 02:17:36 PM PDT 24
Peak memory 200472 kb
Host smart-b20361c5-0536-49e6-89b7-96b1208156ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680806341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.680806341
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.373372505
Short name T22
Test name
Test status
Simulation time 40917687057 ps
CPU time 42.55 seconds
Started Apr 02 02:17:00 PM PDT 24
Finished Apr 02 02:17:42 PM PDT 24
Peak memory 200436 kb
Host smart-90d4a44d-69f8-45bc-ab57-dc3c73d0049f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373372505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.373372505
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2811738915
Short name T631
Test name
Test status
Simulation time 63064118303 ps
CPU time 64.73 seconds
Started Apr 02 02:17:04 PM PDT 24
Finished Apr 02 02:18:09 PM PDT 24
Peak memory 200460 kb
Host smart-616ec517-c325-4d4d-adae-796ce7997864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811738915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2811738915
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2386357783
Short name T618
Test name
Test status
Simulation time 9741849267 ps
CPU time 5.89 seconds
Started Apr 02 02:17:03 PM PDT 24
Finished Apr 02 02:17:09 PM PDT 24
Peak memory 200152 kb
Host smart-5c0949b7-0c47-4fdd-b7be-29349a9f4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386357783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2386357783
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.49483396
Short name T1143
Test name
Test status
Simulation time 145786972687 ps
CPU time 64.77 seconds
Started Apr 02 02:17:02 PM PDT 24
Finished Apr 02 02:18:07 PM PDT 24
Peak memory 200084 kb
Host smart-1dea4d04-5851-45dd-abb1-8227174be41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49483396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.49483396
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3193774676
Short name T300
Test name
Test status
Simulation time 10092877390 ps
CPU time 635.11 seconds
Started Apr 02 02:17:04 PM PDT 24
Finished Apr 02 02:27:39 PM PDT 24
Peak memory 200420 kb
Host smart-5167a7a2-25db-4cbd-bfcf-82324b66b5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193774676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3193774676
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2865942617
Short name T367
Test name
Test status
Simulation time 1400984476 ps
CPU time 2.05 seconds
Started Apr 02 02:17:00 PM PDT 24
Finished Apr 02 02:17:03 PM PDT 24
Peak memory 197272 kb
Host smart-a5eb4aef-a1ae-4011-a537-ba779de5c04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865942617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2865942617
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.104511336
Short name T185
Test name
Test status
Simulation time 116107839249 ps
CPU time 45.23 seconds
Started Apr 02 02:17:01 PM PDT 24
Finished Apr 02 02:17:46 PM PDT 24
Peak memory 200520 kb
Host smart-2ad75766-7bdc-49db-b26f-0584ce9293ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104511336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.104511336
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3950437857
Short name T556
Test name
Test status
Simulation time 1446892622 ps
CPU time 1.22 seconds
Started Apr 02 02:17:01 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 195892 kb
Host smart-2cb282dd-800b-4517-9d01-6503fdb7541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950437857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3950437857
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4105556679
Short name T466
Test name
Test status
Simulation time 265273967 ps
CPU time 1.28 seconds
Started Apr 02 02:16:56 PM PDT 24
Finished Apr 02 02:16:57 PM PDT 24
Peak memory 198820 kb
Host smart-ce68db4c-4c04-4a7e-b216-e4600f2b993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105556679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4105556679
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.4236324234
Short name T1111
Test name
Test status
Simulation time 192644433784 ps
CPU time 780.39 seconds
Started Apr 02 02:17:03 PM PDT 24
Finished Apr 02 02:30:04 PM PDT 24
Peak memory 200484 kb
Host smart-1f010566-882e-402b-bf1e-879f9b7489ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236324234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4236324234
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1278063047
Short name T664
Test name
Test status
Simulation time 922777855 ps
CPU time 1.8 seconds
Started Apr 02 02:17:00 PM PDT 24
Finished Apr 02 02:17:02 PM PDT 24
Peak memory 199260 kb
Host smart-fb1d64cb-4c85-45aa-a381-6eea066033d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278063047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1278063047
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.279512291
Short name T1141
Test name
Test status
Simulation time 42843884613 ps
CPU time 75.11 seconds
Started Apr 02 02:16:55 PM PDT 24
Finished Apr 02 02:18:10 PM PDT 24
Peak memory 200376 kb
Host smart-138d061e-492a-4dac-b1b5-f233eb921d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279512291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.279512291
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.624839308
Short name T212
Test name
Test status
Simulation time 40266318241 ps
CPU time 14.61 seconds
Started Apr 02 02:25:57 PM PDT 24
Finished Apr 02 02:26:12 PM PDT 24
Peak memory 200328 kb
Host smart-4be2187b-c0c4-403e-a743-e0a683e80712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624839308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.624839308
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1442359973
Short name T195
Test name
Test status
Simulation time 37542588198 ps
CPU time 18.44 seconds
Started Apr 02 02:26:01 PM PDT 24
Finished Apr 02 02:26:19 PM PDT 24
Peak memory 200408 kb
Host smart-045bb084-beb0-477d-842c-f4bef6489312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442359973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1442359973
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1661200566
Short name T429
Test name
Test status
Simulation time 26402733349 ps
CPU time 49.38 seconds
Started Apr 02 02:26:04 PM PDT 24
Finished Apr 02 02:26:53 PM PDT 24
Peak memory 200440 kb
Host smart-0c913785-7e2a-4f5f-8bbb-c2e97dc75393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661200566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1661200566
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.505183706
Short name T227
Test name
Test status
Simulation time 94105385214 ps
CPU time 71.73 seconds
Started Apr 02 02:26:00 PM PDT 24
Finished Apr 02 02:27:12 PM PDT 24
Peak memory 200456 kb
Host smart-2255f2d7-9c33-4bf1-878b-09ee20375856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505183706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.505183706
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2272353064
Short name T313
Test name
Test status
Simulation time 50518309124 ps
CPU time 101.41 seconds
Started Apr 02 02:26:05 PM PDT 24
Finished Apr 02 02:27:46 PM PDT 24
Peak memory 200412 kb
Host smart-1619d40f-4fe8-4ba5-b253-6fa1c9ac97f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272353064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2272353064
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2355493172
Short name T184
Test name
Test status
Simulation time 23237203453 ps
CPU time 37.85 seconds
Started Apr 02 02:26:07 PM PDT 24
Finished Apr 02 02:26:45 PM PDT 24
Peak memory 200268 kb
Host smart-64299532-08b4-43a5-a4d5-a87907441120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355493172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2355493172
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4257382778
Short name T38
Test name
Test status
Simulation time 13852130832 ps
CPU time 28.01 seconds
Started Apr 02 02:26:06 PM PDT 24
Finished Apr 02 02:26:34 PM PDT 24
Peak memory 200520 kb
Host smart-8237f458-4fd8-4ae9-9fd1-8a6ad703b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257382778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4257382778
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3231674165
Short name T240
Test name
Test status
Simulation time 125448087878 ps
CPU time 91.97 seconds
Started Apr 02 02:26:04 PM PDT 24
Finished Apr 02 02:27:36 PM PDT 24
Peak memory 200500 kb
Host smart-1a890458-d7bb-4830-8252-6a4bd88adedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231674165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3231674165
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.412657891
Short name T1161
Test name
Test status
Simulation time 50287799915 ps
CPU time 79.75 seconds
Started Apr 02 02:26:04 PM PDT 24
Finished Apr 02 02:27:24 PM PDT 24
Peak memory 200496 kb
Host smart-917a03ad-86e8-4a3b-b2a0-f01083df182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412657891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.412657891
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.609374299
Short name T603
Test name
Test status
Simulation time 113870159368 ps
CPU time 163.59 seconds
Started Apr 02 02:26:07 PM PDT 24
Finished Apr 02 02:28:51 PM PDT 24
Peak memory 200436 kb
Host smart-53e0ec64-40b4-4aec-8079-51960ccce4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609374299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.609374299
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3732234585
Short name T399
Test name
Test status
Simulation time 17120377 ps
CPU time 0.55 seconds
Started Apr 02 02:17:18 PM PDT 24
Finished Apr 02 02:17:19 PM PDT 24
Peak memory 195884 kb
Host smart-a34cc023-ec2f-4ff1-a6a2-dc8b5fe1efa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732234585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3732234585
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3070738372
Short name T886
Test name
Test status
Simulation time 20832249114 ps
CPU time 27.23 seconds
Started Apr 02 02:17:05 PM PDT 24
Finished Apr 02 02:17:32 PM PDT 24
Peak memory 200464 kb
Host smart-3fdcafe3-f9a3-4114-ab5f-d46c6dba8c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070738372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3070738372
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3392927017
Short name T610
Test name
Test status
Simulation time 71858889066 ps
CPU time 46.41 seconds
Started Apr 02 02:17:08 PM PDT 24
Finished Apr 02 02:17:55 PM PDT 24
Peak memory 200380 kb
Host smart-c0a8d80a-54f0-4461-9e0f-739e7a21cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392927017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3392927017
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.434538427
Short name T220
Test name
Test status
Simulation time 149692387695 ps
CPU time 154.25 seconds
Started Apr 02 02:17:07 PM PDT 24
Finished Apr 02 02:19:41 PM PDT 24
Peak memory 200500 kb
Host smart-0fcb0006-425b-45fb-ac6f-39d826c7a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434538427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.434538427
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3945035707
Short name T497
Test name
Test status
Simulation time 233927816317 ps
CPU time 475.36 seconds
Started Apr 02 02:17:10 PM PDT 24
Finished Apr 02 02:25:06 PM PDT 24
Peak memory 199724 kb
Host smart-0e22ce02-92ff-47e4-bd62-80118fa32cc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945035707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3945035707
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2439201601
Short name T976
Test name
Test status
Simulation time 107790985841 ps
CPU time 650.16 seconds
Started Apr 02 02:17:18 PM PDT 24
Finished Apr 02 02:28:08 PM PDT 24
Peak memory 200504 kb
Host smart-2ba3cd10-84ae-428b-808c-7d80a4d9899f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439201601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2439201601
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3178647265
Short name T594
Test name
Test status
Simulation time 817910263 ps
CPU time 0.81 seconds
Started Apr 02 02:17:19 PM PDT 24
Finished Apr 02 02:17:20 PM PDT 24
Peak memory 196736 kb
Host smart-36b2eafb-cdcb-4e0a-9502-016916b55471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178647265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3178647265
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3020354640
Short name T931
Test name
Test status
Simulation time 16823042119 ps
CPU time 21.82 seconds
Started Apr 02 02:17:10 PM PDT 24
Finished Apr 02 02:17:32 PM PDT 24
Peak memory 199188 kb
Host smart-00c80c80-3522-494f-91d2-a23c1e41e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020354640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3020354640
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4255598312
Short name T482
Test name
Test status
Simulation time 13062204516 ps
CPU time 410.44 seconds
Started Apr 02 02:17:18 PM PDT 24
Finished Apr 02 02:24:08 PM PDT 24
Peak memory 200480 kb
Host smart-f929f477-127a-4b76-b89c-5af013159e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255598312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4255598312
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.281443506
Short name T765
Test name
Test status
Simulation time 4670890909 ps
CPU time 10.32 seconds
Started Apr 02 02:17:07 PM PDT 24
Finished Apr 02 02:17:17 PM PDT 24
Peak memory 199288 kb
Host smart-20d52eb7-7b32-4040-a687-991de355b44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281443506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.281443506
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2158960546
Short name T181
Test name
Test status
Simulation time 53534972019 ps
CPU time 22.66 seconds
Started Apr 02 02:17:09 PM PDT 24
Finished Apr 02 02:17:32 PM PDT 24
Peak memory 200480 kb
Host smart-66030e42-555b-42cf-a1f6-3a15247810a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158960546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2158960546
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2127128597
Short name T390
Test name
Test status
Simulation time 6249767372 ps
CPU time 5.26 seconds
Started Apr 02 02:17:09 PM PDT 24
Finished Apr 02 02:17:14 PM PDT 24
Peak memory 196468 kb
Host smart-a1cf3113-dcc4-4bba-9496-0598f9478f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127128597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2127128597
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4053619892
Short name T607
Test name
Test status
Simulation time 721274677 ps
CPU time 1.71 seconds
Started Apr 02 02:17:03 PM PDT 24
Finished Apr 02 02:17:05 PM PDT 24
Peak memory 200356 kb
Host smart-e4f635cd-48c7-4cf9-8661-f5855e27e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053619892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4053619892
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.421667247
Short name T1066
Test name
Test status
Simulation time 108681087221 ps
CPU time 49.31 seconds
Started Apr 02 02:17:18 PM PDT 24
Finished Apr 02 02:18:07 PM PDT 24
Peak memory 200704 kb
Host smart-bc3cc459-52de-45d7-97fc-30cf69b3f10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421667247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.421667247
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3171837576
Short name T1107
Test name
Test status
Simulation time 144628303456 ps
CPU time 1121.18 seconds
Started Apr 02 02:17:19 PM PDT 24
Finished Apr 02 02:36:01 PM PDT 24
Peak memory 227508 kb
Host smart-11ac84cd-10f8-4070-ba44-3e5dcbfbc152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171837576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3171837576
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2323301502
Short name T659
Test name
Test status
Simulation time 207426990 ps
CPU time 1.35 seconds
Started Apr 02 02:17:17 PM PDT 24
Finished Apr 02 02:17:18 PM PDT 24
Peak memory 200352 kb
Host smart-d0cb65eb-865c-44e2-80ab-d61441a986b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323301502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2323301502
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1376687066
Short name T536
Test name
Test status
Simulation time 98935216234 ps
CPU time 287.5 seconds
Started Apr 02 02:17:03 PM PDT 24
Finished Apr 02 02:21:51 PM PDT 24
Peak memory 200496 kb
Host smart-c654eb9c-c382-4036-9434-e9d141e8542c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376687066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1376687066
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2304194165
Short name T49
Test name
Test status
Simulation time 83955256387 ps
CPU time 27.72 seconds
Started Apr 02 02:26:07 PM PDT 24
Finished Apr 02 02:26:35 PM PDT 24
Peak memory 200460 kb
Host smart-98cfc287-a730-4d27-984e-b2b8c2acf3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304194165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2304194165
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3349114372
Short name T841
Test name
Test status
Simulation time 116780154920 ps
CPU time 51.63 seconds
Started Apr 02 02:26:14 PM PDT 24
Finished Apr 02 02:27:05 PM PDT 24
Peak memory 200444 kb
Host smart-4ac73b9b-035b-41c8-b13b-1ce00662c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349114372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3349114372
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2689559218
Short name T347
Test name
Test status
Simulation time 29512076719 ps
CPU time 48.19 seconds
Started Apr 02 02:26:13 PM PDT 24
Finished Apr 02 02:27:01 PM PDT 24
Peak memory 200476 kb
Host smart-e3c2cd6f-93ba-446c-adf6-ec5785802992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689559218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2689559218
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3424315588
Short name T821
Test name
Test status
Simulation time 109447835185 ps
CPU time 81.1 seconds
Started Apr 02 02:26:15 PM PDT 24
Finished Apr 02 02:27:37 PM PDT 24
Peak memory 200512 kb
Host smart-af423caa-5c83-4505-9f06-8e7a7b25b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424315588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3424315588
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3764299472
Short name T196
Test name
Test status
Simulation time 20137386661 ps
CPU time 30.32 seconds
Started Apr 02 02:26:12 PM PDT 24
Finished Apr 02 02:26:43 PM PDT 24
Peak memory 200424 kb
Host smart-7c68df88-16b8-4a0c-8383-8ba3880f964b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764299472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3764299472
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.585547708
Short name T200
Test name
Test status
Simulation time 74262295308 ps
CPU time 131.39 seconds
Started Apr 02 02:26:17 PM PDT 24
Finished Apr 02 02:28:28 PM PDT 24
Peak memory 200456 kb
Host smart-d5a4e3ca-4ffa-475d-8334-08c0758509e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585547708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.585547708
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2164676092
Short name T461
Test name
Test status
Simulation time 22466342836 ps
CPU time 36.37 seconds
Started Apr 02 02:26:17 PM PDT 24
Finished Apr 02 02:26:53 PM PDT 24
Peak memory 200508 kb
Host smart-97d5f239-0547-4d55-a767-ee27ae468f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164676092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2164676092
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4009694813
Short name T204
Test name
Test status
Simulation time 20562370432 ps
CPU time 15.91 seconds
Started Apr 02 02:26:16 PM PDT 24
Finished Apr 02 02:26:32 PM PDT 24
Peak memory 200124 kb
Host smart-8159003d-fd94-492c-8bd8-922f87a9a012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009694813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4009694813
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2182622762
Short name T488
Test name
Test status
Simulation time 35358008 ps
CPU time 0.54 seconds
Started Apr 02 02:17:31 PM PDT 24
Finished Apr 02 02:17:31 PM PDT 24
Peak memory 195888 kb
Host smart-a2662ba3-80b9-4a24-b29f-d025472b9c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182622762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2182622762
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2354661483
Short name T1123
Test name
Test status
Simulation time 90537452151 ps
CPU time 147.19 seconds
Started Apr 02 02:17:20 PM PDT 24
Finished Apr 02 02:19:48 PM PDT 24
Peak memory 200436 kb
Host smart-cf75393b-0f66-420a-b7ef-990eb8745421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354661483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2354661483
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.133864346
Short name T148
Test name
Test status
Simulation time 32357634131 ps
CPU time 41.89 seconds
Started Apr 02 02:17:20 PM PDT 24
Finished Apr 02 02:18:02 PM PDT 24
Peak memory 200284 kb
Host smart-b4336f03-8d38-4ba9-8620-bd26e3192070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133864346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.133864346
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.790140558
Short name T218
Test name
Test status
Simulation time 77317996352 ps
CPU time 117.12 seconds
Started Apr 02 02:17:21 PM PDT 24
Finished Apr 02 02:19:18 PM PDT 24
Peak memory 200384 kb
Host smart-93fad668-5925-463a-8ac0-5d690e6cdf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790140558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.790140558
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1823819674
Short name T1127
Test name
Test status
Simulation time 12696662325 ps
CPU time 17.17 seconds
Started Apr 02 02:17:23 PM PDT 24
Finished Apr 02 02:17:40 PM PDT 24
Peak memory 200380 kb
Host smart-c93aaa95-acf5-417e-af5d-4783ea6469a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823819674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1823819674
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.49593851
Short name T640
Test name
Test status
Simulation time 95577580566 ps
CPU time 400.9 seconds
Started Apr 02 02:17:29 PM PDT 24
Finished Apr 02 02:24:11 PM PDT 24
Peak memory 200484 kb
Host smart-ed361c23-4fcc-4fbd-8aca-a6a5351cc70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49593851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.49593851
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2179834858
Short name T1082
Test name
Test status
Simulation time 4077356328 ps
CPU time 2.08 seconds
Started Apr 02 02:17:25 PM PDT 24
Finished Apr 02 02:17:27 PM PDT 24
Peak memory 199428 kb
Host smart-554d2312-fef3-40c5-81e1-2df5a7d3a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179834858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2179834858
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.2441506675
Short name T44
Test name
Test status
Simulation time 148682019336 ps
CPU time 128.05 seconds
Started Apr 02 02:17:23 PM PDT 24
Finished Apr 02 02:19:32 PM PDT 24
Peak memory 199268 kb
Host smart-81d92689-07dd-4177-b36a-8c7bc02d3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441506675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2441506675
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1688213042
Short name T79
Test name
Test status
Simulation time 20765214360 ps
CPU time 957.21 seconds
Started Apr 02 02:17:28 PM PDT 24
Finished Apr 02 02:33:25 PM PDT 24
Peak memory 200352 kb
Host smart-a0770199-8899-4ddb-9078-17b61ff3ee78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688213042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1688213042
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1847379748
Short name T812
Test name
Test status
Simulation time 5999854927 ps
CPU time 25.45 seconds
Started Apr 02 02:17:23 PM PDT 24
Finished Apr 02 02:17:48 PM PDT 24
Peak memory 198552 kb
Host smart-ccb6656a-a36c-48c6-ab30-27c057eafa01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847379748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1847379748
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.309797454
Short name T182
Test name
Test status
Simulation time 148634321493 ps
CPU time 72.27 seconds
Started Apr 02 02:17:24 PM PDT 24
Finished Apr 02 02:18:36 PM PDT 24
Peak memory 200436 kb
Host smart-328d3cf1-33d4-4104-92b9-7984387d450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309797454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.309797454
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3563375932
Short name T1157
Test name
Test status
Simulation time 53008846951 ps
CPU time 23.43 seconds
Started Apr 02 02:17:26 PM PDT 24
Finished Apr 02 02:17:49 PM PDT 24
Peak memory 196200 kb
Host smart-30301157-0352-470c-8476-f3167c7b2721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563375932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3563375932
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1629942118
Short name T781
Test name
Test status
Simulation time 490926357 ps
CPU time 1.21 seconds
Started Apr 02 02:17:18 PM PDT 24
Finished Apr 02 02:17:20 PM PDT 24
Peak memory 199324 kb
Host smart-2247301b-853f-4e31-b7b0-2322666765a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629942118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1629942118
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1167622399
Short name T695
Test name
Test status
Simulation time 130152469779 ps
CPU time 370.94 seconds
Started Apr 02 02:17:31 PM PDT 24
Finished Apr 02 02:23:42 PM PDT 24
Peak memory 200500 kb
Host smart-1553deca-2469-4629-ace3-dbf4a003a72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167622399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1167622399
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3885648204
Short name T578
Test name
Test status
Simulation time 43213675085 ps
CPU time 76.12 seconds
Started Apr 02 02:17:30 PM PDT 24
Finished Apr 02 02:18:47 PM PDT 24
Peak memory 215848 kb
Host smart-45e1e497-2601-4a1e-a86d-ab24353a2760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885648204 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3885648204
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.48531351
Short name T1071
Test name
Test status
Simulation time 6901589806 ps
CPU time 10.31 seconds
Started Apr 02 02:17:23 PM PDT 24
Finished Apr 02 02:17:34 PM PDT 24
Peak memory 199776 kb
Host smart-29e0b840-ec44-40e3-ab07-ed27d10b182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48531351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.48531351
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2785229759
Short name T283
Test name
Test status
Simulation time 59348601125 ps
CPU time 44.3 seconds
Started Apr 02 02:17:17 PM PDT 24
Finished Apr 02 02:18:01 PM PDT 24
Peak memory 200520 kb
Host smart-8362b101-e593-4bad-9fcc-9c3e9f0c12a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785229759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2785229759
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.725782780
Short name T777
Test name
Test status
Simulation time 8251472621 ps
CPU time 8.38 seconds
Started Apr 02 02:26:16 PM PDT 24
Finished Apr 02 02:26:25 PM PDT 24
Peak memory 200480 kb
Host smart-0eeb7217-41e4-4ae0-a7be-d0db31672ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725782780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.725782780
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3831888532
Short name T622
Test name
Test status
Simulation time 137749384492 ps
CPU time 13.04 seconds
Started Apr 02 02:26:21 PM PDT 24
Finished Apr 02 02:26:34 PM PDT 24
Peak memory 200264 kb
Host smart-9ae53099-eccf-4caa-beb3-ab2afb225110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831888532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3831888532
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1377399797
Short name T1097
Test name
Test status
Simulation time 48331315603 ps
CPU time 72.03 seconds
Started Apr 02 02:26:20 PM PDT 24
Finished Apr 02 02:27:32 PM PDT 24
Peak memory 200472 kb
Host smart-f4528492-7cdd-49ba-b269-e085b1119103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377399797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1377399797
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3973152685
Short name T755
Test name
Test status
Simulation time 30752972121 ps
CPU time 112.12 seconds
Started Apr 02 02:26:19 PM PDT 24
Finished Apr 02 02:28:12 PM PDT 24
Peak memory 200492 kb
Host smart-34163cd3-a985-460c-88b1-460a1a27c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973152685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3973152685
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3868478843
Short name T14
Test name
Test status
Simulation time 51860014319 ps
CPU time 23.83 seconds
Started Apr 02 02:26:20 PM PDT 24
Finished Apr 02 02:26:44 PM PDT 24
Peak memory 200440 kb
Host smart-4b2f0708-bbc4-4ba2-b1ef-209c942ac0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868478843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3868478843
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4091551464
Short name T870
Test name
Test status
Simulation time 79043571660 ps
CPU time 35.97 seconds
Started Apr 02 02:26:18 PM PDT 24
Finished Apr 02 02:26:54 PM PDT 24
Peak memory 200436 kb
Host smart-e8e4c376-6455-431a-b1f3-f13a1bdf2b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091551464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4091551464
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.450714497
Short name T1150
Test name
Test status
Simulation time 78437855288 ps
CPU time 121.23 seconds
Started Apr 02 02:26:21 PM PDT 24
Finished Apr 02 02:28:22 PM PDT 24
Peak memory 200512 kb
Host smart-413b8984-8739-4877-ad04-4dcf21dd960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450714497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.450714497
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.258183564
Short name T547
Test name
Test status
Simulation time 298445005429 ps
CPU time 29.33 seconds
Started Apr 02 02:26:21 PM PDT 24
Finished Apr 02 02:26:50 PM PDT 24
Peak memory 200496 kb
Host smart-b3733715-cdf3-407a-9afa-cfeda7926345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258183564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.258183564
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1816281838
Short name T936
Test name
Test status
Simulation time 18711921993 ps
CPU time 8.67 seconds
Started Apr 02 02:26:21 PM PDT 24
Finished Apr 02 02:26:29 PM PDT 24
Peak memory 200444 kb
Host smart-9d923b89-2547-4b8a-ad37-94dec22def2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816281838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1816281838
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1621427
Short name T621
Test name
Test status
Simulation time 13829360 ps
CPU time 0.54 seconds
Started Apr 02 02:17:40 PM PDT 24
Finished Apr 02 02:17:41 PM PDT 24
Peak memory 195844 kb
Host smart-b6d572f7-459a-4bc5-973e-1c1fdbdccf95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1621427
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3256874497
Short name T1154
Test name
Test status
Simulation time 40925424170 ps
CPU time 16.58 seconds
Started Apr 02 02:17:36 PM PDT 24
Finished Apr 02 02:17:53 PM PDT 24
Peak memory 200496 kb
Host smart-2d2ce09f-ae04-445d-b792-c2af443864b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256874497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3256874497
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2561350787
Short name T595
Test name
Test status
Simulation time 29508956030 ps
CPU time 46.12 seconds
Started Apr 02 02:17:33 PM PDT 24
Finished Apr 02 02:18:19 PM PDT 24
Peak memory 200488 kb
Host smart-7c764540-b3b2-40a5-9c16-827b6dc17e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561350787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2561350787
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2488230239
Short name T1010
Test name
Test status
Simulation time 22989859156 ps
CPU time 40.67 seconds
Started Apr 02 02:17:35 PM PDT 24
Finished Apr 02 02:18:16 PM PDT 24
Peak memory 200212 kb
Host smart-3b634c40-76b4-4edb-9e9f-834fda4410aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488230239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2488230239
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2035843764
Short name T527
Test name
Test status
Simulation time 35035027177 ps
CPU time 8.51 seconds
Started Apr 02 02:17:36 PM PDT 24
Finished Apr 02 02:17:45 PM PDT 24
Peak memory 200432 kb
Host smart-a20b5c81-47ce-4e8d-81e9-3bb030370275
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035843764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2035843764
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_loopback.2349350929
Short name T356
Test name
Test status
Simulation time 11361645317 ps
CPU time 24.01 seconds
Started Apr 02 02:17:39 PM PDT 24
Finished Apr 02 02:18:03 PM PDT 24
Peak memory 200508 kb
Host smart-51fea1b7-d7ef-4e28-b159-4adebfce66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349350929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2349350929
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1972093172
Short name T972
Test name
Test status
Simulation time 16399588178 ps
CPU time 27.41 seconds
Started Apr 02 02:17:34 PM PDT 24
Finished Apr 02 02:18:01 PM PDT 24
Peak memory 199324 kb
Host smart-50fe1f18-b5e0-4e94-af7e-a33afae442c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972093172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1972093172
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2428117864
Short name T932
Test name
Test status
Simulation time 12496424162 ps
CPU time 660.1 seconds
Started Apr 02 02:17:36 PM PDT 24
Finished Apr 02 02:28:37 PM PDT 24
Peak memory 200492 kb
Host smart-4edb40ac-2056-423c-b194-931261463217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428117864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2428117864
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.706884965
Short name T417
Test name
Test status
Simulation time 2646026162 ps
CPU time 16.89 seconds
Started Apr 02 02:17:34 PM PDT 24
Finished Apr 02 02:17:51 PM PDT 24
Peak memory 198668 kb
Host smart-89f62c31-d5c8-46d3-9483-de960b9a7ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706884965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.706884965
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.654648569
Short name T734
Test name
Test status
Simulation time 66683837725 ps
CPU time 57.53 seconds
Started Apr 02 02:17:39 PM PDT 24
Finished Apr 02 02:18:37 PM PDT 24
Peak memory 200496 kb
Host smart-bebdcd2b-4c19-458a-9080-9b59e56748ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654648569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.654648569
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.4092409483
Short name T470
Test name
Test status
Simulation time 2818290179 ps
CPU time 4.81 seconds
Started Apr 02 02:17:40 PM PDT 24
Finished Apr 02 02:17:45 PM PDT 24
Peak memory 196500 kb
Host smart-33f176f5-af32-417e-aa49-fa345914568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092409483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.4092409483
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3682179538
Short name T534
Test name
Test status
Simulation time 6326030944 ps
CPU time 5.63 seconds
Started Apr 02 02:17:31 PM PDT 24
Finished Apr 02 02:17:37 PM PDT 24
Peak memory 200380 kb
Host smart-d56bd58b-0e82-4885-80b8-b71f845f2310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682179538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3682179538
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3224751957
Short name T627
Test name
Test status
Simulation time 237302688376 ps
CPU time 558.2 seconds
Started Apr 02 02:17:39 PM PDT 24
Finished Apr 02 02:26:57 PM PDT 24
Peak memory 200460 kb
Host smart-1463b13e-ced4-4884-94ea-7cb43fbcc6dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224751957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3224751957
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1546676425
Short name T34
Test name
Test status
Simulation time 29168998913 ps
CPU time 676.26 seconds
Started Apr 02 02:17:38 PM PDT 24
Finished Apr 02 02:28:55 PM PDT 24
Peak memory 215708 kb
Host smart-b09de384-813a-44f7-ae77-af4029411b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546676425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1546676425
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.628017822
Short name T310
Test name
Test status
Simulation time 1104889966 ps
CPU time 3.57 seconds
Started Apr 02 02:17:38 PM PDT 24
Finished Apr 02 02:17:42 PM PDT 24
Peak memory 199132 kb
Host smart-14eaa13c-5915-4c71-a03a-2cd96813da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628017822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.628017822
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.347726295
Short name T648
Test name
Test status
Simulation time 138495879594 ps
CPU time 22.85 seconds
Started Apr 02 02:17:32 PM PDT 24
Finished Apr 02 02:17:55 PM PDT 24
Peak memory 200180 kb
Host smart-bd87d66a-9571-446e-9101-f3a65981fa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347726295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.347726295
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3527368203
Short name T650
Test name
Test status
Simulation time 13959122404 ps
CPU time 11.74 seconds
Started Apr 02 02:26:20 PM PDT 24
Finished Apr 02 02:26:32 PM PDT 24
Peak memory 200452 kb
Host smart-73092683-c34e-4ef2-b754-e71c13ee338b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527368203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3527368203
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3648579731
Short name T714
Test name
Test status
Simulation time 38048327708 ps
CPU time 58.8 seconds
Started Apr 02 02:26:23 PM PDT 24
Finished Apr 02 02:27:22 PM PDT 24
Peak memory 200460 kb
Host smart-f9c80a09-8844-4ebb-9996-8bc4ad513409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648579731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3648579731
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1139759040
Short name T1112
Test name
Test status
Simulation time 23583051437 ps
CPU time 33.53 seconds
Started Apr 02 02:26:29 PM PDT 24
Finished Apr 02 02:27:03 PM PDT 24
Peak memory 200436 kb
Host smart-6e668e44-d3f4-4643-91b0-a5d6ec049f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139759040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1139759040
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3141629321
Short name T324
Test name
Test status
Simulation time 34096670160 ps
CPU time 15.9 seconds
Started Apr 02 02:26:33 PM PDT 24
Finished Apr 02 02:26:50 PM PDT 24
Peak memory 200464 kb
Host smart-dda0ae6b-a585-4895-b777-197db1a0a85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141629321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3141629321
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2290657220
Short name T814
Test name
Test status
Simulation time 185344143879 ps
CPU time 122.52 seconds
Started Apr 02 02:26:33 PM PDT 24
Finished Apr 02 02:28:35 PM PDT 24
Peak memory 200464 kb
Host smart-d820ef12-0d70-43ba-80cc-a0770399a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290657220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2290657220
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1786051645
Short name T384
Test name
Test status
Simulation time 17775223910 ps
CPU time 12.79 seconds
Started Apr 02 02:26:31 PM PDT 24
Finished Apr 02 02:26:44 PM PDT 24
Peak memory 200296 kb
Host smart-021f65d5-07d1-4345-be29-369265e9b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786051645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1786051645
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.364236234
Short name T694
Test name
Test status
Simulation time 19668078520 ps
CPU time 24.13 seconds
Started Apr 02 02:26:32 PM PDT 24
Finished Apr 02 02:26:56 PM PDT 24
Peak memory 200444 kb
Host smart-befaad67-a8fa-4ac3-bd37-22345ae6209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364236234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.364236234
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1749989790
Short name T975
Test name
Test status
Simulation time 22114909143 ps
CPU time 35.01 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:27:10 PM PDT 24
Peak memory 200472 kb
Host smart-abcc92c1-7fd5-473d-9c23-bfa6a9e307dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749989790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1749989790
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4020759395
Short name T766
Test name
Test status
Simulation time 56595872347 ps
CPU time 14.93 seconds
Started Apr 02 02:26:33 PM PDT 24
Finished Apr 02 02:26:49 PM PDT 24
Peak memory 200496 kb
Host smart-9d56a910-4529-491a-a292-d5e8f217eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020759395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4020759395
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.856157708
Short name T744
Test name
Test status
Simulation time 12498070 ps
CPU time 0.57 seconds
Started Apr 02 02:17:57 PM PDT 24
Finished Apr 02 02:17:58 PM PDT 24
Peak memory 195908 kb
Host smart-3d5f505b-b797-47e5-a016-114a5476099e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856157708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.856157708
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.296229206
Short name T539
Test name
Test status
Simulation time 190854618976 ps
CPU time 116.99 seconds
Started Apr 02 02:17:41 PM PDT 24
Finished Apr 02 02:19:38 PM PDT 24
Peak memory 200476 kb
Host smart-126766ea-3ed8-438c-b9c7-e1af4b45cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296229206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.296229206
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2970710891
Short name T450
Test name
Test status
Simulation time 68200340803 ps
CPU time 27.5 seconds
Started Apr 02 02:17:40 PM PDT 24
Finished Apr 02 02:18:08 PM PDT 24
Peak memory 198412 kb
Host smart-0d7f995e-3fba-4109-af25-3871922030ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970710891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2970710891
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3579607701
Short name T718
Test name
Test status
Simulation time 169281829885 ps
CPU time 50.31 seconds
Started Apr 02 02:17:40 PM PDT 24
Finished Apr 02 02:18:31 PM PDT 24
Peak memory 200348 kb
Host smart-1520580d-1dcd-4cd9-bba3-8483d8bb5f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579607701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3579607701
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2248621294
Short name T890
Test name
Test status
Simulation time 41104409359 ps
CPU time 69.06 seconds
Started Apr 02 02:17:44 PM PDT 24
Finished Apr 02 02:18:54 PM PDT 24
Peak memory 200492 kb
Host smart-f0193fcf-737e-4ebb-abf9-aa93a5a270a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248621294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2248621294
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1507886345
Short name T916
Test name
Test status
Simulation time 47243391768 ps
CPU time 287.09 seconds
Started Apr 02 02:17:52 PM PDT 24
Finished Apr 02 02:22:40 PM PDT 24
Peak memory 200468 kb
Host smart-0e473537-62db-48aa-8586-76b019c0cfc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507886345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1507886345
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1446991211
Short name T591
Test name
Test status
Simulation time 11445387239 ps
CPU time 10.84 seconds
Started Apr 02 02:17:47 PM PDT 24
Finished Apr 02 02:17:59 PM PDT 24
Peak memory 200480 kb
Host smart-b1bc26e1-cc2d-4c5c-9511-e97a6e73a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446991211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1446991211
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1372495957
Short name T584
Test name
Test status
Simulation time 146409065148 ps
CPU time 160.64 seconds
Started Apr 02 02:17:48 PM PDT 24
Finished Apr 02 02:20:28 PM PDT 24
Peak memory 199892 kb
Host smart-fd06738c-06f1-4895-80de-102c24714a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372495957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1372495957
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2664261374
Short name T291
Test name
Test status
Simulation time 14952407654 ps
CPU time 68.8 seconds
Started Apr 02 02:17:50 PM PDT 24
Finished Apr 02 02:18:59 PM PDT 24
Peak memory 200464 kb
Host smart-deb2661d-66c4-4082-bebd-310e36649d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664261374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2664261374
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.3366928154
Short name T571
Test name
Test status
Simulation time 3369892336 ps
CPU time 20.09 seconds
Started Apr 02 02:17:44 PM PDT 24
Finished Apr 02 02:18:04 PM PDT 24
Peak memory 199436 kb
Host smart-8ca3b4fc-691b-4191-8abb-15752fd47061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366928154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3366928154
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.783921593
Short name T1095
Test name
Test status
Simulation time 48456317091 ps
CPU time 42.62 seconds
Started Apr 02 02:17:47 PM PDT 24
Finished Apr 02 02:18:30 PM PDT 24
Peak memory 200264 kb
Host smart-05e9082e-6b7e-4303-8520-cc03d99b37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783921593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.783921593
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2551731052
Short name T623
Test name
Test status
Simulation time 4206975491 ps
CPU time 2.18 seconds
Started Apr 02 02:17:48 PM PDT 24
Finished Apr 02 02:17:50 PM PDT 24
Peak memory 196544 kb
Host smart-2fd6f105-8f1e-44fd-9840-a917f21a2bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551731052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2551731052
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1327723556
Short name T644
Test name
Test status
Simulation time 106067924 ps
CPU time 0.86 seconds
Started Apr 02 02:17:41 PM PDT 24
Finished Apr 02 02:17:42 PM PDT 24
Peak memory 197400 kb
Host smart-f06a12d3-cc3f-49bf-9184-9e53d8d7b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327723556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1327723556
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.533904328
Short name T175
Test name
Test status
Simulation time 246950076454 ps
CPU time 304.16 seconds
Started Apr 02 02:17:51 PM PDT 24
Finished Apr 02 02:22:55 PM PDT 24
Peak memory 208848 kb
Host smart-d5c66450-4b0e-4e17-bc79-77efcda9dd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533904328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.533904328
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2200502936
Short name T944
Test name
Test status
Simulation time 15546780325 ps
CPU time 164.33 seconds
Started Apr 02 02:17:52 PM PDT 24
Finished Apr 02 02:20:37 PM PDT 24
Peak memory 210068 kb
Host smart-9a06e56c-1b33-4929-a0df-cf0dc7e9df05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200502936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2200502936
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.347071768
Short name T1152
Test name
Test status
Simulation time 1900067961 ps
CPU time 2.17 seconds
Started Apr 02 02:17:47 PM PDT 24
Finished Apr 02 02:17:50 PM PDT 24
Peak memory 199304 kb
Host smart-8f7efa54-9ff5-4283-b9e1-d244bfb6ceb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347071768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.347071768
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.167266215
Short name T422
Test name
Test status
Simulation time 84933846568 ps
CPU time 61.49 seconds
Started Apr 02 02:17:41 PM PDT 24
Finished Apr 02 02:18:43 PM PDT 24
Peak memory 200396 kb
Host smart-cb3ee0e9-6e9d-43df-84ae-07facf145e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167266215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.167266215
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1860315721
Short name T453
Test name
Test status
Simulation time 60411602995 ps
CPU time 195.4 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:29:50 PM PDT 24
Peak memory 200412 kb
Host smart-3b017af9-2f61-4787-ba9e-05c015d5ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860315721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1860315721
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2903098535
Short name T918
Test name
Test status
Simulation time 154810797102 ps
CPU time 325.03 seconds
Started Apr 02 02:26:40 PM PDT 24
Finished Apr 02 02:32:05 PM PDT 24
Peak memory 200456 kb
Host smart-18dc232f-25c0-43bb-9a91-3f5f2d8d2723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903098535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2903098535
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1452681709
Short name T301
Test name
Test status
Simulation time 26800668723 ps
CPU time 26.83 seconds
Started Apr 02 02:26:35 PM PDT 24
Finished Apr 02 02:27:02 PM PDT 24
Peak memory 200432 kb
Host smart-9489f051-d31c-45f7-b4d2-9f27424bef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452681709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1452681709
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2601760120
Short name T543
Test name
Test status
Simulation time 138442712705 ps
CPU time 55.56 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:27:30 PM PDT 24
Peak memory 200360 kb
Host smart-9f32539c-f872-4f76-8c50-6b901fe89c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601760120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2601760120
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.347093298
Short name T465
Test name
Test status
Simulation time 154446388966 ps
CPU time 120.52 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:28:34 PM PDT 24
Peak memory 200524 kb
Host smart-b610c30f-2cd3-4f27-ab10-bac1f2988990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347093298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.347093298
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4210492780
Short name T908
Test name
Test status
Simulation time 25966652570 ps
CPU time 42.43 seconds
Started Apr 02 02:26:36 PM PDT 24
Finished Apr 02 02:27:19 PM PDT 24
Peak memory 200408 kb
Host smart-52eb1c1d-c23a-469a-9d17-7ec88d48e080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210492780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4210492780
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3823609441
Short name T219
Test name
Test status
Simulation time 141623737107 ps
CPU time 73.96 seconds
Started Apr 02 02:26:34 PM PDT 24
Finished Apr 02 02:27:49 PM PDT 24
Peak memory 200436 kb
Host smart-7c387632-cd36-476a-9708-adf5fd228bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823609441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3823609441
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.425716308
Short name T835
Test name
Test status
Simulation time 22238857 ps
CPU time 0.52 seconds
Started Apr 02 02:12:12 PM PDT 24
Finished Apr 02 02:12:12 PM PDT 24
Peak memory 195868 kb
Host smart-d3896f2f-f16f-450f-98e7-aff585383bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425716308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.425716308
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2760728638
Short name T824
Test name
Test status
Simulation time 158384387036 ps
CPU time 343.1 seconds
Started Apr 02 02:11:59 PM PDT 24
Finished Apr 02 02:17:42 PM PDT 24
Peak memory 200468 kb
Host smart-dcd97bae-4719-4736-8627-27a39c8a0030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760728638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2760728638
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2849187977
Short name T959
Test name
Test status
Simulation time 35838961234 ps
CPU time 100.01 seconds
Started Apr 02 02:12:03 PM PDT 24
Finished Apr 02 02:13:43 PM PDT 24
Peak memory 200388 kb
Host smart-54e27f89-51f1-4256-aa6b-56a838212320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849187977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2849187977
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2953723586
Short name T112
Test name
Test status
Simulation time 145698421465 ps
CPU time 208.79 seconds
Started Apr 02 02:12:02 PM PDT 24
Finished Apr 02 02:15:30 PM PDT 24
Peak memory 200468 kb
Host smart-69642a53-64d0-4143-bcf3-614932f842f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953723586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2953723586
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2990393909
Short name T1182
Test name
Test status
Simulation time 50118435278 ps
CPU time 22.01 seconds
Started Apr 02 02:12:02 PM PDT 24
Finished Apr 02 02:12:24 PM PDT 24
Peak memory 200472 kb
Host smart-fa0da1f5-8fb1-4732-b451-ac74ec8be314
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990393909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2990393909
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3291053130
Short name T275
Test name
Test status
Simulation time 196737622855 ps
CPU time 79.6 seconds
Started Apr 02 02:12:09 PM PDT 24
Finished Apr 02 02:13:29 PM PDT 24
Peak memory 200488 kb
Host smart-a4e2f90f-7978-4021-bc2e-81560c742b37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291053130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3291053130
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.4252831641
Short name T410
Test name
Test status
Simulation time 1842755682 ps
CPU time 3.65 seconds
Started Apr 02 02:12:09 PM PDT 24
Finished Apr 02 02:12:13 PM PDT 24
Peak memory 198528 kb
Host smart-30bc13f4-92cb-4fd0-9e29-ce97e2326705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252831641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4252831641
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.834923158
Short name T1029
Test name
Test status
Simulation time 8820810518 ps
CPU time 16.72 seconds
Started Apr 02 02:12:02 PM PDT 24
Finished Apr 02 02:12:19 PM PDT 24
Peak memory 200480 kb
Host smart-9f6b9300-6545-4232-8bf2-fd4638ae4c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834923158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.834923158
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.4202099329
Short name T882
Test name
Test status
Simulation time 19763296893 ps
CPU time 1189.12 seconds
Started Apr 02 02:12:11 PM PDT 24
Finished Apr 02 02:32:00 PM PDT 24
Peak memory 200372 kb
Host smart-245e0a5b-40de-451c-adc7-ab5ec042e099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202099329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4202099329
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1151293880
Short name T391
Test name
Test status
Simulation time 1166372307 ps
CPU time 2.51 seconds
Started Apr 02 02:12:01 PM PDT 24
Finished Apr 02 02:12:04 PM PDT 24
Peak memory 198432 kb
Host smart-91f55a28-753f-4594-a4af-08588847c374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151293880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1151293880
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1390782664
Short name T1035
Test name
Test status
Simulation time 126414543331 ps
CPU time 229.44 seconds
Started Apr 02 02:12:06 PM PDT 24
Finished Apr 02 02:15:55 PM PDT 24
Peak memory 200408 kb
Host smart-89fc092f-5d43-496f-9241-12c052f3c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390782664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1390782664
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1887427568
Short name T587
Test name
Test status
Simulation time 5380883594 ps
CPU time 10.23 seconds
Started Apr 02 02:12:04 PM PDT 24
Finished Apr 02 02:12:14 PM PDT 24
Peak memory 196532 kb
Host smart-5c0f279b-24d4-4718-96a5-64ac4dcae276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887427568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1887427568
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2726842428
Short name T102
Test name
Test status
Simulation time 43893020 ps
CPU time 0.75 seconds
Started Apr 02 02:12:12 PM PDT 24
Finished Apr 02 02:12:13 PM PDT 24
Peak memory 218748 kb
Host smart-019ccbfb-cc12-472f-89fb-964238e9f564
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726842428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2726842428
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2608106637
Short name T1009
Test name
Test status
Simulation time 535175424 ps
CPU time 0.9 seconds
Started Apr 02 02:11:57 PM PDT 24
Finished Apr 02 02:11:58 PM PDT 24
Peak memory 198976 kb
Host smart-a9eb2eef-324c-40f1-80b8-9f3010e27bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608106637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2608106637
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.128982906
Short name T481
Test name
Test status
Simulation time 104479222788 ps
CPU time 382.96 seconds
Started Apr 02 02:12:12 PM PDT 24
Finished Apr 02 02:18:36 PM PDT 24
Peak memory 200500 kb
Host smart-73fa065c-1dd9-4dff-a4c9-a59ed659f219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128982906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.128982906
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2980090394
Short name T780
Test name
Test status
Simulation time 48014605231 ps
CPU time 555.26 seconds
Started Apr 02 02:12:08 PM PDT 24
Finished Apr 02 02:21:24 PM PDT 24
Peak memory 225412 kb
Host smart-f16f9981-d324-4562-bfda-1fe093e36eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980090394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2980090394
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1194415975
Short name T467
Test name
Test status
Simulation time 6768988287 ps
CPU time 21.57 seconds
Started Apr 02 02:12:05 PM PDT 24
Finished Apr 02 02:12:27 PM PDT 24
Peak memory 200268 kb
Host smart-44fb57f6-8c39-4488-9eaf-3f3a4cb67844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194415975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1194415975
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3496291551
Short name T446
Test name
Test status
Simulation time 10257650622 ps
CPU time 14.45 seconds
Started Apr 02 02:12:00 PM PDT 24
Finished Apr 02 02:12:14 PM PDT 24
Peak memory 197320 kb
Host smart-d5655ebe-7c03-47d8-b141-77cedc525a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496291551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3496291551
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3563686522
Short name T26
Test name
Test status
Simulation time 37547992 ps
CPU time 0.53 seconds
Started Apr 02 02:18:05 PM PDT 24
Finished Apr 02 02:18:06 PM PDT 24
Peak memory 194816 kb
Host smart-f8f2738e-a573-4fa8-9e3f-4e8bb5bf9696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563686522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3563686522
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3466407053
Short name T500
Test name
Test status
Simulation time 50090177913 ps
CPU time 86.25 seconds
Started Apr 02 02:17:58 PM PDT 24
Finished Apr 02 02:19:25 PM PDT 24
Peak memory 200472 kb
Host smart-53c0520d-7997-4dbf-a6a8-0de7e7b2893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466407053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3466407053
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4270408574
Short name T769
Test name
Test status
Simulation time 263728664608 ps
CPU time 50 seconds
Started Apr 02 02:17:57 PM PDT 24
Finished Apr 02 02:18:48 PM PDT 24
Peak memory 200396 kb
Host smart-6cabc8ce-2a0f-4771-b570-75f1694766c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270408574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4270408574
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3025676879
Short name T923
Test name
Test status
Simulation time 4013318942 ps
CPU time 10.26 seconds
Started Apr 02 02:17:58 PM PDT 24
Finished Apr 02 02:18:08 PM PDT 24
Peak memory 200492 kb
Host smart-a2103098-db34-4379-b89d-b6b5291bb98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025676879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3025676879
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.313985729
Short name T395
Test name
Test status
Simulation time 14373213394 ps
CPU time 6.57 seconds
Started Apr 02 02:18:01 PM PDT 24
Finished Apr 02 02:18:07 PM PDT 24
Peak memory 198128 kb
Host smart-5be5fcba-3c51-4592-8db9-32b632f40be6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313985729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.313985729
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3366844142
Short name T920
Test name
Test status
Simulation time 140604924044 ps
CPU time 531.72 seconds
Started Apr 02 02:18:07 PM PDT 24
Finished Apr 02 02:26:59 PM PDT 24
Peak memory 200408 kb
Host smart-f2f4dd80-2c63-4378-93e2-ff69320f13dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366844142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3366844142
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2621212141
Short name T674
Test name
Test status
Simulation time 771208998 ps
CPU time 1.9 seconds
Started Apr 02 02:18:07 PM PDT 24
Finished Apr 02 02:18:09 PM PDT 24
Peak memory 196512 kb
Host smart-411c802f-c5a0-473a-8e6d-5573a252be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621212141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2621212141
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1789802413
Short name T1068
Test name
Test status
Simulation time 116393056716 ps
CPU time 243.58 seconds
Started Apr 02 02:18:00 PM PDT 24
Finished Apr 02 02:22:04 PM PDT 24
Peak memory 200688 kb
Host smart-672259e0-ff52-4b06-8e76-8c29b72328a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789802413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1789802413
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1937235680
Short name T428
Test name
Test status
Simulation time 18357630673 ps
CPU time 484.84 seconds
Started Apr 02 02:18:05 PM PDT 24
Finished Apr 02 02:26:10 PM PDT 24
Peak memory 200484 kb
Host smart-8de64a90-4737-403b-ad69-75b2067430c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1937235680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1937235680
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4157512302
Short name T496
Test name
Test status
Simulation time 1584434623 ps
CPU time 6.35 seconds
Started Apr 02 02:17:56 PM PDT 24
Finished Apr 02 02:18:03 PM PDT 24
Peak memory 198480 kb
Host smart-4415f47b-a954-4fd1-b86b-de5262ea446e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157512302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4157512302
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.910060614
Short name T1138
Test name
Test status
Simulation time 19439470528 ps
CPU time 18.72 seconds
Started Apr 02 02:18:05 PM PDT 24
Finished Apr 02 02:18:24 PM PDT 24
Peak memory 200516 kb
Host smart-e68d3e5d-3167-4060-b7ed-3bf14c410c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910060614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.910060614
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.118544528
Short name T498
Test name
Test status
Simulation time 24613642383 ps
CPU time 10.37 seconds
Started Apr 02 02:18:02 PM PDT 24
Finished Apr 02 02:18:12 PM PDT 24
Peak memory 196764 kb
Host smart-9597c97e-62c1-4f5b-926c-f857da8b6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118544528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.118544528
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1440532899
Short name T322
Test name
Test status
Simulation time 462611219 ps
CPU time 1.71 seconds
Started Apr 02 02:17:53 PM PDT 24
Finished Apr 02 02:17:55 PM PDT 24
Peak memory 199840 kb
Host smart-a5699641-f4eb-4285-ab8f-d869a65b1931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440532899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1440532899
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3622299237
Short name T950
Test name
Test status
Simulation time 187199753499 ps
CPU time 195.47 seconds
Started Apr 02 02:18:04 PM PDT 24
Finished Apr 02 02:21:20 PM PDT 24
Peak memory 200476 kb
Host smart-14cc6d3c-a4c4-40cb-b6d2-fee0d37141ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622299237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3622299237
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1741437896
Short name T63
Test name
Test status
Simulation time 89282310849 ps
CPU time 1028.7 seconds
Started Apr 02 02:18:03 PM PDT 24
Finished Apr 02 02:35:12 PM PDT 24
Peak memory 225488 kb
Host smart-8d36df95-7887-4219-b1cb-69bfc78ee469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741437896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1741437896
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2049984149
Short name T983
Test name
Test status
Simulation time 2245526666 ps
CPU time 2.31 seconds
Started Apr 02 02:18:04 PM PDT 24
Finished Apr 02 02:18:07 PM PDT 24
Peak memory 200080 kb
Host smart-6f197409-21e2-4455-abdf-b3cdca1c1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049984149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2049984149
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.856526271
Short name T968
Test name
Test status
Simulation time 78992599412 ps
CPU time 162.01 seconds
Started Apr 02 02:17:53 PM PDT 24
Finished Apr 02 02:20:35 PM PDT 24
Peak memory 200404 kb
Host smart-69866c02-3c25-4e59-be9e-1e4c428853b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856526271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.856526271
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4127794647
Short name T3
Test name
Test status
Simulation time 11924253 ps
CPU time 0.55 seconds
Started Apr 02 02:18:18 PM PDT 24
Finished Apr 02 02:18:18 PM PDT 24
Peak memory 195876 kb
Host smart-f19d20a8-a664-4122-a73f-2d31b3a6628d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127794647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4127794647
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2260316541
Short name T284
Test name
Test status
Simulation time 101651763464 ps
CPU time 30.46 seconds
Started Apr 02 02:18:09 PM PDT 24
Finished Apr 02 02:18:40 PM PDT 24
Peak memory 200440 kb
Host smart-8e9c7bd7-b2dd-4044-bd44-42815dec1857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260316541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2260316541
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1159996139
Short name T948
Test name
Test status
Simulation time 37094586301 ps
CPU time 35.26 seconds
Started Apr 02 02:18:09 PM PDT 24
Finished Apr 02 02:18:44 PM PDT 24
Peak memory 200472 kb
Host smart-d64b6f63-066d-417b-aea7-40089a71b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159996139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1159996139
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2922540778
Short name T620
Test name
Test status
Simulation time 91355927461 ps
CPU time 87.4 seconds
Started Apr 02 02:18:08 PM PDT 24
Finished Apr 02 02:19:35 PM PDT 24
Peak memory 200496 kb
Host smart-c8757564-23a9-41ae-8201-a7e64ebba9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922540778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2922540778
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3406890857
Short name T750
Test name
Test status
Simulation time 8434093197 ps
CPU time 23.45 seconds
Started Apr 02 02:18:14 PM PDT 24
Finished Apr 02 02:18:37 PM PDT 24
Peak memory 200204 kb
Host smart-9a3c03c1-f0fd-423c-86b9-d2518bdd7134
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406890857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3406890857
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3614482843
Short name T458
Test name
Test status
Simulation time 126241560861 ps
CPU time 856.66 seconds
Started Apr 02 02:18:19 PM PDT 24
Finished Apr 02 02:32:36 PM PDT 24
Peak memory 200416 kb
Host smart-a037dd16-3071-45cd-84b8-c9022ca5a8dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614482843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3614482843
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2085075944
Short name T909
Test name
Test status
Simulation time 5376905142 ps
CPU time 15.52 seconds
Started Apr 02 02:18:16 PM PDT 24
Finished Apr 02 02:18:32 PM PDT 24
Peak memory 199740 kb
Host smart-fd719a7a-e19b-41a6-9bc9-ec035057a5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085075944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2085075944
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.681393570
Short name T290
Test name
Test status
Simulation time 1936745973 ps
CPU time 111.8 seconds
Started Apr 02 02:18:17 PM PDT 24
Finished Apr 02 02:20:09 PM PDT 24
Peak memory 200360 kb
Host smart-ea2c9b98-0aa2-402f-8d81-5b5410036f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=681393570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.681393570
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2351103642
Short name T741
Test name
Test status
Simulation time 5786260624 ps
CPU time 21.67 seconds
Started Apr 02 02:18:08 PM PDT 24
Finished Apr 02 02:18:30 PM PDT 24
Peak memory 198568 kb
Host smart-a8bd4770-47df-421e-aa94-c0a016071e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351103642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2351103642
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1868531802
Short name T439
Test name
Test status
Simulation time 95919290164 ps
CPU time 42.9 seconds
Started Apr 02 02:18:16 PM PDT 24
Finished Apr 02 02:18:59 PM PDT 24
Peak memory 200512 kb
Host smart-cd70acbd-2a2c-4e7c-b62a-44f53e48728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868531802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1868531802
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2888081563
Short name T473
Test name
Test status
Simulation time 2672640886 ps
CPU time 1.73 seconds
Started Apr 02 02:18:10 PM PDT 24
Finished Apr 02 02:18:12 PM PDT 24
Peak memory 196476 kb
Host smart-b60df317-d19f-414f-a08b-aea4c0242b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888081563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2888081563
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.744576186
Short name T302
Test name
Test status
Simulation time 5954350948 ps
CPU time 16.66 seconds
Started Apr 02 02:18:08 PM PDT 24
Finished Apr 02 02:18:25 PM PDT 24
Peak memory 200256 kb
Host smart-8cb9b059-746c-4871-8ba5-35a44d4c3b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744576186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.744576186
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3278144694
Short name T805
Test name
Test status
Simulation time 527343824632 ps
CPU time 66.26 seconds
Started Apr 02 02:18:17 PM PDT 24
Finished Apr 02 02:19:23 PM PDT 24
Peak memory 208864 kb
Host smart-c08a7962-0ef8-42e7-9d53-3eebf21327b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278144694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3278144694
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3465360980
Short name T785
Test name
Test status
Simulation time 780610411370 ps
CPU time 1262.52 seconds
Started Apr 02 02:18:15 PM PDT 24
Finished Apr 02 02:39:18 PM PDT 24
Peak memory 229468 kb
Host smart-b243de5c-284a-4fc5-81ae-8d96d52c91fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465360980 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3465360980
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.931924925
Short name T699
Test name
Test status
Simulation time 940691084 ps
CPU time 3.15 seconds
Started Apr 02 02:18:16 PM PDT 24
Finished Apr 02 02:18:19 PM PDT 24
Peak memory 198924 kb
Host smart-9e8afd78-1964-4c6a-9ad3-056e66f5a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931924925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.931924925
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.447087073
Short name T859
Test name
Test status
Simulation time 82590660711 ps
CPU time 33.03 seconds
Started Apr 02 02:18:08 PM PDT 24
Finished Apr 02 02:18:41 PM PDT 24
Peak memory 200436 kb
Host smart-4d877461-3926-43b7-87d9-a9cc0932580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447087073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.447087073
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2736951330
Short name T789
Test name
Test status
Simulation time 10733583 ps
CPU time 0.55 seconds
Started Apr 02 02:18:28 PM PDT 24
Finished Apr 02 02:18:28 PM PDT 24
Peak memory 195868 kb
Host smart-8344d79d-2cf4-43a6-8327-12bb9fae35fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736951330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2736951330
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2204378718
Short name T645
Test name
Test status
Simulation time 101495860633 ps
CPU time 36.19 seconds
Started Apr 02 02:18:21 PM PDT 24
Finished Apr 02 02:18:57 PM PDT 24
Peak memory 200408 kb
Host smart-3a8d8775-6fd0-4dd6-93a5-7c9f6acbc57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204378718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2204378718
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2881964460
Short name T940
Test name
Test status
Simulation time 24710355980 ps
CPU time 11.21 seconds
Started Apr 02 02:18:21 PM PDT 24
Finished Apr 02 02:18:33 PM PDT 24
Peak memory 200508 kb
Host smart-e4ee166f-133c-46cc-9aff-b3c3f4190c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881964460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2881964460
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3096000015
Short name T205
Test name
Test status
Simulation time 42892825050 ps
CPU time 39.23 seconds
Started Apr 02 02:18:21 PM PDT 24
Finished Apr 02 02:19:00 PM PDT 24
Peak memory 200464 kb
Host smart-471f5e7a-625d-4fad-8e07-f1206ccdcd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096000015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3096000015
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1956463114
Short name T917
Test name
Test status
Simulation time 27508356957 ps
CPU time 17.35 seconds
Started Apr 02 02:18:21 PM PDT 24
Finished Apr 02 02:18:38 PM PDT 24
Peak memory 200484 kb
Host smart-50c06750-7406-424b-8be0-f76ce72cff25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956463114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1956463114
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1063368646
Short name T449
Test name
Test status
Simulation time 186975124241 ps
CPU time 383.84 seconds
Started Apr 02 02:18:25 PM PDT 24
Finished Apr 02 02:24:49 PM PDT 24
Peak memory 200420 kb
Host smart-187a0bd1-eae3-44b4-a98b-28cba859bbd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063368646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1063368646
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3102188498
Short name T6
Test name
Test status
Simulation time 1787102963 ps
CPU time 2.17 seconds
Started Apr 02 02:18:27 PM PDT 24
Finished Apr 02 02:18:29 PM PDT 24
Peak memory 197560 kb
Host smart-da4e7732-7b02-4868-8747-61f21bf33581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102188498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3102188498
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.387757563
Short name T582
Test name
Test status
Simulation time 102519312333 ps
CPU time 89.72 seconds
Started Apr 02 02:18:22 PM PDT 24
Finished Apr 02 02:19:52 PM PDT 24
Peak memory 200656 kb
Host smart-2bf3ef06-b409-4f13-a44a-4367dfdcb35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387757563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.387757563
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.458177071
Short name T837
Test name
Test status
Simulation time 4974787949 ps
CPU time 81.22 seconds
Started Apr 02 02:18:27 PM PDT 24
Finished Apr 02 02:19:48 PM PDT 24
Peak memory 200372 kb
Host smart-c39e9302-7b71-4665-a566-e5b31928fac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458177071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.458177071
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1345009804
Short name T715
Test name
Test status
Simulation time 1590535006 ps
CPU time 3.22 seconds
Started Apr 02 02:18:20 PM PDT 24
Finished Apr 02 02:18:23 PM PDT 24
Peak memory 198484 kb
Host smart-4c17b790-2247-42d1-ab84-21e7f216b095
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345009804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1345009804
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1116767087
Short name T1005
Test name
Test status
Simulation time 33883138161 ps
CPU time 66.07 seconds
Started Apr 02 02:18:26 PM PDT 24
Finished Apr 02 02:19:32 PM PDT 24
Peak memory 200456 kb
Host smart-e508a47c-3ff1-46b0-aa7c-ebb047123d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116767087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1116767087
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2850914536
Short name T1124
Test name
Test status
Simulation time 5141435527 ps
CPU time 9.21 seconds
Started Apr 02 02:18:24 PM PDT 24
Finished Apr 02 02:18:34 PM PDT 24
Peak memory 196700 kb
Host smart-99428f9b-82be-454a-8515-17fcb65f7d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850914536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2850914536
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3004770628
Short name T388
Test name
Test status
Simulation time 111609488 ps
CPU time 0.87 seconds
Started Apr 02 02:18:17 PM PDT 24
Finished Apr 02 02:18:18 PM PDT 24
Peak memory 197736 kb
Host smart-5d23e049-5261-4967-88d6-1bcceb6d7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004770628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3004770628
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2863402713
Short name T55
Test name
Test status
Simulation time 321002799124 ps
CPU time 130.5 seconds
Started Apr 02 02:18:27 PM PDT 24
Finished Apr 02 02:20:38 PM PDT 24
Peak memory 200412 kb
Host smart-b7e59797-f6dd-4f64-b0c8-df5cf596c764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863402713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2863402713
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1263634164
Short name T901
Test name
Test status
Simulation time 73839225015 ps
CPU time 519.81 seconds
Started Apr 02 02:18:28 PM PDT 24
Finished Apr 02 02:27:08 PM PDT 24
Peak memory 217144 kb
Host smart-1f8b00fd-b281-474e-99b5-7187e49cb00c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263634164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1263634164
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2043652104
Short name T566
Test name
Test status
Simulation time 1212031205 ps
CPU time 1.49 seconds
Started Apr 02 02:18:26 PM PDT 24
Finished Apr 02 02:18:28 PM PDT 24
Peak memory 198760 kb
Host smart-9f730c67-097a-420f-a8f3-b1c3383816d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043652104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2043652104
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3796159861
Short name T1165
Test name
Test status
Simulation time 66861399201 ps
CPU time 57.31 seconds
Started Apr 02 02:18:18 PM PDT 24
Finished Apr 02 02:19:15 PM PDT 24
Peak memory 200496 kb
Host smart-b5ea98fc-d734-46c9-bf20-c4ea1b724141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796159861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3796159861
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.32576989
Short name T451
Test name
Test status
Simulation time 25257522 ps
CPU time 0.54 seconds
Started Apr 02 02:18:38 PM PDT 24
Finished Apr 02 02:18:39 PM PDT 24
Peak memory 195888 kb
Host smart-b5b362fe-4338-42ff-83e1-7c2e14c6c856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.32576989
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2237301582
Short name T1134
Test name
Test status
Simulation time 71376676169 ps
CPU time 33.03 seconds
Started Apr 02 02:18:30 PM PDT 24
Finished Apr 02 02:19:04 PM PDT 24
Peak memory 200440 kb
Host smart-b189892b-d777-4310-a036-381da6849e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237301582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2237301582
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1569361351
Short name T1101
Test name
Test status
Simulation time 55651815702 ps
CPU time 26.68 seconds
Started Apr 02 02:18:31 PM PDT 24
Finished Apr 02 02:18:58 PM PDT 24
Peak memory 200416 kb
Host smart-40b3a31b-7c31-478f-9e75-a027459b8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569361351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1569361351
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2340255574
Short name T206
Test name
Test status
Simulation time 10358843276 ps
CPU time 14.18 seconds
Started Apr 02 02:18:31 PM PDT 24
Finished Apr 02 02:18:46 PM PDT 24
Peak memory 198984 kb
Host smart-f3131dba-030d-448d-866e-262b2c27de91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340255574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2340255574
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3201078446
Short name T605
Test name
Test status
Simulation time 72899847303 ps
CPU time 112.42 seconds
Started Apr 02 02:18:35 PM PDT 24
Finished Apr 02 02:20:28 PM PDT 24
Peak memory 200448 kb
Host smart-5040b1ff-2c9a-49e9-a174-c68567acf702
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201078446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3201078446
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1347846560
Short name T792
Test name
Test status
Simulation time 68246468912 ps
CPU time 662.68 seconds
Started Apr 02 02:18:39 PM PDT 24
Finished Apr 02 02:29:42 PM PDT 24
Peak memory 200476 kb
Host smart-2f176b60-729d-48f1-a7df-4e7717e8bcde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347846560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1347846560
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1720752887
Short name T1014
Test name
Test status
Simulation time 11481229103 ps
CPU time 22.27 seconds
Started Apr 02 02:18:39 PM PDT 24
Finished Apr 02 02:19:01 PM PDT 24
Peak memory 199188 kb
Host smart-f752446f-b939-4551-94a5-5c9be7fd8e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720752887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1720752887
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.160034949
Short name T1030
Test name
Test status
Simulation time 47683388856 ps
CPU time 80.23 seconds
Started Apr 02 02:18:34 PM PDT 24
Finished Apr 02 02:19:55 PM PDT 24
Peak memory 200732 kb
Host smart-5d9b4588-659f-4e2e-ab06-c48d270b16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160034949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.160034949
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.921505365
Short name T43
Test name
Test status
Simulation time 14659251512 ps
CPU time 182.91 seconds
Started Apr 02 02:18:38 PM PDT 24
Finished Apr 02 02:21:42 PM PDT 24
Peak memory 200464 kb
Host smart-1e9ccb27-ba44-4f39-acb8-e9c1af3a4068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921505365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.921505365
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2786131810
Short name T871
Test name
Test status
Simulation time 2743536528 ps
CPU time 4.01 seconds
Started Apr 02 02:18:38 PM PDT 24
Finished Apr 02 02:18:42 PM PDT 24
Peak memory 198548 kb
Host smart-3c9b72b9-e327-4b93-bed1-5b6e3d32a119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786131810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2786131810
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2516794196
Short name T783
Test name
Test status
Simulation time 185736919212 ps
CPU time 52.56 seconds
Started Apr 02 02:18:35 PM PDT 24
Finished Apr 02 02:19:28 PM PDT 24
Peak memory 200468 kb
Host smart-64d924e4-115e-4ad5-8b9c-d67cb40213b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516794196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2516794196
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.128865565
Short name T579
Test name
Test status
Simulation time 37366872591 ps
CPU time 32.31 seconds
Started Apr 02 02:18:34 PM PDT 24
Finished Apr 02 02:19:07 PM PDT 24
Peak memory 196672 kb
Host smart-5de7e892-4975-47ff-8db8-7525e49527a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128865565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.128865565
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.263993430
Short name T888
Test name
Test status
Simulation time 690036451 ps
CPU time 3.68 seconds
Started Apr 02 02:18:29 PM PDT 24
Finished Apr 02 02:18:32 PM PDT 24
Peak memory 198744 kb
Host smart-2fbbe25b-14ad-4a11-b5fb-d9cd8cfeb2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263993430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.263993430
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.867692818
Short name T122
Test name
Test status
Simulation time 321455799006 ps
CPU time 688.54 seconds
Started Apr 02 02:18:39 PM PDT 24
Finished Apr 02 02:30:07 PM PDT 24
Peak memory 208896 kb
Host smart-59430037-d370-4299-8088-b65620f6ecc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867692818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.867692818
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3577676657
Short name T679
Test name
Test status
Simulation time 68896352339 ps
CPU time 489.89 seconds
Started Apr 02 02:18:38 PM PDT 24
Finished Apr 02 02:26:48 PM PDT 24
Peak memory 225404 kb
Host smart-6f560e54-d245-45b3-8daa-3e20d115571d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577676657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3577676657
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2628206460
Short name T942
Test name
Test status
Simulation time 6609817317 ps
CPU time 22.06 seconds
Started Apr 02 02:18:37 PM PDT 24
Finished Apr 02 02:18:59 PM PDT 24
Peak memory 200380 kb
Host smart-9f9a6820-f295-46f3-adbb-44d446ba95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628206460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2628206460
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.372009889
Short name T1129
Test name
Test status
Simulation time 64499203771 ps
CPU time 54.87 seconds
Started Apr 02 02:18:28 PM PDT 24
Finished Apr 02 02:19:23 PM PDT 24
Peak memory 200468 kb
Host smart-38249a79-50bc-456a-b26a-3a4b8872925d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372009889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.372009889
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.520405797
Short name T1094
Test name
Test status
Simulation time 14462936 ps
CPU time 0.54 seconds
Started Apr 02 02:18:51 PM PDT 24
Finished Apr 02 02:18:52 PM PDT 24
Peak memory 195900 kb
Host smart-145a5cc0-ccbf-4791-9164-c86e5f71ce70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520405797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.520405797
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.413662074
Short name T889
Test name
Test status
Simulation time 196598683629 ps
CPU time 270.91 seconds
Started Apr 02 02:18:39 PM PDT 24
Finished Apr 02 02:23:10 PM PDT 24
Peak memory 200464 kb
Host smart-4e0da482-7cf8-4752-9e58-50d92acf1ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413662074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.413662074
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3654887600
Short name T735
Test name
Test status
Simulation time 26680941400 ps
CPU time 21.31 seconds
Started Apr 02 02:18:39 PM PDT 24
Finished Apr 02 02:19:01 PM PDT 24
Peak memory 200448 kb
Host smart-6da8d621-a856-488e-bb27-f46b3cd8a955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654887600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3654887600
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1174051089
Short name T166
Test name
Test status
Simulation time 64010842022 ps
CPU time 31.37 seconds
Started Apr 02 02:18:41 PM PDT 24
Finished Apr 02 02:19:13 PM PDT 24
Peak memory 200480 kb
Host smart-de75a7fb-eb70-4ba8-9b35-cd95b702acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174051089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1174051089
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4004849495
Short name T411
Test name
Test status
Simulation time 11926423822 ps
CPU time 6.94 seconds
Started Apr 02 02:18:42 PM PDT 24
Finished Apr 02 02:18:49 PM PDT 24
Peak memory 199864 kb
Host smart-c4974156-8994-459a-ad54-3907d5739253
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004849495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4004849495
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2104974302
Short name T822
Test name
Test status
Simulation time 56568078902 ps
CPU time 490.29 seconds
Started Apr 02 02:18:52 PM PDT 24
Finished Apr 02 02:27:03 PM PDT 24
Peak memory 200536 kb
Host smart-87465b41-bad6-4ba3-b76c-7d2b806d0d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104974302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2104974302
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1992321444
Short name T969
Test name
Test status
Simulation time 2138710916 ps
CPU time 3.9 seconds
Started Apr 02 02:18:50 PM PDT 24
Finished Apr 02 02:18:54 PM PDT 24
Peak memory 199668 kb
Host smart-4cf3211a-dcc9-477d-b347-8a514ee5986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992321444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1992321444
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2926309483
Short name T345
Test name
Test status
Simulation time 54960626503 ps
CPU time 10.92 seconds
Started Apr 02 02:18:42 PM PDT 24
Finished Apr 02 02:18:53 PM PDT 24
Peak memory 195176 kb
Host smart-61064ada-43aa-4e62-b0a6-c93546ebdcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926309483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2926309483
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.682818296
Short name T276
Test name
Test status
Simulation time 15611247176 ps
CPU time 208.71 seconds
Started Apr 02 02:18:48 PM PDT 24
Finished Apr 02 02:22:17 PM PDT 24
Peak memory 200436 kb
Host smart-9b4f23f2-152b-45e2-be1a-30bf7f6d4f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682818296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.682818296
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1172738983
Short name T978
Test name
Test status
Simulation time 1815195826 ps
CPU time 3.96 seconds
Started Apr 02 02:18:43 PM PDT 24
Finished Apr 02 02:18:47 PM PDT 24
Peak memory 198596 kb
Host smart-faf8d327-a6a1-48f1-82c9-5cc2fb5208e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172738983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1172738983
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.998512676
Short name T575
Test name
Test status
Simulation time 29611766675 ps
CPU time 46.36 seconds
Started Apr 02 02:18:43 PM PDT 24
Finished Apr 02 02:19:29 PM PDT 24
Peak memory 200420 kb
Host smart-482e682e-ba3f-4647-bd51-cf12a2a6efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998512676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.998512676
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.761386158
Short name T537
Test name
Test status
Simulation time 32531710228 ps
CPU time 51.45 seconds
Started Apr 02 02:18:43 PM PDT 24
Finished Apr 02 02:19:35 PM PDT 24
Peak memory 196756 kb
Host smart-68773bcc-aa3e-4236-9c43-4f6799202f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761386158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.761386158
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2647234729
Short name T75
Test name
Test status
Simulation time 862691720 ps
CPU time 1.86 seconds
Started Apr 02 02:18:37 PM PDT 24
Finished Apr 02 02:18:39 PM PDT 24
Peak memory 200020 kb
Host smart-6df72fb8-357a-49d2-a9d5-623c8eb04d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647234729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2647234729
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1589947593
Short name T707
Test name
Test status
Simulation time 184245588077 ps
CPU time 330.06 seconds
Started Apr 02 02:18:52 PM PDT 24
Finished Apr 02 02:24:22 PM PDT 24
Peak memory 200512 kb
Host smart-aeebd020-3c8f-400b-883e-92ada58518f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589947593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1589947593
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1281666185
Short name T117
Test name
Test status
Simulation time 85415850676 ps
CPU time 1105.49 seconds
Started Apr 02 02:18:53 PM PDT 24
Finished Apr 02 02:37:18 PM PDT 24
Peak memory 217168 kb
Host smart-f7f90a43-c991-4205-99ea-084a8929a726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281666185 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1281666185
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.816791220
Short name T366
Test name
Test status
Simulation time 999409356 ps
CPU time 2.08 seconds
Started Apr 02 02:18:50 PM PDT 24
Finished Apr 02 02:18:53 PM PDT 24
Peak memory 199120 kb
Host smart-cc3225df-9de5-4b74-9ae1-3e547804277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816791220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.816791220
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1467913853
Short name T418
Test name
Test status
Simulation time 37294456084 ps
CPU time 63.95 seconds
Started Apr 02 02:18:37 PM PDT 24
Finished Apr 02 02:19:41 PM PDT 24
Peak memory 200524 kb
Host smart-ad91d024-1423-452d-956f-1472cab0f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467913853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1467913853
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.969337775
Short name T952
Test name
Test status
Simulation time 38138424 ps
CPU time 0.59 seconds
Started Apr 02 02:19:04 PM PDT 24
Finished Apr 02 02:19:04 PM PDT 24
Peak memory 195872 kb
Host smart-9dbd5bff-6b07-4a9b-b05d-a1701e8463d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969337775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.969337775
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.53531123
Short name T389
Test name
Test status
Simulation time 40030452329 ps
CPU time 79.46 seconds
Started Apr 02 02:18:53 PM PDT 24
Finished Apr 02 02:20:14 PM PDT 24
Peak memory 200316 kb
Host smart-3388d7c0-3e86-4886-aa96-6525d3c58346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53531123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.53531123
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.728509381
Short name T405
Test name
Test status
Simulation time 115778918346 ps
CPU time 35.43 seconds
Started Apr 02 02:18:55 PM PDT 24
Finished Apr 02 02:19:31 PM PDT 24
Peak memory 200140 kb
Host smart-3bf405ee-9ad6-4188-a9e1-7e2165264ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728509381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.728509381
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3956349600
Short name T1148
Test name
Test status
Simulation time 93619739752 ps
CPU time 51.43 seconds
Started Apr 02 02:18:55 PM PDT 24
Finished Apr 02 02:19:47 PM PDT 24
Peak memory 200384 kb
Host smart-89f03e1d-c064-480f-be4f-6b2f2f7425ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956349600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3956349600
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.195387478
Short name T855
Test name
Test status
Simulation time 57219325761 ps
CPU time 153.28 seconds
Started Apr 02 02:19:03 PM PDT 24
Finished Apr 02 02:21:37 PM PDT 24
Peak memory 200496 kb
Host smart-93dd4cdc-71b8-445e-b603-2d32ff896751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195387478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.195387478
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2411700309
Short name T732
Test name
Test status
Simulation time 6897253247 ps
CPU time 5.74 seconds
Started Apr 02 02:19:02 PM PDT 24
Finished Apr 02 02:19:08 PM PDT 24
Peak memory 200388 kb
Host smart-c42d0856-11db-4003-b6ee-24941e7f7410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411700309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2411700309
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.2873681289
Short name T568
Test name
Test status
Simulation time 51412737388 ps
CPU time 17.29 seconds
Started Apr 02 02:18:59 PM PDT 24
Finished Apr 02 02:19:16 PM PDT 24
Peak memory 200516 kb
Host smart-09c16824-d40c-41a2-b5f4-e6650021ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873681289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2873681289
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1400378286
Short name T897
Test name
Test status
Simulation time 10166672601 ps
CPU time 112.8 seconds
Started Apr 02 02:19:05 PM PDT 24
Finished Apr 02 02:20:57 PM PDT 24
Peak memory 200476 kb
Host smart-98bd1f54-f152-4ca1-af5d-00b76167a1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1400378286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1400378286
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.289275837
Short name T423
Test name
Test status
Simulation time 4003871049 ps
CPU time 7.8 seconds
Started Apr 02 02:18:55 PM PDT 24
Finished Apr 02 02:19:03 PM PDT 24
Peak memory 198528 kb
Host smart-f62c8682-ffb6-4eea-8d68-9fbb48c4a38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289275837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.289275837
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2563168673
Short name T260
Test name
Test status
Simulation time 232972881011 ps
CPU time 122.14 seconds
Started Apr 02 02:19:00 PM PDT 24
Finished Apr 02 02:21:02 PM PDT 24
Peak memory 200340 kb
Host smart-5499f59a-acb3-4ac7-a040-65b6e370a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563168673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2563168673
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3574632164
Short name T974
Test name
Test status
Simulation time 3197466342 ps
CPU time 5.09 seconds
Started Apr 02 02:18:59 PM PDT 24
Finished Apr 02 02:19:04 PM PDT 24
Peak memory 196484 kb
Host smart-a0ee502a-b4d2-470e-8140-3e4d29d57214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574632164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3574632164
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2097609396
Short name T706
Test name
Test status
Simulation time 290972358 ps
CPU time 1.08 seconds
Started Apr 02 02:18:51 PM PDT 24
Finished Apr 02 02:18:52 PM PDT 24
Peak memory 198756 kb
Host smart-6eba45f0-7862-4ee2-ac1f-27f4770fa73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097609396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2097609396
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.1215272529
Short name T1040
Test name
Test status
Simulation time 625880417454 ps
CPU time 592.34 seconds
Started Apr 02 02:19:04 PM PDT 24
Finished Apr 02 02:28:57 PM PDT 24
Peak memory 208968 kb
Host smart-c0623bc3-b35c-4c5b-9c4b-04494c4f224f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215272529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.1215272529
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.4183256449
Short name T296
Test name
Test status
Simulation time 35209165385 ps
CPU time 662.86 seconds
Started Apr 02 02:19:03 PM PDT 24
Finished Apr 02 02:30:06 PM PDT 24
Peak memory 216956 kb
Host smart-b98d747c-5cfc-4a08-bd2f-8c0478ada2a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183256449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.4183256449
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3955535293
Short name T530
Test name
Test status
Simulation time 2145462663 ps
CPU time 2.16 seconds
Started Apr 02 02:19:05 PM PDT 24
Finished Apr 02 02:19:07 PM PDT 24
Peak memory 200272 kb
Host smart-e3765a88-4e70-4c21-9907-c28bbe2d3d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955535293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3955535293
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2984157537
Short name T13
Test name
Test status
Simulation time 43304306671 ps
CPU time 13.12 seconds
Started Apr 02 02:18:53 PM PDT 24
Finished Apr 02 02:19:06 PM PDT 24
Peak memory 198300 kb
Host smart-69eb1b77-b77c-4f5b-929f-2eeecaabd77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984157537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2984157537
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2136814620
Short name T369
Test name
Test status
Simulation time 57058700 ps
CPU time 0.55 seconds
Started Apr 02 02:19:13 PM PDT 24
Finished Apr 02 02:19:14 PM PDT 24
Peak memory 195864 kb
Host smart-5163b3fe-ea54-43f8-9a8e-5631709315bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136814620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2136814620
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.120195913
Short name T1056
Test name
Test status
Simulation time 48716182752 ps
CPU time 66.85 seconds
Started Apr 02 02:19:07 PM PDT 24
Finished Apr 02 02:20:15 PM PDT 24
Peak memory 200388 kb
Host smart-a08c38b5-cac7-45d6-a4e1-e8737c32049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120195913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.120195913
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2749091546
Short name T1063
Test name
Test status
Simulation time 111562047257 ps
CPU time 49.41 seconds
Started Apr 02 02:19:05 PM PDT 24
Finished Apr 02 02:19:54 PM PDT 24
Peak memory 200480 kb
Host smart-87616923-9061-453b-b3f2-0974a27e1a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749091546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2749091546
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3692106701
Short name T790
Test name
Test status
Simulation time 150100700386 ps
CPU time 24.21 seconds
Started Apr 02 02:19:06 PM PDT 24
Finished Apr 02 02:19:31 PM PDT 24
Peak memory 200388 kb
Host smart-d62f5a01-a729-4cd8-b0a7-390eb42ccc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692106701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3692106701
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2583876156
Short name T1175
Test name
Test status
Simulation time 29077832549 ps
CPU time 7.3 seconds
Started Apr 02 02:19:05 PM PDT 24
Finished Apr 02 02:19:12 PM PDT 24
Peak memory 199272 kb
Host smart-637c7ce4-c7f6-42d0-909f-eba708fbe013
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583876156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2583876156
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.4249037081
Short name T1059
Test name
Test status
Simulation time 58922033367 ps
CPU time 467.52 seconds
Started Apr 02 02:19:11 PM PDT 24
Finished Apr 02 02:27:00 PM PDT 24
Peak memory 200428 kb
Host smart-706c1d98-46d0-4cc2-916b-35c3901d6584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249037081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.4249037081
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1619708289
Short name T982
Test name
Test status
Simulation time 7493551747 ps
CPU time 4.24 seconds
Started Apr 02 02:19:08 PM PDT 24
Finished Apr 02 02:19:13 PM PDT 24
Peak memory 199064 kb
Host smart-e3bb07f5-9ffd-45a8-b781-8c883d062d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619708289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1619708289
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2160667211
Short name T887
Test name
Test status
Simulation time 236609793237 ps
CPU time 86.99 seconds
Started Apr 02 02:19:09 PM PDT 24
Finished Apr 02 02:20:36 PM PDT 24
Peak memory 208844 kb
Host smart-8ef73bde-6ad1-4301-9b8d-001e9ff3b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160667211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2160667211
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1583412979
Short name T403
Test name
Test status
Simulation time 5146230041 ps
CPU time 62.17 seconds
Started Apr 02 02:19:08 PM PDT 24
Finished Apr 02 02:20:11 PM PDT 24
Peak memory 200476 kb
Host smart-48fac795-d28f-49ed-93a5-ee9d531bc283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583412979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1583412979
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2843306196
Short name T362
Test name
Test status
Simulation time 5629924195 ps
CPU time 22.28 seconds
Started Apr 02 02:19:05 PM PDT 24
Finished Apr 02 02:19:27 PM PDT 24
Peak memory 199084 kb
Host smart-8712042e-63fc-46f9-ae76-aa895db10a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843306196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2843306196
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1124527653
Short name T902
Test name
Test status
Simulation time 52284827517 ps
CPU time 69.96 seconds
Started Apr 02 02:19:09 PM PDT 24
Finished Apr 02 02:20:19 PM PDT 24
Peak memory 200484 kb
Host smart-0ae4f6c9-cf10-4ed1-ae41-c8cb61477e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124527653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1124527653
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.4232957295
Short name T315
Test name
Test status
Simulation time 3792648755 ps
CPU time 2.04 seconds
Started Apr 02 02:19:08 PM PDT 24
Finished Apr 02 02:19:10 PM PDT 24
Peak memory 196732 kb
Host smart-75b8cbb0-8c89-4ec7-a8d6-07f538be14e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232957295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.4232957295
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.331704711
Short name T491
Test name
Test status
Simulation time 506688733 ps
CPU time 2.79 seconds
Started Apr 02 02:19:02 PM PDT 24
Finished Apr 02 02:19:05 PM PDT 24
Peak memory 200376 kb
Host smart-2dc7e969-8779-43bb-8c82-dcd1055d98e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331704711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.331704711
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1073028400
Short name T1022
Test name
Test status
Simulation time 174000867420 ps
CPU time 165.78 seconds
Started Apr 02 02:19:13 PM PDT 24
Finished Apr 02 02:21:58 PM PDT 24
Peak memory 200560 kb
Host smart-e2d389b6-4515-444c-9d23-ce56febf365c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073028400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1073028400
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1147313209
Short name T46
Test name
Test status
Simulation time 174189091067 ps
CPU time 1090.62 seconds
Started Apr 02 02:19:11 PM PDT 24
Finished Apr 02 02:37:23 PM PDT 24
Peak memory 228468 kb
Host smart-d4c5003f-0f4f-4654-9ccc-4f68f8623367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147313209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1147313209
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.4051735000
Short name T990
Test name
Test status
Simulation time 1110615683 ps
CPU time 1.47 seconds
Started Apr 02 02:19:09 PM PDT 24
Finished Apr 02 02:19:12 PM PDT 24
Peak memory 199088 kb
Host smart-696128c9-4a00-40e3-a50a-8389c5060dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051735000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.4051735000
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1816789565
Short name T804
Test name
Test status
Simulation time 68747708152 ps
CPU time 123.97 seconds
Started Apr 02 02:19:06 PM PDT 24
Finished Apr 02 02:21:11 PM PDT 24
Peak memory 200480 kb
Host smart-875dc6d7-1221-4f99-a76d-011cb470076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816789565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1816789565
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2396380755
Short name T1023
Test name
Test status
Simulation time 39448618 ps
CPU time 0.52 seconds
Started Apr 02 02:19:26 PM PDT 24
Finished Apr 02 02:19:27 PM PDT 24
Peak memory 195888 kb
Host smart-c0ba0426-403c-4826-8395-9406d90455a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396380755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2396380755
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1611055574
Short name T415
Test name
Test status
Simulation time 120152725208 ps
CPU time 97.77 seconds
Started Apr 02 02:19:15 PM PDT 24
Finished Apr 02 02:20:53 PM PDT 24
Peak memory 200356 kb
Host smart-b334ae05-1a3f-446f-b992-2cd56a10d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611055574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1611055574
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4115564457
Short name T352
Test name
Test status
Simulation time 37347678363 ps
CPU time 26.25 seconds
Started Apr 02 02:19:18 PM PDT 24
Finished Apr 02 02:19:45 PM PDT 24
Peak memory 200488 kb
Host smart-13b60bc0-23e3-4422-9583-b890da0e2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115564457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4115564457
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4251345924
Short name T143
Test name
Test status
Simulation time 16639882627 ps
CPU time 16.44 seconds
Started Apr 02 02:19:19 PM PDT 24
Finished Apr 02 02:19:36 PM PDT 24
Peak memory 200420 kb
Host smart-0102d769-56c3-4f86-9e24-e8315595995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251345924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4251345924
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2951917992
Short name T1128
Test name
Test status
Simulation time 106189510521 ps
CPU time 84.44 seconds
Started Apr 02 02:19:19 PM PDT 24
Finished Apr 02 02:20:44 PM PDT 24
Peak memory 200340 kb
Host smart-9ceac4a1-e93a-4c03-9989-c5027f0ce0ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951917992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2951917992
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3871116789
Short name T533
Test name
Test status
Simulation time 99075767024 ps
CPU time 814.71 seconds
Started Apr 02 02:19:22 PM PDT 24
Finished Apr 02 02:32:57 PM PDT 24
Peak memory 200504 kb
Host smart-aa954e48-28c5-4e8a-82a1-4a38bd6b04d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871116789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3871116789
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2165002324
Short name T941
Test name
Test status
Simulation time 23681324 ps
CPU time 0.58 seconds
Started Apr 02 02:19:24 PM PDT 24
Finished Apr 02 02:19:25 PM PDT 24
Peak memory 196236 kb
Host smart-62514680-56b1-421c-a158-1d33cca623ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165002324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2165002324
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3283199973
Short name T265
Test name
Test status
Simulation time 210211553589 ps
CPU time 208.25 seconds
Started Apr 02 02:19:21 PM PDT 24
Finished Apr 02 02:22:49 PM PDT 24
Peak memory 200796 kb
Host smart-7c1972e0-7b96-427b-8e0b-7473ccee1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283199973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3283199973
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.3393660648
Short name T729
Test name
Test status
Simulation time 11066742491 ps
CPU time 601.9 seconds
Started Apr 02 02:19:25 PM PDT 24
Finished Apr 02 02:29:27 PM PDT 24
Peak memory 200444 kb
Host smart-78eb5424-7675-46a6-b315-a4ea60093191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393660648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3393660648
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3518368176
Short name T479
Test name
Test status
Simulation time 5421545387 ps
CPU time 8.83 seconds
Started Apr 02 02:19:18 PM PDT 24
Finished Apr 02 02:19:27 PM PDT 24
Peak memory 198592 kb
Host smart-3a6405e7-a5ef-4bd9-9f7e-363b7bc9c6e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518368176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3518368176
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3804751272
Short name T550
Test name
Test status
Simulation time 52979611896 ps
CPU time 43.32 seconds
Started Apr 02 02:19:23 PM PDT 24
Finished Apr 02 02:20:07 PM PDT 24
Peak memory 200428 kb
Host smart-22a8a8b5-85ff-4b26-a58b-977455067fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804751272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3804751272
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1924114310
Short name T382
Test name
Test status
Simulation time 2645597356 ps
CPU time 1.73 seconds
Started Apr 02 02:19:24 PM PDT 24
Finished Apr 02 02:19:26 PM PDT 24
Peak memory 196188 kb
Host smart-28f3c7db-4c8a-4809-8dc1-022b4cd9b5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924114310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1924114310
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1488034078
Short name T676
Test name
Test status
Simulation time 84776644 ps
CPU time 0.86 seconds
Started Apr 02 02:19:17 PM PDT 24
Finished Apr 02 02:19:18 PM PDT 24
Peak memory 197564 kb
Host smart-4d9308e0-e206-49c1-9b80-30d9e47ce8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488034078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1488034078
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.166969634
Short name T1008
Test name
Test status
Simulation time 297233682309 ps
CPU time 745.17 seconds
Started Apr 02 02:19:28 PM PDT 24
Finished Apr 02 02:31:53 PM PDT 24
Peak memory 200460 kb
Host smart-1a8bc984-4472-419d-b7e0-8025eb486aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166969634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.166969634
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.128322330
Short name T21
Test name
Test status
Simulation time 28840599058 ps
CPU time 105.17 seconds
Started Apr 02 02:19:24 PM PDT 24
Finished Apr 02 02:21:10 PM PDT 24
Peak memory 211400 kb
Host smart-7b0561af-ff6f-49e8-8f5c-fb863ac7c48b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128322330 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.128322330
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.764850106
Short name T635
Test name
Test status
Simulation time 6497830783 ps
CPU time 19.86 seconds
Started Apr 02 02:19:24 PM PDT 24
Finished Apr 02 02:19:44 PM PDT 24
Peak memory 199756 kb
Host smart-9189ec81-889b-4344-b7c9-e00798b6ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764850106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.764850106
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.479421186
Short name T406
Test name
Test status
Simulation time 48006199674 ps
CPU time 11.94 seconds
Started Apr 02 02:19:14 PM PDT 24
Finished Apr 02 02:19:27 PM PDT 24
Peak memory 200364 kb
Host smart-27bbd389-d333-4e1a-8f9c-579787d4b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479421186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.479421186
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1431758011
Short name T797
Test name
Test status
Simulation time 24824059 ps
CPU time 0.54 seconds
Started Apr 02 02:19:39 PM PDT 24
Finished Apr 02 02:19:40 PM PDT 24
Peak memory 195864 kb
Host smart-c74d113d-643c-43ec-bd1b-760361ff3594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431758011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1431758011
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2901829474
Short name T601
Test name
Test status
Simulation time 74229831547 ps
CPU time 47.12 seconds
Started Apr 02 02:19:32 PM PDT 24
Finished Apr 02 02:20:19 PM PDT 24
Peak memory 200500 kb
Host smart-aca51403-4008-40ad-a46a-1c8e08878fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901829474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2901829474
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3093847211
Short name T372
Test name
Test status
Simulation time 164454824063 ps
CPU time 180.91 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:22:31 PM PDT 24
Peak memory 200420 kb
Host smart-02aa0991-e23d-450c-b96e-798cc235acdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093847211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3093847211
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1235773963
Short name T192
Test name
Test status
Simulation time 31616440256 ps
CPU time 13.89 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:19:44 PM PDT 24
Peak memory 200452 kb
Host smart-f4853a77-88a5-4790-9ea5-c497a11e83dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235773963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1235773963
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3725572651
Short name T1136
Test name
Test status
Simulation time 7513087441 ps
CPU time 5.39 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:19:36 PM PDT 24
Peak memory 200448 kb
Host smart-2f5d8efb-b1f7-47b2-bbaa-d43a03b3ad35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725572651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3725572651
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4273591083
Short name T771
Test name
Test status
Simulation time 49448550004 ps
CPU time 257.9 seconds
Started Apr 02 02:19:33 PM PDT 24
Finished Apr 02 02:23:51 PM PDT 24
Peak memory 200416 kb
Host smart-cb80e4a6-6cec-49f7-aa32-0db254076ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273591083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4273591083
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2091906473
Short name T1
Test name
Test status
Simulation time 4171296228 ps
CPU time 5.87 seconds
Started Apr 02 02:19:34 PM PDT 24
Finished Apr 02 02:19:41 PM PDT 24
Peak memory 200164 kb
Host smart-4539b146-3ef6-4e61-95e5-644d3bdd1ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091906473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2091906473
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3068410266
Short name T668
Test name
Test status
Simulation time 62568964597 ps
CPU time 30.52 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:20:01 PM PDT 24
Peak memory 199524 kb
Host smart-7ee42385-4c42-49df-9503-71a4d076fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068410266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3068410266
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3411067248
Short name T965
Test name
Test status
Simulation time 18819904853 ps
CPU time 210.25 seconds
Started Apr 02 02:19:34 PM PDT 24
Finished Apr 02 02:23:05 PM PDT 24
Peak memory 200468 kb
Host smart-dad6ecb6-4b36-4baa-aec4-a2ccecd92745
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3411067248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3411067248
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1662064025
Short name T879
Test name
Test status
Simulation time 7151709516 ps
CPU time 15.94 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:19:46 PM PDT 24
Peak memory 198376 kb
Host smart-89f74e7c-4b61-4f27-b529-41c38f410b95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662064025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1662064025
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4069552626
Short name T800
Test name
Test status
Simulation time 149465938372 ps
CPU time 165.13 seconds
Started Apr 02 02:19:33 PM PDT 24
Finished Apr 02 02:22:18 PM PDT 24
Peak memory 200520 kb
Host smart-884bb226-95bf-4adc-9bf7-38cc686da9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069552626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4069552626
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3369211277
Short name T1122
Test name
Test status
Simulation time 3846700433 ps
CPU time 6.56 seconds
Started Apr 02 02:19:35 PM PDT 24
Finished Apr 02 02:19:42 PM PDT 24
Peak memory 196420 kb
Host smart-0e40b9a9-ada2-4c58-8f43-bc6e21a560fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369211277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3369211277
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1841475505
Short name T1002
Test name
Test status
Simulation time 544388109 ps
CPU time 1.17 seconds
Started Apr 02 02:19:35 PM PDT 24
Finished Apr 02 02:19:37 PM PDT 24
Peak memory 199268 kb
Host smart-69a2321d-6f94-4e07-859e-c2286c4518f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841475505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1841475505
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.389334724
Short name T612
Test name
Test status
Simulation time 121069929609 ps
CPU time 202.75 seconds
Started Apr 02 02:19:40 PM PDT 24
Finished Apr 02 02:23:03 PM PDT 24
Peak memory 200396 kb
Host smart-a8f0141d-1749-4a18-800e-0c74ddafc153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389334724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.389334724
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4178814012
Short name T661
Test name
Test status
Simulation time 56549041534 ps
CPU time 404.4 seconds
Started Apr 02 02:19:40 PM PDT 24
Finished Apr 02 02:26:25 PM PDT 24
Peak memory 208784 kb
Host smart-ab4200c0-1795-4aeb-91ab-03c6313f6ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178814012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4178814012
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1807580017
Short name T624
Test name
Test status
Simulation time 1052864847 ps
CPU time 2.77 seconds
Started Apr 02 02:19:35 PM PDT 24
Finished Apr 02 02:19:38 PM PDT 24
Peak memory 199176 kb
Host smart-f48b94e6-2d74-40cd-9170-600caa066f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807580017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1807580017
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1035251204
Short name T770
Test name
Test status
Simulation time 31986697222 ps
CPU time 54.72 seconds
Started Apr 02 02:19:30 PM PDT 24
Finished Apr 02 02:20:25 PM PDT 24
Peak memory 200388 kb
Host smart-44ae6efb-1307-46d0-b338-666b4d26768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035251204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1035251204
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2123151307
Short name T1178
Test name
Test status
Simulation time 54968508 ps
CPU time 0.52 seconds
Started Apr 02 02:19:48 PM PDT 24
Finished Apr 02 02:19:48 PM PDT 24
Peak memory 195884 kb
Host smart-e42378ad-18ad-4564-a94b-b761467bf895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123151307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2123151307
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2923321713
Short name T726
Test name
Test status
Simulation time 27035403316 ps
CPU time 25.09 seconds
Started Apr 02 02:19:39 PM PDT 24
Finished Apr 02 02:20:04 PM PDT 24
Peak memory 200368 kb
Host smart-e004cca1-3264-413c-b4f4-a49201211e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923321713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2923321713
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3424886423
Short name T906
Test name
Test status
Simulation time 209376719929 ps
CPU time 342.67 seconds
Started Apr 02 02:19:40 PM PDT 24
Finished Apr 02 02:25:23 PM PDT 24
Peak memory 200436 kb
Host smart-f72beac3-1984-4214-9526-ac1f392b4f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424886423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3424886423
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.549423418
Short name T904
Test name
Test status
Simulation time 23912889526 ps
CPU time 38.92 seconds
Started Apr 02 02:19:41 PM PDT 24
Finished Apr 02 02:20:20 PM PDT 24
Peak memory 200280 kb
Host smart-174f5bb4-0b57-4b52-ad2b-adaf56a8ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549423418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.549423418
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3720724393
Short name T653
Test name
Test status
Simulation time 11516397302 ps
CPU time 18.12 seconds
Started Apr 02 02:19:41 PM PDT 24
Finished Apr 02 02:19:59 PM PDT 24
Peak memory 196580 kb
Host smart-de5638ba-826c-4752-84fb-78ccc892cee6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720724393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3720724393
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.193519543
Short name T1146
Test name
Test status
Simulation time 131844174529 ps
CPU time 211.6 seconds
Started Apr 02 02:19:49 PM PDT 24
Finished Apr 02 02:23:21 PM PDT 24
Peak memory 200460 kb
Host smart-24ac64ca-3cac-4e61-bfdd-ce88f30f90e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193519543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.193519543
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.4021132827
Short name T522
Test name
Test status
Simulation time 4784745714 ps
CPU time 11.65 seconds
Started Apr 02 02:19:44 PM PDT 24
Finished Apr 02 02:19:56 PM PDT 24
Peak memory 199292 kb
Host smart-86522e52-53c7-440e-92c1-a590ecd6f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021132827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.4021132827
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1885562685
Short name T501
Test name
Test status
Simulation time 48621159242 ps
CPU time 146.17 seconds
Started Apr 02 02:19:41 PM PDT 24
Finished Apr 02 02:22:08 PM PDT 24
Peak memory 199328 kb
Host smart-c40c5e75-adf1-4207-89ca-596e26239df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885562685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1885562685
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1092784544
Short name T1062
Test name
Test status
Simulation time 3193299154 ps
CPU time 14.55 seconds
Started Apr 02 02:19:41 PM PDT 24
Finished Apr 02 02:19:55 PM PDT 24
Peak memory 198848 kb
Host smart-1cb83ce1-0a93-4de3-aaf8-4eb11f477277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092784544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1092784544
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1301453867
Short name T287
Test name
Test status
Simulation time 34832064357 ps
CPU time 55.01 seconds
Started Apr 02 02:19:43 PM PDT 24
Finished Apr 02 02:20:39 PM PDT 24
Peak memory 200484 kb
Host smart-ebacec30-7ee7-40db-ab77-64d76d480ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301453867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1301453867
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1273084169
Short name T421
Test name
Test status
Simulation time 39649428758 ps
CPU time 12.26 seconds
Started Apr 02 02:19:44 PM PDT 24
Finished Apr 02 02:19:56 PM PDT 24
Peak memory 196180 kb
Host smart-6229941e-95df-4113-8952-7268a9097408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273084169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1273084169
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1019651243
Short name T1151
Test name
Test status
Simulation time 113478639 ps
CPU time 0.78 seconds
Started Apr 02 02:19:41 PM PDT 24
Finished Apr 02 02:19:42 PM PDT 24
Peak memory 197400 kb
Host smart-231091d1-ed31-4e2c-8d23-ef909cc19c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019651243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1019651243
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1867954498
Short name T493
Test name
Test status
Simulation time 32346432815 ps
CPU time 1225.07 seconds
Started Apr 02 02:19:49 PM PDT 24
Finished Apr 02 02:40:14 PM PDT 24
Peak memory 217224 kb
Host smart-c86ed853-605e-481d-b99e-83acfb1ff503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867954498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1867954498
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.547508884
Short name T485
Test name
Test status
Simulation time 6330709418 ps
CPU time 15.11 seconds
Started Apr 02 02:19:46 PM PDT 24
Finished Apr 02 02:20:01 PM PDT 24
Peak memory 199868 kb
Host smart-01c06a67-5a09-4f50-9a93-c2e4e80c1ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547508884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.547508884
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.72732071
Short name T325
Test name
Test status
Simulation time 14980225711 ps
CPU time 11.9 seconds
Started Apr 02 02:19:39 PM PDT 24
Finished Apr 02 02:19:52 PM PDT 24
Peak memory 200516 kb
Host smart-61fc78cd-4fec-4968-b397-ee24fb23f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72732071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.72732071
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.15342837
Short name T549
Test name
Test status
Simulation time 29724183 ps
CPU time 0.52 seconds
Started Apr 02 02:12:29 PM PDT 24
Finished Apr 02 02:12:30 PM PDT 24
Peak memory 194884 kb
Host smart-b899b7e3-0b26-49a1-9515-4f56f6f90784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15342837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.15342837
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1872915440
Short name T596
Test name
Test status
Simulation time 52407673034 ps
CPU time 76.58 seconds
Started Apr 02 02:12:15 PM PDT 24
Finished Apr 02 02:13:32 PM PDT 24
Peak memory 200532 kb
Host smart-d5ad9469-9e74-46e0-bfb3-7dae2f9e9a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872915440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1872915440
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.232176143
Short name T638
Test name
Test status
Simulation time 44072955515 ps
CPU time 70.97 seconds
Started Apr 02 02:12:17 PM PDT 24
Finished Apr 02 02:13:28 PM PDT 24
Peak memory 200492 kb
Host smart-c64c7947-9696-4dfb-b330-47617ea8fc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232176143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.232176143
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3994714060
Short name T272
Test name
Test status
Simulation time 173515948647 ps
CPU time 204.67 seconds
Started Apr 02 02:12:27 PM PDT 24
Finished Apr 02 02:15:53 PM PDT 24
Peak memory 200340 kb
Host smart-2d54534e-f016-4d87-b6a8-85b18c42ea45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994714060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3994714060
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1986087600
Short name T1144
Test name
Test status
Simulation time 117124608 ps
CPU time 0.7 seconds
Started Apr 02 02:12:24 PM PDT 24
Finished Apr 02 02:12:25 PM PDT 24
Peak memory 196488 kb
Host smart-e380273b-21e3-43f3-98d6-6a7df3e86b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986087600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1986087600
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.819046976
Short name T727
Test name
Test status
Simulation time 92582359990 ps
CPU time 154.83 seconds
Started Apr 02 02:12:19 PM PDT 24
Finished Apr 02 02:14:54 PM PDT 24
Peak memory 200564 kb
Host smart-5a145459-c565-4e10-8513-cf0e997b185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819046976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.819046976
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3662444890
Short name T262
Test name
Test status
Simulation time 11183690450 ps
CPU time 144.97 seconds
Started Apr 02 02:12:26 PM PDT 24
Finished Apr 02 02:14:52 PM PDT 24
Peak memory 200352 kb
Host smart-753b9a81-46ad-42b4-816c-ef60a934fa0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662444890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3662444890
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2479883382
Short name T18
Test name
Test status
Simulation time 7517987061 ps
CPU time 64.07 seconds
Started Apr 02 02:12:15 PM PDT 24
Finished Apr 02 02:13:19 PM PDT 24
Peak memory 199780 kb
Host smart-ff3929b9-dd38-43c5-89b2-47631d8fa92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479883382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2479883382
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3092047509
Short name T872
Test name
Test status
Simulation time 46378142373 ps
CPU time 68.35 seconds
Started Apr 02 02:12:19 PM PDT 24
Finished Apr 02 02:13:28 PM PDT 24
Peak memory 199504 kb
Host smart-fd896444-e07d-4a93-bc2c-e59979f53023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092047509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3092047509
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.943025674
Short name T1092
Test name
Test status
Simulation time 547863289 ps
CPU time 1.03 seconds
Started Apr 02 02:12:20 PM PDT 24
Finished Apr 02 02:12:21 PM PDT 24
Peak memory 195828 kb
Host smart-e856a1ef-e060-4f43-a698-5f9b1dc58fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943025674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.943025674
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3723960424
Short name T28
Test name
Test status
Simulation time 381807347 ps
CPU time 0.86 seconds
Started Apr 02 02:12:26 PM PDT 24
Finished Apr 02 02:12:27 PM PDT 24
Peak memory 218936 kb
Host smart-a76e0a86-4fb6-4e0b-914a-16957cbbf110
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723960424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3723960424
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2641572161
Short name T400
Test name
Test status
Simulation time 11562165654 ps
CPU time 20.89 seconds
Started Apr 02 02:12:10 PM PDT 24
Finished Apr 02 02:12:31 PM PDT 24
Peak memory 200296 kb
Host smart-792244ee-21b1-45dc-88ca-c1db83b1bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641572161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2641572161
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2669925950
Short name T689
Test name
Test status
Simulation time 325591638803 ps
CPU time 836.11 seconds
Started Apr 02 02:12:25 PM PDT 24
Finished Apr 02 02:26:21 PM PDT 24
Peak memory 200396 kb
Host smart-6f154ffa-d75c-4cc5-a01c-657df4e92d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669925950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2669925950
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3155540855
Short name T24
Test name
Test status
Simulation time 14177118353 ps
CPU time 164.01 seconds
Started Apr 02 02:12:26 PM PDT 24
Finished Apr 02 02:15:10 PM PDT 24
Peak memory 210096 kb
Host smart-7e23a184-e5a7-43d8-ac9e-f2a270d7e98c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155540855 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3155540855
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1064190992
Short name T609
Test name
Test status
Simulation time 12835989903 ps
CPU time 18.85 seconds
Started Apr 02 02:12:24 PM PDT 24
Finished Apr 02 02:12:43 PM PDT 24
Peak memory 200288 kb
Host smart-8da95983-8ea4-4b88-8819-091d505c93b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064190992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1064190992
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.482994394
Short name T759
Test name
Test status
Simulation time 98499126505 ps
CPU time 185.96 seconds
Started Apr 02 02:12:15 PM PDT 24
Finished Apr 02 02:15:21 PM PDT 24
Peak memory 200352 kb
Host smart-302fa380-8528-41ac-99ce-20c8108421b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482994394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.482994394
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3664598375
Short name T961
Test name
Test status
Simulation time 13977430 ps
CPU time 0.55 seconds
Started Apr 02 02:20:01 PM PDT 24
Finished Apr 02 02:20:01 PM PDT 24
Peak memory 195764 kb
Host smart-182215f8-1262-4d2c-98b4-ebee5cc3c823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664598375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3664598375
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2294137050
Short name T660
Test name
Test status
Simulation time 117515607735 ps
CPU time 357.76 seconds
Started Apr 02 02:19:52 PM PDT 24
Finished Apr 02 02:25:50 PM PDT 24
Peak memory 200520 kb
Host smart-92c64428-eaa1-46e4-b962-723f6b3da6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294137050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2294137050
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2203565970
Short name T558
Test name
Test status
Simulation time 73551814258 ps
CPU time 37.9 seconds
Started Apr 02 02:19:54 PM PDT 24
Finished Apr 02 02:20:32 PM PDT 24
Peak memory 200396 kb
Host smart-f6fa712b-240c-4efb-b0fc-496576eec938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203565970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2203565970
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.3018028508
Short name T499
Test name
Test status
Simulation time 147289578336 ps
CPU time 223.15 seconds
Started Apr 02 02:19:55 PM PDT 24
Finished Apr 02 02:23:38 PM PDT 24
Peak memory 198860 kb
Host smart-0089e350-4dd9-4e32-8f35-9d702d77dfa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018028508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3018028508
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.949363726
Short name T303
Test name
Test status
Simulation time 78006910341 ps
CPU time 158.08 seconds
Started Apr 02 02:19:59 PM PDT 24
Finished Apr 02 02:22:37 PM PDT 24
Peak memory 200464 kb
Host smart-18f8f43b-6704-4138-8bec-43a7eeb743d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=949363726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.949363726
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2683909606
Short name T455
Test name
Test status
Simulation time 2755123879 ps
CPU time 2.84 seconds
Started Apr 02 02:20:01 PM PDT 24
Finished Apr 02 02:20:04 PM PDT 24
Peak memory 199696 kb
Host smart-54e119e1-27d2-4430-8576-84b0721a8bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683909606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2683909606
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.178207561
Short name T776
Test name
Test status
Simulation time 8635332444 ps
CPU time 13.92 seconds
Started Apr 02 02:19:55 PM PDT 24
Finished Apr 02 02:20:09 PM PDT 24
Peak memory 195776 kb
Host smart-c028e364-ea5f-40eb-9056-f5e5b0392a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178207561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.178207561
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3757622951
Short name T628
Test name
Test status
Simulation time 15975977281 ps
CPU time 795.42 seconds
Started Apr 02 02:19:58 PM PDT 24
Finished Apr 02 02:33:13 PM PDT 24
Peak memory 200428 kb
Host smart-a98e054c-e627-47de-a332-08b826cd82c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757622951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3757622951
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4270719886
Short name T8
Test name
Test status
Simulation time 2926378429 ps
CPU time 6.94 seconds
Started Apr 02 02:19:56 PM PDT 24
Finished Apr 02 02:20:03 PM PDT 24
Peak memory 199452 kb
Host smart-1bb13a75-b436-4311-aebe-5ddd7c15673c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270719886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4270719886
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3882270056
Short name T784
Test name
Test status
Simulation time 97434632241 ps
CPU time 77.84 seconds
Started Apr 02 02:19:58 PM PDT 24
Finished Apr 02 02:21:16 PM PDT 24
Peak memory 200464 kb
Host smart-1d44278b-4039-40e7-880c-8c9ef8052543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882270056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3882270056
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1365533939
Short name T312
Test name
Test status
Simulation time 3381703732 ps
CPU time 5.89 seconds
Started Apr 02 02:19:54 PM PDT 24
Finished Apr 02 02:20:00 PM PDT 24
Peak memory 196264 kb
Host smart-02c5b952-6e5d-49d6-b2b0-b386fc49c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365533939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1365533939
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2148402892
Short name T666
Test name
Test status
Simulation time 504736747 ps
CPU time 3.56 seconds
Started Apr 02 02:19:48 PM PDT 24
Finished Apr 02 02:19:51 PM PDT 24
Peak memory 199304 kb
Host smart-d33a05fa-47f3-40a6-936a-e1ad2ceebc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148402892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2148402892
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1468907624
Short name T709
Test name
Test status
Simulation time 90516694269 ps
CPU time 140.18 seconds
Started Apr 02 02:20:03 PM PDT 24
Finished Apr 02 02:22:24 PM PDT 24
Peak memory 200452 kb
Host smart-a6e8f492-8bd2-49c2-bbda-a0ee8690341c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468907624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1468907624
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2614524156
Short name T61
Test name
Test status
Simulation time 413992907805 ps
CPU time 550.16 seconds
Started Apr 02 02:20:01 PM PDT 24
Finished Apr 02 02:29:12 PM PDT 24
Peak memory 225340 kb
Host smart-a5326a10-ad68-4e5b-904a-cc4449dd56bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614524156 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2614524156
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1862092802
Short name T76
Test name
Test status
Simulation time 932798290 ps
CPU time 1.67 seconds
Started Apr 02 02:19:58 PM PDT 24
Finished Apr 02 02:20:00 PM PDT 24
Peak memory 199132 kb
Host smart-0f27b1e3-0696-4f49-aa06-0b9745054149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862092802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1862092802
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2151958885
Short name T295
Test name
Test status
Simulation time 44311045464 ps
CPU time 70.99 seconds
Started Apr 02 02:19:52 PM PDT 24
Finished Apr 02 02:21:03 PM PDT 24
Peak memory 200432 kb
Host smart-fb770aa9-67b8-4f6c-a8ba-f5a55f589292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151958885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2151958885
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3888085001
Short name T1007
Test name
Test status
Simulation time 52269962 ps
CPU time 0.54 seconds
Started Apr 02 02:20:16 PM PDT 24
Finished Apr 02 02:20:17 PM PDT 24
Peak memory 195780 kb
Host smart-d7a9ee79-3359-4dc2-b88f-1601e8f48d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888085001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3888085001
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3123381100
Short name T912
Test name
Test status
Simulation time 58972454195 ps
CPU time 45.7 seconds
Started Apr 02 02:20:04 PM PDT 24
Finished Apr 02 02:20:50 PM PDT 24
Peak memory 200472 kb
Host smart-a45b03df-38ff-4f70-a528-a32df7c27e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123381100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3123381100
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3515260601
Short name T730
Test name
Test status
Simulation time 67265045059 ps
CPU time 118.58 seconds
Started Apr 02 02:20:03 PM PDT 24
Finished Apr 02 02:22:02 PM PDT 24
Peak memory 200432 kb
Host smart-b39ce3ab-c079-4e26-a859-4923d7b85254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515260601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3515260601
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3338283854
Short name T953
Test name
Test status
Simulation time 75445737939 ps
CPU time 56.14 seconds
Started Apr 02 02:20:01 PM PDT 24
Finished Apr 02 02:20:57 PM PDT 24
Peak memory 200392 kb
Host smart-895e1658-6e32-40ee-8651-55d1d896baa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338283854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3338283854
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4220495208
Short name T846
Test name
Test status
Simulation time 21117046399 ps
CPU time 7.77 seconds
Started Apr 02 02:20:06 PM PDT 24
Finished Apr 02 02:20:13 PM PDT 24
Peak memory 198108 kb
Host smart-de833d68-d946-406c-b322-c2b8093ce511
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220495208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4220495208
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1006494191
Short name T1033
Test name
Test status
Simulation time 167290778309 ps
CPU time 310.02 seconds
Started Apr 02 02:20:09 PM PDT 24
Finished Apr 02 02:25:19 PM PDT 24
Peak memory 200408 kb
Host smart-07db48e9-107d-41d2-8e38-bd041f1096b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006494191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1006494191
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.228816207
Short name T343
Test name
Test status
Simulation time 1578180759 ps
CPU time 3.43 seconds
Started Apr 02 02:20:10 PM PDT 24
Finished Apr 02 02:20:14 PM PDT 24
Peak memory 197972 kb
Host smart-72293968-81cb-4471-96fc-256a3164b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228816207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.228816207
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3949525018
Short name T1169
Test name
Test status
Simulation time 34694439670 ps
CPU time 29.73 seconds
Started Apr 02 02:20:05 PM PDT 24
Finished Apr 02 02:20:35 PM PDT 24
Peak memory 199200 kb
Host smart-1957e56f-84f3-4e64-9760-84b9894dc860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949525018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3949525018
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1860352181
Short name T810
Test name
Test status
Simulation time 15065220241 ps
CPU time 172.6 seconds
Started Apr 02 02:20:08 PM PDT 24
Finished Apr 02 02:23:01 PM PDT 24
Peak memory 200464 kb
Host smart-dc0868a9-7b6f-45c0-b241-a7d9a4a38eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860352181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1860352181
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1521875025
Short name T1079
Test name
Test status
Simulation time 4645683990 ps
CPU time 16.78 seconds
Started Apr 02 02:20:03 PM PDT 24
Finished Apr 02 02:20:20 PM PDT 24
Peak memory 199732 kb
Host smart-97ebaf1a-d9d6-441d-8862-2839f88ccd57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521875025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1521875025
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2940713398
Short name T523
Test name
Test status
Simulation time 114085219370 ps
CPU time 48.24 seconds
Started Apr 02 02:20:07 PM PDT 24
Finished Apr 02 02:20:55 PM PDT 24
Peak memory 200408 kb
Host smart-7e7d84e8-3efc-4071-88d8-6f69853e8f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940713398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2940713398
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3922297884
Short name T541
Test name
Test status
Simulation time 2237148511 ps
CPU time 2.49 seconds
Started Apr 02 02:20:05 PM PDT 24
Finished Apr 02 02:20:08 PM PDT 24
Peak memory 195928 kb
Host smart-da2c02fd-5461-4615-aba6-56f3dbcb1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922297884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3922297884
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3575353834
Short name T427
Test name
Test status
Simulation time 673406871 ps
CPU time 1.73 seconds
Started Apr 02 02:20:02 PM PDT 24
Finished Apr 02 02:20:04 PM PDT 24
Peak memory 199928 kb
Host smart-d5b60179-8d62-4b4d-b61b-a5dd90815a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575353834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3575353834
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3151519013
Short name T787
Test name
Test status
Simulation time 226663335931 ps
CPU time 584.69 seconds
Started Apr 02 02:20:10 PM PDT 24
Finished Apr 02 02:29:55 PM PDT 24
Peak memory 216956 kb
Host smart-189c92d4-c4ef-404f-abd6-32e1d966ff07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151519013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3151519013
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3515622314
Short name T700
Test name
Test status
Simulation time 307371580 ps
CPU time 1.2 seconds
Started Apr 02 02:20:09 PM PDT 24
Finished Apr 02 02:20:10 PM PDT 24
Peak memory 198464 kb
Host smart-08f79d0e-fac9-4aca-906d-6dc4877a1a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515622314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3515622314
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.784141555
Short name T133
Test name
Test status
Simulation time 159028446212 ps
CPU time 36.8 seconds
Started Apr 02 02:20:02 PM PDT 24
Finished Apr 02 02:20:39 PM PDT 24
Peak memory 200528 kb
Host smart-04ed2cbd-be73-44a3-9164-8f15e6b2c112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784141555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.784141555
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3814699770
Short name T943
Test name
Test status
Simulation time 17379161 ps
CPU time 0.53 seconds
Started Apr 02 02:20:24 PM PDT 24
Finished Apr 02 02:20:25 PM PDT 24
Peak memory 195356 kb
Host smart-33c3757f-522a-4375-83e1-40e210f82e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814699770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3814699770
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3754350938
Short name T442
Test name
Test status
Simulation time 183771176285 ps
CPU time 551.8 seconds
Started Apr 02 02:20:20 PM PDT 24
Finished Apr 02 02:29:32 PM PDT 24
Peak memory 200488 kb
Host smart-a3a2a51e-efb3-4815-bb37-14e54653d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754350938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3754350938
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1613693260
Short name T355
Test name
Test status
Simulation time 53918781807 ps
CPU time 18.21 seconds
Started Apr 02 02:20:15 PM PDT 24
Finished Apr 02 02:20:34 PM PDT 24
Peak memory 200484 kb
Host smart-a14c520b-594f-47a9-a2a1-706d3bcd0040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613693260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1613693260
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3579335682
Short name T134
Test name
Test status
Simulation time 6410241290 ps
CPU time 6.16 seconds
Started Apr 02 02:20:17 PM PDT 24
Finished Apr 02 02:20:24 PM PDT 24
Peak memory 200444 kb
Host smart-7d9c57be-3fe0-4c40-86cf-ff4253545b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579335682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3579335682
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1107058088
Short name T72
Test name
Test status
Simulation time 47685193706 ps
CPU time 22.74 seconds
Started Apr 02 02:20:17 PM PDT 24
Finished Apr 02 02:20:40 PM PDT 24
Peak memory 200396 kb
Host smart-6546a4f9-0a21-4e9a-abb7-3867cbf1672d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107058088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1107058088
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4032539805
Short name T834
Test name
Test status
Simulation time 86565073843 ps
CPU time 143.3 seconds
Started Apr 02 02:20:22 PM PDT 24
Finished Apr 02 02:22:45 PM PDT 24
Peak memory 200424 kb
Host smart-89b6b936-2cd0-45a5-bf82-d2b4ecedd9ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032539805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4032539805
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.129207812
Short name T476
Test name
Test status
Simulation time 5222333241 ps
CPU time 8.54 seconds
Started Apr 02 02:20:19 PM PDT 24
Finished Apr 02 02:20:28 PM PDT 24
Peak memory 197192 kb
Host smart-861ed72f-dd82-48a7-899f-8c808e82f346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129207812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.129207812
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1875438332
Short name T348
Test name
Test status
Simulation time 113287726342 ps
CPU time 113.39 seconds
Started Apr 02 02:20:18 PM PDT 24
Finished Apr 02 02:22:12 PM PDT 24
Peak memory 200708 kb
Host smart-02ce515a-afaf-4acd-88d7-6e3bc88b9ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875438332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1875438332
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1744422100
Short name T393
Test name
Test status
Simulation time 11718471521 ps
CPU time 707.75 seconds
Started Apr 02 02:20:19 PM PDT 24
Finished Apr 02 02:32:07 PM PDT 24
Peak memory 200500 kb
Host smart-22ef0d70-1a5c-4d03-8789-eb235cc5d5d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1744422100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1744422100
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.157656026
Short name T854
Test name
Test status
Simulation time 3160152304 ps
CPU time 24.95 seconds
Started Apr 02 02:20:16 PM PDT 24
Finished Apr 02 02:20:41 PM PDT 24
Peak memory 198844 kb
Host smart-35f3b574-1bdc-4b03-992a-4882d7a67303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=157656026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.157656026
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.343551690
Short name T317
Test name
Test status
Simulation time 274752939268 ps
CPU time 73.06 seconds
Started Apr 02 02:20:16 PM PDT 24
Finished Apr 02 02:21:30 PM PDT 24
Peak memory 200120 kb
Host smart-ef587fa4-4ba7-43e9-9348-6db982222f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343551690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.343551690
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.116709517
Short name T926
Test name
Test status
Simulation time 3870599264 ps
CPU time 3.35 seconds
Started Apr 02 02:20:17 PM PDT 24
Finished Apr 02 02:20:21 PM PDT 24
Peak memory 196832 kb
Host smart-2cd7d5f2-9a67-48ee-a3c2-95202e512086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116709517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.116709517
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4160157210
Short name T647
Test name
Test status
Simulation time 501476923 ps
CPU time 1.45 seconds
Started Apr 02 02:20:13 PM PDT 24
Finished Apr 02 02:20:15 PM PDT 24
Peak memory 198800 kb
Host smart-34a9a427-4498-4bb0-a733-d5502fef974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160157210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4160157210
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.2311742299
Short name T796
Test name
Test status
Simulation time 254153980133 ps
CPU time 140.22 seconds
Started Apr 02 02:20:25 PM PDT 24
Finished Apr 02 02:22:45 PM PDT 24
Peak memory 216712 kb
Host smart-38f4050d-8a9a-4ccb-8cbe-c3ed99587c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311742299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2311742299
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2232225279
Short name T80
Test name
Test status
Simulation time 51872517078 ps
CPU time 667.83 seconds
Started Apr 02 02:20:23 PM PDT 24
Finished Apr 02 02:31:31 PM PDT 24
Peak memory 216900 kb
Host smart-95d014e4-717c-45f6-b16f-a3d3f6e0ee11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232225279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2232225279
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2904623428
Short name T1080
Test name
Test status
Simulation time 1160038032 ps
CPU time 3.81 seconds
Started Apr 02 02:20:21 PM PDT 24
Finished Apr 02 02:20:25 PM PDT 24
Peak memory 199012 kb
Host smart-87bdcf28-125b-4449-af25-beb7c119da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904623428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2904623428
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3318086286
Short name T934
Test name
Test status
Simulation time 23685588106 ps
CPU time 27.52 seconds
Started Apr 02 02:20:14 PM PDT 24
Finished Apr 02 02:20:42 PM PDT 24
Peak memory 200384 kb
Host smart-8709a151-a5ba-4893-b85e-6341c91c5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318086286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3318086286
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.961917638
Short name T826
Test name
Test status
Simulation time 12195360 ps
CPU time 0.52 seconds
Started Apr 02 02:20:41 PM PDT 24
Finished Apr 02 02:20:42 PM PDT 24
Peak memory 194776 kb
Host smart-af348e62-1712-40c9-bba3-dfe8e8eab033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961917638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.961917638
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.358494956
Short name T815
Test name
Test status
Simulation time 208104055214 ps
CPU time 78.15 seconds
Started Apr 02 02:20:27 PM PDT 24
Finished Apr 02 02:21:46 PM PDT 24
Peak memory 200504 kb
Host smart-577e2895-1e9f-475b-9180-14764a760283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358494956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.358494956
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1728388034
Short name T528
Test name
Test status
Simulation time 68419194618 ps
CPU time 29.14 seconds
Started Apr 02 02:20:30 PM PDT 24
Finished Apr 02 02:20:59 PM PDT 24
Peak memory 200452 kb
Host smart-d0cb068b-5a93-4769-b453-f3a4c7bf1283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728388034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1728388034
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.687338978
Short name T231
Test name
Test status
Simulation time 132397723403 ps
CPU time 206.69 seconds
Started Apr 02 02:20:28 PM PDT 24
Finished Apr 02 02:23:55 PM PDT 24
Peak memory 200496 kb
Host smart-4c71c3f9-dd74-4a58-880c-8ce9cb3f18d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687338978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.687338978
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2199220459
Short name T636
Test name
Test status
Simulation time 4535623749 ps
CPU time 12.65 seconds
Started Apr 02 02:20:34 PM PDT 24
Finished Apr 02 02:20:47 PM PDT 24
Peak memory 200496 kb
Host smart-b44f1e94-408f-4d74-a0a9-5208b5c4be4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199220459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2199220459
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3808897117
Short name T404
Test name
Test status
Simulation time 115920686636 ps
CPU time 909.8 seconds
Started Apr 02 02:20:36 PM PDT 24
Finished Apr 02 02:35:47 PM PDT 24
Peak memory 200436 kb
Host smart-97e6e912-9744-4ac9-a46d-01d3005751e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808897117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3808897117
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.151172543
Short name T437
Test name
Test status
Simulation time 9571458785 ps
CPU time 12.62 seconds
Started Apr 02 02:20:34 PM PDT 24
Finished Apr 02 02:20:46 PM PDT 24
Peak memory 200124 kb
Host smart-6ddc524b-d441-40d4-afd2-00f04f54f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151172543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.151172543
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.440151219
Short name T277
Test name
Test status
Simulation time 106645285552 ps
CPU time 156.72 seconds
Started Apr 02 02:20:34 PM PDT 24
Finished Apr 02 02:23:11 PM PDT 24
Peak memory 200748 kb
Host smart-102f55af-bb1b-48b9-8aa5-7a8884e468f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440151219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.440151219
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1793191882
Short name T1006
Test name
Test status
Simulation time 5654184668 ps
CPU time 225.32 seconds
Started Apr 02 02:20:36 PM PDT 24
Finished Apr 02 02:24:22 PM PDT 24
Peak memory 200484 kb
Host smart-24c45266-cefc-4feb-b2b0-1e77ef5535cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793191882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1793191882
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3642084691
Short name T1041
Test name
Test status
Simulation time 6975809146 ps
CPU time 10.89 seconds
Started Apr 02 02:20:28 PM PDT 24
Finished Apr 02 02:20:39 PM PDT 24
Peak memory 200368 kb
Host smart-d735af9b-70f4-46e7-87a3-5edd3106926f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3642084691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3642084691
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3601920934
Short name T154
Test name
Test status
Simulation time 148652500409 ps
CPU time 62.49 seconds
Started Apr 02 02:20:34 PM PDT 24
Finished Apr 02 02:21:36 PM PDT 24
Peak memory 200532 kb
Host smart-77db75b8-8f78-4501-9fad-13838f39eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601920934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3601920934
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2612816841
Short name T332
Test name
Test status
Simulation time 68152125117 ps
CPU time 27.89 seconds
Started Apr 02 02:20:33 PM PDT 24
Finished Apr 02 02:21:01 PM PDT 24
Peak memory 196228 kb
Host smart-db23b0b4-adb0-499c-8782-ecad8f79ad42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612816841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2612816841
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1000352225
Short name T885
Test name
Test status
Simulation time 5882776738 ps
CPU time 14.28 seconds
Started Apr 02 02:20:29 PM PDT 24
Finished Apr 02 02:20:43 PM PDT 24
Peak memory 200464 kb
Host smart-ab1273a9-68ea-47d1-a401-48772baf624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000352225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1000352225
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3934447342
Short name T928
Test name
Test status
Simulation time 763180043954 ps
CPU time 866.29 seconds
Started Apr 02 02:20:38 PM PDT 24
Finished Apr 02 02:35:05 PM PDT 24
Peak memory 208992 kb
Host smart-1891cd2d-36b9-4763-abed-9321cc7155b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934447342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3934447342
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.489584036
Short name T1055
Test name
Test status
Simulation time 43042835062 ps
CPU time 123.12 seconds
Started Apr 02 02:20:36 PM PDT 24
Finished Apr 02 02:22:40 PM PDT 24
Peak memory 211244 kb
Host smart-cdc1cd7c-9577-4f06-9e6e-0906fce6b982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489584036 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.489584036
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3884168999
Short name T408
Test name
Test status
Simulation time 7469332000 ps
CPU time 12.5 seconds
Started Apr 02 02:20:32 PM PDT 24
Finished Apr 02 02:20:45 PM PDT 24
Peak memory 200420 kb
Host smart-43bedb4e-6c8d-4cd8-aa7a-d801285767ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884168999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3884168999
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2984809612
Short name T1013
Test name
Test status
Simulation time 116020825375 ps
CPU time 309.21 seconds
Started Apr 02 02:20:29 PM PDT 24
Finished Apr 02 02:25:38 PM PDT 24
Peak memory 200436 kb
Host smart-3c136b86-2389-4c06-afc0-b30c7719b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984809612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2984809612
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.409498070
Short name T365
Test name
Test status
Simulation time 45766970 ps
CPU time 0.55 seconds
Started Apr 02 02:20:52 PM PDT 24
Finished Apr 02 02:20:54 PM PDT 24
Peak memory 194920 kb
Host smart-583c0ffe-f02d-46b4-b5a6-36f67c8ad018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409498070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.409498070
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1746272385
Short name T625
Test name
Test status
Simulation time 81300123248 ps
CPU time 94.58 seconds
Started Apr 02 02:20:42 PM PDT 24
Finished Apr 02 02:22:17 PM PDT 24
Peak memory 200456 kb
Host smart-ffd485d5-fc07-4460-9461-9b7ff2eb40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746272385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1746272385
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1709775285
Short name T572
Test name
Test status
Simulation time 30066415789 ps
CPU time 14.01 seconds
Started Apr 02 02:20:42 PM PDT 24
Finished Apr 02 02:20:56 PM PDT 24
Peak memory 199820 kb
Host smart-d0efbc1e-e851-469e-9c04-fd36f9557db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709775285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1709775285
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3546735426
Short name T863
Test name
Test status
Simulation time 104075170030 ps
CPU time 47.01 seconds
Started Apr 02 02:20:45 PM PDT 24
Finished Apr 02 02:21:32 PM PDT 24
Peak memory 200480 kb
Host smart-900571f4-7474-403b-84f7-78f5d12f13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546735426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3546735426
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2922902617
Short name T1027
Test name
Test status
Simulation time 51055420530 ps
CPU time 70.57 seconds
Started Apr 02 02:20:43 PM PDT 24
Finished Apr 02 02:21:54 PM PDT 24
Peak memory 196608 kb
Host smart-799e8e26-ce72-4a5a-b9f5-76a781a87c6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922902617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2922902617
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.811375955
Short name T995
Test name
Test status
Simulation time 121653030427 ps
CPU time 471.79 seconds
Started Apr 02 02:20:52 PM PDT 24
Finished Apr 02 02:28:45 PM PDT 24
Peak memory 200352 kb
Host smart-38eb0565-2164-42f4-8b41-9d4795999fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811375955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.811375955
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3639008823
Short name T896
Test name
Test status
Simulation time 8455788254 ps
CPU time 3.43 seconds
Started Apr 02 02:20:49 PM PDT 24
Finished Apr 02 02:20:54 PM PDT 24
Peak memory 200296 kb
Host smart-e66d129a-fe77-44d0-aed1-57843035f277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639008823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3639008823
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2415293004
Short name T304
Test name
Test status
Simulation time 62199625542 ps
CPU time 135.45 seconds
Started Apr 02 02:20:48 PM PDT 24
Finished Apr 02 02:23:04 PM PDT 24
Peak memory 208984 kb
Host smart-5643e456-4ff5-462f-89f8-decd4a5bb13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415293004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2415293004
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1073279733
Short name T1110
Test name
Test status
Simulation time 16966497445 ps
CPU time 460.98 seconds
Started Apr 02 02:20:48 PM PDT 24
Finished Apr 02 02:28:29 PM PDT 24
Peak memory 200496 kb
Host smart-bc2c2159-2ed8-494e-9ebd-e7f726812714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1073279733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1073279733
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4232090639
Short name T585
Test name
Test status
Simulation time 1376506444 ps
CPU time 2.76 seconds
Started Apr 02 02:20:43 PM PDT 24
Finished Apr 02 02:20:47 PM PDT 24
Peak memory 198344 kb
Host smart-817228ab-b7d5-4bb9-a5eb-971be743ec91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232090639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4232090639
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.838019143
Short name T165
Test name
Test status
Simulation time 239179277133 ps
CPU time 74.98 seconds
Started Apr 02 02:20:47 PM PDT 24
Finished Apr 02 02:22:02 PM PDT 24
Peak memory 200132 kb
Host smart-0b5b6aeb-6ebd-4d64-95b7-46b080172c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838019143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.838019143
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3188906442
Short name T319
Test name
Test status
Simulation time 2624387814 ps
CPU time 1.62 seconds
Started Apr 02 02:20:47 PM PDT 24
Finished Apr 02 02:20:49 PM PDT 24
Peak memory 196204 kb
Host smart-1631e4ad-a137-4f55-9525-ebd62de7b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188906442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3188906442
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1184275428
Short name T749
Test name
Test status
Simulation time 554512046 ps
CPU time 2.91 seconds
Started Apr 02 02:20:41 PM PDT 24
Finished Apr 02 02:20:44 PM PDT 24
Peak memory 200036 kb
Host smart-b0bff048-fbd0-4781-8f55-52d72a821418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184275428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1184275428
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2284369577
Short name T234
Test name
Test status
Simulation time 338195553199 ps
CPU time 97.9 seconds
Started Apr 02 02:20:52 PM PDT 24
Finished Apr 02 02:22:30 PM PDT 24
Peak memory 200480 kb
Host smart-7b40136e-82c7-44d2-a63c-2992b3c28275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284369577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2284369577
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3026187481
Short name T113
Test name
Test status
Simulation time 12285336101 ps
CPU time 110.71 seconds
Started Apr 02 02:20:51 PM PDT 24
Finished Apr 02 02:22:42 PM PDT 24
Peak memory 208784 kb
Host smart-0acc187b-abed-4370-aa52-26b7ab069d9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026187481 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3026187481
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1672317879
Short name T452
Test name
Test status
Simulation time 840144062 ps
CPU time 1.37 seconds
Started Apr 02 02:20:48 PM PDT 24
Finished Apr 02 02:20:50 PM PDT 24
Peak memory 199444 kb
Host smart-9f09a24f-06a3-45b4-9780-9ae06c362297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672317879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1672317879
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3773602449
Short name T895
Test name
Test status
Simulation time 12555330035 ps
CPU time 11.53 seconds
Started Apr 02 02:20:41 PM PDT 24
Finished Apr 02 02:20:54 PM PDT 24
Peak memory 200472 kb
Host smart-a9616749-b290-4071-bf2e-f0033e9b9a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773602449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3773602449
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2123567284
Short name T1078
Test name
Test status
Simulation time 11579618 ps
CPU time 0.54 seconds
Started Apr 02 02:21:09 PM PDT 24
Finished Apr 02 02:21:09 PM PDT 24
Peak memory 195848 kb
Host smart-9bbc6d19-74d9-4acc-9c02-50a3298e4803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123567284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2123567284
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3325469574
Short name T1053
Test name
Test status
Simulation time 132963163847 ps
CPU time 21.92 seconds
Started Apr 02 02:20:55 PM PDT 24
Finished Apr 02 02:21:17 PM PDT 24
Peak memory 200448 kb
Host smart-7d4550e4-ffdf-4724-856c-f0ca9d1cc2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325469574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3325469574
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.938266280
Short name T225
Test name
Test status
Simulation time 179896999331 ps
CPU time 61.66 seconds
Started Apr 02 02:20:57 PM PDT 24
Finished Apr 02 02:21:58 PM PDT 24
Peak memory 200476 kb
Host smart-f832dbc3-390e-49cd-9dc0-05562a15570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938266280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.938266280
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.608337698
Short name T494
Test name
Test status
Simulation time 29411924393 ps
CPU time 22.29 seconds
Started Apr 02 02:20:56 PM PDT 24
Finished Apr 02 02:21:18 PM PDT 24
Peak memory 200436 kb
Host smart-8694ef44-27dd-43f2-a467-7534f8060164
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608337698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.608337698
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3995550845
Short name T852
Test name
Test status
Simulation time 61514634846 ps
CPU time 158.45 seconds
Started Apr 02 02:21:10 PM PDT 24
Finished Apr 02 02:23:49 PM PDT 24
Peak memory 200444 kb
Host smart-b2ff6706-4224-45d2-b2f0-79e5b5249222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995550845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3995550845
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.879124489
Short name T379
Test name
Test status
Simulation time 439746629 ps
CPU time 0.87 seconds
Started Apr 02 02:21:04 PM PDT 24
Finished Apr 02 02:21:05 PM PDT 24
Peak memory 196616 kb
Host smart-cf71e00f-b5fa-40b1-8854-8cfe1ea7c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879124489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.879124489
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.836545400
Short name T477
Test name
Test status
Simulation time 289913029728 ps
CPU time 54.65 seconds
Started Apr 02 02:20:59 PM PDT 24
Finished Apr 02 02:21:54 PM PDT 24
Peak memory 200700 kb
Host smart-9265ab22-db49-4740-b6f3-edaa6c541cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836545400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.836545400
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.99993012
Short name T842
Test name
Test status
Simulation time 23339797440 ps
CPU time 307.76 seconds
Started Apr 02 02:21:06 PM PDT 24
Finished Apr 02 02:26:14 PM PDT 24
Peak memory 200416 kb
Host smart-4d2ed6e5-5878-40a3-bf83-ce7dca993675
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99993012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.99993012
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3939565496
Short name T1117
Test name
Test status
Simulation time 6879628774 ps
CPU time 15.52 seconds
Started Apr 02 02:20:55 PM PDT 24
Finished Apr 02 02:21:11 PM PDT 24
Peak memory 199708 kb
Host smart-2ceac678-5358-4d63-adba-3d9e2ef1c333
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939565496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3939565496
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4179051508
Short name T1067
Test name
Test status
Simulation time 38721769831 ps
CPU time 74.36 seconds
Started Apr 02 02:21:00 PM PDT 24
Finished Apr 02 02:22:15 PM PDT 24
Peak memory 200460 kb
Host smart-df12cc2a-cbe8-4494-bb92-4a7e3f4fd33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179051508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4179051508
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.634809890
Short name T856
Test name
Test status
Simulation time 5849774646 ps
CPU time 8.91 seconds
Started Apr 02 02:21:00 PM PDT 24
Finished Apr 02 02:21:09 PM PDT 24
Peak memory 196448 kb
Host smart-eac5e44d-8936-4ae4-baac-0ebe88afab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634809890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.634809890
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.124711429
Short name T326
Test name
Test status
Simulation time 5894119608 ps
CPU time 13.81 seconds
Started Apr 02 02:20:51 PM PDT 24
Finished Apr 02 02:21:06 PM PDT 24
Peak memory 200412 kb
Host smart-a1f5d6b6-daa7-475d-a6cb-01fccc79f5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124711429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.124711429
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3856381393
Short name T1091
Test name
Test status
Simulation time 520404187167 ps
CPU time 132.69 seconds
Started Apr 02 02:21:08 PM PDT 24
Finished Apr 02 02:23:21 PM PDT 24
Peak memory 200416 kb
Host smart-6e58578b-a9da-455c-b47b-12234b912f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856381393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3856381393
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.932744592
Short name T189
Test name
Test status
Simulation time 170782487335 ps
CPU time 830.75 seconds
Started Apr 02 02:21:07 PM PDT 24
Finished Apr 02 02:34:58 PM PDT 24
Peak memory 230256 kb
Host smart-d9cee829-a883-4974-93cc-6a78f1a70631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932744592 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.932744592
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.660689925
Short name T552
Test name
Test status
Simulation time 6447130007 ps
CPU time 7.68 seconds
Started Apr 02 02:21:06 PM PDT 24
Finished Apr 02 02:21:13 PM PDT 24
Peak memory 199716 kb
Host smart-86c4faa0-f47f-4cd5-b9cf-9b2cf7153c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660689925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.660689925
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.866939900
Short name T11
Test name
Test status
Simulation time 108188005801 ps
CPU time 39.93 seconds
Started Apr 02 02:20:52 PM PDT 24
Finished Apr 02 02:21:33 PM PDT 24
Peak memory 200400 kb
Host smart-c9f59e46-8e37-4ec3-b908-2523daa9018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866939900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.866939900
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.749768257
Short name T554
Test name
Test status
Simulation time 35146111 ps
CPU time 0.53 seconds
Started Apr 02 02:21:17 PM PDT 24
Finished Apr 02 02:21:17 PM PDT 24
Peak memory 195888 kb
Host smart-93867378-d303-480f-a79e-30809d379350
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749768257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.749768257
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2404748504
Short name T273
Test name
Test status
Simulation time 42340326192 ps
CPU time 77.03 seconds
Started Apr 02 02:21:10 PM PDT 24
Finished Apr 02 02:22:27 PM PDT 24
Peak memory 200392 kb
Host smart-91c7717b-4c83-450e-bce3-58b3851d88ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404748504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2404748504
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.984099858
Short name T758
Test name
Test status
Simulation time 62063723678 ps
CPU time 25.19 seconds
Started Apr 02 02:21:12 PM PDT 24
Finished Apr 02 02:21:37 PM PDT 24
Peak memory 200376 kb
Host smart-a2ce5222-beac-4543-b70f-f6e8b8b26329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984099858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.984099858
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.96138061
Short name T141
Test name
Test status
Simulation time 29909952587 ps
CPU time 51.43 seconds
Started Apr 02 02:21:12 PM PDT 24
Finished Apr 02 02:22:04 PM PDT 24
Peak memory 200164 kb
Host smart-436ff132-eedc-41a5-b3cd-5859871158ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96138061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.96138061
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.815069319
Short name T1064
Test name
Test status
Simulation time 18121920018 ps
CPU time 39.02 seconds
Started Apr 02 02:21:11 PM PDT 24
Finished Apr 02 02:21:50 PM PDT 24
Peak memory 200412 kb
Host smart-8b2bce05-ba98-4088-abb9-bcf0113ff97f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815069319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.815069319
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.13528901
Short name T930
Test name
Test status
Simulation time 219075336245 ps
CPU time 361.33 seconds
Started Apr 02 02:21:17 PM PDT 24
Finished Apr 02 02:27:18 PM PDT 24
Peak memory 200472 kb
Host smart-1693730b-51eb-4ea6-aa50-ada4619a9aac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13528901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.13528901
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4164204306
Short name T104
Test name
Test status
Simulation time 427443930 ps
CPU time 0.83 seconds
Started Apr 02 02:21:18 PM PDT 24
Finished Apr 02 02:21:19 PM PDT 24
Peak memory 196592 kb
Host smart-f5086d17-f320-4a29-81ad-3c26efff7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164204306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4164204306
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.727954010
Short name T665
Test name
Test status
Simulation time 180075084950 ps
CPU time 289.29 seconds
Started Apr 02 02:21:11 PM PDT 24
Finished Apr 02 02:26:00 PM PDT 24
Peak memory 216288 kb
Host smart-a1a4d255-cf10-4148-ac45-429f4a8a2a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727954010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.727954010
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.116452278
Short name T1073
Test name
Test status
Simulation time 16938080706 ps
CPU time 186.67 seconds
Started Apr 02 02:21:16 PM PDT 24
Finished Apr 02 02:24:23 PM PDT 24
Peak memory 200460 kb
Host smart-1b8e9b9a-199d-40b0-8746-084f32c50b15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116452278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.116452278
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.966626775
Short name T775
Test name
Test status
Simulation time 4014865966 ps
CPU time 27.75 seconds
Started Apr 02 02:21:11 PM PDT 24
Finished Apr 02 02:21:39 PM PDT 24
Peak memory 198800 kb
Host smart-de7c300b-9b6c-47ed-a8fc-5a59467a0c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966626775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.966626775
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.518811068
Short name T688
Test name
Test status
Simulation time 118147517108 ps
CPU time 80.87 seconds
Started Apr 02 02:21:11 PM PDT 24
Finished Apr 02 02:22:31 PM PDT 24
Peak memory 200444 kb
Host smart-a5dc5446-d6b8-4f84-8759-670a633f649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518811068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.518811068
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3770081657
Short name T1081
Test name
Test status
Simulation time 3589278655 ps
CPU time 6.53 seconds
Started Apr 02 02:21:12 PM PDT 24
Finished Apr 02 02:21:18 PM PDT 24
Peak memory 196772 kb
Host smart-d48c4537-aa31-468e-88a7-d09a1a0367a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770081657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3770081657
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3525791671
Short name T803
Test name
Test status
Simulation time 986214568 ps
CPU time 3.29 seconds
Started Apr 02 02:21:07 PM PDT 24
Finished Apr 02 02:21:11 PM PDT 24
Peak memory 199364 kb
Host smart-d55195b6-0a54-409e-bdcb-b7fc1015d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525791671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3525791671
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1097931591
Short name T123
Test name
Test status
Simulation time 43119688616 ps
CPU time 520.81 seconds
Started Apr 02 02:21:17 PM PDT 24
Finished Apr 02 02:29:58 PM PDT 24
Peak memory 200448 kb
Host smart-b3b597f7-7f0d-4feb-9cb2-7b55a6c6bb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097931591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1097931591
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1781252934
Short name T702
Test name
Test status
Simulation time 492637339927 ps
CPU time 704.92 seconds
Started Apr 02 02:21:16 PM PDT 24
Finished Apr 02 02:33:01 PM PDT 24
Peak memory 217160 kb
Host smart-6b6e4b76-7fd8-48f5-80d8-afc640c77cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781252934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1781252934
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2232960315
Short name T925
Test name
Test status
Simulation time 6787781717 ps
CPU time 28.99 seconds
Started Apr 02 02:21:16 PM PDT 24
Finished Apr 02 02:21:45 PM PDT 24
Peak memory 200216 kb
Host smart-5ad6e619-3cf9-4221-a829-a9e8e8165b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232960315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2232960315
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1757487690
Short name T47
Test name
Test status
Simulation time 90257464879 ps
CPU time 37.01 seconds
Started Apr 02 02:21:12 PM PDT 24
Finished Apr 02 02:21:49 PM PDT 24
Peak memory 200476 kb
Host smart-f35db4d9-cf80-458b-8506-1014e2823a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757487690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1757487690
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.151798067
Short name T960
Test name
Test status
Simulation time 13701922 ps
CPU time 0.54 seconds
Started Apr 02 02:21:31 PM PDT 24
Finished Apr 02 02:21:32 PM PDT 24
Peak memory 195832 kb
Host smart-5bc3ec92-a8bb-4d6d-95f6-332a0202c598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151798067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.151798067
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.115699388
Short name T1070
Test name
Test status
Simulation time 28461517118 ps
CPU time 48.23 seconds
Started Apr 02 02:21:17 PM PDT 24
Finished Apr 02 02:22:05 PM PDT 24
Peak memory 200420 kb
Host smart-d76a5a2e-544f-4013-aa2e-d7b49430d721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115699388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.115699388
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4055070907
Short name T964
Test name
Test status
Simulation time 165017758196 ps
CPU time 271.19 seconds
Started Apr 02 02:21:18 PM PDT 24
Finished Apr 02 02:25:49 PM PDT 24
Peak memory 200444 kb
Host smart-921766ea-5400-4897-8425-b1c3da6082e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055070907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4055070907
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1875101081
Short name T773
Test name
Test status
Simulation time 28624097108 ps
CPU time 50.02 seconds
Started Apr 02 02:21:18 PM PDT 24
Finished Apr 02 02:22:08 PM PDT 24
Peak memory 200500 kb
Host smart-f093ff8f-cac0-437a-88a8-0dc5d173a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875101081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1875101081
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4048573315
Short name T1126
Test name
Test status
Simulation time 39654297560 ps
CPU time 17.2 seconds
Started Apr 02 02:21:22 PM PDT 24
Finished Apr 02 02:21:39 PM PDT 24
Peak memory 200416 kb
Host smart-ae886f4a-712d-4f52-abbb-07a0304c79a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048573315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4048573315
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3665739511
Short name T288
Test name
Test status
Simulation time 96555216944 ps
CPU time 272.24 seconds
Started Apr 02 02:21:27 PM PDT 24
Finished Apr 02 02:25:59 PM PDT 24
Peak memory 200548 kb
Host smart-f4634159-1b2f-4941-a5ee-2e85b4d545ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665739511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3665739511
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.4054347179
Short name T652
Test name
Test status
Simulation time 7088186844 ps
CPU time 18.96 seconds
Started Apr 02 02:21:26 PM PDT 24
Finished Apr 02 02:21:45 PM PDT 24
Peak memory 200336 kb
Host smart-b4661544-2031-4726-8ccc-458cab5793fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054347179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.4054347179
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3465510267
Short name T599
Test name
Test status
Simulation time 25558547476 ps
CPU time 37.43 seconds
Started Apr 02 02:21:24 PM PDT 24
Finished Apr 02 02:22:02 PM PDT 24
Peak memory 199752 kb
Host smart-c57cdd7a-c1b6-476e-8c0e-c2005a393134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465510267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3465510267
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1589926026
Short name T1147
Test name
Test status
Simulation time 11913931324 ps
CPU time 477.67 seconds
Started Apr 02 02:21:25 PM PDT 24
Finished Apr 02 02:29:23 PM PDT 24
Peak memory 200452 kb
Host smart-06247d2d-1900-44b0-b1fb-6956ab17e4c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589926026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1589926026
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4192937211
Short name T4
Test name
Test status
Simulation time 3186218485 ps
CPU time 17.4 seconds
Started Apr 02 02:21:23 PM PDT 24
Finished Apr 02 02:21:40 PM PDT 24
Peak memory 199432 kb
Host smart-e8f7413d-d51c-4de6-aa4a-47270e092696
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192937211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4192937211
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.404564037
Short name T991
Test name
Test status
Simulation time 147168223449 ps
CPU time 23.16 seconds
Started Apr 02 02:21:26 PM PDT 24
Finished Apr 02 02:21:49 PM PDT 24
Peak memory 200392 kb
Host smart-2a798a9f-149b-4a76-aceb-ebafe1f2aced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404564037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.404564037
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.640000169
Short name T1166
Test name
Test status
Simulation time 4512208794 ps
CPU time 1.13 seconds
Started Apr 02 02:21:25 PM PDT 24
Finished Apr 02 02:21:27 PM PDT 24
Peak memory 196700 kb
Host smart-04d44dd3-534b-44c7-b41d-7f270e001f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640000169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.640000169
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.262510893
Short name T813
Test name
Test status
Simulation time 6081488247 ps
CPU time 16.41 seconds
Started Apr 02 02:21:19 PM PDT 24
Finished Apr 02 02:21:36 PM PDT 24
Peak memory 200432 kb
Host smart-616db6db-ce13-45e5-b108-f4708d44e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262510893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.262510893
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2110013925
Short name T507
Test name
Test status
Simulation time 115437210272 ps
CPU time 710.98 seconds
Started Apr 02 02:21:30 PM PDT 24
Finished Apr 02 02:33:21 PM PDT 24
Peak memory 200432 kb
Host smart-b4db3dee-3726-432d-b0d8-5f3d7f12f42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110013925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2110013925
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3520450880
Short name T174
Test name
Test status
Simulation time 147226422787 ps
CPU time 419.11 seconds
Started Apr 02 02:21:25 PM PDT 24
Finished Apr 02 02:28:24 PM PDT 24
Peak memory 208732 kb
Host smart-36bdf3be-dc65-44e4-b6b7-082ccd7788f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520450880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3520450880
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3046617136
Short name T20
Test name
Test status
Simulation time 4184354230 ps
CPU time 1.6 seconds
Started Apr 02 02:21:26 PM PDT 24
Finished Apr 02 02:21:27 PM PDT 24
Peak memory 198924 kb
Host smart-63f6baf4-2a5c-496c-af7b-784d3e38c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046617136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3046617136
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.75850408
Short name T788
Test name
Test status
Simulation time 41211762311 ps
CPU time 9.24 seconds
Started Apr 02 02:21:19 PM PDT 24
Finished Apr 02 02:21:29 PM PDT 24
Peak memory 198768 kb
Host smart-98a7583b-b20a-4187-91fc-eda93e4eb577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75850408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.75850408
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2044306159
Short name T861
Test name
Test status
Simulation time 14548486 ps
CPU time 0.56 seconds
Started Apr 02 02:21:41 PM PDT 24
Finished Apr 02 02:21:42 PM PDT 24
Peak memory 195824 kb
Host smart-8e1b1022-bda1-43a7-8e35-f1a503c70d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044306159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2044306159
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2161731595
Short name T140
Test name
Test status
Simulation time 64402353344 ps
CPU time 50.28 seconds
Started Apr 02 02:21:32 PM PDT 24
Finished Apr 02 02:22:22 PM PDT 24
Peak memory 200448 kb
Host smart-62992d4c-5e00-49fa-a4b1-71a7f5db13f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161731595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2161731595
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.220473880
Short name T1135
Test name
Test status
Simulation time 14206146702 ps
CPU time 20.11 seconds
Started Apr 02 02:21:32 PM PDT 24
Finished Apr 02 02:21:52 PM PDT 24
Peak memory 200416 kb
Host smart-22335994-eac6-423d-982c-0e378d9c9c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220473880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.220473880
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4142074594
Short name T412
Test name
Test status
Simulation time 26110401139 ps
CPU time 30.72 seconds
Started Apr 02 02:21:33 PM PDT 24
Finished Apr 02 02:22:04 PM PDT 24
Peak memory 200452 kb
Host smart-093cb2e7-6b6e-4245-9178-ffaa6e71497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142074594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4142074594
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2878983428
Short name T525
Test name
Test status
Simulation time 45133776974 ps
CPU time 69.71 seconds
Started Apr 02 02:21:38 PM PDT 24
Finished Apr 02 02:22:47 PM PDT 24
Peak memory 200328 kb
Host smart-3c0edb5a-f895-4c20-b701-7a1aefd0187b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878983428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2878983428
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3272475522
Short name T397
Test name
Test status
Simulation time 84351380506 ps
CPU time 458.36 seconds
Started Apr 02 02:21:40 PM PDT 24
Finished Apr 02 02:29:19 PM PDT 24
Peak memory 200360 kb
Host smart-245d9647-4b0e-4094-be21-d5c2b04042c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272475522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3272475522
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4067514320
Short name T52
Test name
Test status
Simulation time 7500344095 ps
CPU time 16.71 seconds
Started Apr 02 02:21:44 PM PDT 24
Finished Apr 02 02:22:01 PM PDT 24
Peak memory 199504 kb
Host smart-75a7c12b-8424-4b4e-b05c-469f94dd9c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067514320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4067514320
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3989221051
Short name T911
Test name
Test status
Simulation time 30919400834 ps
CPU time 56.94 seconds
Started Apr 02 02:21:36 PM PDT 24
Finished Apr 02 02:22:33 PM PDT 24
Peak memory 200740 kb
Host smart-0e4cd98d-3b6b-494e-bec2-82b272acb9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989221051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3989221051
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3230839595
Short name T1074
Test name
Test status
Simulation time 27761250420 ps
CPU time 665.11 seconds
Started Apr 02 02:21:40 PM PDT 24
Finished Apr 02 02:32:45 PM PDT 24
Peak memory 200500 kb
Host smart-ed57aa58-ff2f-41ef-bf49-5410813b3f85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230839595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3230839595
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1782099508
Short name T548
Test name
Test status
Simulation time 7906757093 ps
CPU time 18.14 seconds
Started Apr 02 02:21:33 PM PDT 24
Finished Apr 02 02:21:52 PM PDT 24
Peak memory 199540 kb
Host smart-9d46b675-d399-41ba-bd1e-1ab34faeba02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782099508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1782099508
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2980159916
Short name T545
Test name
Test status
Simulation time 176582814137 ps
CPU time 146.79 seconds
Started Apr 02 02:21:36 PM PDT 24
Finished Apr 02 02:24:03 PM PDT 24
Peak memory 200460 kb
Host smart-493cc9ec-43ea-43c6-a141-4d654842afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980159916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2980159916
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1682030010
Short name T833
Test name
Test status
Simulation time 3190937633 ps
CPU time 2.08 seconds
Started Apr 02 02:21:37 PM PDT 24
Finished Apr 02 02:21:40 PM PDT 24
Peak memory 196468 kb
Host smart-062278c4-866a-43da-9b24-9d9e26a2a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682030010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1682030010
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3484903372
Short name T1083
Test name
Test status
Simulation time 5352215862 ps
CPU time 6.01 seconds
Started Apr 02 02:21:31 PM PDT 24
Finished Apr 02 02:21:37 PM PDT 24
Peak memory 200244 kb
Host smart-cbe19871-9d26-474b-a0e2-bccf55fabd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484903372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3484903372
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2285510775
Short name T1047
Test name
Test status
Simulation time 128204014801 ps
CPU time 128.27 seconds
Started Apr 02 02:21:41 PM PDT 24
Finished Apr 02 02:23:49 PM PDT 24
Peak memory 200524 kb
Host smart-8bb22c33-43d3-422c-97da-dd896fa4ee2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285510775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2285510775
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1201222395
Short name T1069
Test name
Test status
Simulation time 64836786977 ps
CPU time 274.85 seconds
Started Apr 02 02:21:42 PM PDT 24
Finished Apr 02 02:26:17 PM PDT 24
Peak memory 216980 kb
Host smart-b63473a7-8a4e-428c-bcfe-cf0dbc8d8441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201222395 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1201222395
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3734182450
Short name T542
Test name
Test status
Simulation time 732329026 ps
CPU time 2.41 seconds
Started Apr 02 02:21:43 PM PDT 24
Finished Apr 02 02:21:46 PM PDT 24
Peak memory 199120 kb
Host smart-0f121c4d-1a8c-4c6d-86f8-5443d03306af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734182450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3734182450
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.263929404
Short name T353
Test name
Test status
Simulation time 21225269181 ps
CPU time 41.07 seconds
Started Apr 02 02:21:39 PM PDT 24
Finished Apr 02 02:22:21 PM PDT 24
Peak memory 200436 kb
Host smart-3c3363e6-5d92-4434-9f1b-2676e2509cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263929404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.263929404
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2274657926
Short name T503
Test name
Test status
Simulation time 17789815 ps
CPU time 0.54 seconds
Started Apr 02 02:21:59 PM PDT 24
Finished Apr 02 02:22:00 PM PDT 24
Peak memory 195888 kb
Host smart-e032b3e1-8a3a-4ac6-8897-ff97c2836faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274657926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2274657926
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3087589948
Short name T1042
Test name
Test status
Simulation time 172987581753 ps
CPU time 65.95 seconds
Started Apr 02 02:21:44 PM PDT 24
Finished Apr 02 02:22:50 PM PDT 24
Peak memory 200504 kb
Host smart-bcd0359a-cb18-44a9-aea2-160622e07e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087589948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3087589948
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4106055689
Short name T1044
Test name
Test status
Simulation time 15970921831 ps
CPU time 9.58 seconds
Started Apr 02 02:21:47 PM PDT 24
Finished Apr 02 02:21:57 PM PDT 24
Peak memory 199616 kb
Host smart-308dcff7-8d6e-4074-9819-47fee594d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106055689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4106055689
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.4164658264
Short name T1153
Test name
Test status
Simulation time 79269088579 ps
CPU time 124.41 seconds
Started Apr 02 02:21:49 PM PDT 24
Finished Apr 02 02:23:54 PM PDT 24
Peak memory 200476 kb
Host smart-172e19ee-2415-4632-9695-f2519a1774c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164658264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4164658264
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2483077269
Short name T831
Test name
Test status
Simulation time 10320434566 ps
CPU time 8.8 seconds
Started Apr 02 02:21:51 PM PDT 24
Finished Apr 02 02:22:00 PM PDT 24
Peak memory 197416 kb
Host smart-5af5933b-9ada-4eda-bd72-dd684f6d9294
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483077269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2483077269
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2293855427
Short name T604
Test name
Test status
Simulation time 52675481990 ps
CPU time 223.23 seconds
Started Apr 02 02:21:54 PM PDT 24
Finished Apr 02 02:25:38 PM PDT 24
Peak memory 200472 kb
Host smart-3dd7ff6e-67cd-41f8-a609-4229f6c6aac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293855427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2293855427
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1340260762
Short name T394
Test name
Test status
Simulation time 1120194680 ps
CPU time 2.13 seconds
Started Apr 02 02:21:50 PM PDT 24
Finished Apr 02 02:21:53 PM PDT 24
Peak memory 195884 kb
Host smart-1eb31a4e-0d5e-4c94-8266-d130f7f9bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340260762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1340260762
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.2353877645
Short name T988
Test name
Test status
Simulation time 22059904268 ps
CPU time 18.66 seconds
Started Apr 02 02:21:47 PM PDT 24
Finished Apr 02 02:22:06 PM PDT 24
Peak memory 200256 kb
Host smart-5e2e5878-5d81-4631-80fd-d2c10e4c07d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353877645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2353877645
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3763531251
Short name T615
Test name
Test status
Simulation time 11591684870 ps
CPU time 514.22 seconds
Started Apr 02 02:21:57 PM PDT 24
Finished Apr 02 02:30:31 PM PDT 24
Peak memory 200492 kb
Host smart-6d84eb8b-da7d-4ad4-ad7c-723025e0355e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3763531251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3763531251
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2952773649
Short name T762
Test name
Test status
Simulation time 4816828660 ps
CPU time 40.17 seconds
Started Apr 02 02:21:50 PM PDT 24
Finished Apr 02 02:22:31 PM PDT 24
Peak memory 198808 kb
Host smart-67636f66-05b3-4ae5-a507-afa468ab4cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952773649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2952773649
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3555276791
Short name T829
Test name
Test status
Simulation time 541104944417 ps
CPU time 38.98 seconds
Started Apr 02 02:21:49 PM PDT 24
Finished Apr 02 02:22:29 PM PDT 24
Peak memory 200416 kb
Host smart-23ebb57e-ec74-4c65-ba1c-bc86a1864ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555276791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3555276791
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.788379507
Short name T323
Test name
Test status
Simulation time 3943525147 ps
CPU time 2.8 seconds
Started Apr 02 02:21:49 PM PDT 24
Finished Apr 02 02:21:52 PM PDT 24
Peak memory 196452 kb
Host smart-214b7c03-01ad-45f2-85d4-6b35134f90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788379507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.788379507
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2603685934
Short name T862
Test name
Test status
Simulation time 6294730976 ps
CPU time 22.39 seconds
Started Apr 02 02:21:40 PM PDT 24
Finished Apr 02 02:22:03 PM PDT 24
Peak memory 199760 kb
Host smart-1c5e9845-914e-49f4-bb34-306e748a14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603685934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2603685934
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.172769781
Short name T1004
Test name
Test status
Simulation time 288885147268 ps
CPU time 627.56 seconds
Started Apr 02 02:21:59 PM PDT 24
Finished Apr 02 02:32:27 PM PDT 24
Peak memory 200480 kb
Host smart-921e8d14-9683-4fc0-837b-2a34bda5a868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172769781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.172769781
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.247476157
Short name T794
Test name
Test status
Simulation time 588406847762 ps
CPU time 1087.83 seconds
Started Apr 02 02:21:58 PM PDT 24
Finished Apr 02 02:40:07 PM PDT 24
Peak memory 226620 kb
Host smart-3ba1aafe-377f-496b-893d-39e30ed05f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247476157 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.247476157
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2100731270
Short name T844
Test name
Test status
Simulation time 1002973460 ps
CPU time 3.87 seconds
Started Apr 02 02:21:52 PM PDT 24
Finished Apr 02 02:21:56 PM PDT 24
Peak memory 199960 kb
Host smart-4ee41399-fba3-4b9a-98ab-ebcff0724e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100731270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2100731270
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3475225581
Short name T1133
Test name
Test status
Simulation time 32078886381 ps
CPU time 7.34 seconds
Started Apr 02 02:21:45 PM PDT 24
Finished Apr 02 02:21:52 PM PDT 24
Peak memory 200452 kb
Host smart-de3e7218-b821-4b11-b737-d134d2e7eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475225581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3475225581
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3567883208
Short name T540
Test name
Test status
Simulation time 29830825 ps
CPU time 0.54 seconds
Started Apr 02 02:12:45 PM PDT 24
Finished Apr 02 02:12:46 PM PDT 24
Peak memory 195336 kb
Host smart-0289e65e-b8a1-4e44-8031-f231296ff8e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567883208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3567883208
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1552625058
Short name T874
Test name
Test status
Simulation time 30125524114 ps
CPU time 25.76 seconds
Started Apr 02 02:12:29 PM PDT 24
Finished Apr 02 02:12:55 PM PDT 24
Peak memory 200464 kb
Host smart-6efed9f7-6bac-47da-86d4-1fdb24f4dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552625058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1552625058
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4067851028
Short name T608
Test name
Test status
Simulation time 52871612755 ps
CPU time 41.29 seconds
Started Apr 02 02:12:28 PM PDT 24
Finished Apr 02 02:13:10 PM PDT 24
Peak memory 200392 kb
Host smart-6f006390-0f28-42d2-93cf-91d81be1850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067851028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4067851028
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3207031023
Short name T159
Test name
Test status
Simulation time 7416356569 ps
CPU time 4.63 seconds
Started Apr 02 02:12:30 PM PDT 24
Finished Apr 02 02:12:35 PM PDT 24
Peak memory 200532 kb
Host smart-a43f7c37-aca5-46b6-aa74-a931b5b14b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207031023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3207031023
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.747143229
Short name T691
Test name
Test status
Simulation time 258462502045 ps
CPU time 92.47 seconds
Started Apr 02 02:12:34 PM PDT 24
Finished Apr 02 02:14:06 PM PDT 24
Peak memory 200376 kb
Host smart-b1c865d6-20b4-46ec-9f86-8e5409ff4427
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747143229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.747143229
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4006734378
Short name T474
Test name
Test status
Simulation time 55131105696 ps
CPU time 232.76 seconds
Started Apr 02 02:12:38 PM PDT 24
Finished Apr 02 02:16:31 PM PDT 24
Peak memory 200384 kb
Host smart-6d3d044c-3a4f-4ba7-a60d-c7444b6ca44f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006734378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4006734378
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2933759199
Short name T402
Test name
Test status
Simulation time 7175489214 ps
CPU time 4.31 seconds
Started Apr 02 02:12:37 PM PDT 24
Finished Apr 02 02:12:42 PM PDT 24
Peak memory 198880 kb
Host smart-48303c82-18b1-4fcf-91c7-8de54fee7cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933759199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2933759199
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1583872460
Short name T687
Test name
Test status
Simulation time 6192125419 ps
CPU time 8.96 seconds
Started Apr 02 02:12:35 PM PDT 24
Finished Apr 02 02:12:44 PM PDT 24
Peak memory 200544 kb
Host smart-f3bd25f0-d6bd-4fc7-8e55-3531e92fbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583872460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1583872460
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3136230094
Short name T430
Test name
Test status
Simulation time 20741567374 ps
CPU time 85.49 seconds
Started Apr 02 02:12:36 PM PDT 24
Finished Apr 02 02:14:02 PM PDT 24
Peak memory 200512 kb
Host smart-72db30cc-a5f7-4149-b863-66a7441c5b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136230094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3136230094
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.532285745
Short name T434
Test name
Test status
Simulation time 1298520002 ps
CPU time 1.1 seconds
Started Apr 02 02:12:35 PM PDT 24
Finished Apr 02 02:12:36 PM PDT 24
Peak memory 196204 kb
Host smart-e14e5d1d-889c-4250-baa3-38a016519cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532285745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.532285745
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2876123377
Short name T731
Test name
Test status
Simulation time 28659510208 ps
CPU time 25.46 seconds
Started Apr 02 02:12:37 PM PDT 24
Finished Apr 02 02:13:02 PM PDT 24
Peak memory 200400 kb
Host smart-4c079c6f-ad96-4bcf-b0cd-6f5ebc358c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876123377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2876123377
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1123419287
Short name T593
Test name
Test status
Simulation time 49054199098 ps
CPU time 41.82 seconds
Started Apr 02 02:12:32 PM PDT 24
Finished Apr 02 02:13:14 PM PDT 24
Peak memory 196152 kb
Host smart-ae8a1ef5-b849-4ce0-9575-7c4eb9b06e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123419287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1123419287
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1389441222
Short name T751
Test name
Test status
Simulation time 297841470 ps
CPU time 0.87 seconds
Started Apr 02 02:12:31 PM PDT 24
Finished Apr 02 02:12:32 PM PDT 24
Peak memory 198600 kb
Host smart-f95929ee-0d1e-4635-aa19-f43145c9dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389441222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1389441222
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2369405961
Short name T1051
Test name
Test status
Simulation time 145004028147 ps
CPU time 854.74 seconds
Started Apr 02 02:12:40 PM PDT 24
Finished Apr 02 02:26:55 PM PDT 24
Peak memory 200464 kb
Host smart-c37902f2-59bc-46ed-9e0d-0aaa68eb2ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369405961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2369405961
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1436041656
Short name T116
Test name
Test status
Simulation time 70916199029 ps
CPU time 206.24 seconds
Started Apr 02 02:12:39 PM PDT 24
Finished Apr 02 02:16:05 PM PDT 24
Peak memory 217176 kb
Host smart-9205fcf0-ce8f-49d0-917d-9087a1de734b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436041656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1436041656
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1075969064
Short name T598
Test name
Test status
Simulation time 2157252180 ps
CPU time 2.8 seconds
Started Apr 02 02:12:36 PM PDT 24
Finished Apr 02 02:12:40 PM PDT 24
Peak memory 198844 kb
Host smart-2cba1402-c437-46d0-8cb7-955664bb4cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075969064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1075969064
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3000007479
Short name T368
Test name
Test status
Simulation time 16872547206 ps
CPU time 22.23 seconds
Started Apr 02 02:12:30 PM PDT 24
Finished Apr 02 02:12:52 PM PDT 24
Peak memory 200456 kb
Host smart-c96016ee-eb06-4d08-8fd8-5f6777d7a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000007479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3000007479
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2251722199
Short name T1171
Test name
Test status
Simulation time 109613610404 ps
CPU time 47.07 seconds
Started Apr 02 02:22:01 PM PDT 24
Finished Apr 02 02:22:48 PM PDT 24
Peak memory 200516 kb
Host smart-2e42c61b-18d3-4761-b5fa-bb834f955a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251722199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2251722199
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1269947694
Short name T721
Test name
Test status
Simulation time 66905021804 ps
CPU time 456.07 seconds
Started Apr 02 02:21:59 PM PDT 24
Finished Apr 02 02:29:35 PM PDT 24
Peak memory 208728 kb
Host smart-6f6fd2f8-bc67-48de-b6ee-ff89028b2cd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269947694 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1269947694
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3930466018
Short name T331
Test name
Test status
Simulation time 111383591235 ps
CPU time 42.56 seconds
Started Apr 02 02:21:59 PM PDT 24
Finished Apr 02 02:22:42 PM PDT 24
Peak memory 200516 kb
Host smart-58a17ced-cb2f-4674-843f-6e3ffa5079a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930466018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3930466018
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1398047129
Short name T409
Test name
Test status
Simulation time 101420643094 ps
CPU time 91.03 seconds
Started Apr 02 02:22:01 PM PDT 24
Finished Apr 02 02:23:33 PM PDT 24
Peak memory 200448 kb
Host smart-2a916d64-5811-4c9e-8f55-d7cf728bd189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398047129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1398047129
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.520169766
Short name T64
Test name
Test status
Simulation time 52585559217 ps
CPU time 699.53 seconds
Started Apr 02 02:22:04 PM PDT 24
Finished Apr 02 02:33:44 PM PDT 24
Peak memory 217224 kb
Host smart-303333cd-8eb9-4ba1-ae9e-eb54acc80e33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520169766 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.520169766
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.630623251
Short name T252
Test name
Test status
Simulation time 75377548267 ps
CPU time 30.72 seconds
Started Apr 02 02:22:02 PM PDT 24
Finished Apr 02 02:22:32 PM PDT 24
Peak memory 200340 kb
Host smart-a3187b2a-d549-4585-b6cd-ebd6223f33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630623251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.630623251
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2986826291
Short name T60
Test name
Test status
Simulation time 320786287312 ps
CPU time 729.09 seconds
Started Apr 02 02:22:05 PM PDT 24
Finished Apr 02 02:34:14 PM PDT 24
Peak memory 225452 kb
Host smart-72c8e251-7b8c-4247-8f39-862b59259b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986826291 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2986826291
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.448691846
Short name T570
Test name
Test status
Simulation time 83906979490 ps
CPU time 110.27 seconds
Started Apr 02 02:22:09 PM PDT 24
Finished Apr 02 02:23:59 PM PDT 24
Peak memory 200448 kb
Host smart-7d572248-f2e4-4580-9b15-87176d51cb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448691846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.448691846
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1214245840
Short name T947
Test name
Test status
Simulation time 82674876202 ps
CPU time 303.35 seconds
Started Apr 02 02:22:09 PM PDT 24
Finished Apr 02 02:27:13 PM PDT 24
Peak memory 217252 kb
Host smart-0f7e47bc-8303-4ffb-bee2-e7fa3fde55bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214245840 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1214245840
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2898975555
Short name T1019
Test name
Test status
Simulation time 16111582404 ps
CPU time 13.39 seconds
Started Apr 02 02:22:05 PM PDT 24
Finished Apr 02 02:22:19 PM PDT 24
Peak memory 200352 kb
Host smart-3358b1f3-c021-47cd-bcad-27a2f720b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898975555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2898975555
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1867968435
Short name T115
Test name
Test status
Simulation time 33064198541 ps
CPU time 276.98 seconds
Started Apr 02 02:22:06 PM PDT 24
Finished Apr 02 02:26:43 PM PDT 24
Peak memory 214464 kb
Host smart-1b0f51f1-30d0-40c9-8b00-c3cb52ac0870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867968435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1867968435
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.304802740
Short name T120
Test name
Test status
Simulation time 137221232453 ps
CPU time 57.51 seconds
Started Apr 02 02:22:09 PM PDT 24
Finished Apr 02 02:23:06 PM PDT 24
Peak memory 200408 kb
Host smart-bce096cc-be11-4ff5-8a45-b43b36275ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304802740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.304802740
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2703407213
Short name T1139
Test name
Test status
Simulation time 21359278019 ps
CPU time 466.15 seconds
Started Apr 02 02:22:09 PM PDT 24
Finished Apr 02 02:29:56 PM PDT 24
Peak memory 215912 kb
Host smart-543682da-9680-4c6e-873c-9c1c6810f21e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703407213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2703407213
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3991886117
Short name T364
Test name
Test status
Simulation time 112682635018 ps
CPU time 82.62 seconds
Started Apr 02 02:22:11 PM PDT 24
Finished Apr 02 02:23:33 PM PDT 24
Peak memory 200440 kb
Host smart-36d8e68b-bf42-43b1-9134-7b98cbc90e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991886117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3991886117
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.3814944618
Short name T791
Test name
Test status
Simulation time 17623959627 ps
CPU time 163.37 seconds
Started Apr 02 02:22:11 PM PDT 24
Finished Apr 02 02:24:54 PM PDT 24
Peak memory 216868 kb
Host smart-ac3cdcdf-ce1a-4dbb-b661-1d4b188a0428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814944618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.3814944618
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1042683141
Short name T344
Test name
Test status
Simulation time 48876774614 ps
CPU time 20.74 seconds
Started Apr 02 02:22:09 PM PDT 24
Finished Apr 02 02:22:29 PM PDT 24
Peak memory 200492 kb
Host smart-872de50a-c67c-4bc0-9d0a-f1f249c1d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042683141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1042683141
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2090622707
Short name T748
Test name
Test status
Simulation time 25251036660 ps
CPU time 317.61 seconds
Started Apr 02 02:22:13 PM PDT 24
Finished Apr 02 02:27:31 PM PDT 24
Peak memory 217220 kb
Host smart-84313666-5511-4baf-8847-6545aa795d59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090622707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2090622707
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2738724375
Short name T858
Test name
Test status
Simulation time 30047721 ps
CPU time 0.52 seconds
Started Apr 02 02:12:59 PM PDT 24
Finished Apr 02 02:12:59 PM PDT 24
Peak memory 195300 kb
Host smart-8d25d324-c3b3-4bf8-ba9c-d55e6aeb9e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738724375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2738724375
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3301526788
Short name T677
Test name
Test status
Simulation time 16515179922 ps
CPU time 29.98 seconds
Started Apr 02 02:12:41 PM PDT 24
Finished Apr 02 02:13:12 PM PDT 24
Peak memory 200396 kb
Host smart-a673ab9d-03d0-459d-b69e-2572b9d634c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301526788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3301526788
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3809453207
Short name T850
Test name
Test status
Simulation time 62760149637 ps
CPU time 93.27 seconds
Started Apr 02 02:12:47 PM PDT 24
Finished Apr 02 02:14:21 PM PDT 24
Peak memory 200412 kb
Host smart-f3343870-cb25-49f4-a2c9-0cbd41960a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809453207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3809453207
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4271462099
Short name T251
Test name
Test status
Simulation time 113925575079 ps
CPU time 58.28 seconds
Started Apr 02 02:12:46 PM PDT 24
Finished Apr 02 02:13:45 PM PDT 24
Peak memory 200516 kb
Host smart-499c71fa-8689-435b-b3ec-8a5378b9ac66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271462099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4271462099
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.428066612
Short name T339
Test name
Test status
Simulation time 60850130417 ps
CPU time 24.61 seconds
Started Apr 02 02:12:57 PM PDT 24
Finished Apr 02 02:13:22 PM PDT 24
Peak memory 200400 kb
Host smart-3d5a7c60-4741-4a91-b061-d8ee7bc43ee8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428066612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.428066612
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3903964764
Short name T680
Test name
Test status
Simulation time 48235656089 ps
CPU time 93.92 seconds
Started Apr 02 02:12:59 PM PDT 24
Finished Apr 02 02:14:33 PM PDT 24
Peak memory 200496 kb
Host smart-2cde69f1-6c4c-4fc0-b99d-d5fece9680a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903964764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3903964764
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1434944486
Short name T448
Test name
Test status
Simulation time 551769182 ps
CPU time 1.03 seconds
Started Apr 02 02:12:56 PM PDT 24
Finished Apr 02 02:12:57 PM PDT 24
Peak memory 196576 kb
Host smart-cb90af49-d6bc-45b1-8640-597d23d513f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434944486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1434944486
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1957767098
Short name T519
Test name
Test status
Simulation time 89603220331 ps
CPU time 42 seconds
Started Apr 02 02:12:57 PM PDT 24
Finished Apr 02 02:13:39 PM PDT 24
Peak memory 200664 kb
Host smart-2d91bac0-b975-488e-81cf-e3d9b58091e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957767098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1957767098
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.3944558187
Short name T1098
Test name
Test status
Simulation time 18565619994 ps
CPU time 236.5 seconds
Started Apr 02 02:13:00 PM PDT 24
Finished Apr 02 02:16:57 PM PDT 24
Peak memory 200436 kb
Host smart-a5f84cd5-23fd-494a-82f1-6e925618ca74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944558187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3944558187
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2526249343
Short name T567
Test name
Test status
Simulation time 1184888736 ps
CPU time 1 seconds
Started Apr 02 02:12:52 PM PDT 24
Finished Apr 02 02:12:53 PM PDT 24
Peak memory 195936 kb
Host smart-964807b7-3f07-4d03-8dd1-da4735e2ff63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526249343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2526249343
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.421175161
Short name T997
Test name
Test status
Simulation time 15908132481 ps
CPU time 17.95 seconds
Started Apr 02 02:12:57 PM PDT 24
Finished Apr 02 02:13:15 PM PDT 24
Peak memory 200352 kb
Host smart-0d4a612c-c79a-42b7-84bc-e30a4ee250dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421175161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.421175161
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.4046798233
Short name T723
Test name
Test status
Simulation time 4553055406 ps
CPU time 8.23 seconds
Started Apr 02 02:12:56 PM PDT 24
Finished Apr 02 02:13:05 PM PDT 24
Peak memory 196428 kb
Host smart-124d50e2-d794-41b8-b248-10dd6fdcd64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046798233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.4046798233
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.587424181
Short name T1076
Test name
Test status
Simulation time 124391058 ps
CPU time 0.91 seconds
Started Apr 02 02:12:46 PM PDT 24
Finished Apr 02 02:12:47 PM PDT 24
Peak memory 197492 kb
Host smart-674d5912-62d4-4720-95fb-c5bfaf4a6714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587424181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.587424181
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.636865012
Short name T119
Test name
Test status
Simulation time 263769194533 ps
CPU time 997.1 seconds
Started Apr 02 02:12:56 PM PDT 24
Finished Apr 02 02:29:33 PM PDT 24
Peak memory 200456 kb
Host smart-b0db3ddc-466e-45df-a68a-c3e9f7c86def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636865012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.636865012
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2412991180
Short name T186
Test name
Test status
Simulation time 229121943479 ps
CPU time 727.3 seconds
Started Apr 02 02:12:56 PM PDT 24
Finished Apr 02 02:25:04 PM PDT 24
Peak memory 225428 kb
Host smart-337cb37c-2006-49eb-a376-f060e792b979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412991180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2412991180
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3282693418
Short name T489
Test name
Test status
Simulation time 400549039 ps
CPU time 1.47 seconds
Started Apr 02 02:12:53 PM PDT 24
Finished Apr 02 02:12:55 PM PDT 24
Peak memory 198396 kb
Host smart-2623234a-629f-4238-9518-895e7658e8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282693418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3282693418
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3990032747
Short name T690
Test name
Test status
Simulation time 31605971592 ps
CPU time 52.59 seconds
Started Apr 02 02:12:44 PM PDT 24
Finished Apr 02 02:13:37 PM PDT 24
Peak memory 200448 kb
Host smart-a0e27980-3a8a-4023-9501-f0e88b6381e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990032747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3990032747
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.214973120
Short name T513
Test name
Test status
Simulation time 20323404874 ps
CPU time 34.35 seconds
Started Apr 02 02:22:14 PM PDT 24
Finished Apr 02 02:22:48 PM PDT 24
Peak memory 200452 kb
Host smart-2a78fa3a-b689-42e4-8488-d58693888dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214973120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.214973120
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3178322997
Short name T130
Test name
Test status
Simulation time 43227065339 ps
CPU time 272.89 seconds
Started Apr 02 02:22:13 PM PDT 24
Finished Apr 02 02:26:46 PM PDT 24
Peak memory 216948 kb
Host smart-7b8f59b9-83ee-46c0-96e0-5a5686414e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178322997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3178322997
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1319452743
Short name T510
Test name
Test status
Simulation time 22325561539 ps
CPU time 49.85 seconds
Started Apr 02 02:22:13 PM PDT 24
Finished Apr 02 02:23:03 PM PDT 24
Peak memory 200400 kb
Host smart-c5bafbac-8a03-4a24-89ae-170c20d54a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319452743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1319452743
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3189564616
Short name T670
Test name
Test status
Simulation time 37480715835 ps
CPU time 819.53 seconds
Started Apr 02 02:22:16 PM PDT 24
Finished Apr 02 02:35:57 PM PDT 24
Peak memory 215996 kb
Host smart-d328714a-3d9f-4d93-b1ea-f9cbdb6254b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189564616 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3189564616
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1091872887
Short name T232
Test name
Test status
Simulation time 63494148264 ps
CPU time 27.26 seconds
Started Apr 02 02:22:16 PM PDT 24
Finished Apr 02 02:22:44 PM PDT 24
Peak memory 200432 kb
Host smart-602a10b7-3118-4ef5-aef2-81a7d23ccbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091872887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1091872887
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2416464365
Short name T992
Test name
Test status
Simulation time 32307187241 ps
CPU time 504.37 seconds
Started Apr 02 02:22:18 PM PDT 24
Finished Apr 02 02:30:43 PM PDT 24
Peak memory 213924 kb
Host smart-25cba112-87e9-4aba-ab16-181cb60c826e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416464365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2416464365
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2171350023
Short name T433
Test name
Test status
Simulation time 20359688942 ps
CPU time 35.73 seconds
Started Apr 02 02:22:16 PM PDT 24
Finished Apr 02 02:22:53 PM PDT 24
Peak memory 200368 kb
Host smart-316b8553-f6df-449b-a3a1-71ce8969060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171350023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2171350023
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1358152623
Short name T1057
Test name
Test status
Simulation time 282053258930 ps
CPU time 682.95 seconds
Started Apr 02 02:22:17 PM PDT 24
Finished Apr 02 02:33:41 PM PDT 24
Peak memory 225632 kb
Host smart-fe475005-4af8-4328-9205-790058984b64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358152623 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1358152623
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3919155546
Short name T1180
Test name
Test status
Simulation time 18598064895 ps
CPU time 21.49 seconds
Started Apr 02 02:22:19 PM PDT 24
Finished Apr 02 02:22:41 PM PDT 24
Peak memory 200220 kb
Host smart-7c79d20e-6090-42e1-bc53-387d448465b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919155546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3919155546
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3647928348
Short name T58
Test name
Test status
Simulation time 20301504016 ps
CPU time 258.22 seconds
Started Apr 02 02:22:26 PM PDT 24
Finished Apr 02 02:26:44 PM PDT 24
Peak memory 216188 kb
Host smart-58e5d1c4-5a41-435d-a1e0-e29f79bbbf9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647928348 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3647928348
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2163844542
Short name T149
Test name
Test status
Simulation time 121272666065 ps
CPU time 20.92 seconds
Started Apr 02 02:22:20 PM PDT 24
Finished Apr 02 02:22:42 PM PDT 24
Peak memory 200404 kb
Host smart-2bcabdba-9c0c-4734-b742-6390841ced5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163844542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2163844542
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3871897055
Short name T818
Test name
Test status
Simulation time 164306946538 ps
CPU time 294.52 seconds
Started Apr 02 02:22:26 PM PDT 24
Finished Apr 02 02:27:21 PM PDT 24
Peak memory 216932 kb
Host smart-49bd6ba1-eb25-4e08-9267-b38be82b9ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871897055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3871897055
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1905290832
Short name T228
Test name
Test status
Simulation time 53082976259 ps
CPU time 24.76 seconds
Started Apr 02 02:22:23 PM PDT 24
Finished Apr 02 02:22:48 PM PDT 24
Peak memory 200428 kb
Host smart-c1272260-6b93-46d4-9168-5bbf71401d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905290832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1905290832
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3990605201
Short name T1034
Test name
Test status
Simulation time 30186834300 ps
CPU time 363.25 seconds
Started Apr 02 02:22:23 PM PDT 24
Finished Apr 02 02:28:27 PM PDT 24
Peak memory 216292 kb
Host smart-82fddfda-1072-443b-96f1-5585788fc0d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990605201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3990605201
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.428833497
Short name T2
Test name
Test status
Simulation time 29888459274 ps
CPU time 14.18 seconds
Started Apr 02 02:22:27 PM PDT 24
Finished Apr 02 02:22:41 PM PDT 24
Peak memory 200416 kb
Host smart-e4427c9a-4204-4b9a-83b8-0e24b50095d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428833497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.428833497
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.733048544
Short name T1037
Test name
Test status
Simulation time 34369151599 ps
CPU time 526.22 seconds
Started Apr 02 02:22:23 PM PDT 24
Finished Apr 02 02:31:10 PM PDT 24
Peak memory 217108 kb
Host smart-fffa7780-bca5-407f-82bd-f5663dc6e073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733048544 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.733048544
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.308573036
Short name T298
Test name
Test status
Simulation time 94628531073 ps
CPU time 993.05 seconds
Started Apr 02 02:22:24 PM PDT 24
Finished Apr 02 02:38:58 PM PDT 24
Peak memory 225368 kb
Host smart-c3992623-ba97-496d-9a0a-1ce519c2b8d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308573036 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.308573036
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1272168159
Short name T1104
Test name
Test status
Simulation time 328729376240 ps
CPU time 739.86 seconds
Started Apr 02 02:22:24 PM PDT 24
Finished Apr 02 02:34:45 PM PDT 24
Peak memory 228104 kb
Host smart-049ecf59-c869-40d1-b4cf-d8c5e9b0baf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272168159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1272168159
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2750173962
Short name T518
Test name
Test status
Simulation time 12670294 ps
CPU time 0.55 seconds
Started Apr 02 02:13:17 PM PDT 24
Finished Apr 02 02:13:18 PM PDT 24
Peak memory 195880 kb
Host smart-8c288942-b0e5-4e59-9a6e-98f915c5ebd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750173962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2750173962
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2901491577
Short name T1113
Test name
Test status
Simulation time 27359334500 ps
CPU time 45.64 seconds
Started Apr 02 02:12:55 PM PDT 24
Finished Apr 02 02:13:41 PM PDT 24
Peak memory 200460 kb
Host smart-da74355b-8f85-4fea-9a7b-aef0f612c00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901491577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2901491577
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2407658603
Short name T843
Test name
Test status
Simulation time 160512949843 ps
CPU time 25.71 seconds
Started Apr 02 02:12:57 PM PDT 24
Finished Apr 02 02:13:23 PM PDT 24
Peak memory 200420 kb
Host smart-1e2f54e4-39f7-4264-a6b4-e9b5d811c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407658603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2407658603
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3395871818
Short name T752
Test name
Test status
Simulation time 97806488592 ps
CPU time 46.83 seconds
Started Apr 02 02:13:03 PM PDT 24
Finished Apr 02 02:13:50 PM PDT 24
Peak memory 200476 kb
Host smart-ec95782f-daa4-4c47-9d76-b5cdd2a76851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395871818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3395871818
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1985258429
Short name T654
Test name
Test status
Simulation time 38206670403 ps
CPU time 60.12 seconds
Started Apr 02 02:13:01 PM PDT 24
Finished Apr 02 02:14:01 PM PDT 24
Peak memory 200108 kb
Host smart-43508887-1c61-4e5f-89af-7f9799d743e0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985258429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1985258429
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3214594292
Short name T35
Test name
Test status
Simulation time 44223339859 ps
CPU time 267.97 seconds
Started Apr 02 02:13:09 PM PDT 24
Finished Apr 02 02:17:37 PM PDT 24
Peak memory 200460 kb
Host smart-aefe0da1-60ad-4e7d-bc9d-6a653f620481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214594292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3214594292
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1408920453
Short name T1159
Test name
Test status
Simulation time 12030751536 ps
CPU time 22.52 seconds
Started Apr 02 02:13:06 PM PDT 24
Finished Apr 02 02:13:28 PM PDT 24
Peak memory 198524 kb
Host smart-b04049c3-4646-40df-ae39-67868a6ff097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408920453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1408920453
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1117421244
Short name T419
Test name
Test status
Simulation time 67044389334 ps
CPU time 115.28 seconds
Started Apr 02 02:13:01 PM PDT 24
Finished Apr 02 02:14:57 PM PDT 24
Peak memory 200684 kb
Host smart-3aeb28fb-4fe6-4bd6-ad9f-956bfbc1dbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117421244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1117421244
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.480265823
Short name T320
Test name
Test status
Simulation time 10042790963 ps
CPU time 44.77 seconds
Started Apr 02 02:13:07 PM PDT 24
Finished Apr 02 02:13:52 PM PDT 24
Peak memory 200440 kb
Host smart-2d9d9b13-e045-4c5d-ad59-cce8dabddfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480265823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.480265823
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3826046050
Short name T951
Test name
Test status
Simulation time 3375977374 ps
CPU time 13.39 seconds
Started Apr 02 02:12:58 PM PDT 24
Finished Apr 02 02:13:12 PM PDT 24
Peak memory 199384 kb
Host smart-5f44f1a7-daaf-4ce1-867d-8635694f512a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826046050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3826046050
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2726945511
Short name T742
Test name
Test status
Simulation time 31480628251 ps
CPU time 62.97 seconds
Started Apr 02 02:13:02 PM PDT 24
Finished Apr 02 02:14:05 PM PDT 24
Peak memory 200452 kb
Host smart-a83de79e-5519-4a6a-b958-b9a108ba8127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726945511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2726945511
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3429509183
Short name T335
Test name
Test status
Simulation time 25586484164 ps
CPU time 11.17 seconds
Started Apr 02 02:13:03 PM PDT 24
Finished Apr 02 02:13:14 PM PDT 24
Peak memory 196520 kb
Host smart-97ff011e-7b84-4d00-827d-6b0246d97e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429509183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3429509183
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.737749507
Short name T71
Test name
Test status
Simulation time 496552434 ps
CPU time 1.44 seconds
Started Apr 02 02:12:55 PM PDT 24
Finished Apr 02 02:12:56 PM PDT 24
Peak memory 200044 kb
Host smart-aec0a368-9e84-47e4-bacd-7c7be04085cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737749507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.737749507
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.333085355
Short name T557
Test name
Test status
Simulation time 1397946800 ps
CPU time 3.27 seconds
Started Apr 02 02:13:13 PM PDT 24
Finished Apr 02 02:13:16 PM PDT 24
Peak memory 199052 kb
Host smart-26f554b9-d03d-4aa3-ad4a-bb3e89140040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333085355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.333085355
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2404294460
Short name T19
Test name
Test status
Simulation time 101324060060 ps
CPU time 1961.57 seconds
Started Apr 02 02:13:10 PM PDT 24
Finished Apr 02 02:45:51 PM PDT 24
Peak memory 225148 kb
Host smart-8eb0de05-def1-4c8f-abe9-c3cf5718a72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404294460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2404294460
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2983305703
Short name T745
Test name
Test status
Simulation time 809966756 ps
CPU time 2.64 seconds
Started Apr 02 02:13:07 PM PDT 24
Finished Apr 02 02:13:09 PM PDT 24
Peak memory 199176 kb
Host smart-953a8749-3573-4a1c-b598-db0cf8efdfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983305703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2983305703
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2110429234
Short name T955
Test name
Test status
Simulation time 24401857031 ps
CPU time 21.28 seconds
Started Apr 02 02:12:58 PM PDT 24
Finished Apr 02 02:13:19 PM PDT 24
Peak memory 200252 kb
Host smart-c9f98ba5-1f7b-417a-b634-10feca7a44df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110429234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2110429234
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3236305150
Short name T378
Test name
Test status
Simulation time 68538270484 ps
CPU time 24.74 seconds
Started Apr 02 02:22:30 PM PDT 24
Finished Apr 02 02:22:55 PM PDT 24
Peak memory 200468 kb
Host smart-b5d8bd57-30b7-4a24-81d5-b37f4d27040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236305150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3236305150
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1265646582
Short name T505
Test name
Test status
Simulation time 104533481153 ps
CPU time 450.28 seconds
Started Apr 02 02:22:28 PM PDT 24
Finished Apr 02 02:29:58 PM PDT 24
Peak memory 210836 kb
Host smart-4c3287ee-f9ad-4b8d-b781-72748ae0838b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265646582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1265646582
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3120687265
Short name T979
Test name
Test status
Simulation time 96159129705 ps
CPU time 41.64 seconds
Started Apr 02 02:22:31 PM PDT 24
Finished Apr 02 02:23:13 PM PDT 24
Peak memory 200392 kb
Host smart-3c4f4db7-9cdc-4514-947b-f2694aab563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120687265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3120687265
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.653039200
Short name T1177
Test name
Test status
Simulation time 83337184245 ps
CPU time 1083.79 seconds
Started Apr 02 02:22:30 PM PDT 24
Finished Apr 02 02:40:34 PM PDT 24
Peak memory 216876 kb
Host smart-b6b5734f-00b4-4bc2-acdd-e179c22b0eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653039200 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.653039200
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.244561268
Short name T1120
Test name
Test status
Simulation time 26535636003 ps
CPU time 32.18 seconds
Started Apr 02 02:22:31 PM PDT 24
Finished Apr 02 02:23:03 PM PDT 24
Peak memory 200480 kb
Host smart-e6cc76c2-b758-4ef8-8777-4da58061c483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244561268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.244561268
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3771667678
Short name T893
Test name
Test status
Simulation time 70221914497 ps
CPU time 18.84 seconds
Started Apr 02 02:22:31 PM PDT 24
Finished Apr 02 02:22:50 PM PDT 24
Peak memory 200440 kb
Host smart-3ae730de-b2e1-4b6b-964f-22c32a543211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771667678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3771667678
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1584756700
Short name T253
Test name
Test status
Simulation time 453571638694 ps
CPU time 42.96 seconds
Started Apr 02 02:22:35 PM PDT 24
Finished Apr 02 02:23:18 PM PDT 24
Peak memory 200436 kb
Host smart-16c049fa-fe11-4b81-a35f-8921671a7a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584756700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1584756700
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4191847733
Short name T866
Test name
Test status
Simulation time 88404158483 ps
CPU time 947.31 seconds
Started Apr 02 02:22:36 PM PDT 24
Finished Apr 02 02:38:23 PM PDT 24
Peak memory 217144 kb
Host smart-756d1781-85da-498d-a2a2-8f4235933c44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191847733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4191847733
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3806082060
Short name T349
Test name
Test status
Simulation time 53507001239 ps
CPU time 64.41 seconds
Started Apr 02 02:22:34 PM PDT 24
Finished Apr 02 02:23:39 PM PDT 24
Peak memory 200504 kb
Host smart-403f6955-bf27-41ab-8ea8-fe7bccf6de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806082060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3806082060
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.451566237
Short name T350
Test name
Test status
Simulation time 657133830322 ps
CPU time 1519.45 seconds
Started Apr 02 02:22:36 PM PDT 24
Finished Apr 02 02:47:55 PM PDT 24
Peak memory 226492 kb
Host smart-ed36ece3-4a9e-4cc4-bff5-4373971723e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451566237 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.451566237
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3890441372
Short name T145
Test name
Test status
Simulation time 17009183671 ps
CPU time 29.25 seconds
Started Apr 02 02:22:34 PM PDT 24
Finished Apr 02 02:23:03 PM PDT 24
Peak memory 200344 kb
Host smart-14c5b01e-669a-4662-9dfd-bc233714b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890441372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3890441372
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1780310645
Short name T285
Test name
Test status
Simulation time 23388236065 ps
CPU time 221.1 seconds
Started Apr 02 02:22:34 PM PDT 24
Finished Apr 02 02:26:15 PM PDT 24
Peak memory 216960 kb
Host smart-08fe4a11-aebf-4c7e-8510-34629b4171c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780310645 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1780310645
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.444855565
Short name T761
Test name
Test status
Simulation time 22602041705 ps
CPU time 10.72 seconds
Started Apr 02 02:22:35 PM PDT 24
Finished Apr 02 02:22:46 PM PDT 24
Peak memory 200372 kb
Host smart-4b95f757-4519-4e7d-a028-2749f8683ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444855565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.444855565
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1649792639
Short name T246
Test name
Test status
Simulation time 79698641719 ps
CPU time 325.05 seconds
Started Apr 02 02:22:35 PM PDT 24
Finished Apr 02 02:28:00 PM PDT 24
Peak memory 217208 kb
Host smart-e2aece4c-5c7a-45a5-98a0-540e0be381eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649792639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1649792639
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.287380887
Short name T736
Test name
Test status
Simulation time 21222630616 ps
CPU time 44.1 seconds
Started Apr 02 02:22:39 PM PDT 24
Finished Apr 02 02:23:23 PM PDT 24
Peak memory 200440 kb
Host smart-9cc2883f-3066-4f41-8746-05f300d79ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287380887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.287380887
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.979671423
Short name T956
Test name
Test status
Simulation time 14569293524 ps
CPU time 162.54 seconds
Started Apr 02 02:22:38 PM PDT 24
Finished Apr 02 02:25:21 PM PDT 24
Peak memory 216868 kb
Host smart-bb713f46-08c4-44a7-9ada-e534fdd887e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979671423 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.979671423
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3081563505
Short name T1065
Test name
Test status
Simulation time 21984150208 ps
CPU time 32.49 seconds
Started Apr 02 02:22:39 PM PDT 24
Finished Apr 02 02:23:12 PM PDT 24
Peak memory 200480 kb
Host smart-591743b3-7750-4241-b72c-529d7c9d2136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081563505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3081563505
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1946589662
Short name T59
Test name
Test status
Simulation time 182576508363 ps
CPU time 546.15 seconds
Started Apr 02 02:22:37 PM PDT 24
Finished Apr 02 02:31:44 PM PDT 24
Peak memory 225432 kb
Host smart-f0c95aa2-1ece-4dda-a576-efc7a3c9e818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946589662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1946589662
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.816816303
Short name T922
Test name
Test status
Simulation time 11962322 ps
CPU time 0.58 seconds
Started Apr 02 02:13:33 PM PDT 24
Finished Apr 02 02:13:34 PM PDT 24
Peak memory 195856 kb
Host smart-b2e3f265-89ce-4314-999a-35c8f3513fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816816303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.816816303
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1608280046
Short name T847
Test name
Test status
Simulation time 328989833583 ps
CPU time 85.33 seconds
Started Apr 02 02:13:17 PM PDT 24
Finished Apr 02 02:14:42 PM PDT 24
Peak memory 200380 kb
Host smart-55f4d31e-3e64-4d87-b324-ce13187ae85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608280046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1608280046
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.233324519
Short name T747
Test name
Test status
Simulation time 48054577058 ps
CPU time 20.56 seconds
Started Apr 02 02:13:21 PM PDT 24
Finished Apr 02 02:13:41 PM PDT 24
Peak memory 200428 kb
Host smart-1919b684-76be-42e7-915a-ee6c36972c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233324519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.233324519
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3369956610
Short name T152
Test name
Test status
Simulation time 10914241333 ps
CPU time 19.38 seconds
Started Apr 02 02:13:23 PM PDT 24
Finished Apr 02 02:13:42 PM PDT 24
Peak memory 200456 kb
Host smart-8aa07ec5-d9ba-4543-90f7-728b11523a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369956610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3369956610
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2071295278
Short name T801
Test name
Test status
Simulation time 10951944726 ps
CPU time 4.72 seconds
Started Apr 02 02:13:25 PM PDT 24
Finished Apr 02 02:13:30 PM PDT 24
Peak memory 197164 kb
Host smart-bf03eb8d-67a4-450d-9cb1-30ae3ab5f88e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071295278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2071295278
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3729744109
Short name T849
Test name
Test status
Simulation time 71596360194 ps
CPU time 124.6 seconds
Started Apr 02 02:13:31 PM PDT 24
Finished Apr 02 02:15:36 PM PDT 24
Peak memory 200472 kb
Host smart-abcb13df-32db-4cb9-a1b7-25abce28634b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3729744109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3729744109
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1885756236
Short name T1093
Test name
Test status
Simulation time 12935229717 ps
CPU time 7.74 seconds
Started Apr 02 02:13:25 PM PDT 24
Finished Apr 02 02:13:33 PM PDT 24
Peak memory 199196 kb
Host smart-471f9163-f6bf-4132-ae00-5d8331a2e96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885756236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1885756236
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1438350168
Short name T39
Test name
Test status
Simulation time 129718559304 ps
CPU time 60.52 seconds
Started Apr 02 02:13:27 PM PDT 24
Finished Apr 02 02:14:27 PM PDT 24
Peak memory 200548 kb
Host smart-b68ca9ce-7ec7-429f-bc4f-1cd53b8027fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438350168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1438350168
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2185796398
Short name T396
Test name
Test status
Simulation time 13818073870 ps
CPU time 839.45 seconds
Started Apr 02 02:13:31 PM PDT 24
Finished Apr 02 02:27:30 PM PDT 24
Peak memory 200536 kb
Host smart-34d5c2bc-9361-4e28-9aa8-458d8868c5a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185796398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2185796398
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3480211240
Short name T340
Test name
Test status
Simulation time 6416433527 ps
CPU time 28.61 seconds
Started Apr 02 02:13:25 PM PDT 24
Finished Apr 02 02:13:53 PM PDT 24
Peak memory 199880 kb
Host smart-9cf76c4b-a08e-4f27-aa2b-c771fa2ba9c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480211240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3480211240
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3869566908
Short name T1032
Test name
Test status
Simulation time 166431787667 ps
CPU time 63.5 seconds
Started Apr 02 02:13:28 PM PDT 24
Finished Apr 02 02:14:32 PM PDT 24
Peak memory 200472 kb
Host smart-a93351bc-5fd3-4ea5-8524-73fc08ce0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869566908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3869566908
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3510425930
Short name T937
Test name
Test status
Simulation time 2455508096 ps
CPU time 1.84 seconds
Started Apr 02 02:13:31 PM PDT 24
Finished Apr 02 02:13:33 PM PDT 24
Peak memory 196260 kb
Host smart-0fa42dad-f8f6-47b1-a15e-c30756b12c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510425930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3510425930
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4232507202
Short name T1131
Test name
Test status
Simulation time 143079799 ps
CPU time 0.82 seconds
Started Apr 02 02:13:17 PM PDT 24
Finished Apr 02 02:13:18 PM PDT 24
Peak memory 198552 kb
Host smart-18039399-9e60-48bf-b74c-663fcfd43584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232507202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4232507202
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3338647372
Short name T1016
Test name
Test status
Simulation time 7373718741 ps
CPU time 108.29 seconds
Started Apr 02 02:13:31 PM PDT 24
Finished Apr 02 02:15:20 PM PDT 24
Peak memory 216968 kb
Host smart-131661bd-40a6-4b19-b707-17209708a395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338647372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3338647372
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.381682664
Short name T484
Test name
Test status
Simulation time 580327350 ps
CPU time 1.75 seconds
Started Apr 02 02:13:30 PM PDT 24
Finished Apr 02 02:13:32 PM PDT 24
Peak memory 199076 kb
Host smart-145fb9ba-16b6-4663-8447-1b7185ce3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381682664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.381682664
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2270440943
Short name T1132
Test name
Test status
Simulation time 36748446945 ps
CPU time 15.63 seconds
Started Apr 02 02:13:18 PM PDT 24
Finished Apr 02 02:13:34 PM PDT 24
Peak memory 200196 kb
Host smart-6305f898-82cd-4d77-a10a-b49f33843c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270440943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2270440943
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1591418389
Short name T1025
Test name
Test status
Simulation time 114986506642 ps
CPU time 113.53 seconds
Started Apr 02 02:22:42 PM PDT 24
Finished Apr 02 02:24:36 PM PDT 24
Peak memory 200520 kb
Host smart-54e4cc0d-865d-4192-8103-a160ddaeaa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591418389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1591418389
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.417472222
Short name T31
Test name
Test status
Simulation time 11107142012 ps
CPU time 42.25 seconds
Started Apr 02 02:22:41 PM PDT 24
Finished Apr 02 02:23:24 PM PDT 24
Peak memory 216244 kb
Host smart-4fb32f84-87f9-46b8-98d5-f61cf689322b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417472222 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.417472222
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1031013789
Short name T696
Test name
Test status
Simulation time 42389477532 ps
CPU time 44.06 seconds
Started Apr 02 02:22:47 PM PDT 24
Finished Apr 02 02:23:31 PM PDT 24
Peak memory 200488 kb
Host smart-b27b915c-b883-4e9d-ba2f-d2d64a774d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031013789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1031013789
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3928011865
Short name T224
Test name
Test status
Simulation time 185316401205 ps
CPU time 554.87 seconds
Started Apr 02 02:22:48 PM PDT 24
Finished Apr 02 02:32:03 PM PDT 24
Peak memory 225364 kb
Host smart-2102f1ef-5482-4698-90ba-51a6101e4b76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928011865 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3928011865
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3939035367
Short name T247
Test name
Test status
Simulation time 17625490994 ps
CPU time 30.64 seconds
Started Apr 02 02:22:49 PM PDT 24
Finished Apr 02 02:23:20 PM PDT 24
Peak memory 200424 kb
Host smart-72e116cb-3ab3-49aa-8339-1c674eb26835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939035367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3939035367
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.160272501
Short name T336
Test name
Test status
Simulation time 23527064340 ps
CPU time 175.1 seconds
Started Apr 02 02:22:49 PM PDT 24
Finished Apr 02 02:25:44 PM PDT 24
Peak memory 216456 kb
Host smart-99e30a30-86fe-4ef4-a93a-f991e52d50a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160272501 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.160272501
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.4207003175
Short name T1061
Test name
Test status
Simulation time 22224693607 ps
CPU time 10.97 seconds
Started Apr 02 02:22:49 PM PDT 24
Finished Apr 02 02:23:00 PM PDT 24
Peak memory 200312 kb
Host smart-4c051a60-6081-400c-a08c-d242616aaa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207003175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.4207003175
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2389429327
Short name T938
Test name
Test status
Simulation time 187541548373 ps
CPU time 542.76 seconds
Started Apr 02 02:22:49 PM PDT 24
Finished Apr 02 02:31:52 PM PDT 24
Peak memory 211708 kb
Host smart-c779511e-de8d-4695-830a-c07c3a718eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389429327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2389429327
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.716978529
Short name T137
Test name
Test status
Simulation time 2510790348 ps
CPU time 5.4 seconds
Started Apr 02 02:22:48 PM PDT 24
Finished Apr 02 02:22:54 PM PDT 24
Peak memory 200416 kb
Host smart-fbdc5d96-3327-4268-9fa6-2bb152037efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716978529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.716978529
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2100501194
Short name T73
Test name
Test status
Simulation time 69411899161 ps
CPU time 138.79 seconds
Started Apr 02 02:22:52 PM PDT 24
Finished Apr 02 02:25:10 PM PDT 24
Peak memory 211988 kb
Host smart-26298aab-7151-4e2b-8662-76379ffc5e35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100501194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2100501194
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.852317705
Short name T1045
Test name
Test status
Simulation time 79920718258 ps
CPU time 9.25 seconds
Started Apr 02 02:22:54 PM PDT 24
Finished Apr 02 02:23:03 PM PDT 24
Peak memory 200332 kb
Host smart-e6623083-dfc4-4821-b934-97b104edfcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852317705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.852317705
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.715975013
Short name T786
Test name
Test status
Simulation time 28661947148 ps
CPU time 296.76 seconds
Started Apr 02 02:22:57 PM PDT 24
Finished Apr 02 02:27:54 PM PDT 24
Peak memory 217212 kb
Host smart-e336f7db-a0fa-4c50-8995-ee9bf92520a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715975013 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.715975013
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1485930719
Short name T432
Test name
Test status
Simulation time 171042245721 ps
CPU time 35.44 seconds
Started Apr 02 02:22:57 PM PDT 24
Finished Apr 02 02:23:32 PM PDT 24
Peak memory 200392 kb
Host smart-2cb8163c-5a1d-4555-87df-80961a41b04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485930719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1485930719
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1871704383
Short name T508
Test name
Test status
Simulation time 120857551353 ps
CPU time 286.8 seconds
Started Apr 02 02:23:00 PM PDT 24
Finished Apr 02 02:27:47 PM PDT 24
Peak memory 200396 kb
Host smart-3c8feec1-3e48-4558-9ebf-70f59a1c9f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871704383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1871704383
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1858676836
Short name T684
Test name
Test status
Simulation time 105947667662 ps
CPU time 333.02 seconds
Started Apr 02 02:23:01 PM PDT 24
Finished Apr 02 02:28:34 PM PDT 24
Peak memory 216876 kb
Host smart-1a492bf4-1a4d-43c8-af2c-90b1c73dc544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858676836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1858676836
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2070402024
Short name T53
Test name
Test status
Simulation time 192596620557 ps
CPU time 62.93 seconds
Started Apr 02 02:23:00 PM PDT 24
Finished Apr 02 02:24:03 PM PDT 24
Peak memory 200524 kb
Host smart-927effc4-a727-467a-b705-bb900cda66dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070402024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2070402024
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2382626665
Short name T555
Test name
Test status
Simulation time 75585894667 ps
CPU time 1731.57 seconds
Started Apr 02 02:22:58 PM PDT 24
Finished Apr 02 02:51:50 PM PDT 24
Peak memory 217220 kb
Host smart-63357ad9-c0df-44bb-b354-024e163eb459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382626665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2382626665
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1104255790
Short name T1036
Test name
Test status
Simulation time 25306223891 ps
CPU time 291.55 seconds
Started Apr 02 02:23:04 PM PDT 24
Finished Apr 02 02:27:55 PM PDT 24
Peak memory 213496 kb
Host smart-e29cd4e5-70e2-4d7c-88d6-3e6dedbb8103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104255790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1104255790
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2534767643
Short name T799
Test name
Test status
Simulation time 11867738 ps
CPU time 0.54 seconds
Started Apr 02 02:13:45 PM PDT 24
Finished Apr 02 02:13:46 PM PDT 24
Peak memory 194860 kb
Host smart-ed524cda-11f9-4a6f-b8f1-f09ebc0ce609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534767643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2534767643
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1688134112
Short name T314
Test name
Test status
Simulation time 28023837666 ps
CPU time 23.83 seconds
Started Apr 02 02:13:34 PM PDT 24
Finished Apr 02 02:13:58 PM PDT 24
Peak memory 200432 kb
Host smart-cde7ea26-e336-4977-b6ec-325f464761c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688134112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1688134112
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2489669680
Short name T774
Test name
Test status
Simulation time 33145313597 ps
CPU time 26.31 seconds
Started Apr 02 02:13:35 PM PDT 24
Finished Apr 02 02:14:02 PM PDT 24
Peak memory 200416 kb
Host smart-7527c62e-bffb-4302-afa7-88e9e2f31cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489669680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2489669680
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3476750440
Short name T268
Test name
Test status
Simulation time 26080484183 ps
CPU time 14.86 seconds
Started Apr 02 02:13:36 PM PDT 24
Finished Apr 02 02:13:51 PM PDT 24
Peak memory 200460 kb
Host smart-66688099-793c-4e22-b82a-8c6098ad0331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476750440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3476750440
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3512324683
Short name T827
Test name
Test status
Simulation time 47175823573 ps
CPU time 45.02 seconds
Started Apr 02 02:13:37 PM PDT 24
Finished Apr 02 02:14:22 PM PDT 24
Peak memory 200380 kb
Host smart-c41d195f-6f4d-429d-8fa9-f7aae8e78cd8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512324683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3512324683
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4063833554
Short name T657
Test name
Test status
Simulation time 101551353198 ps
CPU time 192.99 seconds
Started Apr 02 02:13:46 PM PDT 24
Finished Apr 02 02:16:59 PM PDT 24
Peak memory 200524 kb
Host smart-9c7b6aec-f252-4f91-b7cc-a88a98b5f368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063833554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4063833554
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2172636603
Short name T475
Test name
Test status
Simulation time 903861729 ps
CPU time 1.85 seconds
Started Apr 02 02:13:43 PM PDT 24
Finished Apr 02 02:13:45 PM PDT 24
Peak memory 195968 kb
Host smart-da299ece-bd40-4fcc-a749-cd3ffd3a7dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172636603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2172636603
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.376944813
Short name T820
Test name
Test status
Simulation time 69064414694 ps
CPU time 55.48 seconds
Started Apr 02 02:13:37 PM PDT 24
Finished Apr 02 02:14:32 PM PDT 24
Peak memory 200716 kb
Host smart-8f9d3fdf-42f0-44ae-941d-0e7bbac2b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376944813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.376944813
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3831521410
Short name T376
Test name
Test status
Simulation time 7105827071 ps
CPU time 238.5 seconds
Started Apr 02 02:13:45 PM PDT 24
Finished Apr 02 02:17:44 PM PDT 24
Peak memory 200388 kb
Host smart-3d5889a4-2616-4c45-b5cc-44ab31032be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831521410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3831521410
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4130214874
Short name T105
Test name
Test status
Simulation time 2860301931 ps
CPU time 10.69 seconds
Started Apr 02 02:13:33 PM PDT 24
Finished Apr 02 02:13:44 PM PDT 24
Peak memory 198768 kb
Host smart-b0c8aeb3-028d-4461-bc30-15d506f6054a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130214874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4130214874
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2810636279
Short name T487
Test name
Test status
Simulation time 106927477524 ps
CPU time 23.6 seconds
Started Apr 02 02:13:40 PM PDT 24
Finished Apr 02 02:14:04 PM PDT 24
Peak memory 200300 kb
Host smart-6eb1f200-c867-4dd8-ad3f-c01f155119e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810636279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2810636279
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2727014014
Short name T373
Test name
Test status
Simulation time 46254642853 ps
CPU time 77.84 seconds
Started Apr 02 02:13:36 PM PDT 24
Finished Apr 02 02:14:54 PM PDT 24
Peak memory 196172 kb
Host smart-a8b1aa51-1d89-4dd2-9101-35967c2262ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727014014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2727014014
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2357089542
Short name T447
Test name
Test status
Simulation time 435721357 ps
CPU time 2.07 seconds
Started Apr 02 02:13:33 PM PDT 24
Finished Apr 02 02:13:35 PM PDT 24
Peak memory 199080 kb
Host smart-e8ee80ea-39c3-4503-b73e-0cb5ea14d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357089542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2357089542
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1311468219
Short name T898
Test name
Test status
Simulation time 179916335276 ps
CPU time 108.97 seconds
Started Apr 02 02:13:47 PM PDT 24
Finished Apr 02 02:15:36 PM PDT 24
Peak memory 200372 kb
Host smart-01ced86a-acc5-404b-a713-a426f474dd71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311468219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1311468219
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1742301743
Short name T919
Test name
Test status
Simulation time 248467085877 ps
CPU time 560.12 seconds
Started Apr 02 02:13:47 PM PDT 24
Finished Apr 02 02:23:07 PM PDT 24
Peak memory 225412 kb
Host smart-d9cec0cd-f65f-4e8e-9cfe-67e8e3a8aa30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742301743 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1742301743
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.258907234
Short name T398
Test name
Test status
Simulation time 866797964 ps
CPU time 2.95 seconds
Started Apr 02 02:13:42 PM PDT 24
Finished Apr 02 02:13:45 PM PDT 24
Peak memory 198908 kb
Host smart-1803982c-888a-40aa-81dd-96774af4f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258907234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.258907234
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1798745034
Short name T927
Test name
Test status
Simulation time 103478538151 ps
CPU time 59.78 seconds
Started Apr 02 02:13:36 PM PDT 24
Finished Apr 02 02:14:36 PM PDT 24
Peak memory 200448 kb
Host smart-b680362c-f977-4993-86d7-58b94ea18bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798745034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1798745034
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1826597128
Short name T483
Test name
Test status
Simulation time 92135231315 ps
CPU time 1119.56 seconds
Started Apr 02 02:23:05 PM PDT 24
Finished Apr 02 02:41:44 PM PDT 24
Peak memory 228012 kb
Host smart-025c6488-020a-464c-b307-5aa973f1804d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826597128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1826597128
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.4281147915
Short name T463
Test name
Test status
Simulation time 8134310692 ps
CPU time 13.33 seconds
Started Apr 02 02:23:04 PM PDT 24
Finished Apr 02 02:23:17 PM PDT 24
Peak memory 200340 kb
Host smart-79f2f224-e651-46d4-8614-beb7d5010d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281147915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4281147915
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1679805190
Short name T633
Test name
Test status
Simulation time 50579624124 ps
CPU time 355.82 seconds
Started Apr 02 02:23:04 PM PDT 24
Finished Apr 02 02:29:00 PM PDT 24
Peak memory 217172 kb
Host smart-dc7ebdf5-87d8-4770-9470-9c5b63d44014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679805190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1679805190
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1282675122
Short name T299
Test name
Test status
Simulation time 51562000093 ps
CPU time 50.15 seconds
Started Apr 02 02:23:08 PM PDT 24
Finished Apr 02 02:23:58 PM PDT 24
Peak memory 200452 kb
Host smart-9fd5a367-9019-4058-95df-eeee3293a8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282675122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1282675122
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1196590253
Short name T1077
Test name
Test status
Simulation time 52478406263 ps
CPU time 319.64 seconds
Started Apr 02 02:23:10 PM PDT 24
Finished Apr 02 02:28:30 PM PDT 24
Peak memory 217252 kb
Host smart-f329d4f4-23bf-462b-8954-26eb893a08fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196590253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1196590253
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1874340100
Short name T516
Test name
Test status
Simulation time 110260392022 ps
CPU time 54.11 seconds
Started Apr 02 02:23:11 PM PDT 24
Finished Apr 02 02:24:06 PM PDT 24
Peak memory 200448 kb
Host smart-8d9d3acb-b76e-4e50-a6e6-2b92b76abd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874340100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1874340100
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.745713115
Short name T221
Test name
Test status
Simulation time 119645864090 ps
CPU time 278.28 seconds
Started Apr 02 02:23:11 PM PDT 24
Finished Apr 02 02:27:49 PM PDT 24
Peak memory 217212 kb
Host smart-fdf5c497-767d-4a5b-a97b-add58b1bd762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745713115 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.745713115
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2708878251
Short name T509
Test name
Test status
Simulation time 25102070973 ps
CPU time 12.36 seconds
Started Apr 02 02:23:11 PM PDT 24
Finished Apr 02 02:23:24 PM PDT 24
Peak memory 200360 kb
Host smart-218ac726-12f6-4558-a37f-a7137608d705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708878251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2708878251
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3383441069
Short name T114
Test name
Test status
Simulation time 26154521907 ps
CPU time 199.95 seconds
Started Apr 02 02:23:16 PM PDT 24
Finished Apr 02 02:26:37 PM PDT 24
Peak memory 208732 kb
Host smart-be3b07d7-448a-4fd5-967f-1945e67bb12b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383441069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3383441069
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.4222069103
Short name T1155
Test name
Test status
Simulation time 58576696043 ps
CPU time 71.7 seconds
Started Apr 02 02:23:15 PM PDT 24
Finished Apr 02 02:24:27 PM PDT 24
Peak memory 200476 kb
Host smart-80f86855-b034-4153-a6b0-c0119e1f780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222069103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.4222069103
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4132323817
Short name T561
Test name
Test status
Simulation time 44501059503 ps
CPU time 734.45 seconds
Started Apr 02 02:23:15 PM PDT 24
Finished Apr 02 02:35:30 PM PDT 24
Peak memory 213296 kb
Host smart-b89dabae-a292-4fbc-8c67-614aa3f03205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132323817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4132323817
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.971985022
Short name T187
Test name
Test status
Simulation time 123107281657 ps
CPU time 188.77 seconds
Started Apr 02 02:23:19 PM PDT 24
Finished Apr 02 02:26:28 PM PDT 24
Peak memory 200396 kb
Host smart-191a7016-705e-4729-a947-cfbe369cc571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971985022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.971985022
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1168436788
Short name T161
Test name
Test status
Simulation time 84051369197 ps
CPU time 531.87 seconds
Started Apr 02 02:23:22 PM PDT 24
Finished Apr 02 02:32:15 PM PDT 24
Peak memory 216852 kb
Host smart-7c0d3464-746c-4fe9-9b43-278821f740ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168436788 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1168436788
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3473212251
Short name T202
Test name
Test status
Simulation time 41817622984 ps
CPU time 27.33 seconds
Started Apr 02 02:23:20 PM PDT 24
Finished Apr 02 02:23:47 PM PDT 24
Peak memory 200300 kb
Host smart-1058a62b-a3ba-4af1-bc7d-ce8d4b9a1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473212251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3473212251
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.449534943
Short name T173
Test name
Test status
Simulation time 154602319061 ps
CPU time 318.28 seconds
Started Apr 02 02:23:17 PM PDT 24
Finished Apr 02 02:28:35 PM PDT 24
Peak memory 216732 kb
Host smart-e71a309c-c477-43dd-a6dd-d24bbbf0f5c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449534943 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.449534943
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1093156677
Short name T840
Test name
Test status
Simulation time 42155322466 ps
CPU time 17.36 seconds
Started Apr 02 02:23:17 PM PDT 24
Finished Apr 02 02:23:35 PM PDT 24
Peak memory 200484 kb
Host smart-dc3d0a66-eb6b-4c0a-9188-23c5e010e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093156677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1093156677
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3710254334
Short name T763
Test name
Test status
Simulation time 419882269461 ps
CPU time 549.67 seconds
Started Apr 02 02:23:16 PM PDT 24
Finished Apr 02 02:32:27 PM PDT 24
Peak memory 213972 kb
Host smart-1cd319c0-19b6-401b-8a43-98fbaaf0756e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710254334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3710254334
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%