Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	114695	1			T1	6		T2	9		T3	122
all_values[1]	114695	1			T1	6		T2	9		T3	122
all_values[2]	114695	1			T1	6		T2	9		T3	122
all_values[3]	114695	1			T1	6		T2	9		T3	122
all_values[4]	114695	1			T1	6		T2	9		T3	122
all_values[5]	114695	1			T1	6		T2	9		T3	122
all_values[6]	114695	1			T1	6		T2	9		T3	122
all_values[7]	114695	1			T1	6		T2	9		T3	122

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465444

1

T1

23

T2

36

T3

840

auto[1]

452116

1

T1

25

T2

36

T3

136

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

861846

1

T1

40

T2

61

T3

858

auto[1]

55714

1

T1

8

T2

11

T3

118

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38411	1			T3	4		T4	25		T5	752
all_values[0]	auto[0]	auto[1]	21113	1			T1	2		T2	4		T3	115
all_values[0]	auto[1]	auto[0]	32771	1			T1	1		T5	103		T8	6
all_values[0]	auto[1]	auto[1]	22400	1			T1	3		T2	5		T3	3
all_values[1]	auto[0]	auto[0]	57327	1			T1	4		T2	4		T3	121
all_values[1]	auto[0]	auto[1]	1702	1			T10	2		T12	1		T13	11
all_values[1]	auto[1]	auto[0]	54002	1			T1	2		T2	5		T3	1
all_values[1]	auto[1]	auto[1]	1664	1			T8	6		T38	1		T104	37
all_values[2]	auto[0]	auto[0]	54205	1			T1	1		T2	2		T3	119
all_values[2]	auto[0]	auto[1]	2851	1			T1	2		T4	2		T5	2
all_values[2]	auto[1]	auto[0]	55023	1			T1	2		T2	5		T3	3
all_values[2]	auto[1]	auto[1]	2616	1			T1	1		T2	2		T4	3
all_values[3]	auto[0]	auto[0]	59283	1			T1	1		T2	9		T3	10
all_values[3]	auto[0]	auto[1]	316	1			T15	1		T32	1		T22	2
all_values[3]	auto[1]	auto[0]	54727	1			T1	5		T3	112		T4	44
all_values[3]	auto[1]	auto[1]	369	1			T13	1		T14	1		T16	2
all_values[4]	auto[0]	auto[0]	59099	1			T1	4		T2	4		T3	119
all_values[4]	auto[0]	auto[1]	478	1			T14	4		T16	2		T19	2
all_values[4]	auto[1]	auto[0]	54563	1			T1	2		T2	5		T3	3
all_values[4]	auto[1]	auto[1]	555	1			T14	11		T32	2		T22	5
all_values[5]	auto[0]	auto[0]	56085	1			T1	3		T2	2		T3	114
all_values[5]	auto[0]	auto[1]	237	1			T16	4		T19	1		T32	2
all_values[5]	auto[1]	auto[0]	58189	1			T1	3		T2	7		T3	8
all_values[5]	auto[1]	auto[1]	184	1			T16	1		T19	2		T32	4
all_values[6]	auto[0]	auto[0]	59152	1			T1	2		T2	9		T3	116
all_values[6]	auto[0]	auto[1]	232	1			T16	1		T19	2		T32	3
all_values[6]	auto[1]	auto[0]	55093	1			T1	4		T3	6		T4	3
all_values[6]	auto[1]	auto[1]	218	1			T16	2		T19	1		T32	2
all_values[7]	auto[0]	auto[0]	54516	1			T1	4		T2	2		T3	122
all_values[7]	auto[0]	auto[1]	437	1			T16	4		T32	4		T44	2
all_values[7]	auto[1]	auto[0]	59400	1			T1	2		T2	7		T4	34
all_values[7]	auto[1]	auto[1]	342	1			T14	5		T16	1		T19	2