Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2589

1

T1

1

T2

1

T3

6

auto[UartRx]

2589

1

T1

1

T2

1

T3

6

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4557	1			T1	2		T2	2		T3	6
values[1]	42	1			T3	1		T25	1		T35	1
values[2]	51	1			T36	1		T37	1		T49	1
values[3]	53	1			T16	2		T19	2		T32	1
values[4]	61	1			T16	1		T32	1		T34	2
values[5]	66	1			T16	1		T35	2		T36	3
values[6]	54	1			T32	2		T36	2		T108	1
values[7]	60	1			T3	1		T25	1		T32	1
values[8]	61	1			T3	2		T25	1		T19	3
values[9]	60	1			T3	1		T25	1		T32	1
values[10]	71	1			T32	3		T33	1		T37	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2372	1			T1	1		T2	1		T3	5
auto[UartTx]	values[1]	15	1			T25	1		T37	2		T108	1
auto[UartTx]	values[2]	17	1			T49	1		T277	1		T112	1
auto[UartTx]	values[3]	16	1			T16	1		T33	1		T37	1
auto[UartTx]	values[4]	32	1			T16	1		T32	1		T108	2
auto[UartTx]	values[5]	15	1			T35	1		T272	1		T308	1
auto[UartTx]	values[6]	19	1			T32	1		T272	2		T309	1
auto[UartTx]	values[7]	17	1			T25	1		T36	1		T310	1
auto[UartTx]	values[8]	19	1			T3	1		T19	1		T49	1
auto[UartTx]	values[9]	22	1			T25	1		T35	1		T36	1
auto[UartTx]	values[10]	30	1			T32	1		T37	1		T108	1
auto[UartRx]	values[0]	2185	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	27	1			T3	1		T35	1		T277	1
auto[UartRx]	values[2]	34	1			T36	1		T37	1		T277	1
auto[UartRx]	values[3]	37	1			T16	1		T19	2		T32	1
auto[UartRx]	values[4]	29	1			T34	2		T35	1		T277	1
auto[UartRx]	values[5]	51	1			T16	1		T35	1		T36	3
auto[UartRx]	values[6]	35	1			T32	1		T36	2		T108	1
auto[UartRx]	values[7]	43	1			T3	1		T32	1		T33	1
auto[UartRx]	values[8]	42	1			T3	1		T25	1		T19	2
auto[UartRx]	values[9]	38	1			T3	1		T32	1		T37	1
auto[UartRx]	values[10]	41	1			T32	2		T33	1		T108	1