Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2462	1			T1	1		T2	1		T3	7
auto[BaudRate115200]	2100	1			T1	1		T2	3		T3	15
auto[BaudRate230400]	2121	1			T2	2		T3	10		T4	3
auto[BaudRate128Kbps]	2090	1			T2	3		T3	12		T5	2
auto[BaudRate256Kbps]	2420	1			T1	2		T2	1		T3	3
auto[BaudRate1Mbps]	1894	1			T1	1		T2	4		T3	1
auto[BaudRate1p5Mbps]	1379	1			T1	2		T2	2		T3	6

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1531	1			T6	5		T276	5		T40	5
freqs[25]	1695	1			T12	10		T39	7		T24	45
freqs[48]	527	1			T7	2		T311	5		T312	16
freqs[50]	269	1			T10	10		T11	2		T42	2
freqs[100]	1137	1			T4	10		T105	10		T21	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	260	1			T6	5		T46	1		T144	2
auto[BaudRate9600]	freqs[25]	258	1			T39	1		T24	6		T125	2
auto[BaudRate9600]	freqs[48]	108	1			T311	5		T312	16		T281	1
auto[BaudRate9600]	freqs[50]	33	1			T10	1		T42	2		T118	1
auto[BaudRate9600]	freqs[100]	164	1			T21	1		T116	2		T156	2
auto[BaudRate115200]	freqs[24]	223	1			T40	1		T124	2		T144	1
auto[BaudRate115200]	freqs[25]	260	1			T39	1		T24	9		T15	2
auto[BaudRate115200]	freqs[48]	69	1			T281	1		T282	4		T278	3
auto[BaudRate115200]	freqs[50]	44	1			T10	2		T118	2		T127	1
auto[BaudRate115200]	freqs[100]	137	1			T4	1		T105	2		T116	2
auto[BaudRate230400]	freqs[24]	217	1			T276	1		T40	2		T46	2
auto[BaudRate230400]	freqs[25]	244	1			T24	6		T15	1		T257	4
auto[BaudRate230400]	freqs[48]	60	1			T7	1		T283	1		T281	1
auto[BaudRate230400]	freqs[50]	34	1			T10	1		T11	1		T118	2
auto[BaudRate230400]	freqs[100]	149	1			T4	3		T105	1		T116	1
auto[BaudRate128Kbps]	freqs[24]	226	1			T276	2		T46	2		T124	2
auto[BaudRate128Kbps]	freqs[25]	269	1			T39	1		T125	1		T257	2
auto[BaudRate128Kbps]	freqs[48]	67	1			T283	1		T282	3		T278	3
auto[BaudRate128Kbps]	freqs[50]	42	1			T10	2		T127	1		T192	1
auto[BaudRate128Kbps]	freqs[100]	168	1			T105	4		T116	2		T156	2
auto[BaudRate256Kbps]	freqs[24]	240	1			T40	1		T144	2		T264	2
auto[BaudRate256Kbps]	freqs[25]	272	1			T12	3		T39	3		T24	15
auto[BaudRate256Kbps]	freqs[48]	67	1			T281	1		T282	4		T278	1
auto[BaudRate256Kbps]	freqs[50]	41	1			T10	2		T118	2		T192	2
auto[BaudRate256Kbps]	freqs[100]	172	1			T4	1		T105	3		T156	1
auto[BaudRate1Mbps]	freqs[24]	240	1			T276	1		T123	2		T124	3
auto[BaudRate1Mbps]	freqs[25]	272	1			T12	4		T24	6		T15	1
auto[BaudRate1Mbps]	freqs[48]	83	1			T7	1		T281	1		T282	2
auto[BaudRate1Mbps]	freqs[50]	40	1			T11	1		T118	1		T127	1
auto[BaudRate1Mbps]	freqs[100]	174	1			T4	1		T116	2		T156	2
auto[BaudRate1p5Mbps]	freqs[25]	120	1			T12	3		T39	1		T24	3
auto[BaudRate1p5Mbps]	freqs[48]	73	1			T281	1		T304	3		T259	1
auto[BaudRate1p5Mbps]	freqs[50]	35	1			T10	2		T192	1		T300	1
auto[BaudRate1p5Mbps]	freqs[100]	173	1			T4	4		T21	1		T116	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded