Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31092084	1			T1	178		T2	149		T3	35843
all_levels[1]	172072	1			T1	1		T2	14		T3	15
all_levels[2]	2341	1			T1	3		T2	3		T12	26
all_levels[3]	1044	1			T2	2		T13	2		T115	1
all_levels[4]	704	1			T2	1		T20	2		T13	2
all_levels[5]	559	1			T1	1		T2	1		T20	1
all_levels[6]	433	1			T2	2		T13	1		T115	2
all_levels[7]	353	1			T1	1		T2	2		T20	2
all_levels[8]	294	1			T2	1		T10	2		T13	2
all_levels[9]	245	1			T2	1		T13	1		T115	3
all_levels[10]	232	1			T2	1		T13	1		T115	1
all_levels[11]	209	1			T115	1		T103	2		T104	1
all_levels[12]	142	1			T105	1		T41	1		T48	1
all_levels[13]	144	1			T10	1		T38	1		T103	1
all_levels[14]	125	1			T10	1		T115	1		T103	2
all_levels[15]	109	1			T103	1		T105	2		T16	1
all_levels[16]	115	1			T8	5		T115	1		T105	2
all_levels[17]	101	1			T105	1		T116	1		T33	1
all_levels[18]	72	1			T117	1		T33	4		T118	1
all_levels[19]	70	1			T119	3		T120	3		T121	1
all_levels[20]	110	1			T4	1		T115	1		T120	2
all_levels[21]	74	1			T10	1		T115	1		T103	1
all_levels[22]	68	1			T13	1		T103	2		T122	1
all_levels[23]	56	1			T123	1		T124	1		T120	1
all_levels[24]	55	1			T125	2		T126	1		T23	1
all_levels[25]	50	1			T124	1		T122	2		T127	1
all_levels[26]	42	1			T41	1		T49	1		T111	1
all_levels[27]	43	1			T128	1		T116	1		T129	1
all_levels[28]	41	1			T122	1		T116	1		T33	1
all_levels[29]	28	1			T34	1		T130	1		T108	1
all_levels[30]	43	1			T38	2		T15	1		T117	1
all_levels[31]	39	1			T131	1		T34	1		T132	1
all_levels[32]	28	1			T124	1		T131	1		T132	1
all_levels[33]	27	1			T133	1		T134	2		T135	1
all_levels[34]	31	1			T136	1		T132	1		T133	1
all_levels[35]	30	1			T4	1		T111	1		T137	2
all_levels[36]	28	1			T124	1		T120	2		T136	1
all_levels[37]	28	1			T117	1		T120	2		T132	1
all_levels[38]	16	1			T138	1		T139	1		T140	1
all_levels[39]	24	1			T141	1		T142	1		T143	1
all_levels[40]	19	1			T144	1		T122	1		T33	1
all_levels[41]	32	1			T10	1		T106	2		T138	1
all_levels[42]	21	1			T112	1		T145	1		T146	1
all_levels[43]	16	1			T147	1		T92	1		T148	1
all_levels[44]	32	1			T144	1		T149	3		T150	2
all_levels[45]	18	1			T151	1		T138	1		T141	1
all_levels[46]	23	1			T15	1		T121	1		T152	1
all_levels[47]	17	1			T153	1		T152	1		T154	1
all_levels[48]	15	1			T130	1		T146	1		T155	1
all_levels[49]	8	1			T39	1		T156	1		T146	1
all_levels[50]	6	1			T121	1		T157	1		T158	1
all_levels[51]	17	1			T159	4		T160	5		T161	1
all_levels[52]	10	1			T15	1		T145	1		T162	1
all_levels[53]	11	1			T134	1		T163	1		T164	1
all_levels[54]	12	1			T111	2		T165	1		T166	1
all_levels[55]	9	1			T4	1		T167	1		T97	1
all_levels[56]	10	1			T4	1		T10	1		T92	1
all_levels[57]	8	1			T168	1		T169	1		T170	2
all_levels[58]	9	1			T106	1		T23	1		T49	2
all_levels[59]	5	1			T123	1		T155	1		T98	1
all_levels[60]	12	1			T23	1		T130	1		T171	1
all_levels[61]	12	1			T10	3		T39	1		T138	1
all_levels[62]	13	1			T39	1		T167	1		T49	1
all_levels[63]	14	1			T34	1		T158	1		T168	1
all_levels[64]	115	1			T13	1		T15	1		T34	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31267888

1

T1

184

T2

177

T3

35850

auto[1]

4885

1

T3

8

T6

1

T8

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[49] , all_levels[50]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31087687	1			T1	178		T2	149		T3	35835
all_levels[0]	auto[1]	4397	1			T3	8		T6	1		T8	1
all_levels[1]	auto[0]	172000	1			T1	1		T2	14		T3	15
all_levels[1]	auto[1]	72	1			T46	1		T106	2		T131	1
all_levels[2]	auto[0]	2312	1			T1	3		T2	3		T12	26
all_levels[2]	auto[1]	29	1			T41	1		T126	1		T120	1
all_levels[3]	auto[0]	1028	1			T2	2		T13	2		T115	1
all_levels[3]	auto[1]	16	1			T104	1		T157	2		T172	3
all_levels[4]	auto[0]	689	1			T2	1		T20	2		T13	2
all_levels[4]	auto[1]	15	1			T128	1		T125	1		T131	1
all_levels[5]	auto[0]	541	1			T1	1		T2	1		T20	1
all_levels[5]	auto[1]	18	1			T128	3		T106	1		T120	1
all_levels[6]	auto[0]	413	1			T2	2		T13	1		T115	2
all_levels[6]	auto[1]	20	1			T151	1		T127	2		T129	2
all_levels[7]	auto[0]	331	1			T1	1		T2	2		T20	2
all_levels[7]	auto[1]	22	1			T38	2		T156	1		T167	1
all_levels[8]	auto[0]	280	1			T2	1		T10	2		T13	2
all_levels[8]	auto[1]	14	1			T134	1		T173	3		T174	2
all_levels[9]	auto[0]	232	1			T2	1		T13	1		T115	3
all_levels[9]	auto[1]	13	1			T175	2		T176	1		T177	1
all_levels[10]	auto[0]	217	1			T2	1		T13	1		T115	1
all_levels[10]	auto[1]	15	1			T178	2		T179	1		T180	3
all_levels[11]	auto[0]	202	1			T115	1		T103	2		T104	1
all_levels[11]	auto[1]	7	1			T181	2		T51	1		T182	1
all_levels[12]	auto[0]	135	1			T105	1		T41	1		T48	1
all_levels[12]	auto[1]	7	1			T136	2		T176	2		T66	1
all_levels[13]	auto[0]	131	1			T10	1		T38	1		T103	1
all_levels[13]	auto[1]	13	1			T36	3		T183	1		T184	1
all_levels[14]	auto[0]	116	1			T10	1		T115	1		T103	2
all_levels[14]	auto[1]	9	1			T123	1		T185	1		T186	1
all_levels[15]	auto[0]	98	1			T103	1		T105	2		T16	1
all_levels[15]	auto[1]	11	1			T187	1		T188	1		T189	2
all_levels[16]	auto[0]	98	1			T8	1		T115	1		T105	1
all_levels[16]	auto[1]	17	1			T8	4		T105	1		T190	1
all_levels[17]	auto[0]	93	1			T105	1		T116	1		T33	1
all_levels[17]	auto[1]	8	1			T191	1		T184	1		T189	2
all_levels[18]	auto[0]	69	1			T117	1		T33	4		T118	1
all_levels[18]	auto[1]	3	1			T192	1		T193	1		T194	1
all_levels[19]	auto[0]	65	1			T119	3		T120	2		T121	1
all_levels[19]	auto[1]	5	1			T120	1		T195	1		T196	1
all_levels[20]	auto[0]	71	1			T4	1		T115	1		T120	2
all_levels[20]	auto[1]	39	1			T197	1		T198	35		T199	1
all_levels[21]	auto[0]	63	1			T10	1		T115	1		T103	1
all_levels[21]	auto[1]	11	1			T157	1		T200	1		T201	3
all_levels[22]	auto[0]	65	1			T13	1		T103	2		T122	1
all_levels[22]	auto[1]	3	1			T202	1		T203	1		T204	1
all_levels[23]	auto[0]	52	1			T123	1		T124	1		T120	1
all_levels[23]	auto[1]	4	1			T202	1		T205	2		T206	1
all_levels[24]	auto[0]	53	1			T125	2		T126	1		T23	1
all_levels[24]	auto[1]	2	1			T151	2		-	-		-	-
all_levels[25]	auto[0]	49	1			T124	1		T122	2		T127	1
all_levels[25]	auto[1]	1	1			T207	1		-	-		-	-
all_levels[26]	auto[0]	40	1			T41	1		T49	1		T111	1
all_levels[26]	auto[1]	2	1			T208	1		T209	1		-	-
all_levels[27]	auto[0]	39	1			T128	1		T116	1		T129	1
all_levels[27]	auto[1]	4	1			T210	1		T92	1		T211	1
all_levels[28]	auto[0]	34	1			T122	1		T116	1		T33	1
all_levels[28]	auto[1]	7	1			T184	1		T212	2		T213	1
all_levels[29]	auto[0]	26	1			T34	1		T130	1		T108	1
all_levels[29]	auto[1]	2	1			T214	1		T215	1		-	-
all_levels[30]	auto[0]	40	1			T38	1		T15	1		T117	1
all_levels[30]	auto[1]	3	1			T38	1		T216	1		T217	1
all_levels[31]	auto[0]	34	1			T131	1		T34	1		T132	1
all_levels[31]	auto[1]	5	1			T218	3		T219	2		-	-
all_levels[32]	auto[0]	25	1			T124	1		T131	1		T132	1
all_levels[32]	auto[1]	3	1			T172	1		T220	2		-	-
all_levels[33]	auto[0]	25	1			T133	1		T134	1		T135	1
all_levels[33]	auto[1]	2	1			T134	1		T221	1		-	-
all_levels[34]	auto[0]	30	1			T136	1		T132	1		T133	1
all_levels[34]	auto[1]	1	1			T164	1		-	-		-	-
all_levels[35]	auto[0]	27	1			T4	1		T111	1		T137	1
all_levels[35]	auto[1]	3	1			T137	1		T222	2		-	-
all_levels[36]	auto[0]	24	1			T124	1		T120	1		T136	1
all_levels[36]	auto[1]	4	1			T120	1		T223	2		T224	1
all_levels[37]	auto[0]	23	1			T117	1		T120	1		T132	1
all_levels[37]	auto[1]	5	1			T120	1		T225	1		T226	3
all_levels[38]	auto[0]	16	1			T138	1		T139	1		T140	1
all_levels[39]	auto[0]	22	1			T141	1		T142	1		T143	1
all_levels[39]	auto[1]	2	1			T170	1		T227	1		-	-
all_levels[40]	auto[0]	18	1			T144	1		T122	1		T33	1
all_levels[40]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[41]	auto[0]	25	1			T10	1		T106	1		T138	1
all_levels[41]	auto[1]	7	1			T106	1		T210	1		T229	1
all_levels[42]	auto[0]	21	1			T112	1		T145	1		T146	1
all_levels[43]	auto[0]	15	1			T147	1		T92	1		T148	1
all_levels[43]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[44]	auto[0]	29	1			T144	1		T149	1		T150	2
all_levels[44]	auto[1]	3	1			T149	2		T231	1		-	-
all_levels[45]	auto[0]	18	1			T151	1		T138	1		T141	1
all_levels[46]	auto[0]	18	1			T15	1		T121	1		T152	1
all_levels[46]	auto[1]	5	1			T140	1		T148	3		T232	1
all_levels[47]	auto[0]	14	1			T153	1		T152	1		T154	1
all_levels[47]	auto[1]	3	1			T233	1		T234	2		-	-
all_levels[48]	auto[0]	10	1			T130	1		T146	1		T155	1
all_levels[48]	auto[1]	5	1			T235	4		T236	1		-	-
all_levels[49]	auto[0]	8	1			T39	1		T156	1		T146	1
all_levels[50]	auto[0]	6	1			T121	1		T157	1		T158	1
all_levels[51]	auto[0]	9	1			T159	1		T160	2		T161	1
all_levels[51]	auto[1]	8	1			T159	3		T160	3		T237	2
all_levels[52]	auto[0]	8	1			T15	1		T145	1		T162	1
all_levels[52]	auto[1]	2	1			T238	2		-	-		-	-
all_levels[53]	auto[0]	10	1			T134	1		T163	1		T164	1
all_levels[53]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[54]	auto[0]	9	1			T111	2		T165	1		T166	1
all_levels[54]	auto[1]	3	1			T240	1		T241	2		-	-
all_levels[55]	auto[0]	8	1			T4	1		T167	1		T97	1
all_levels[55]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[56]	auto[0]	10	1			T4	1		T10	1		T92	1
all_levels[57]	auto[0]	5	1			T168	1		T169	1		T170	1
all_levels[57]	auto[1]	3	1			T170	1		T243	2		-	-
all_levels[58]	auto[0]	9	1			T106	1		T23	1		T49	2
all_levels[59]	auto[0]	5	1			T123	1		T155	1		T98	1
all_levels[60]	auto[0]	9	1			T23	1		T130	1		T171	1
all_levels[60]	auto[1]	3	1			T226	1		T212	1		T244	1
all_levels[61]	auto[0]	10	1			T10	2		T39	1		T138	1
all_levels[61]	auto[1]	2	1			T10	1		T245	1		-	-
all_levels[62]	auto[0]	12	1			T39	1		T167	1		T49	1
all_levels[62]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[63]	auto[0]	10	1			T34	1		T158	1		T168	1
all_levels[63]	auto[1]	4	1			T247	4		-	-		-	-
all_levels[64]	auto[0]	97	1			T13	1		T15	1		T34	1
all_levels[64]	auto[1]	18	1			T173	1		T208	1		T248	1