Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	114695	1			T1	6		T2	9		T3	122
all_pins[1]	114695	1			T1	6		T2	9		T3	122
all_pins[2]	114695	1			T1	6		T2	9		T3	122
all_pins[3]	114695	1			T1	6		T2	9		T3	122
all_pins[4]	114695	1			T1	6		T2	9		T3	122
all_pins[5]	114695	1			T1	6		T2	9		T3	122
all_pins[6]	114695	1			T1	6		T2	9		T3	122
all_pins[7]	114695	1			T1	6		T2	9		T3	122

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	888247	1			T1	42		T2	65		T3	973
values[0x1]	29313	1			T1	6		T2	7		T3	3
transitions[0x0=>0x1]	28152	1			T1	6		T2	7		T3	3
transitions[0x1=>0x0]	27723	1			T1	5		T2	7		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92216	1			T1	3		T2	4		T3	119
all_pins[0]	values[0x1]	22479	1			T1	3		T2	5		T3	3
all_pins[0]	transitions[0x0=>0x1]	21930	1			T1	3		T2	5		T3	3
all_pins[0]	transitions[0x1=>0x0]	1115	1			T8	6		T38	1		T104	37
all_pins[1]	values[0x0]	113031	1			T1	6		T2	9		T3	122
all_pins[1]	values[0x1]	1664	1			T8	6		T38	1		T104	37
all_pins[1]	transitions[0x0=>0x1]	1575	1			T8	6		T38	1		T104	37
all_pins[1]	transitions[0x1=>0x0]	2584	1			T1	1		T2	2		T4	3
all_pins[2]	values[0x0]	112022	1			T1	5		T2	7		T3	122
all_pins[2]	values[0x1]	2673	1			T1	1		T2	2		T4	3
all_pins[2]	transitions[0x0=>0x1]	2590	1			T1	1		T2	2		T4	3
all_pins[2]	transitions[0x1=>0x0]	286	1			T13	1		T14	1		T16	2
all_pins[3]	values[0x0]	114326	1			T1	6		T2	9		T3	122
all_pins[3]	values[0x1]	369	1			T13	1		T14	1		T16	2
all_pins[3]	transitions[0x0=>0x1]	300	1			T13	1		T14	1		T16	2
all_pins[3]	transitions[0x1=>0x0]	486	1			T14	11		T32	2		T22	5
all_pins[4]	values[0x0]	114140	1			T1	6		T2	9		T3	122
all_pins[4]	values[0x1]	555	1			T14	11		T32	2		T22	5
all_pins[4]	transitions[0x0=>0x1]	460	1			T14	11		T32	2		T22	5
all_pins[4]	transitions[0x1=>0x0]	155	1			T14	1		T16	1		T19	2
all_pins[5]	values[0x0]	114445	1			T1	6		T2	9		T3	122
all_pins[5]	values[0x1]	250	1			T14	1		T16	1		T19	2
all_pins[5]	transitions[0x0=>0x1]	201	1			T14	1		T16	1		T19	2
all_pins[5]	transitions[0x1=>0x0]	932	1			T1	2		T20	3		T38	1
all_pins[6]	values[0x0]	113714	1			T1	4		T2	9		T3	122
all_pins[6]	values[0x1]	981	1			T1	2		T20	3		T38	1
all_pins[6]	transitions[0x0=>0x1]	914	1			T1	2		T20	3		T38	1
all_pins[6]	transitions[0x1=>0x0]	275	1			T14	5		T19	1		T22	1
all_pins[7]	values[0x0]	114353	1			T1	6		T2	9		T3	122
all_pins[7]	values[0x1]	342	1			T14	5		T16	1		T19	2
all_pins[7]	transitions[0x0=>0x1]	182	1			T14	5		T19	1		T22	1
all_pins[7]	transitions[0x1=>0x0]	21890	1			T1	2		T2	5		T3	3