Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6702482	1			T1	27		T2	91		T3	35775
all_levels[1]	1053401	1			T1	117		T2	14		T4	5
all_levels[2]	483627	1			T1	9		T2	23		T3	5
all_levels[3]	245210	1			T1	5		T2	10		T3	3
all_levels[4]	424878	1			T1	27		T2	1		T3	2
all_levels[5]	245479	1			T5	4352		T12	33		T20	2
all_levels[6]	272995	1			T2	6		T5	6345		T8	4
all_levels[7]	232996	1			T2	2		T3	65		T4	1
all_levels[8]	255154	1			T4	1		T5	2281		T12	33
all_levels[9]	330809	1			T5	2293		T12	26		T38	2
all_levels[10]	290919	1			T2	6		T5	2285		T12	41
all_levels[11]	247095	1			T2	2		T5	2286		T10	3
all_levels[12]	423598	1			T5	2290		T10	3		T12	37
all_levels[13]	258567	1			T5	2294		T12	34		T20	4
all_levels[14]	226701	1			T4	1		T5	2295		T12	31
all_levels[15]	319699	1			T5	2290		T12	39		T103	5
all_levels[16]	315714	1			T5	2289		T12	34		T13	2
all_levels[17]	218673	1			T2	5		T5	2291		T12	34
all_levels[18]	254385	1			T2	2		T4	1		T5	2293
all_levels[19]	238286	1			T2	2		T5	2287		T12	32
all_levels[20]	239930	1			T4	3		T5	2292		T12	34
all_levels[21]	454584	1			T5	2281		T12	33		T20	9
all_levels[22]	316096	1			T5	2294		T12	35		T38	3
all_levels[23]	220520	1			T5	2292		T12	31		T38	1
all_levels[24]	529654	1			T5	2278		T12	39		T20	2
all_levels[25]	391115	1			T5	30484		T12	39		T20	3
all_levels[26]	288483	1			T4	5		T5	2295		T12	36
all_levels[27]	269843	1			T2	4		T4	4		T5	2287
all_levels[28]	255450	1			T2	10		T5	2291		T10	3
all_levels[29]	202101	1			T5	2281		T12	34		T20	2
all_levels[30]	267511	1			T5	2439		T12	32		T252	4685
all_levels[31]	552542	1			T5	13595		T12	1514		T252	4614
all_levels[32]	14243747	1			T4	15		T5	95935		T10	8

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31267888

1

T1

184

T2

177

T3

35850

auto[1]

4356

1

T1

1

T2

1

T6

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6700174	1			T1	27		T2	91		T3	35775
all_levels[0]	auto[1]	2308	1			T6	1		T8	1		T10	1
all_levels[1]	auto[0]	1053123	1			T1	117		T2	14		T4	5
all_levels[1]	auto[1]	278	1			T10	3		T13	3		T41	2
all_levels[2]	auto[0]	483597	1			T1	8		T2	22		T3	5
all_levels[2]	auto[1]	30	1			T1	1		T2	1		T117	4
all_levels[3]	auto[0]	245070	1			T1	5		T2	10		T3	3
all_levels[3]	auto[1]	140	1			T10	1		T13	1		T14	24
all_levels[4]	auto[0]	424847	1			T1	27		T2	1		T3	2
all_levels[4]	auto[1]	31	1			T38	1		T123	1		T314	1
all_levels[5]	auto[0]	245448	1			T5	4352		T12	33		T20	2
all_levels[5]	auto[1]	31	1			T175	3		T136	1		T315	1
all_levels[6]	auto[0]	272967	1			T2	6		T5	6345		T8	1
all_levels[6]	auto[1]	28	1			T8	3		T41	1		T119	1
all_levels[7]	auto[0]	232738	1			T2	2		T3	65		T4	1
all_levels[7]	auto[1]	258	1			T105	2		T126	1		T110	8
all_levels[8]	auto[0]	255131	1			T4	1		T5	2281		T12	33
all_levels[8]	auto[1]	23	1			T167	1		T176	1		T290	2
all_levels[9]	auto[0]	330790	1			T5	2293		T12	26		T38	2
all_levels[9]	auto[1]	19	1			T125	1		T316	1		T317	3
all_levels[10]	auto[0]	290890	1			T2	6		T5	2285		T12	41
all_levels[10]	auto[1]	29	1			T314	1		T305	1		T318	1
all_levels[11]	auto[0]	247077	1			T2	2		T5	2286		T10	2
all_levels[11]	auto[1]	18	1			T10	1		T106	1		T133	2
all_levels[12]	auto[0]	423580	1			T5	2290		T10	2		T12	37
all_levels[12]	auto[1]	18	1			T10	1		T41	1		T15	2
all_levels[13]	auto[0]	258535	1			T5	2294		T12	34		T20	4
all_levels[13]	auto[1]	32	1			T46	1		T120	1		T319	1
all_levels[14]	auto[0]	226687	1			T4	1		T5	2295		T12	31
all_levels[14]	auto[1]	14	1			T23	1		T320	2		T321	2
all_levels[15]	auto[0]	319523	1			T5	2290		T12	39		T103	5
all_levels[15]	auto[1]	176	1			T273	2		T293	1		T107	4
all_levels[16]	auto[0]	315690	1			T5	2289		T12	34		T13	1
all_levels[16]	auto[1]	24	1			T13	1		T200	2		T294	1
all_levels[17]	auto[0]	218640	1			T2	5		T5	2291		T12	34
all_levels[17]	auto[1]	33	1			T125	2		T126	2		T111	1
all_levels[18]	auto[0]	254375	1			T2	2		T4	1		T5	2293
all_levels[18]	auto[1]	10	1			T159	1		T322	1		T323	1
all_levels[19]	auto[0]	238253	1			T2	2		T5	2287		T12	32
all_levels[19]	auto[1]	33	1			T274	1		T282	1		T324	2
all_levels[20]	auto[0]	239911	1			T4	3		T5	2292		T12	34
all_levels[20]	auto[1]	19	1			T125	1		T260	1		T200	1
all_levels[21]	auto[0]	454566	1			T5	2281		T12	33		T20	9
all_levels[21]	auto[1]	18	1			T49	1		T137	1		T197	1
all_levels[22]	auto[0]	316078	1			T5	2294		T12	35		T38	3
all_levels[22]	auto[1]	18	1			T128	3		T137	1		T197	1
all_levels[23]	auto[0]	220507	1			T5	2292		T12	31		T38	1
all_levels[23]	auto[1]	13	1			T200	1		T325	2		T143	1
all_levels[24]	auto[0]	529629	1			T5	2278		T12	39		T20	2
all_levels[24]	auto[1]	25	1			T103	1		T48	1		T126	2
all_levels[25]	auto[0]	391094	1			T5	30484		T12	39		T20	3
all_levels[25]	auto[1]	21	1			T105	1		T131	1		T273	1
all_levels[26]	auto[0]	288469	1			T4	5		T5	2295		T12	36
all_levels[26]	auto[1]	14	1			T40	1		T117	1		T179	1
all_levels[27]	auto[0]	269828	1			T2	4		T4	4		T5	2287
all_levels[27]	auto[1]	15	1			T38	1		T104	1		T228	2
all_levels[28]	auto[0]	255428	1			T2	10		T5	2291		T10	2
all_levels[28]	auto[1]	22	1			T10	1		T49	1		T326	1
all_levels[29]	auto[0]	202082	1			T5	2281		T12	34		T20	2
all_levels[29]	auto[1]	19	1			T105	3		T106	2		T273	1
all_levels[30]	auto[0]	267492	1			T5	2439		T12	32		T252	4685
all_levels[30]	auto[1]	19	1			T157	3		T108	1		T305	2
all_levels[31]	auto[0]	552507	1			T5	13595		T12	1514		T252	4614
all_levels[31]	auto[1]	35	1			T127	1		T327	1		T183	1
all_levels[32]	auto[0]	14243162	1			T4	15		T5	95935		T10	7
all_levels[32]	auto[1]	585	1			T10	1		T12	1		T252	1