Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	898	1			T16	7		T19	7		T32	11
all_values[1]	898	1			T16	7		T19	7		T32	11
all_values[2]	898	1			T16	7		T19	7		T32	11
all_values[3]	898	1			T16	7		T19	7		T32	11
all_values[4]	898	1			T16	7		T19	7		T32	11
all_values[5]	898	1			T16	7		T19	7		T32	11
all_values[6]	898	1			T16	7		T19	7		T32	11
all_values[7]	898	1			T16	7		T19	7		T32	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3930

1

T16

27

T19

37

T32

42

auto[1]

3254

1

T16

29

T19

19

T32

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2582

1

T16

19

T19

25

T32

38

auto[1]

4602

1

T16

37

T19

31

T32

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4230

1

T16

30

T19

32

T32

61

auto[1]

2954

1

T16

26

T19

24

T32

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	302	1			T16	3		T19	4		T32	2
all_values[0]	auto[0]	auto[1]	auto[1]	227	1			T16	2		T32	6		T33	2
all_values[0]	auto[1]	auto[0]	auto[1]	218	1			T19	2		T32	1		T33	4
all_values[0]	auto[1]	auto[1]	auto[1]	151	1			T16	2		T19	1		T32	2
all_values[1]	auto[0]	auto[0]	auto[0]	286	1			T16	2		T19	2		T32	3
all_values[1]	auto[0]	auto[1]	auto[0]	241	1			T16	1		T19	2		T32	3
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T19	1		T32	3		T33	1
all_values[1]	auto[1]	auto[1]	auto[1]	189	1			T16	4		T19	2		T32	2
all_values[2]	auto[0]	auto[0]	auto[0]	193	1			T16	1		T19	4		T32	5
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T19	1		T35	2		T37	3
all_values[2]	auto[0]	auto[1]	auto[0]	159	1			T16	2		T19	1		T32	4
all_values[2]	auto[0]	auto[1]	auto[1]	98	1			T16	1		T33	2		T35	2
all_values[2]	auto[1]	auto[0]	auto[1]	209	1			T16	2		T19	1		T32	1
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T16	1		T32	1		T33	4
all_values[3]	auto[0]	auto[0]	auto[0]	187	1			T16	2		T19	1		T32	4
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T33	1		T35	1		T37	2
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T16	3		T19	3		T32	3
all_values[3]	auto[0]	auto[1]	auto[1]	106	1			T32	1		T33	1		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T19	3		T32	2		T33	1
all_values[3]	auto[1]	auto[1]	auto[1]	187	1			T16	2		T32	1		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	179	1			T16	2		T19	1		T32	2
all_values[4]	auto[0]	auto[0]	auto[1]	104	1			T16	1		T19	1		T32	1
all_values[4]	auto[0]	auto[1]	auto[0]	156	1			T16	1		T19	2		T32	2
all_values[4]	auto[0]	auto[1]	auto[1]	93	1			T32	2		T33	2		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T16	2		T19	2		T32	4
all_values[4]	auto[1]	auto[1]	auto[1]	173	1			T16	1		T19	1		T33	1
all_values[5]	auto[0]	auto[0]	auto[0]	200	1			T16	1		T19	3		T33	1
all_values[5]	auto[0]	auto[0]	auto[1]	87	1			T16	2		T32	2		T33	1
all_values[5]	auto[0]	auto[1]	auto[0]	163	1			T16	1		T32	3		T33	1
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T32	3		T35	2		T108	1
all_values[5]	auto[1]	auto[0]	auto[1]	231	1			T16	2		T19	3		T32	1
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T16	1		T19	1		T32	2
all_values[6]	auto[0]	auto[0]	auto[0]	196	1			T16	1		T19	1		T32	4
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T32	1		T33	2		T35	1
all_values[6]	auto[0]	auto[1]	auto[0]	146	1			T16	1		T19	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[1]	101	1			T16	2		T32	1		T108	1
all_values[6]	auto[1]	auto[0]	auto[1]	208	1			T16	1		T19	3		T32	3
all_values[6]	auto[1]	auto[1]	auto[1]	148	1			T16	2		T19	2		T32	1
all_values[7]	auto[0]	auto[0]	auto[0]	187	1			T16	1		T19	2		T33	1
all_values[7]	auto[0]	auto[0]	auto[1]	104	1			T32	3		T35	4		T114	2
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T19	2		T32	4		T33	4
all_values[7]	auto[0]	auto[1]	auto[1]	92	1			T19	1		T32	1		T114	1
all_values[7]	auto[1]	auto[0]	auto[1]	206	1			T16	4		T19	2		T33	1
all_values[7]	auto[1]	auto[1]	auto[1]	161	1			T16	2		T32	3		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal