Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.28 99.27 97.95 100.00 98.80 100.00 99.64


Total test records in report: 1318
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T1253 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4005374362 Apr 04 12:40:07 PM PDT 24 Apr 04 12:40:09 PM PDT 24 15891245 ps
T1254 /workspace/coverage/cover_reg_top/19.uart_intr_test.2940981238 Apr 04 12:40:31 PM PDT 24 Apr 04 12:40:31 PM PDT 24 13735122 ps
T1255 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1113794691 Apr 04 12:40:17 PM PDT 24 Apr 04 12:40:18 PM PDT 24 25679663 ps
T1256 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.663999209 Apr 04 12:40:28 PM PDT 24 Apr 04 12:40:29 PM PDT 24 52159829 ps
T1257 /workspace/coverage/cover_reg_top/3.uart_tl_errors.290924422 Apr 04 12:39:47 PM PDT 24 Apr 04 12:39:49 PM PDT 24 73963103 ps
T1258 /workspace/coverage/cover_reg_top/49.uart_intr_test.3469530790 Apr 04 12:41:59 PM PDT 24 Apr 04 12:42:00 PM PDT 24 14681814 ps
T1259 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1916641367 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:09 PM PDT 24 58350833 ps
T60 /workspace/coverage/cover_reg_top/16.uart_csr_rw.779870635 Apr 04 12:40:17 PM PDT 24 Apr 04 12:40:18 PM PDT 24 15300837 ps
T61 /workspace/coverage/cover_reg_top/11.uart_csr_rw.841031036 Apr 04 12:40:05 PM PDT 24 Apr 04 12:40:07 PM PDT 24 14567322 ps
T1260 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2668750434 Apr 04 12:40:18 PM PDT 24 Apr 04 12:40:19 PM PDT 24 37751059 ps
T1261 /workspace/coverage/cover_reg_top/26.uart_intr_test.958879970 Apr 04 12:40:29 PM PDT 24 Apr 04 12:40:29 PM PDT 24 60559448 ps
T1262 /workspace/coverage/cover_reg_top/35.uart_intr_test.2643435900 Apr 04 12:40:34 PM PDT 24 Apr 04 12:40:35 PM PDT 24 13790828 ps
T1263 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4185448356 Apr 04 12:40:05 PM PDT 24 Apr 04 12:40:07 PM PDT 24 389987685 ps
T1264 /workspace/coverage/cover_reg_top/46.uart_intr_test.1621878171 Apr 04 12:40:33 PM PDT 24 Apr 04 12:40:34 PM PDT 24 65202466 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.649043980 Apr 04 12:39:44 PM PDT 24 Apr 04 12:39:45 PM PDT 24 26528765 ps
T1266 /workspace/coverage/cover_reg_top/16.uart_intr_test.3998288647 Apr 04 12:40:21 PM PDT 24 Apr 04 12:40:21 PM PDT 24 25475484 ps
T1267 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2985753549 Apr 04 12:40:18 PM PDT 24 Apr 04 12:40:19 PM PDT 24 17986158 ps
T1268 /workspace/coverage/cover_reg_top/23.uart_intr_test.1997556142 Apr 04 12:40:38 PM PDT 24 Apr 04 12:40:39 PM PDT 24 39042501 ps
T1269 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2607698787 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:08 PM PDT 24 20734275 ps
T1270 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2333352285 Apr 04 12:39:44 PM PDT 24 Apr 04 12:39:46 PM PDT 24 527462255 ps
T1271 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3577895957 Apr 04 12:40:57 PM PDT 24 Apr 04 12:40:58 PM PDT 24 114015412 ps
T1272 /workspace/coverage/cover_reg_top/29.uart_intr_test.626378480 Apr 04 12:40:31 PM PDT 24 Apr 04 12:40:31 PM PDT 24 10997527 ps
T1273 /workspace/coverage/cover_reg_top/36.uart_intr_test.1569032463 Apr 04 12:40:30 PM PDT 24 Apr 04 12:40:30 PM PDT 24 11678057 ps
T1274 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2092092259 Apr 04 12:40:18 PM PDT 24 Apr 04 12:40:20 PM PDT 24 23792591 ps
T1275 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1272456617 Apr 04 12:40:04 PM PDT 24 Apr 04 12:40:07 PM PDT 24 39164685 ps
T1276 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2728857616 Apr 04 12:40:31 PM PDT 24 Apr 04 12:40:31 PM PDT 24 33951467 ps
T1277 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1190785936 Apr 04 12:40:28 PM PDT 24 Apr 04 12:40:29 PM PDT 24 58025987 ps
T1278 /workspace/coverage/cover_reg_top/2.uart_intr_test.3154505234 Apr 04 12:39:44 PM PDT 24 Apr 04 12:39:44 PM PDT 24 11863748 ps
T1279 /workspace/coverage/cover_reg_top/18.uart_tl_errors.4071170500 Apr 04 12:40:29 PM PDT 24 Apr 04 12:40:31 PM PDT 24 329691050 ps
T1280 /workspace/coverage/cover_reg_top/12.uart_csr_rw.747327633 Apr 04 12:40:17 PM PDT 24 Apr 04 12:40:18 PM PDT 24 84187992 ps
T1281 /workspace/coverage/cover_reg_top/44.uart_intr_test.2674743443 Apr 04 12:40:32 PM PDT 24 Apr 04 12:40:32 PM PDT 24 11212634 ps
T1282 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1631098084 Apr 04 12:39:54 PM PDT 24 Apr 04 12:39:54 PM PDT 24 23969291 ps
T1283 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1011027822 Apr 04 12:40:22 PM PDT 24 Apr 04 12:40:23 PM PDT 24 379593386 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1924130683 Apr 04 12:39:36 PM PDT 24 Apr 04 12:39:38 PM PDT 24 208961109 ps
T1285 /workspace/coverage/cover_reg_top/3.uart_intr_test.1708440371 Apr 04 12:39:42 PM PDT 24 Apr 04 12:39:43 PM PDT 24 26426039 ps
T1286 /workspace/coverage/cover_reg_top/11.uart_intr_test.3675538880 Apr 04 12:40:04 PM PDT 24 Apr 04 12:40:07 PM PDT 24 34310579 ps
T1287 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2165199114 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:09 PM PDT 24 242193145 ps
T1288 /workspace/coverage/cover_reg_top/41.uart_intr_test.4142285068 Apr 04 12:40:29 PM PDT 24 Apr 04 12:40:34 PM PDT 24 31219976 ps
T1289 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1951549437 Apr 04 12:40:17 PM PDT 24 Apr 04 12:40:18 PM PDT 24 46379280 ps
T1290 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2672945661 Apr 04 12:39:52 PM PDT 24 Apr 04 12:39:54 PM PDT 24 25101797 ps
T1291 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.519433628 Apr 04 12:39:37 PM PDT 24 Apr 04 12:39:39 PM PDT 24 44784550 ps
T1292 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2814857827 Apr 04 12:39:43 PM PDT 24 Apr 04 12:39:44 PM PDT 24 30113112 ps
T1293 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1344403209 Apr 04 12:39:39 PM PDT 24 Apr 04 12:39:40 PM PDT 24 27480225 ps
T1294 /workspace/coverage/cover_reg_top/13.uart_tl_errors.887797193 Apr 04 12:40:18 PM PDT 24 Apr 04 12:40:20 PM PDT 24 96464021 ps
T1295 /workspace/coverage/cover_reg_top/9.uart_intr_test.2788141236 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:08 PM PDT 24 18790154 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.849258260 Apr 04 12:40:18 PM PDT 24 Apr 04 12:40:19 PM PDT 24 22210849 ps
T1297 /workspace/coverage/cover_reg_top/42.uart_intr_test.317645715 Apr 04 12:40:38 PM PDT 24 Apr 04 12:40:39 PM PDT 24 16159630 ps
T1298 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1091947933 Apr 04 12:39:53 PM PDT 24 Apr 04 12:39:54 PM PDT 24 192374377 ps
T1299 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1482017791 Apr 04 12:39:54 PM PDT 24 Apr 04 12:39:56 PM PDT 24 68160155 ps
T1300 /workspace/coverage/cover_reg_top/31.uart_intr_test.2347583244 Apr 04 12:40:38 PM PDT 24 Apr 04 12:40:39 PM PDT 24 49645041 ps
T1301 /workspace/coverage/cover_reg_top/22.uart_intr_test.4043371332 Apr 04 12:40:34 PM PDT 24 Apr 04 12:40:35 PM PDT 24 21771465 ps
T1302 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2922439164 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:08 PM PDT 24 17650920 ps
T1303 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3679197857 Apr 04 12:39:54 PM PDT 24 Apr 04 12:39:55 PM PDT 24 36466084 ps
T1304 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2389939263 Apr 04 12:39:53 PM PDT 24 Apr 04 12:39:55 PM PDT 24 31698579 ps
T1305 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3362403621 Apr 04 12:40:31 PM PDT 24 Apr 04 12:40:32 PM PDT 24 1007978871 ps
T1306 /workspace/coverage/cover_reg_top/6.uart_csr_rw.120830444 Apr 04 12:39:52 PM PDT 24 Apr 04 12:39:52 PM PDT 24 14538715 ps
T1307 /workspace/coverage/cover_reg_top/45.uart_intr_test.131923368 Apr 04 12:40:38 PM PDT 24 Apr 04 12:40:39 PM PDT 24 24685195 ps
T1308 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2056438194 Apr 04 12:40:06 PM PDT 24 Apr 04 12:40:08 PM PDT 24 221280936 ps
T1309 /workspace/coverage/cover_reg_top/18.uart_intr_test.2628303691 Apr 04 12:40:29 PM PDT 24 Apr 04 12:40:30 PM PDT 24 52804463 ps
T1310 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.767702375 Apr 04 12:39:53 PM PDT 24 Apr 04 12:39:54 PM PDT 24 14750213 ps
T1311 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1176554318 Apr 04 12:40:28 PM PDT 24 Apr 04 12:40:29 PM PDT 24 46396141 ps
T1312 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2029630849 Apr 04 12:40:04 PM PDT 24 Apr 04 12:40:05 PM PDT 24 24008008 ps
T1313 /workspace/coverage/cover_reg_top/21.uart_intr_test.3300716826 Apr 04 12:40:33 PM PDT 24 Apr 04 12:40:34 PM PDT 24 58771099 ps
T1314 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2258993491 Apr 04 12:39:42 PM PDT 24 Apr 04 12:39:43 PM PDT 24 35086732 ps
T1315 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2396246318 Apr 04 12:40:31 PM PDT 24 Apr 04 12:40:32 PM PDT 24 252288086 ps
T1316 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3465205275 Apr 04 12:40:05 PM PDT 24 Apr 04 12:40:06 PM PDT 24 51771313 ps
T1317 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3010198050 Apr 04 12:39:53 PM PDT 24 Apr 04 12:39:54 PM PDT 24 20272071 ps
T1318 /workspace/coverage/cover_reg_top/27.uart_intr_test.4125465052 Apr 04 12:40:30 PM PDT 24 Apr 04 12:40:30 PM PDT 24 34840248 ps

Test location /workspace/coverage/default/45.uart_tx_rx.4172328462
Short name T2
Test name
Test status
Simulation time 38403594673 ps
CPU time 33.74 seconds
Started Apr 04 02:11:29 PM PDT 24
Finished Apr 04 02:12:03 PM PDT 24
Peak memory 200872 kb
Host smart-db28f75f-1030-4f54-b752-2c18a43c79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172328462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4172328462
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1319676144
Short name T32
Test name
Test status
Simulation time 256682403043 ps
CPU time 1875.29 seconds
Started Apr 04 02:07:37 PM PDT 24
Finished Apr 04 02:38:52 PM PDT 24
Peak memory 230076 kb
Host smart-7ae25a1b-5a64-4492-9e16-b1a2ebdb84d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319676144 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1319676144
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1924505801
Short name T34
Test name
Test status
Simulation time 719930206828 ps
CPU time 1551.95 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:38:34 PM PDT 24
Peak memory 233936 kb
Host smart-37def229-f061-465f-a4e7-604253355c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924505801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1924505801
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.638707326
Short name T23
Test name
Test status
Simulation time 312439780550 ps
CPU time 784.21 seconds
Started Apr 04 02:09:59 PM PDT 24
Finished Apr 04 02:23:04 PM PDT 24
Peak memory 200852 kb
Host smart-5394cf69-56ab-4bcb-a3c9-824329d7cf7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638707326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.638707326
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2870972223
Short name T108
Test name
Test status
Simulation time 341067731102 ps
CPU time 1675.41 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:36:23 PM PDT 24
Peak memory 233884 kb
Host smart-2483ed95-8e62-45df-a9b0-a673f9b8ec1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870972223 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2870972223
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2660710520
Short name T112
Test name
Test status
Simulation time 435361870334 ps
CPU time 1335.7 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:34:31 PM PDT 24
Peak memory 231316 kb
Host smart-f6072255-99fe-4098-9a1e-1271073fd6c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660710520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2660710520
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2487944042
Short name T12
Test name
Test status
Simulation time 118757267478 ps
CPU time 307.24 seconds
Started Apr 04 02:10:42 PM PDT 24
Finished Apr 04 02:15:50 PM PDT 24
Peak memory 200824 kb
Host smart-1afe5ebf-fb83-4fd7-a92d-a78c28b255ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487944042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2487944042
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_stress_all.3289825155
Short name T157
Test name
Test status
Simulation time 306360136704 ps
CPU time 653.2 seconds
Started Apr 04 02:08:28 PM PDT 24
Finished Apr 04 02:19:22 PM PDT 24
Peak memory 200836 kb
Host smart-1b031354-f98a-4f97-abfe-fe8da4980326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289825155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3289825155
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3797283581
Short name T29
Test name
Test status
Simulation time 138742158 ps
CPU time 0.76 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:05:53 PM PDT 24
Peak memory 218840 kb
Host smart-e61260b5-222b-4d49-aa40-4d785fd74dbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797283581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3797283581
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3488771549
Short name T33
Test name
Test status
Simulation time 122134121409 ps
CPU time 688.21 seconds
Started Apr 04 02:08:21 PM PDT 24
Finished Apr 04 02:19:49 PM PDT 24
Peak memory 217292 kb
Host smart-c77cb05c-2673-4fc6-888e-c86247a33afa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488771549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3488771549
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3182651548
Short name T10
Test name
Test status
Simulation time 127227300601 ps
CPU time 101.61 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:09:31 PM PDT 24
Peak memory 200832 kb
Host smart-b532462e-2177-4f69-8ee8-5105023cfe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182651548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3182651548
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1932624683
Short name T16
Test name
Test status
Simulation time 52555027188 ps
CPU time 420.57 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:20:04 PM PDT 24
Peak memory 217528 kb
Host smart-35d643b3-c479-47c1-ada0-70347494bf0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932624683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1932624683
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1166145285
Short name T111
Test name
Test status
Simulation time 198807593164 ps
CPU time 1105.35 seconds
Started Apr 04 02:10:11 PM PDT 24
Finished Apr 04 02:28:37 PM PDT 24
Peak memory 217284 kb
Host smart-8d568c62-5eb7-4873-b219-bfd46a909bd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166145285 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1166145285
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.293007104
Short name T133
Test name
Test status
Simulation time 283174629426 ps
CPU time 127.92 seconds
Started Apr 04 02:06:20 PM PDT 24
Finished Apr 04 02:08:29 PM PDT 24
Peak memory 209332 kb
Host smart-97819ee2-88ae-4dfe-b5b3-0872deab5504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293007104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.293007104
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1301971750
Short name T145
Test name
Test status
Simulation time 155127185604 ps
CPU time 247.41 seconds
Started Apr 04 02:11:38 PM PDT 24
Finished Apr 04 02:15:46 PM PDT 24
Peak memory 200852 kb
Host smart-7dbce05d-88ac-45f6-b653-367e723506ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301971750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1301971750
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1573675360
Short name T83
Test name
Test status
Simulation time 72958460 ps
CPU time 1.3 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 199324 kb
Host smart-1d171370-f431-48a2-9f1e-76897ef7a3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573675360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1573675360
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/49.uart_stress_all.2807325223
Short name T159
Test name
Test status
Simulation time 214815344119 ps
CPU time 107.82 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:14:04 PM PDT 24
Peak memory 201100 kb
Host smart-3eb5adad-91d7-4baa-bf01-61a8cc56ee21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807325223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2807325223
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_alert_test.3828505831
Short name T27
Test name
Test status
Simulation time 47474968 ps
CPU time 0.54 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:00 PM PDT 24
Peak memory 196240 kb
Host smart-b3164f8e-8fb9-4065-a9b4-d7890f589b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828505831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3828505831
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2777858679
Short name T49
Test name
Test status
Simulation time 458792859459 ps
CPU time 1254.52 seconds
Started Apr 04 02:10:41 PM PDT 24
Finished Apr 04 02:31:37 PM PDT 24
Peak memory 232212 kb
Host smart-c7a73b45-220b-4734-9b17-a42aed0cb72c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777858679 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2777858679
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.504679411
Short name T55
Test name
Test status
Simulation time 35018692 ps
CPU time 0.61 seconds
Started Apr 04 12:39:38 PM PDT 24
Finished Apr 04 12:39:39 PM PDT 24
Peak memory 195428 kb
Host smart-72f1b540-aaec-4747-a850-90b39473b4d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504679411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.504679411
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.4189892058
Short name T259
Test name
Test status
Simulation time 120954850070 ps
CPU time 367.47 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:20:02 PM PDT 24
Peak memory 200704 kb
Host smart-5af0a21e-caf5-4473-912c-98c7f53247bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189892058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4189892058
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2208196728
Short name T126
Test name
Test status
Simulation time 77543137498 ps
CPU time 54.34 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:16:07 PM PDT 24
Peak memory 200780 kb
Host smart-9fa35636-a26b-4b8e-ac6e-99be9834ff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208196728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2208196728
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.710378092
Short name T228
Test name
Test status
Simulation time 169241889693 ps
CPU time 1016.31 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:25:35 PM PDT 24
Peak memory 217352 kb
Host smart-c6ccbd02-0097-4c3f-a97e-d600b3a2d8ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710378092 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.710378092
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1672069495
Short name T104
Test name
Test status
Simulation time 231997172891 ps
CPU time 110.73 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:14:18 PM PDT 24
Peak memory 200776 kb
Host smart-1977758e-c98b-4f70-b3df-79d70a070142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672069495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1672069495
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.841031036
Short name T61
Test name
Test status
Simulation time 14567322 ps
CPU time 0.63 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 195388 kb
Host smart-368edb08-713c-41c4-9ac5-1fd5d5353614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841031036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.841031036
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3834829811
Short name T272
Test name
Test status
Simulation time 92214377525 ps
CPU time 1307.37 seconds
Started Apr 04 02:11:05 PM PDT 24
Finished Apr 04 02:32:53 PM PDT 24
Peak memory 217236 kb
Host smart-2cdb155a-3d52-41ed-9a26-3b66f8994f3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834829811 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3834829811
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3765572038
Short name T185
Test name
Test status
Simulation time 78680737250 ps
CPU time 126.18 seconds
Started Apr 04 02:14:45 PM PDT 24
Finished Apr 04 02:16:51 PM PDT 24
Peak memory 200792 kb
Host smart-af49b4b2-c93a-439e-b305-2753c4efcb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765572038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3765572038
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.1463199066
Short name T143
Test name
Test status
Simulation time 256342905889 ps
CPU time 124.28 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:10:54 PM PDT 24
Peak memory 217364 kb
Host smart-d7fbd1d0-7221-4bcf-a05d-49ae5698da05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463199066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1463199066
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2159454925
Short name T167
Test name
Test status
Simulation time 25999812938 ps
CPU time 15.23 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:14:24 PM PDT 24
Peak memory 200816 kb
Host smart-c227112b-24bf-4208-a9f7-ec7e425510aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159454925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2159454925
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3462759534
Short name T134
Test name
Test status
Simulation time 350556409288 ps
CPU time 416.84 seconds
Started Apr 04 02:12:30 PM PDT 24
Finished Apr 04 02:19:28 PM PDT 24
Peak memory 217300 kb
Host smart-0b293082-6a1f-4a97-9181-b390fb271bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462759534 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3462759534
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.3928888532
Short name T130
Test name
Test status
Simulation time 328360950448 ps
CPU time 265.66 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:12:22 PM PDT 24
Peak memory 200788 kb
Host smart-df7ca02e-1657-4081-8c8c-cef15dc87fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928888532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3928888532
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3660145705
Short name T88
Test name
Test status
Simulation time 137924028 ps
CPU time 1.36 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 199392 kb
Host smart-20fa3fd1-4d29-4376-aefb-0e2f3802e902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660145705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3660145705
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1216217760
Short name T240
Test name
Test status
Simulation time 103097539691 ps
CPU time 214.56 seconds
Started Apr 04 02:13:15 PM PDT 24
Finished Apr 04 02:16:50 PM PDT 24
Peak memory 200924 kb
Host smart-bc1610ff-693b-488d-8d83-b926caac25da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216217760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1216217760
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1862478249
Short name T127
Test name
Test status
Simulation time 18371675430 ps
CPU time 22.21 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:13:26 PM PDT 24
Peak memory 200880 kb
Host smart-07f3cfcc-ce1d-4831-9af4-f455224aae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862478249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1862478249
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_noise_filter.741177705
Short name T301
Test name
Test status
Simulation time 281036445352 ps
CPU time 181.22 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:12:07 PM PDT 24
Peak memory 200368 kb
Host smart-b18187b9-630a-4b78-9bf3-698d2cb6b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741177705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.741177705
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3017503500
Short name T306
Test name
Test status
Simulation time 123898994985 ps
CPU time 687.77 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:18:39 PM PDT 24
Peak memory 225180 kb
Host smart-9c844205-8d89-46ce-95e5-490ec091749b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017503500 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3017503500
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.639248539
Short name T184
Test name
Test status
Simulation time 73717170153 ps
CPU time 19.07 seconds
Started Apr 04 02:14:09 PM PDT 24
Finished Apr 04 02:14:28 PM PDT 24
Peak memory 200812 kb
Host smart-b69bfeef-25c4-4f44-9010-bcec27c6c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639248539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.639248539
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1162645916
Short name T140
Test name
Test status
Simulation time 144132676192 ps
CPU time 259.19 seconds
Started Apr 04 02:14:43 PM PDT 24
Finished Apr 04 02:19:02 PM PDT 24
Peak memory 200896 kb
Host smart-826eb474-504a-4c8b-b6ab-9de6b97a976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162645916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1162645916
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2313794152
Short name T170
Test name
Test status
Simulation time 194754518376 ps
CPU time 74.95 seconds
Started Apr 04 02:14:56 PM PDT 24
Finished Apr 04 02:16:11 PM PDT 24
Peak memory 200908 kb
Host smart-a4b3d1a6-c69e-439a-bc11-923283f04dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313794152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2313794152
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.564377411
Short name T120
Test name
Test status
Simulation time 71429738158 ps
CPU time 52.7 seconds
Started Apr 04 02:15:25 PM PDT 24
Finished Apr 04 02:16:18 PM PDT 24
Peak memory 200828 kb
Host smart-b889d16d-206f-4561-a67f-69ea8bf398e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564377411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.564377411
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2565488870
Short name T123
Test name
Test status
Simulation time 38506438646 ps
CPU time 15.62 seconds
Started Apr 04 02:15:27 PM PDT 24
Finished Apr 04 02:15:42 PM PDT 24
Peak memory 200860 kb
Host smart-43d99f70-f24d-407c-aa37-dda5bd94b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565488870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2565488870
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1700006889
Short name T216
Test name
Test status
Simulation time 24841132751 ps
CPU time 24.71 seconds
Started Apr 04 02:06:58 PM PDT 24
Finished Apr 04 02:07:23 PM PDT 24
Peak memory 200876 kb
Host smart-30af922c-157d-4923-8a9d-746b0d1e86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700006889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1700006889
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1859436613
Short name T172
Test name
Test status
Simulation time 130051970301 ps
CPU time 183.7 seconds
Started Apr 04 02:13:29 PM PDT 24
Finished Apr 04 02:16:33 PM PDT 24
Peak memory 200908 kb
Host smart-15c89664-bba0-480b-8712-006d4b8016d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859436613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1859436613
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3043772680
Short name T281
Test name
Test status
Simulation time 95636961976 ps
CPU time 70.37 seconds
Started Apr 04 02:07:33 PM PDT 24
Finished Apr 04 02:08:45 PM PDT 24
Peak memory 200368 kb
Host smart-ed8fdf76-67ac-4b52-a7e8-cb73ec5e0f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043772680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3043772680
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2622633221
Short name T247
Test name
Test status
Simulation time 235317250980 ps
CPU time 35.58 seconds
Started Apr 04 02:06:37 PM PDT 24
Finished Apr 04 02:07:12 PM PDT 24
Peak memory 200820 kb
Host smart-1f91e218-54c4-40ce-9d05-63805c30d3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622633221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2622633221
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_noise_filter.608440771
Short name T268
Test name
Test status
Simulation time 23147717106 ps
CPU time 40.92 seconds
Started Apr 04 02:06:00 PM PDT 24
Finished Apr 04 02:06:41 PM PDT 24
Peak memory 200380 kb
Host smart-39aca886-71cd-4bd0-b082-0dbaaad5bcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608440771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.608440771
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1669081465
Short name T883
Test name
Test status
Simulation time 30134359617 ps
CPU time 13.29 seconds
Started Apr 04 02:13:08 PM PDT 24
Finished Apr 04 02:13:21 PM PDT 24
Peak memory 200900 kb
Host smart-9dc51703-4214-4fda-8cec-dc5016c2a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669081465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1669081465
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1454011505
Short name T263
Test name
Test status
Simulation time 151812445534 ps
CPU time 264.44 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:11:25 PM PDT 24
Peak memory 200780 kb
Host smart-214f130f-9794-4699-b05b-552c7071bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454011505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1454011505
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1023703766
Short name T580
Test name
Test status
Simulation time 14091239609 ps
CPU time 14.39 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:07 PM PDT 24
Peak memory 200768 kb
Host smart-4a4d8962-a7fd-4f96-8be7-e9109f5b2bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023703766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1023703766
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4156096428
Short name T164
Test name
Test status
Simulation time 28522488766 ps
CPU time 22.43 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:14:29 PM PDT 24
Peak memory 200796 kb
Host smart-461c72de-dfd8-405d-8617-44c68b28a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156096428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4156096428
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.1277911438
Short name T1039
Test name
Test status
Simulation time 352330285840 ps
CPU time 228.43 seconds
Started Apr 04 02:08:05 PM PDT 24
Finished Apr 04 02:11:53 PM PDT 24
Peak memory 200780 kb
Host smart-d292974e-d82b-480f-9b1c-2c345cc1222b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277911438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1277911438
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2260374783
Short name T208
Test name
Test status
Simulation time 88134771228 ps
CPU time 34.82 seconds
Started Apr 04 02:14:33 PM PDT 24
Finished Apr 04 02:15:08 PM PDT 24
Peak memory 200912 kb
Host smart-896a9fca-a5c1-40c0-b131-ce19d118a01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260374783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2260374783
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2763906772
Short name T176
Test name
Test status
Simulation time 49908175007 ps
CPU time 27.93 seconds
Started Apr 04 02:14:58 PM PDT 24
Finished Apr 04 02:15:26 PM PDT 24
Peak memory 200884 kb
Host smart-7a9ffabb-0af8-456f-8735-fe6668a4fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763906772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2763906772
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2774329782
Short name T202
Test name
Test status
Simulation time 152879724458 ps
CPU time 65.46 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:16:16 PM PDT 24
Peak memory 200876 kb
Host smart-e302e650-484b-45b9-93ed-e5b5f9a109b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774329782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2774329782
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1514881941
Short name T151
Test name
Test status
Simulation time 26322943405 ps
CPU time 44.5 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:15:56 PM PDT 24
Peak memory 200836 kb
Host smart-d2245567-e66c-4204-9f60-41bca1c7561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514881941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1514881941
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.3618518920
Short name T198
Test name
Test status
Simulation time 299255743421 ps
CPU time 300.08 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:16:42 PM PDT 24
Peak memory 200892 kb
Host smart-cb40e8bf-c7c2-431b-87d1-2bda93f83095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618518920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3618518920
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2258162273
Short name T113
Test name
Test status
Simulation time 144582808 ps
CPU time 1.37 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 199256 kb
Host smart-d05b9095-21c1-4dd6-a81d-45adb937e3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258162273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2258162273
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_stress_all.3428010046
Short name T246
Test name
Test status
Simulation time 186442980876 ps
CPU time 78.91 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:08:19 PM PDT 24
Peak memory 200832 kb
Host smart-a5a08922-a853-41e2-a66d-83d9bb5117a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428010046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3428010046
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.893944782
Short name T218
Test name
Test status
Simulation time 44596174590 ps
CPU time 31.21 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:13:48 PM PDT 24
Peak memory 200848 kb
Host smart-64b2d85b-53c8-4bb3-b456-8e6ee09bb7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893944782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.893944782
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.429619077
Short name T234
Test name
Test status
Simulation time 30201660628 ps
CPU time 5.33 seconds
Started Apr 04 02:13:21 PM PDT 24
Finished Apr 04 02:13:26 PM PDT 24
Peak memory 200888 kb
Host smart-8de0b0fe-c5a0-44c3-9a0e-0d40176d4171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429619077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.429619077
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4154931122
Short name T192
Test name
Test status
Simulation time 75680669137 ps
CPU time 65.07 seconds
Started Apr 04 02:13:28 PM PDT 24
Finished Apr 04 02:14:34 PM PDT 24
Peak memory 200800 kb
Host smart-ae7256c1-632d-41bb-9ea9-ba246b0946b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154931122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4154931122
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2694680616
Short name T242
Test name
Test status
Simulation time 7428057364 ps
CPU time 13.42 seconds
Started Apr 04 02:13:43 PM PDT 24
Finished Apr 04 02:13:56 PM PDT 24
Peak memory 200676 kb
Host smart-611a6e37-3a52-4423-b552-b7626880dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694680616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2694680616
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3170836180
Short name T226
Test name
Test status
Simulation time 107263665455 ps
CPU time 48.37 seconds
Started Apr 04 02:13:43 PM PDT 24
Finished Apr 04 02:14:31 PM PDT 24
Peak memory 200908 kb
Host smart-54586201-5de0-4875-b899-f1f9995e05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170836180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3170836180
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.299984911
Short name T222
Test name
Test status
Simulation time 106342006888 ps
CPU time 80.94 seconds
Started Apr 04 02:13:41 PM PDT 24
Finished Apr 04 02:15:03 PM PDT 24
Peak memory 200776 kb
Host smart-d77ca90e-ef61-4738-a9c6-d8086e1b7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299984911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.299984911
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.130418528
Short name T149
Test name
Test status
Simulation time 149296051562 ps
CPU time 56.18 seconds
Started Apr 04 02:07:23 PM PDT 24
Finished Apr 04 02:08:20 PM PDT 24
Peak memory 200784 kb
Host smart-3962fce6-3b9c-45ec-a8e5-913ff190b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130418528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.130418528
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1020747212
Short name T211
Test name
Test status
Simulation time 33046337397 ps
CPU time 66.28 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:15:00 PM PDT 24
Peak memory 200900 kb
Host smart-03e7d896-5142-44b9-aa7b-4772ae153e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020747212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1020747212
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1938293653
Short name T215
Test name
Test status
Simulation time 150750248833 ps
CPU time 154.97 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:16:41 PM PDT 24
Peak memory 200800 kb
Host smart-53b09d81-dcb1-4322-9de5-3a7927fb12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938293653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1938293653
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.445681812
Short name T238
Test name
Test status
Simulation time 94619350324 ps
CPU time 80.76 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:15:28 PM PDT 24
Peak memory 200800 kb
Host smart-5d367438-e08c-4cfa-8bba-f120f52c9e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445681812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.445681812
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2030290033
Short name T235
Test name
Test status
Simulation time 32953485823 ps
CPU time 16 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:15:11 PM PDT 24
Peak memory 200848 kb
Host smart-7bdf9657-199e-432c-8bb2-7a679eb5743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030290033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2030290033
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.828632692
Short name T509
Test name
Test status
Simulation time 63114987180 ps
CPU time 254.87 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:13:34 PM PDT 24
Peak memory 216364 kb
Host smart-e651c9a4-3fb8-4149-9c26-99f133994f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828632692 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.828632692
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1327823040
Short name T230
Test name
Test status
Simulation time 114336063652 ps
CPU time 428.93 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:17:46 PM PDT 24
Peak memory 200740 kb
Host smart-53a1cfd9-b6c0-44b7-8654-1d9b5b541145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327823040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1327823040
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4032382642
Short name T239
Test name
Test status
Simulation time 148484327104 ps
CPU time 133.05 seconds
Started Apr 04 02:12:29 PM PDT 24
Finished Apr 04 02:14:43 PM PDT 24
Peak memory 200676 kb
Host smart-aa43d374-9019-4fa8-a9e0-f7168e570be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032382642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4032382642
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4087066715
Short name T207
Test name
Test status
Simulation time 64066236377 ps
CPU time 53.19 seconds
Started Apr 04 02:12:55 PM PDT 24
Finished Apr 04 02:13:48 PM PDT 24
Peak memory 200820 kb
Host smart-e49bffa6-6137-43ec-ad4b-30835d61a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087066715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4087066715
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1672276657
Short name T1251
Test name
Test status
Simulation time 39825347 ps
CPU time 0.66 seconds
Started Apr 04 12:39:36 PM PDT 24
Finished Apr 04 12:39:37 PM PDT 24
Peak memory 195456 kb
Host smart-e33944a1-ce1b-46b9-9ee4-9446fe08de29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672276657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1672276657
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4185042260
Short name T1249
Test name
Test status
Simulation time 139408053 ps
CPU time 1.56 seconds
Started Apr 04 12:39:34 PM PDT 24
Finished Apr 04 12:39:36 PM PDT 24
Peak memory 197760 kb
Host smart-edd07acc-de66-4ab8-8f5b-2fed62660901
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185042260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4185042260
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2543211765
Short name T57
Test name
Test status
Simulation time 17833451 ps
CPU time 0.62 seconds
Started Apr 04 12:39:38 PM PDT 24
Finished Apr 04 12:39:39 PM PDT 24
Peak memory 195320 kb
Host smart-491f9be7-eb20-4ddb-8ce7-ccba8db8630a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543211765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2543211765
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.519433628
Short name T1291
Test name
Test status
Simulation time 44784550 ps
CPU time 0.77 seconds
Started Apr 04 12:39:37 PM PDT 24
Finished Apr 04 12:39:39 PM PDT 24
Peak memory 199032 kb
Host smart-352050df-3b2f-45a8-aa89-0c723b7a989b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519433628 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.519433628
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.237738679
Short name T1246
Test name
Test status
Simulation time 81420335 ps
CPU time 0.55 seconds
Started Apr 04 12:39:35 PM PDT 24
Finished Apr 04 12:39:36 PM PDT 24
Peak memory 194364 kb
Host smart-f068f9ad-61c9-4891-99b0-99ec510b12a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237738679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.237738679
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1344403209
Short name T1293
Test name
Test status
Simulation time 27480225 ps
CPU time 0.73 seconds
Started Apr 04 12:39:39 PM PDT 24
Finished Apr 04 12:39:40 PM PDT 24
Peak memory 196792 kb
Host smart-79cb9c97-f33f-4674-b19e-6d879feb4fc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344403209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1344403209
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2206053510
Short name T1228
Test name
Test status
Simulation time 119864866 ps
CPU time 0.96 seconds
Started Apr 04 12:39:34 PM PDT 24
Finished Apr 04 12:39:35 PM PDT 24
Peak memory 199568 kb
Host smart-342868c4-9eb0-4c09-8ea6-a7392cda7c37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206053510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2206053510
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1924130683
Short name T1284
Test name
Test status
Simulation time 208961109 ps
CPU time 0.96 seconds
Started Apr 04 12:39:36 PM PDT 24
Finished Apr 04 12:39:38 PM PDT 24
Peak memory 198636 kb
Host smart-2c76ca8e-fda2-4619-8c19-7d5c77033aab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924130683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1924130683
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.4030355393
Short name T56
Test name
Test status
Simulation time 29347883 ps
CPU time 0.73 seconds
Started Apr 04 12:40:57 PM PDT 24
Finished Apr 04 12:40:58 PM PDT 24
Peak memory 196332 kb
Host smart-4b90212a-1b5f-43b8-b9ed-fdeffe6079aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030355393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.4030355393
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2258993491
Short name T1314
Test name
Test status
Simulation time 35086732 ps
CPU time 1.36 seconds
Started Apr 04 12:39:42 PM PDT 24
Finished Apr 04 12:39:43 PM PDT 24
Peak memory 197832 kb
Host smart-8404c877-ab1b-488d-a4ac-31dc165a4fb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258993491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2258993491
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3577895957
Short name T1271
Test name
Test status
Simulation time 114015412 ps
CPU time 0.57 seconds
Started Apr 04 12:40:57 PM PDT 24
Finished Apr 04 12:40:58 PM PDT 24
Peak memory 194912 kb
Host smart-81ec1375-7786-4b6d-ba81-68a49e0bcde4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577895957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3577895957
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.649043980
Short name T1265
Test name
Test status
Simulation time 26528765 ps
CPU time 1.3 seconds
Started Apr 04 12:39:44 PM PDT 24
Finished Apr 04 12:39:45 PM PDT 24
Peak memory 200092 kb
Host smart-1b2cf28e-36b6-4e4f-a336-a9dfcd3241b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649043980 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.649043980
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1842985995
Short name T75
Test name
Test status
Simulation time 12199663 ps
CPU time 0.57 seconds
Started Apr 04 12:39:42 PM PDT 24
Finished Apr 04 12:39:43 PM PDT 24
Peak memory 195236 kb
Host smart-4ad32413-1b82-421d-93b3-8b642a4734a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842985995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1842985995
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.105398802
Short name T1201
Test name
Test status
Simulation time 13128952 ps
CPU time 0.59 seconds
Started Apr 04 12:39:43 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 194296 kb
Host smart-e3a13ca2-bd3e-4c37-b346-924c378ef71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105398802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.105398802
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3108053776
Short name T1229
Test name
Test status
Simulation time 53830700 ps
CPU time 0.66 seconds
Started Apr 04 12:39:46 PM PDT 24
Finished Apr 04 12:39:46 PM PDT 24
Peak memory 195788 kb
Host smart-03f390a9-a22f-4f62-a004-6e17c2e55d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108053776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3108053776
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3392740462
Short name T1200
Test name
Test status
Simulation time 75833144 ps
CPU time 1.28 seconds
Started Apr 04 12:39:36 PM PDT 24
Finished Apr 04 12:39:37 PM PDT 24
Peak memory 199992 kb
Host smart-ae03e81b-8f39-407c-ba10-72f08755b59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392740462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3392740462
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2746933194
Short name T84
Test name
Test status
Simulation time 346901387 ps
CPU time 0.93 seconds
Started Apr 04 12:39:37 PM PDT 24
Finished Apr 04 12:39:39 PM PDT 24
Peak memory 198904 kb
Host smart-1777855b-a047-4860-8fba-8739b6e19727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746933194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2746933194
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2797354796
Short name T1239
Test name
Test status
Simulation time 123124256 ps
CPU time 0.9 seconds
Started Apr 04 12:40:07 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 199840 kb
Host smart-70ea283f-c1f4-49ba-9da2-7cd321845453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797354796 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2797354796
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1830128683
Short name T1188
Test name
Test status
Simulation time 63816183 ps
CPU time 0.59 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 195700 kb
Host smart-7a6d6d04-56e3-4532-9922-bd2453aa1246
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830128683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1830128683
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2561680108
Short name T1230
Test name
Test status
Simulation time 12957075 ps
CPU time 0.58 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:05 PM PDT 24
Peak memory 194256 kb
Host smart-e22bd85f-b8d5-4b67-b830-193fdc928752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561680108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2561680108
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3380330156
Short name T76
Test name
Test status
Simulation time 53001719 ps
CPU time 0.73 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 196964 kb
Host smart-cbc86814-b445-4a53-a7eb-b5f677127d4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380330156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3380330156
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1916641367
Short name T1259
Test name
Test status
Simulation time 58350833 ps
CPU time 1.39 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 200060 kb
Host smart-ad401527-ee7b-4226-ad9a-5a1e79fae7a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916641367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1916641367
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3526110321
Short name T86
Test name
Test status
Simulation time 53878837 ps
CPU time 0.97 seconds
Started Apr 04 12:40:08 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 198984 kb
Host smart-a0d85f6e-e6f1-4470-8f44-6619ad66e8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526110321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3526110321
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1113794691
Short name T1255
Test name
Test status
Simulation time 25679663 ps
CPU time 0.76 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 198416 kb
Host smart-f8f4ff0b-7bb5-42a8-9181-211d2d884b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113794691 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1113794691
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3675538880
Short name T1286
Test name
Test status
Simulation time 34310579 ps
CPU time 0.58 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 194304 kb
Host smart-d6bc5033-ed81-4a7d-9e96-a2e487641a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675538880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3675538880
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2928395403
Short name T79
Test name
Test status
Simulation time 156163227 ps
CPU time 0.72 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 196540 kb
Host smart-d1915635-7c9a-4c70-b36b-d04bffb107fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928395403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2928395403
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2056438194
Short name T1308
Test name
Test status
Simulation time 221280936 ps
CPU time 1.37 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 200060 kb
Host smart-7124d009-2bab-41ee-9a26-99fa159e1fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056438194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2056438194
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2165199114
Short name T1287
Test name
Test status
Simulation time 242193145 ps
CPU time 1.31 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 199436 kb
Host smart-bbefc807-cb6b-48c2-924b-24d6202e20de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165199114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2165199114
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.56849706
Short name T1216
Test name
Test status
Simulation time 34235568 ps
CPU time 0.92 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 199752 kb
Host smart-0c3d7268-147b-4fae-9814-df782d9c4a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56849706 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.56849706
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.747327633
Short name T1280
Test name
Test status
Simulation time 84187992 ps
CPU time 0.57 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 195300 kb
Host smart-6b82ad75-2ba6-4fe9-8d42-88db3cd9052e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747327633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.747327633
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2319003422
Short name T1189
Test name
Test status
Simulation time 137729702 ps
CPU time 0.56 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 194224 kb
Host smart-3f16dc4b-66a9-44f0-ac7f-58f9c527fc54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319003422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2319003422
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2668750434
Short name T1260
Test name
Test status
Simulation time 37751059 ps
CPU time 0.75 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 196960 kb
Host smart-830767d4-5852-4fca-919e-0341ffaea740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668750434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2668750434
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1231705034
Short name T1190
Test name
Test status
Simulation time 203968281 ps
CPU time 2.11 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:22 PM PDT 24
Peak memory 200128 kb
Host smart-14613d67-14f0-421f-9069-2752ee936ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231705034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1231705034
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.688095842
Short name T1218
Test name
Test status
Simulation time 39918959 ps
CPU time 0.69 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 198580 kb
Host smart-8e0bedc5-8a5f-4f0b-9822-1f472600c062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688095842 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.688095842
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.380083098
Short name T1220
Test name
Test status
Simulation time 70272270 ps
CPU time 0.61 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 195428 kb
Host smart-61668cd4-f98f-4770-82d6-9f3107b3a971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380083098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.380083098
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.813344495
Short name T1194
Test name
Test status
Simulation time 43776041 ps
CPU time 0.58 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 194332 kb
Host smart-3deafc19-8284-482c-b0c3-ad560d029279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813344495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.813344495
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3626561104
Short name T1222
Test name
Test status
Simulation time 39036769 ps
CPU time 0.68 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 196872 kb
Host smart-b19307c3-9538-4da3-9a1b-dda4bdb138cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626561104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3626561104
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.887797193
Short name T1294
Test name
Test status
Simulation time 96464021 ps
CPU time 2.17 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 200080 kb
Host smart-c1a5f400-3ae2-4940-8f09-0dc55f9ba0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887797193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.887797193
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4140549214
Short name T87
Test name
Test status
Simulation time 90197727 ps
CPU time 1.25 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 199124 kb
Host smart-d00e1081-b607-4c13-abbf-4d3a679b6643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140549214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4140549214
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2985753549
Short name T1267
Test name
Test status
Simulation time 17986158 ps
CPU time 0.68 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 197768 kb
Host smart-2f85dcac-6a0a-4b0e-a329-6be1c3dceee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985753549 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2985753549
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3530168252
Short name T1223
Test name
Test status
Simulation time 16972661 ps
CPU time 0.63 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 195492 kb
Host smart-45fffdea-f7c6-4faf-b8b2-0dffa0f711a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530168252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3530168252
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.726041453
Short name T1245
Test name
Test status
Simulation time 16916543 ps
CPU time 0.56 seconds
Started Apr 04 12:40:16 PM PDT 24
Finished Apr 04 12:40:17 PM PDT 24
Peak memory 194152 kb
Host smart-5ef79619-0e96-45bc-8a85-672eecb757f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726041453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.726041453
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.304449239
Short name T1242
Test name
Test status
Simulation time 15692200 ps
CPU time 0.71 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 196836 kb
Host smart-4cd9b1e7-fc57-4ca0-b57d-e39c1b7efa78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304449239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.304449239
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2092092259
Short name T1274
Test name
Test status
Simulation time 23792591 ps
CPU time 1.23 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 200036 kb
Host smart-0ee6ab2d-3758-465a-af15-e1579fcd7ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092092259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2092092259
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.905176005
Short name T85
Test name
Test status
Simulation time 88301823 ps
CPU time 1.3 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 199392 kb
Host smart-f5f0ae69-53d9-43ce-a0c6-d7dc985ca1dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905176005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.905176005
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4050239330
Short name T1248
Test name
Test status
Simulation time 179153843 ps
CPU time 0.88 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 199712 kb
Host smart-45b49241-94d0-4fa3-b602-8718280472a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050239330 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4050239330
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2888484017
Short name T71
Test name
Test status
Simulation time 39130992 ps
CPU time 0.6 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 195420 kb
Host smart-f846948f-2e9a-4b81-b2de-d1654c603bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888484017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2888484017
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3531120150
Short name T1234
Test name
Test status
Simulation time 49762318 ps
CPU time 0.57 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 194312 kb
Host smart-f4241ae8-3613-4ba0-84d4-ac34fc824b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531120150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3531120150
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3009206440
Short name T1233
Test name
Test status
Simulation time 19892481 ps
CPU time 0.65 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 195820 kb
Host smart-b22af2b9-df6f-4dce-97db-a4a155ccc242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009206440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3009206440
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1951549437
Short name T1289
Test name
Test status
Simulation time 46379280 ps
CPU time 1.05 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 199748 kb
Host smart-bcbacf5e-d5a6-4b1f-906d-85d6d8086b62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951549437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1951549437
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4148217420
Short name T80
Test name
Test status
Simulation time 146004999 ps
CPU time 1.04 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 198872 kb
Host smart-d12b531f-0125-4f55-8079-8c3512ba4de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148217420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4148217420
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4097364666
Short name T1196
Test name
Test status
Simulation time 24429655 ps
CPU time 0.8 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 199784 kb
Host smart-44f00d5a-522b-46fd-a931-8e68dc482619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097364666 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4097364666
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.779870635
Short name T60
Test name
Test status
Simulation time 15300837 ps
CPU time 0.62 seconds
Started Apr 04 12:40:17 PM PDT 24
Finished Apr 04 12:40:18 PM PDT 24
Peak memory 195576 kb
Host smart-deb9af1f-5d8d-457d-b4a1-5be46b9b1c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779870635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.779870635
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3998288647
Short name T1266
Test name
Test status
Simulation time 25475484 ps
CPU time 0.59 seconds
Started Apr 04 12:40:21 PM PDT 24
Finished Apr 04 12:40:21 PM PDT 24
Peak memory 194372 kb
Host smart-5b94f8dc-2851-49d4-9550-2331b14b0c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998288647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3998288647
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.849258260
Short name T1296
Test name
Test status
Simulation time 22210849 ps
CPU time 0.66 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 196480 kb
Host smart-1ff8829d-8cf4-4796-9b60-cef829e0b3bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849258260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.849258260
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.510546789
Short name T1181
Test name
Test status
Simulation time 152824172 ps
CPU time 1.44 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 200068 kb
Host smart-bcbbe0b7-68f9-4c90-be86-98c58148b214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510546789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.510546789
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3432512360
Short name T82
Test name
Test status
Simulation time 515524762 ps
CPU time 0.9 seconds
Started Apr 04 12:40:19 PM PDT 24
Finished Apr 04 12:40:20 PM PDT 24
Peak memory 198592 kb
Host smart-4d6655d2-9de5-46d7-bdb1-95ecf5f7479b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432512360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3432512360
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.663999209
Short name T1256
Test name
Test status
Simulation time 52159829 ps
CPU time 0.66 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 197572 kb
Host smart-fd50c1e5-5a41-4eea-a88a-ef8b7183c170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663999209 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.663999209
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2728857616
Short name T1276
Test name
Test status
Simulation time 33951467 ps
CPU time 0.57 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 195404 kb
Host smart-97f2e91b-d176-44c8-9689-66b21f88501a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728857616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2728857616
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1071521706
Short name T1244
Test name
Test status
Simulation time 12712673 ps
CPU time 0.6 seconds
Started Apr 04 12:40:18 PM PDT 24
Finished Apr 04 12:40:19 PM PDT 24
Peak memory 194316 kb
Host smart-d3e6bc00-4861-42d4-bf36-b047c785c66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071521706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1071521706
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4063132639
Short name T74
Test name
Test status
Simulation time 26946464 ps
CPU time 0.75 seconds
Started Apr 04 12:40:32 PM PDT 24
Finished Apr 04 12:40:33 PM PDT 24
Peak memory 197816 kb
Host smart-0db26049-3f69-422c-aa13-65e47a99ceab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063132639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4063132639
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1011027822
Short name T1283
Test name
Test status
Simulation time 379593386 ps
CPU time 1.66 seconds
Started Apr 04 12:40:22 PM PDT 24
Finished Apr 04 12:40:23 PM PDT 24
Peak memory 200064 kb
Host smart-0c276aa9-947a-4734-905d-cbfac6cf716a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011027822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1011027822
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1190785936
Short name T1277
Test name
Test status
Simulation time 58025987 ps
CPU time 0.79 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 199708 kb
Host smart-af16146d-7e66-41e8-8046-6634dc7a49eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190785936 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1190785936
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3838473259
Short name T58
Test name
Test status
Simulation time 79468164 ps
CPU time 0.62 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 195380 kb
Host smart-fa59d26d-faf1-4468-ba8d-a1afebc69b2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838473259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3838473259
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2628303691
Short name T1309
Test name
Test status
Simulation time 52804463 ps
CPU time 0.59 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194432 kb
Host smart-af65a792-c117-496d-9aa1-24ed4d375886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628303691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2628303691
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3582611763
Short name T77
Test name
Test status
Simulation time 28373915 ps
CPU time 0.7 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 195948 kb
Host smart-31762939-4ee9-4e54-bce2-6ab8b0bb0496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582611763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3582611763
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4071170500
Short name T1279
Test name
Test status
Simulation time 329691050 ps
CPU time 1.91 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 200072 kb
Host smart-0177ddef-2490-4e46-bcae-68566adbdb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071170500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4071170500
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3362403621
Short name T1305
Test name
Test status
Simulation time 1007978871 ps
CPU time 1.39 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:32 PM PDT 24
Peak memory 199376 kb
Host smart-1069665e-770f-4ef8-a59f-47dbe2024869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362403621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3362403621
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3973014972
Short name T1193
Test name
Test status
Simulation time 22615563 ps
CPU time 0.73 seconds
Started Apr 04 12:40:34 PM PDT 24
Finished Apr 04 12:40:35 PM PDT 24
Peak memory 198248 kb
Host smart-28be04ff-73b1-4116-bf20-6a557786b2f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973014972 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3973014972
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1176554318
Short name T1311
Test name
Test status
Simulation time 46396141 ps
CPU time 0.62 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 195496 kb
Host smart-f1cf7b33-9fb5-4074-83f0-14c12063f566
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176554318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1176554318
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2940981238
Short name T1254
Test name
Test status
Simulation time 13735122 ps
CPU time 0.61 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194284 kb
Host smart-37ad17bd-957b-4eb8-9fbf-a2a41d1497ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940981238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2940981238
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4097406744
Short name T1236
Test name
Test status
Simulation time 20622356 ps
CPU time 0.64 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194668 kb
Host smart-4ce4ed17-3d1d-4be2-a6fe-16a1d561ad83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097406744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4097406744
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.641562478
Short name T1182
Test name
Test status
Simulation time 112119845 ps
CPU time 2.3 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:32 PM PDT 24
Peak memory 200000 kb
Host smart-7c6c9b26-b445-427c-a323-6ba6087a2950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641562478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.641562478
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2396246318
Short name T1315
Test name
Test status
Simulation time 252288086 ps
CPU time 1.42 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:32 PM PDT 24
Peak memory 199328 kb
Host smart-f8e95786-81fc-46c4-ab70-9c29ea9cdd19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396246318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2396246318
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.487811482
Short name T1204
Test name
Test status
Simulation time 75055225 ps
CPU time 0.65 seconds
Started Apr 04 12:39:46 PM PDT 24
Finished Apr 04 12:39:47 PM PDT 24
Peak memory 195352 kb
Host smart-981693c9-46e2-4fa5-a1fb-ece6c0d97cdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487811482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.487811482
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2333352285
Short name T1270
Test name
Test status
Simulation time 527462255 ps
CPU time 2.51 seconds
Started Apr 04 12:39:44 PM PDT 24
Finished Apr 04 12:39:46 PM PDT 24
Peak memory 197916 kb
Host smart-d16be463-e77b-4178-8e3d-9001cf996874
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333352285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2333352285
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.153748033
Short name T1252
Test name
Test status
Simulation time 14249803 ps
CPU time 0.58 seconds
Started Apr 04 12:39:42 PM PDT 24
Finished Apr 04 12:39:43 PM PDT 24
Peak memory 195276 kb
Host smart-bdc66014-2abd-45d2-a62d-b4cb1476f8a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153748033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.153748033
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1302193017
Short name T1199
Test name
Test status
Simulation time 33263632 ps
CPU time 1.43 seconds
Started Apr 04 12:39:45 PM PDT 24
Finished Apr 04 12:39:46 PM PDT 24
Peak memory 200084 kb
Host smart-738bb6d7-0615-4d15-8813-efef5bf48645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302193017 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1302193017
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.219351075
Short name T1240
Test name
Test status
Simulation time 38369476 ps
CPU time 0.56 seconds
Started Apr 04 12:39:46 PM PDT 24
Finished Apr 04 12:39:46 PM PDT 24
Peak memory 195268 kb
Host smart-cc3af428-88f3-4405-a3fc-af2d4287dac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219351075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.219351075
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3154505234
Short name T1278
Test name
Test status
Simulation time 11863748 ps
CPU time 0.54 seconds
Started Apr 04 12:39:44 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 194332 kb
Host smart-24d90d3c-5c23-4fa3-b898-a620baf0eb28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154505234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3154505234
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.102895187
Short name T73
Test name
Test status
Simulation time 75109746 ps
CPU time 0.75 seconds
Started Apr 04 12:40:56 PM PDT 24
Finished Apr 04 12:40:58 PM PDT 24
Peak memory 195156 kb
Host smart-766fb6dd-15c2-4167-bd6c-a93983bcc9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102895187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.102895187
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1221571414
Short name T1205
Test name
Test status
Simulation time 71268808 ps
CPU time 1.05 seconds
Started Apr 04 12:41:04 PM PDT 24
Finished Apr 04 12:41:06 PM PDT 24
Peak memory 199880 kb
Host smart-6b0f339a-ffb6-4015-a26e-14b00aa0527d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221571414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1221571414
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1818087949
Short name T1208
Test name
Test status
Simulation time 323903914 ps
CPU time 1.35 seconds
Started Apr 04 12:39:43 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 199352 kb
Host smart-302f223f-bd7b-4db7-931d-2c43a082473b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818087949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1818087949
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2102542433
Short name T1197
Test name
Test status
Simulation time 15377973 ps
CPU time 0.59 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194304 kb
Host smart-2a5ef0cf-2dbe-473f-afda-bd7ebe9371e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102542433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2102542433
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3300716826
Short name T1313
Test name
Test status
Simulation time 58771099 ps
CPU time 0.55 seconds
Started Apr 04 12:40:33 PM PDT 24
Finished Apr 04 12:40:34 PM PDT 24
Peak memory 194228 kb
Host smart-9dfb7d16-bded-42f8-b853-16a222c7e9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300716826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3300716826
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.4043371332
Short name T1301
Test name
Test status
Simulation time 21771465 ps
CPU time 0.54 seconds
Started Apr 04 12:40:34 PM PDT 24
Finished Apr 04 12:40:35 PM PDT 24
Peak memory 194396 kb
Host smart-e977d179-5303-435f-847a-aa215e424e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043371332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.4043371332
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.1997556142
Short name T1268
Test name
Test status
Simulation time 39042501 ps
CPU time 0.59 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194372 kb
Host smart-60f1d34a-f3c5-4a62-b59e-4b8a1f0820ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997556142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1997556142
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.4293476195
Short name T1203
Test name
Test status
Simulation time 14523477 ps
CPU time 0.56 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194304 kb
Host smart-5c50ca03-59fa-4101-ac8f-c72ec4d20bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293476195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.4293476195
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3917698547
Short name T1211
Test name
Test status
Simulation time 12578625 ps
CPU time 0.55 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194236 kb
Host smart-f76fcd95-62f4-4f78-b689-47c7f699a06d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917698547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3917698547
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.958879970
Short name T1261
Test name
Test status
Simulation time 60559448 ps
CPU time 0.59 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 194288 kb
Host smart-6c68b02f-b36f-49c1-9f24-4cf89da42b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958879970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.958879970
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.4125465052
Short name T1318
Test name
Test status
Simulation time 34840248 ps
CPU time 0.54 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194304 kb
Host smart-77b38235-737a-4f40-9077-a769934ca660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125465052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.4125465052
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2190459625
Short name T1235
Test name
Test status
Simulation time 30679246 ps
CPU time 0.56 seconds
Started Apr 04 12:41:23 PM PDT 24
Finished Apr 04 12:41:24 PM PDT 24
Peak memory 194156 kb
Host smart-2500204d-b0d7-42e9-a6a1-1abaee1fec51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190459625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2190459625
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.626378480
Short name T1272
Test name
Test status
Simulation time 10997527 ps
CPU time 0.57 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194344 kb
Host smart-f4cd0d26-3fd9-4c63-9ce9-ea4d3a2f38e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626378480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.626378480
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2672945661
Short name T1290
Test name
Test status
Simulation time 25101797 ps
CPU time 0.69 seconds
Started Apr 04 12:39:52 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 195296 kb
Host smart-7a67555c-007d-4163-939d-5c336dbb5a7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672945661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2672945661
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2634461872
Short name T1180
Test name
Test status
Simulation time 67703477 ps
CPU time 1.4 seconds
Started Apr 04 12:39:44 PM PDT 24
Finished Apr 04 12:39:45 PM PDT 24
Peak memory 197688 kb
Host smart-7e33080f-2b13-4312-98d0-0279c63c6450
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634461872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2634461872
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2814857827
Short name T1292
Test name
Test status
Simulation time 30113112 ps
CPU time 0.56 seconds
Started Apr 04 12:39:43 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 195328 kb
Host smart-bbf7fdeb-9cbf-4079-8a0a-d55171a718e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814857827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2814857827
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.428633133
Short name T1183
Test name
Test status
Simulation time 28448861 ps
CPU time 0.82 seconds
Started Apr 04 12:39:52 PM PDT 24
Finished Apr 04 12:39:53 PM PDT 24
Peak memory 199652 kb
Host smart-4fc9ee0f-e862-4edf-97d0-9c6604164024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428633133 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.428633133
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.954679611
Short name T1192
Test name
Test status
Simulation time 148356525 ps
CPU time 0.58 seconds
Started Apr 04 12:39:43 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 195356 kb
Host smart-465fedec-314a-4e27-9e0c-b9702d08e1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954679611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.954679611
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1708440371
Short name T1285
Test name
Test status
Simulation time 26426039 ps
CPU time 0.55 seconds
Started Apr 04 12:39:42 PM PDT 24
Finished Apr 04 12:39:43 PM PDT 24
Peak memory 194348 kb
Host smart-2468bcce-be41-4cc9-9363-073dad74dd59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708440371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1708440371
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1250082693
Short name T78
Test name
Test status
Simulation time 258205448 ps
CPU time 0.75 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 196948 kb
Host smart-8fa19ef0-9501-4285-8b13-1f4ba0c87a4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250082693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1250082693
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.290924422
Short name T1257
Test name
Test status
Simulation time 73963103 ps
CPU time 2.03 seconds
Started Apr 04 12:39:47 PM PDT 24
Finished Apr 04 12:39:49 PM PDT 24
Peak memory 199944 kb
Host smart-90b75368-7bfe-44e8-a833-37e1a0c1f326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290924422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.290924422
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1768800144
Short name T81
Test name
Test status
Simulation time 197550781 ps
CPU time 0.96 seconds
Started Apr 04 12:39:43 PM PDT 24
Finished Apr 04 12:39:44 PM PDT 24
Peak memory 198932 kb
Host smart-3cef38d1-7eb1-4bf9-b013-8e915d2a0094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768800144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1768800144
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3564960048
Short name T1207
Test name
Test status
Simulation time 41023076 ps
CPU time 0.56 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 194100 kb
Host smart-c6d78ecd-4215-43ea-bc2b-35d247401ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564960048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3564960048
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2347583244
Short name T1300
Test name
Test status
Simulation time 49645041 ps
CPU time 0.59 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194368 kb
Host smart-7d1b04bd-641b-4510-b642-797250fe98cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347583244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2347583244
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1897521280
Short name T1237
Test name
Test status
Simulation time 14844515 ps
CPU time 0.59 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:28 PM PDT 24
Peak memory 194204 kb
Host smart-97769cc6-6406-4694-b26a-111fc50fb623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897521280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1897521280
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4126328910
Short name T1241
Test name
Test status
Simulation time 116931436 ps
CPU time 0.54 seconds
Started Apr 04 12:40:28 PM PDT 24
Finished Apr 04 12:40:29 PM PDT 24
Peak memory 194132 kb
Host smart-5e8ae5d8-7952-47c6-8d58-e2d980a7f50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126328910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4126328910
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3785761110
Short name T1213
Test name
Test status
Simulation time 33268681 ps
CPU time 0.58 seconds
Started Apr 04 12:40:32 PM PDT 24
Finished Apr 04 12:40:33 PM PDT 24
Peak memory 194276 kb
Host smart-ff432672-b9aa-48a3-97a8-90b8647298e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785761110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3785761110
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2643435900
Short name T1262
Test name
Test status
Simulation time 13790828 ps
CPU time 0.53 seconds
Started Apr 04 12:40:34 PM PDT 24
Finished Apr 04 12:40:35 PM PDT 24
Peak memory 194368 kb
Host smart-cae1b5eb-c44d-4d57-9521-1ddedc0d3856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643435900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2643435900
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1569032463
Short name T1273
Test name
Test status
Simulation time 11678057 ps
CPU time 0.54 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194312 kb
Host smart-f0c1e801-5570-40eb-8564-048f98b514a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569032463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1569032463
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3334764950
Short name T1231
Test name
Test status
Simulation time 120900946 ps
CPU time 0.6 seconds
Started Apr 04 12:41:23 PM PDT 24
Finished Apr 04 12:41:24 PM PDT 24
Peak memory 194212 kb
Host smart-44db7616-b937-4ccd-8f1a-105c5014c59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334764950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3334764950
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.593044625
Short name T1215
Test name
Test status
Simulation time 21720340 ps
CPU time 0.56 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194332 kb
Host smart-3a640f8e-c474-4f87-b126-828b3008f63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593044625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.593044625
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2964520098
Short name T1209
Test name
Test status
Simulation time 25303166 ps
CPU time 0.58 seconds
Started Apr 04 12:40:31 PM PDT 24
Finished Apr 04 12:40:32 PM PDT 24
Peak memory 194252 kb
Host smart-ad615c5c-214c-4311-80ba-c347f880f9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964520098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2964520098
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1548465624
Short name T1186
Test name
Test status
Simulation time 73074043 ps
CPU time 0.66 seconds
Started Apr 04 12:39:55 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 195272 kb
Host smart-ebd65254-ecf1-42d9-a68b-c7eb12242637
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548465624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1548465624
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2769729355
Short name T1221
Test name
Test status
Simulation time 2278805884 ps
CPU time 2.43 seconds
Started Apr 04 12:39:52 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 198024 kb
Host smart-5799cc38-fec1-4929-8854-f0135139bb17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769729355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2769729355
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.140142181
Short name T1219
Test name
Test status
Simulation time 1052747365 ps
CPU time 1.17 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 195356 kb
Host smart-0bed536d-1cb3-4ec4-afc8-4f4590ee9d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140142181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.140142181
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1249648988
Short name T1191
Test name
Test status
Simulation time 16087174 ps
CPU time 0.73 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 197816 kb
Host smart-a6d1cf18-b631-4977-acf9-87cc27c49bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249648988 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1249648988
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3010198050
Short name T1317
Test name
Test status
Simulation time 20272071 ps
CPU time 0.56 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 195408 kb
Host smart-28160b76-5606-4f28-91fe-0a162101d544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010198050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3010198050
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.410004874
Short name T1187
Test name
Test status
Simulation time 11391795 ps
CPU time 0.58 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 194364 kb
Host smart-1ca1e089-6aef-42bb-b29d-bd55389177d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410004874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.410004874
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.767702375
Short name T1310
Test name
Test status
Simulation time 14750213 ps
CPU time 0.67 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 194704 kb
Host smart-34486284-63f4-4d92-9480-c499597467f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767702375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.767702375
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2480601471
Short name T1206
Test name
Test status
Simulation time 497872973 ps
CPU time 1.94 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 200040 kb
Host smart-3d94819d-54b1-4766-b994-3b5385a8d8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480601471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2480601471
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1091947933
Short name T1298
Test name
Test status
Simulation time 192374377 ps
CPU time 0.98 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 199092 kb
Host smart-a573c356-01b2-4907-bc9a-93fd964d7c7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091947933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1091947933
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4012651972
Short name T1210
Test name
Test status
Simulation time 20566521 ps
CPU time 0.55 seconds
Started Apr 04 12:40:30 PM PDT 24
Finished Apr 04 12:40:31 PM PDT 24
Peak memory 194232 kb
Host smart-247adc86-465f-423f-b41f-4e5bf7d8774d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012651972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4012651972
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4142285068
Short name T1288
Test name
Test status
Simulation time 31219976 ps
CPU time 0.58 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:34 PM PDT 24
Peak memory 194248 kb
Host smart-4172da9e-8495-4ac2-9014-50a11f9095b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142285068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4142285068
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.317645715
Short name T1297
Test name
Test status
Simulation time 16159630 ps
CPU time 0.62 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194336 kb
Host smart-1669270a-2619-4ac2-9946-1f83125a0eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317645715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.317645715
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2387537191
Short name T1185
Test name
Test status
Simulation time 51211798 ps
CPU time 0.56 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194288 kb
Host smart-55398a9d-7848-47a7-a164-b3001e247fd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387537191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2387537191
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2674743443
Short name T1281
Test name
Test status
Simulation time 11212634 ps
CPU time 0.58 seconds
Started Apr 04 12:40:32 PM PDT 24
Finished Apr 04 12:40:32 PM PDT 24
Peak memory 194300 kb
Host smart-1a8d2f1e-240a-4fbb-8adf-663c5a832743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674743443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2674743443
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.131923368
Short name T1307
Test name
Test status
Simulation time 24685195 ps
CPU time 0.57 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194336 kb
Host smart-d41ff1d9-37ee-402e-8c99-87b934db3e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131923368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.131923368
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1621878171
Short name T1264
Test name
Test status
Simulation time 65202466 ps
CPU time 0.57 seconds
Started Apr 04 12:40:33 PM PDT 24
Finished Apr 04 12:40:34 PM PDT 24
Peak memory 194164 kb
Host smart-271dbf08-6de9-4b01-b561-6fa891ea22c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621878171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1621878171
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3419029256
Short name T1243
Test name
Test status
Simulation time 25440309 ps
CPU time 0.57 seconds
Started Apr 04 12:40:29 PM PDT 24
Finished Apr 04 12:40:30 PM PDT 24
Peak memory 194296 kb
Host smart-0e419aae-566e-48fe-9ccc-22a1f4e08d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419029256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3419029256
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4090690182
Short name T1184
Test name
Test status
Simulation time 45239336 ps
CPU time 0.57 seconds
Started Apr 04 12:40:38 PM PDT 24
Finished Apr 04 12:40:39 PM PDT 24
Peak memory 194368 kb
Host smart-2a5e0716-fe0d-4bd9-8251-f98ae73d0fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090690182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4090690182
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3469530790
Short name T1258
Test name
Test status
Simulation time 14681814 ps
CPU time 0.69 seconds
Started Apr 04 12:41:59 PM PDT 24
Finished Apr 04 12:42:00 PM PDT 24
Peak memory 193408 kb
Host smart-8cf90618-3cf4-4479-95f1-4f603a63b1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469530790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3469530790
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2389939263
Short name T1304
Test name
Test status
Simulation time 31698579 ps
CPU time 1.46 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 199956 kb
Host smart-c5a193ee-d041-436e-8df4-dea98bc8dc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389939263 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2389939263
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1631098084
Short name T1282
Test name
Test status
Simulation time 23969291 ps
CPU time 0.62 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 195424 kb
Host smart-ccdcaf96-2659-4955-8a3b-8d294df116d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631098084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1631098084
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.7305994
Short name T1247
Test name
Test status
Simulation time 12610131 ps
CPU time 0.57 seconds
Started Apr 04 12:39:55 PM PDT 24
Finished Apr 04 12:39:56 PM PDT 24
Peak memory 194364 kb
Host smart-b2f8287f-c133-4c67-b6d8-d93551b66b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7305994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.7305994
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1666527026
Short name T1217
Test name
Test status
Simulation time 31621539 ps
CPU time 0.72 seconds
Started Apr 04 12:39:53 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 197936 kb
Host smart-8c031db8-7709-4e13-876d-bd0b53727b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666527026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1666527026
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1482017791
Short name T1299
Test name
Test status
Simulation time 68160155 ps
CPU time 1.51 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:56 PM PDT 24
Peak memory 199968 kb
Host smart-6eac3913-50b4-459e-87db-dcd36c21097c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482017791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1482017791
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1598209394
Short name T1202
Test name
Test status
Simulation time 92937808 ps
CPU time 0.95 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 198828 kb
Host smart-b4a94e97-a9c0-4781-b4de-381f158ed928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598209394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1598209394
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2922439164
Short name T1302
Test name
Test status
Simulation time 17650920 ps
CPU time 0.7 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 197632 kb
Host smart-2f23aea5-b4e0-4857-8151-3571974b67b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922439164 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2922439164
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.120830444
Short name T1306
Test name
Test status
Simulation time 14538715 ps
CPU time 0.63 seconds
Started Apr 04 12:39:52 PM PDT 24
Finished Apr 04 12:39:52 PM PDT 24
Peak memory 195404 kb
Host smart-4811c08b-ef1f-43da-aa9c-8e09be13806a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120830444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.120830444
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3099812158
Short name T1214
Test name
Test status
Simulation time 13119842 ps
CPU time 0.56 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:54 PM PDT 24
Peak memory 194240 kb
Host smart-12cbc063-eecf-4868-9a23-643f294be3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099812158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3099812158
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2514840255
Short name T72
Test name
Test status
Simulation time 16295695 ps
CPU time 0.73 seconds
Started Apr 04 12:40:08 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 196016 kb
Host smart-80a5b748-b04e-4f32-99b8-9cdac5a7915e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514840255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2514840255
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3679197857
Short name T1303
Test name
Test status
Simulation time 36466084 ps
CPU time 1.68 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 200004 kb
Host smart-63d67a8e-f958-4498-a308-15a4ccb00726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679197857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3679197857
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2584150332
Short name T1225
Test name
Test status
Simulation time 326308016 ps
CPU time 0.98 seconds
Started Apr 04 12:39:54 PM PDT 24
Finished Apr 04 12:39:55 PM PDT 24
Peak memory 199072 kb
Host smart-fcf90d3a-c402-4d87-a3df-ad412e02301f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584150332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2584150332
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1272456617
Short name T1275
Test name
Test status
Simulation time 39164685 ps
CPU time 1.01 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 199832 kb
Host smart-3a12ec91-a299-463e-87df-9ce207130739
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272456617 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1272456617
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2029630849
Short name T1312
Test name
Test status
Simulation time 24008008 ps
CPU time 0.62 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:05 PM PDT 24
Peak memory 195556 kb
Host smart-952b728c-dc80-469f-ab06-2d13e9476ed0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029630849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2029630849
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1325412575
Short name T1227
Test name
Test status
Simulation time 92006024 ps
CPU time 0.59 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 194392 kb
Host smart-0cdb5222-759e-4a79-a343-0510c757fd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325412575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1325412575
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1612418773
Short name T1224
Test name
Test status
Simulation time 22907359 ps
CPU time 0.67 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 194580 kb
Host smart-aace3519-bd0b-433a-a94b-b9745451eee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612418773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1612418773
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3366487773
Short name T1198
Test name
Test status
Simulation time 97560640 ps
CPU time 1.25 seconds
Started Apr 04 12:40:07 PM PDT 24
Finished Apr 04 12:40:10 PM PDT 24
Peak memory 200028 kb
Host smart-7e2a0a2a-ceda-459f-b7bf-38b1803a5836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366487773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3366487773
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.517544250
Short name T1250
Test name
Test status
Simulation time 197010355 ps
CPU time 0.72 seconds
Started Apr 04 12:40:03 PM PDT 24
Finished Apr 04 12:40:04 PM PDT 24
Peak memory 199040 kb
Host smart-99e76bce-a656-4c4e-9333-bef33a32bb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517544250 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.517544250
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3465205275
Short name T1316
Test name
Test status
Simulation time 51771313 ps
CPU time 0.63 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:06 PM PDT 24
Peak memory 195416 kb
Host smart-72d496ad-00fd-46e1-84f7-88f4834ad4a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465205275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3465205275
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2857313433
Short name T1232
Test name
Test status
Simulation time 18523381 ps
CPU time 0.64 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 194348 kb
Host smart-90cf563f-8e4a-4cc3-a7c8-5a3378599bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857313433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2857313433
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2607698787
Short name T1269
Test name
Test status
Simulation time 20734275 ps
CPU time 0.64 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 196620 kb
Host smart-e68f5e11-6e26-4e20-ba47-0a7317f8efea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607698787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2607698787
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.592906978
Short name T1238
Test name
Test status
Simulation time 1336158700 ps
CPU time 1.43 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 199940 kb
Host smart-a50e6a67-e47d-4e79-a965-44d62e878ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592906978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.592906978
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1180759870
Short name T1212
Test name
Test status
Simulation time 47402034 ps
CPU time 0.96 seconds
Started Apr 04 12:40:04 PM PDT 24
Finished Apr 04 12:40:06 PM PDT 24
Peak memory 198956 kb
Host smart-959e2c07-159b-4dee-86f0-b74dddb3dfa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180759870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1180759870
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4114965906
Short name T1226
Test name
Test status
Simulation time 368771553 ps
CPU time 0.76 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 198128 kb
Host smart-cf9a8ed5-7036-4674-b991-c98d536cdd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114965906 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4114965906
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.278489762
Short name T59
Test name
Test status
Simulation time 17394859 ps
CPU time 0.63 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 195376 kb
Host smart-2e57c8f6-1fa5-4396-b50b-07e783288a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278489762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.278489762
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2788141236
Short name T1295
Test name
Test status
Simulation time 18790154 ps
CPU time 0.58 seconds
Started Apr 04 12:40:06 PM PDT 24
Finished Apr 04 12:40:08 PM PDT 24
Peak memory 194252 kb
Host smart-644c09fd-88fa-4ffd-80d9-85a62329118d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788141236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2788141236
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4005374362
Short name T1253
Test name
Test status
Simulation time 15891245 ps
CPU time 0.75 seconds
Started Apr 04 12:40:07 PM PDT 24
Finished Apr 04 12:40:09 PM PDT 24
Peak memory 197408 kb
Host smart-0d8e58d6-d52b-490c-80b4-c2309ad43370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005374362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4005374362
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3524957056
Short name T1195
Test name
Test status
Simulation time 32700202 ps
CPU time 0.98 seconds
Started Apr 04 12:40:08 PM PDT 24
Finished Apr 04 12:40:10 PM PDT 24
Peak memory 199772 kb
Host smart-fdb3dc44-1ed4-4439-a34c-13ae07052eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524957056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3524957056
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4185448356
Short name T1263
Test name
Test status
Simulation time 389987685 ps
CPU time 1.35 seconds
Started Apr 04 12:40:05 PM PDT 24
Finished Apr 04 12:40:07 PM PDT 24
Peak memory 199368 kb
Host smart-93902737-ee70-45fa-9688-23db61491d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185448356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4185448356
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3807077199
Short name T851
Test name
Test status
Simulation time 20865506 ps
CPU time 0.51 seconds
Started Apr 04 02:05:53 PM PDT 24
Finished Apr 04 02:05:54 PM PDT 24
Peak memory 195580 kb
Host smart-68e62156-e798-4833-a0f5-6ac203206e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807077199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3807077199
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3910861728
Short name T350
Test name
Test status
Simulation time 232893479672 ps
CPU time 338.64 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:11:31 PM PDT 24
Peak memory 200940 kb
Host smart-767dca39-273e-4005-b13c-e3bfe1119d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910861728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3910861728
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1965287521
Short name T613
Test name
Test status
Simulation time 102922645443 ps
CPU time 52.92 seconds
Started Apr 04 02:05:51 PM PDT 24
Finished Apr 04 02:06:44 PM PDT 24
Peak memory 200920 kb
Host smart-ffcae697-8fc4-4142-a14a-618330310796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965287521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1965287521
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.142533131
Short name T245
Test name
Test status
Simulation time 95504357335 ps
CPU time 151.6 seconds
Started Apr 04 02:05:50 PM PDT 24
Finished Apr 04 02:08:22 PM PDT 24
Peak memory 200916 kb
Host smart-329949d7-00e5-4a0b-ae08-501b0e71d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142533131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.142533131
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2565428322
Short name T553
Test name
Test status
Simulation time 45278494223 ps
CPU time 81.95 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:07:14 PM PDT 24
Peak memory 200968 kb
Host smart-cc9bacb7-d987-4ee9-873d-1a074cb9e35f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565428322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2565428322
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1688580020
Short name T926
Test name
Test status
Simulation time 342324276197 ps
CPU time 107.84 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:07:40 PM PDT 24
Peak memory 200840 kb
Host smart-4119081e-6a56-4f74-a60d-39c44c6efc90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688580020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1688580020
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1920280433
Short name T658
Test name
Test status
Simulation time 8553106626 ps
CPU time 19.8 seconds
Started Apr 04 02:05:51 PM PDT 24
Finished Apr 04 02:06:11 PM PDT 24
Peak memory 200224 kb
Host smart-21cc2ccc-bc95-4972-bd1d-10c7ffe1558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920280433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1920280433
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4042579495
Short name T646
Test name
Test status
Simulation time 65307389327 ps
CPU time 121.06 seconds
Started Apr 04 02:05:51 PM PDT 24
Finished Apr 04 02:07:52 PM PDT 24
Peak memory 200968 kb
Host smart-a01fb250-2da1-47cb-9f46-a7df42519cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042579495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4042579495
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3226008751
Short name T503
Test name
Test status
Simulation time 14467175344 ps
CPU time 878.69 seconds
Started Apr 04 02:05:53 PM PDT 24
Finished Apr 04 02:20:31 PM PDT 24
Peak memory 200840 kb
Host smart-c28c217d-22d6-40ca-a113-d90d9f59ea17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226008751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3226008751
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3076176522
Short name T338
Test name
Test status
Simulation time 3151724732 ps
CPU time 13.36 seconds
Started Apr 04 02:05:50 PM PDT 24
Finished Apr 04 02:06:03 PM PDT 24
Peak memory 199032 kb
Host smart-d07a19be-2e35-4928-9972-b77d2c334676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076176522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3076176522
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3193565788
Short name T118
Test name
Test status
Simulation time 30240369874 ps
CPU time 27.53 seconds
Started Apr 04 02:05:51 PM PDT 24
Finished Apr 04 02:06:19 PM PDT 24
Peak memory 200776 kb
Host smart-ffc68ffe-c5bc-436e-841c-9dc864c0cb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193565788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3193565788
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.95695361
Short name T682
Test name
Test status
Simulation time 4956631747 ps
CPU time 2.55 seconds
Started Apr 04 02:05:53 PM PDT 24
Finished Apr 04 02:05:56 PM PDT 24
Peak memory 196792 kb
Host smart-0db512b8-b486-4b0a-bc65-a8d3bda90632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95695361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.95695361
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.872516955
Short name T459
Test name
Test status
Simulation time 661010427 ps
CPU time 2.37 seconds
Started Apr 04 02:05:49 PM PDT 24
Finished Apr 04 02:05:51 PM PDT 24
Peak memory 199132 kb
Host smart-d5d57ff2-aadd-4f32-97d2-19107d0bb9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872516955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.872516955
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.4161572304
Short name T630
Test name
Test status
Simulation time 97979380811 ps
CPU time 256.24 seconds
Started Apr 04 02:05:53 PM PDT 24
Finished Apr 04 02:10:09 PM PDT 24
Peak memory 200776 kb
Host smart-ea6a9b74-b053-4d7c-8043-ed9a2b87d563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161572304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4161572304
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3363094659
Short name T161
Test name
Test status
Simulation time 312022782555 ps
CPU time 1233.18 seconds
Started Apr 04 02:05:50 PM PDT 24
Finished Apr 04 02:26:23 PM PDT 24
Peak memory 226724 kb
Host smart-14be4c5b-1ee1-4148-a6d5-97526c746cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363094659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3363094659
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.721652732
Short name T285
Test name
Test status
Simulation time 6063700445 ps
CPU time 21.96 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:06:14 PM PDT 24
Peak memory 200092 kb
Host smart-e9aa6e62-8dbe-4f05-a363-8a5c46fc9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721652732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.721652732
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2072792037
Short name T970
Test name
Test status
Simulation time 71505261685 ps
CPU time 16.98 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:06:09 PM PDT 24
Peak memory 200864 kb
Host smart-8499a437-6e69-413f-bd46-b55c764c0ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072792037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2072792037
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2291062500
Short name T454
Test name
Test status
Simulation time 15106174 ps
CPU time 0.57 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:06:03 PM PDT 24
Peak memory 196228 kb
Host smart-61028f5d-f0d2-4c0e-9b88-30dcb71e612d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291062500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2291062500
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1128916351
Short name T1121
Test name
Test status
Simulation time 70370380536 ps
CPU time 109.82 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:07:52 PM PDT 24
Peak memory 200940 kb
Host smart-10f817a8-4759-4bb9-8415-65e58ba5ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128916351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1128916351
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.773613354
Short name T697
Test name
Test status
Simulation time 72413951739 ps
CPU time 191.13 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:09:13 PM PDT 24
Peak memory 200812 kb
Host smart-5eca775e-36c2-408e-a8e5-afaecb519141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773613354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.773613354
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2692021346
Short name T656
Test name
Test status
Simulation time 12974095483 ps
CPU time 21.61 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:06:25 PM PDT 24
Peak memory 200624 kb
Host smart-e41ca4d6-78c6-484e-a120-da54229d9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692021346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2692021346
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3138854140
Short name T943
Test name
Test status
Simulation time 11124406202 ps
CPU time 18.81 seconds
Started Apr 04 02:06:01 PM PDT 24
Finished Apr 04 02:06:20 PM PDT 24
Peak memory 197600 kb
Host smart-f0d55fe8-4c77-4cee-a902-76e99f4f0df8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138854140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3138854140
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3485299606
Short name T607
Test name
Test status
Simulation time 93273972710 ps
CPU time 416.52 seconds
Started Apr 04 02:06:05 PM PDT 24
Finished Apr 04 02:13:02 PM PDT 24
Peak memory 200868 kb
Host smart-642b3fb9-60e8-4f0b-843e-b7e24791040e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485299606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3485299606
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3529884865
Short name T552
Test name
Test status
Simulation time 5731017795 ps
CPU time 6.82 seconds
Started Apr 04 02:06:04 PM PDT 24
Finished Apr 04 02:06:11 PM PDT 24
Peak memory 199884 kb
Host smart-fc9dd107-1fc6-44c5-8c1b-f7f060f68957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529884865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3529884865
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.3551635954
Short name T728
Test name
Test status
Simulation time 36441819595 ps
CPU time 124.49 seconds
Started Apr 04 02:06:05 PM PDT 24
Finished Apr 04 02:08:10 PM PDT 24
Peak memory 200900 kb
Host smart-3e033872-2875-4e25-976d-35f91950889a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551635954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3551635954
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.117637788
Short name T1144
Test name
Test status
Simulation time 3965518801 ps
CPU time 31.85 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:06:34 PM PDT 24
Peak memory 198916 kb
Host smart-d1fd396d-75eb-4d98-96e2-20450fe852ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117637788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.117637788
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3413162518
Short name T1068
Test name
Test status
Simulation time 91357879395 ps
CPU time 113.12 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:07:57 PM PDT 24
Peak memory 200728 kb
Host smart-6f28b0f9-0b74-41a4-84ba-aa829c84a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413162518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3413162518
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3250781085
Short name T696
Test name
Test status
Simulation time 1441573679 ps
CPU time 3.09 seconds
Started Apr 04 02:06:01 PM PDT 24
Finished Apr 04 02:06:05 PM PDT 24
Peak memory 196228 kb
Host smart-2d4aab45-a901-43b2-a7fc-3b6344c125e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250781085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3250781085
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1471470521
Short name T30
Test name
Test status
Simulation time 249741439 ps
CPU time 0.77 seconds
Started Apr 04 02:06:01 PM PDT 24
Finished Apr 04 02:06:02 PM PDT 24
Peak memory 218688 kb
Host smart-756df569-4f92-4c05-ae6f-2983a122990a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471470521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1471470521
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2496021744
Short name T825
Test name
Test status
Simulation time 502437872 ps
CPU time 2.12 seconds
Started Apr 04 02:05:53 PM PDT 24
Finished Apr 04 02:05:55 PM PDT 24
Peak memory 199928 kb
Host smart-4372c235-b899-4a50-8329-050d81e00e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496021744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2496021744
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.594414120
Short name T217
Test name
Test status
Simulation time 328968700576 ps
CPU time 630.25 seconds
Started Apr 04 02:06:01 PM PDT 24
Finished Apr 04 02:16:32 PM PDT 24
Peak memory 209112 kb
Host smart-10a7eb92-ce6c-4f89-a78b-e45e85c385c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594414120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.594414120
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3948649495
Short name T1024
Test name
Test status
Simulation time 55525622886 ps
CPU time 297.96 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:11:01 PM PDT 24
Peak memory 217576 kb
Host smart-054f24d2-a667-454c-966c-a42b9ce68320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948649495 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3948649495
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3845774067
Short name T557
Test name
Test status
Simulation time 7481636143 ps
CPU time 19.48 seconds
Started Apr 04 02:06:06 PM PDT 24
Finished Apr 04 02:06:26 PM PDT 24
Peak memory 200808 kb
Host smart-4cf22b2d-bd29-4275-9e3f-78366ad4641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845774067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3845774067
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2482494232
Short name T502
Test name
Test status
Simulation time 78393967638 ps
CPU time 68.3 seconds
Started Apr 04 02:05:52 PM PDT 24
Finished Apr 04 02:07:01 PM PDT 24
Peak memory 200820 kb
Host smart-fbbbea11-ca6e-4ce0-a816-b32110d49ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482494232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2482494232
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3127116313
Short name T121
Test name
Test status
Simulation time 194520261736 ps
CPU time 226.51 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:10:37 PM PDT 24
Peak memory 200116 kb
Host smart-6254272c-d597-42bd-9d71-e1e904e6b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127116313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3127116313
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.277677745
Short name T863
Test name
Test status
Simulation time 59508419491 ps
CPU time 94.34 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:08:24 PM PDT 24
Peak memory 200884 kb
Host smart-d015f210-e4e6-4351-9a61-ea470a0b9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277677745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.277677745
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1363153211
Short name T243
Test name
Test status
Simulation time 20756944572 ps
CPU time 36.71 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200880 kb
Host smart-ba89fb6b-0685-40e5-a6f2-184cbf8fd1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363153211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1363153211
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1882731714
Short name T835
Test name
Test status
Simulation time 25780004477 ps
CPU time 21.05 seconds
Started Apr 04 02:07:02 PM PDT 24
Finished Apr 04 02:07:24 PM PDT 24
Peak memory 200848 kb
Host smart-ff239b2f-ac50-4ab0-94ae-3b78724ed37c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882731714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1882731714
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3257807204
Short name T250
Test name
Test status
Simulation time 109471902493 ps
CPU time 313.93 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:12:14 PM PDT 24
Peak memory 200740 kb
Host smart-cc18591f-6c5e-48ca-97a8-9bbb7a16c3bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257807204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3257807204
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1387196706
Short name T1172
Test name
Test status
Simulation time 6885534383 ps
CPU time 4.92 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:04 PM PDT 24
Peak memory 200636 kb
Host smart-6fa25920-2e2f-41de-8ac7-addde0cb654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387196706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1387196706
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.833960908
Short name T43
Test name
Test status
Simulation time 443066964688 ps
CPU time 46.52 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:07:47 PM PDT 24
Peak memory 201220 kb
Host smart-23e82222-5ff4-468c-97cd-885d343df2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833960908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.833960908
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.630667529
Short name T869
Test name
Test status
Simulation time 10815770351 ps
CPU time 146.5 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:09:28 PM PDT 24
Peak memory 200824 kb
Host smart-320b6075-d3fc-481a-9e58-62db7107684f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630667529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.630667529
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1862257442
Short name T1089
Test name
Test status
Simulation time 6006531832 ps
CPU time 13.18 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:07:14 PM PDT 24
Peak memory 200564 kb
Host smart-0d40f46f-4ef0-4871-8be7-8396ab43e8e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862257442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1862257442
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.302094165
Short name T1077
Test name
Test status
Simulation time 71425924984 ps
CPU time 99.93 seconds
Started Apr 04 02:06:58 PM PDT 24
Finished Apr 04 02:08:38 PM PDT 24
Peak memory 200796 kb
Host smart-7cda497b-fec7-49b9-9148-e18029365c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302094165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.302094165
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1138195790
Short name T783
Test name
Test status
Simulation time 3274551012 ps
CPU time 2.19 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:03 PM PDT 24
Peak memory 196704 kb
Host smart-29a2fffb-b50d-4d3c-9331-eac7336020a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138195790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1138195790
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3727847334
Short name T331
Test name
Test status
Simulation time 459217851 ps
CPU time 1.38 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:06:52 PM PDT 24
Peak memory 200580 kb
Host smart-783fa5a7-c3d5-4b6b-b5f4-6e695601fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727847334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3727847334
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4031409460
Short name T1124
Test name
Test status
Simulation time 70675592629 ps
CPU time 845.73 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:21:05 PM PDT 24
Peak memory 225500 kb
Host smart-6787072d-e0dd-4343-b3f6-96c3c917e15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031409460 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4031409460
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3454012521
Short name T517
Test name
Test status
Simulation time 1849528251 ps
CPU time 1.12 seconds
Started Apr 04 02:06:58 PM PDT 24
Finished Apr 04 02:06:59 PM PDT 24
Peak memory 199316 kb
Host smart-4c60dd69-c2f2-4a44-9b75-be289225a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454012521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3454012521
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2568868252
Short name T1
Test name
Test status
Simulation time 21869275177 ps
CPU time 38.24 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200952 kb
Host smart-4fd15d5c-cfe8-4853-8e30-1789441d8d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568868252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2568868252
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2412785239
Short name T1160
Test name
Test status
Simulation time 45629519082 ps
CPU time 38.44 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:13:43 PM PDT 24
Peak memory 200804 kb
Host smart-c58e28c0-bb82-46c7-94ba-631fc5367220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412785239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2412785239
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4043508060
Short name T544
Test name
Test status
Simulation time 57708768917 ps
CPU time 22.76 seconds
Started Apr 04 02:13:04 PM PDT 24
Finished Apr 04 02:13:27 PM PDT 24
Peak memory 200772 kb
Host smart-1b471159-84ec-40d6-ac68-921232f95112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043508060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4043508060
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.161251219
Short name T287
Test name
Test status
Simulation time 214312015476 ps
CPU time 212.01 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:16:35 PM PDT 24
Peak memory 200680 kb
Host smart-ffa666f4-f451-4a72-b610-cb6efbcc63e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161251219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.161251219
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1734892590
Short name T142
Test name
Test status
Simulation time 10126756259 ps
CPU time 14.99 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:13:20 PM PDT 24
Peak memory 200832 kb
Host smart-d3c3020b-6541-40c8-8714-c639447c3149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734892590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1734892590
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2982546297
Short name T633
Test name
Test status
Simulation time 117155013162 ps
CPU time 116.64 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:15:02 PM PDT 24
Peak memory 200916 kb
Host smart-889115e7-ba11-41d1-a0cd-a3d35d4d0e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982546297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2982546297
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.177029511
Short name T200
Test name
Test status
Simulation time 34593373002 ps
CPU time 75.34 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:14:20 PM PDT 24
Peak memory 200896 kb
Host smart-1118d764-43d9-4cc6-a504-da0398a4307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177029511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.177029511
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2769687839
Short name T597
Test name
Test status
Simulation time 61202483821 ps
CPU time 78.79 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:14:24 PM PDT 24
Peak memory 200796 kb
Host smart-a55cf20c-e910-4f84-97db-d891097470f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769687839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2769687839
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1649929055
Short name T160
Test name
Test status
Simulation time 97232506223 ps
CPU time 26.87 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:13:32 PM PDT 24
Peak memory 200376 kb
Host smart-984f4ff4-7016-481c-8130-338873a40943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649929055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1649929055
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2988905495
Short name T439
Test name
Test status
Simulation time 15417614 ps
CPU time 0.57 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:00 PM PDT 24
Peak memory 196132 kb
Host smart-5310557f-e35d-46a9-a4c7-53cf3d33a8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988905495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2988905495
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3911764854
Short name T777
Test name
Test status
Simulation time 23565263864 ps
CPU time 22.41 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:22 PM PDT 24
Peak memory 200700 kb
Host smart-5dbf12d7-2904-4b19-938c-941661939ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911764854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3911764854
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3648161895
Short name T498
Test name
Test status
Simulation time 22590270163 ps
CPU time 37.59 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:38 PM PDT 24
Peak memory 200852 kb
Host smart-c7a8dcee-9de2-4fa7-b846-6f4d715a2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648161895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3648161895
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.957272979
Short name T718
Test name
Test status
Simulation time 176017809109 ps
CPU time 30.66 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:07:31 PM PDT 24
Peak memory 200888 kb
Host smart-91dce70a-5078-4980-bd9d-54b26bd04cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957272979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.957272979
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.423418115
Short name T407
Test name
Test status
Simulation time 259870345553 ps
CPU time 197.75 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:10:17 PM PDT 24
Peak memory 199844 kb
Host smart-f7e51103-3cb6-424a-98b4-b569e3780480
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423418115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.423418115
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3621899482
Short name T632
Test name
Test status
Simulation time 102556125621 ps
CPU time 546.16 seconds
Started Apr 04 02:07:02 PM PDT 24
Finished Apr 04 02:16:09 PM PDT 24
Peak memory 200780 kb
Host smart-36575d20-b10d-4fe6-8129-ef381f17d6a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3621899482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3621899482
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2113979
Short name T1044
Test name
Test status
Simulation time 3922856064 ps
CPU time 7.52 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:08 PM PDT 24
Peak memory 199240 kb
Host smart-6f2e257b-58e4-402f-9dc1-ef3d0cd4fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2113979
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1431254890
Short name T590
Test name
Test status
Simulation time 227099065080 ps
CPU time 62.23 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:08:03 PM PDT 24
Peak memory 200888 kb
Host smart-c6d284b4-81ec-4bef-a1cc-d319e0b176ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431254890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1431254890
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2044185390
Short name T730
Test name
Test status
Simulation time 15171581891 ps
CPU time 182.75 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:10:04 PM PDT 24
Peak memory 200900 kb
Host smart-3948f5a4-5183-4181-9c43-8089f5525571
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044185390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2044185390
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2513717342
Short name T6
Test name
Test status
Simulation time 2286044777 ps
CPU time 3.96 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:03 PM PDT 24
Peak memory 198924 kb
Host smart-9e14ad19-8ac1-48fa-bcc3-b4e4d511e674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513717342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2513717342
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2674975111
Short name T327
Test name
Test status
Simulation time 88707871330 ps
CPU time 35.03 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:35 PM PDT 24
Peak memory 200868 kb
Host smart-6460fcca-2fb1-4b07-9d52-1b7a011f4ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674975111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2674975111
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.719192327
Short name T972
Test name
Test status
Simulation time 1574719572 ps
CPU time 3.01 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:03 PM PDT 24
Peak memory 196284 kb
Host smart-4a3838e8-a4a2-4e14-aeaa-82e36fdbbdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719192327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.719192327
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3770475299
Short name T875
Test name
Test status
Simulation time 271423965 ps
CPU time 1.05 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:00 PM PDT 24
Peak memory 199540 kb
Host smart-cd5d9f98-93c4-47a1-8f34-387f2c50cf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770475299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3770475299
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1063741170
Short name T489
Test name
Test status
Simulation time 9270177441 ps
CPU time 20.16 seconds
Started Apr 04 02:07:02 PM PDT 24
Finished Apr 04 02:07:23 PM PDT 24
Peak memory 200896 kb
Host smart-69c5d625-1a7f-4dd5-9033-7bd0e3ba5da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063741170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1063741170
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1293860769
Short name T96
Test name
Test status
Simulation time 53282351604 ps
CPU time 601.43 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:17:01 PM PDT 24
Peak memory 217528 kb
Host smart-5fd9c2e5-b2f9-4089-863e-28a7c364b2d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293860769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1293860769
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1935071558
Short name T21
Test name
Test status
Simulation time 6098832512 ps
CPU time 23.71 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:24 PM PDT 24
Peak memory 200824 kb
Host smart-0ff99e32-73ba-4392-b120-a1ed849ed34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935071558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1935071558
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2704911588
Short name T195
Test name
Test status
Simulation time 109141500042 ps
CPU time 94.05 seconds
Started Apr 04 02:13:05 PM PDT 24
Finished Apr 04 02:14:39 PM PDT 24
Peak memory 200820 kb
Host smart-2dbe7ae6-0122-42bb-ad13-aed052d36a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704911588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2704911588
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3465994099
Short name T770
Test name
Test status
Simulation time 67780758712 ps
CPU time 29.31 seconds
Started Apr 04 02:13:17 PM PDT 24
Finished Apr 04 02:13:46 PM PDT 24
Peak memory 200796 kb
Host smart-1b14745c-2f3c-464a-83ff-aab0c01d8c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465994099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3465994099
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1430630559
Short name T317
Test name
Test status
Simulation time 70916920144 ps
CPU time 52.71 seconds
Started Apr 04 02:13:15 PM PDT 24
Finished Apr 04 02:14:08 PM PDT 24
Peak memory 200880 kb
Host smart-be53a16b-d4c6-4a4b-a19e-d1b671e75c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430630559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1430630559
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.402735071
Short name T400
Test name
Test status
Simulation time 31893903297 ps
CPU time 27.67 seconds
Started Apr 04 02:13:21 PM PDT 24
Finished Apr 04 02:13:48 PM PDT 24
Peak memory 200916 kb
Host smart-43229821-6a2f-4223-aa9f-1a4867a30312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402735071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.402735071
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.963162563
Short name T571
Test name
Test status
Simulation time 35265612117 ps
CPU time 25.52 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:13:42 PM PDT 24
Peak memory 200404 kb
Host smart-638591bb-173e-4641-b259-ec5300e4fc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963162563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.963162563
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.4226623931
Short name T232
Test name
Test status
Simulation time 33710468171 ps
CPU time 25.35 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:13:41 PM PDT 24
Peak memory 200896 kb
Host smart-19e40a55-790f-4d69-a900-bdc2365976ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226623931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.4226623931
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1181169803
Short name T842
Test name
Test status
Simulation time 68550032922 ps
CPU time 171.05 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:16:07 PM PDT 24
Peak memory 200824 kb
Host smart-e5496ba8-148f-4f5c-833e-243b65e7923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181169803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1181169803
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1227936683
Short name T366
Test name
Test status
Simulation time 103654587157 ps
CPU time 145.61 seconds
Started Apr 04 02:13:15 PM PDT 24
Finished Apr 04 02:15:41 PM PDT 24
Peak memory 200892 kb
Host smart-89cb531a-6a65-4afc-8548-16df6cc4575e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227936683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1227936683
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4156036987
Short name T290
Test name
Test status
Simulation time 34779861279 ps
CPU time 58.64 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:14:15 PM PDT 24
Peak memory 200900 kb
Host smart-f307f0c4-dcfb-4cde-9631-580f5565cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156036987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4156036987
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2573571000
Short name T335
Test name
Test status
Simulation time 13996350 ps
CPU time 0.56 seconds
Started Apr 04 02:07:15 PM PDT 24
Finished Apr 04 02:07:16 PM PDT 24
Peak memory 196244 kb
Host smart-959543c2-eca6-4aae-95b1-32d1e12d3a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573571000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2573571000
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3839106709
Short name T695
Test name
Test status
Simulation time 223788363470 ps
CPU time 95.33 seconds
Started Apr 04 02:07:01 PM PDT 24
Finished Apr 04 02:08:36 PM PDT 24
Peak memory 200880 kb
Host smart-c78c5ce7-ae8b-4620-9999-b95caaebe35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839106709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3839106709
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3478306929
Short name T669
Test name
Test status
Simulation time 105625579303 ps
CPU time 39.43 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:40 PM PDT 24
Peak memory 200776 kb
Host smart-32d955d9-91de-4acb-959e-3a6f5c9238e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478306929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3478306929
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1838099711
Short name T313
Test name
Test status
Simulation time 55125683763 ps
CPU time 30.87 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:43 PM PDT 24
Peak memory 200868 kb
Host smart-5d37c2ff-774c-4288-84b7-8cbee0a3fd1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838099711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1838099711
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.382219611
Short name T355
Test name
Test status
Simulation time 166065370696 ps
CPU time 418.39 seconds
Started Apr 04 02:07:15 PM PDT 24
Finished Apr 04 02:14:14 PM PDT 24
Peak memory 200836 kb
Host smart-ee54e3fc-6aa9-4451-b5c1-3a461a4c3b80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382219611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.382219611
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.614678775
Short name T995
Test name
Test status
Simulation time 6197096476 ps
CPU time 5.39 seconds
Started Apr 04 02:07:13 PM PDT 24
Finished Apr 04 02:07:18 PM PDT 24
Peak memory 200832 kb
Host smart-2ec918c2-9736-48c5-acc9-ed9e6634476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614678775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.614678775
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1709711734
Short name T523
Test name
Test status
Simulation time 10399945465 ps
CPU time 18.86 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:31 PM PDT 24
Peak memory 198728 kb
Host smart-caee9934-e9a5-4fe7-8a69-2654affab36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709711734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1709711734
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2654912704
Short name T491
Test name
Test status
Simulation time 27198543773 ps
CPU time 369.43 seconds
Started Apr 04 02:07:10 PM PDT 24
Finished Apr 04 02:13:20 PM PDT 24
Peak memory 200840 kb
Host smart-b72b19cd-6ba2-4ed7-b607-184ff7aeb84f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654912704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2654912704
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1766366461
Short name T570
Test name
Test status
Simulation time 3708146643 ps
CPU time 2.79 seconds
Started Apr 04 02:07:13 PM PDT 24
Finished Apr 04 02:07:17 PM PDT 24
Peak memory 199104 kb
Host smart-57634f4c-04d0-44a4-810c-890597eb28b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1766366461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1766366461
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1887610073
Short name T694
Test name
Test status
Simulation time 17254461983 ps
CPU time 29.36 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:43 PM PDT 24
Peak memory 200928 kb
Host smart-67cd0c85-7727-44b5-a835-d32f812e7162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887610073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1887610073
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2716723131
Short name T1015
Test name
Test status
Simulation time 1876655241 ps
CPU time 2.14 seconds
Started Apr 04 02:07:10 PM PDT 24
Finished Apr 04 02:07:13 PM PDT 24
Peak memory 196416 kb
Host smart-5917a0f8-bcf7-4e5e-ae75-a706abcadc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716723131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2716723131
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3291778602
Short name T747
Test name
Test status
Simulation time 313083373 ps
CPU time 0.94 seconds
Started Apr 04 02:06:59 PM PDT 24
Finished Apr 04 02:07:01 PM PDT 24
Peak memory 199324 kb
Host smart-1b9f65b2-5b34-4399-a3fb-a53d98414142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291778602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3291778602
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3617587505
Short name T1028
Test name
Test status
Simulation time 266655038000 ps
CPU time 150.95 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:09:45 PM PDT 24
Peak memory 209204 kb
Host smart-ef7d2613-f0dd-413c-a390-683fa6a92c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617587505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3617587505
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1244294721
Short name T736
Test name
Test status
Simulation time 1259170736 ps
CPU time 6.44 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:18 PM PDT 24
Peak memory 200152 kb
Host smart-8422d2b4-3842-46fe-a944-b50498996f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244294721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1244294721
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.920462846
Short name T1072
Test name
Test status
Simulation time 117822254295 ps
CPU time 55.95 seconds
Started Apr 04 02:07:00 PM PDT 24
Finished Apr 04 02:07:56 PM PDT 24
Peak memory 200792 kb
Host smart-9688a4e2-4911-45ae-b07d-9c3f2cd86728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920462846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.920462846
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2345099884
Short name T1119
Test name
Test status
Simulation time 86145493729 ps
CPU time 309 seconds
Started Apr 04 02:13:22 PM PDT 24
Finished Apr 04 02:18:31 PM PDT 24
Peak memory 200796 kb
Host smart-6d373dcf-b8be-4bdd-98b5-bf1de502e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345099884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2345099884
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1583843791
Short name T539
Test name
Test status
Simulation time 233580180658 ps
CPU time 78.11 seconds
Started Apr 04 02:13:17 PM PDT 24
Finished Apr 04 02:14:35 PM PDT 24
Peak memory 200848 kb
Host smart-762b4ffd-d3f6-4805-909e-4941ca6fca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583843791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1583843791
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.653576818
Short name T278
Test name
Test status
Simulation time 51399150321 ps
CPU time 112.94 seconds
Started Apr 04 02:13:17 PM PDT 24
Finished Apr 04 02:15:10 PM PDT 24
Peak memory 200804 kb
Host smart-479d073d-57db-4289-9dcb-ceb8632e24ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653576818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.653576818
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.34948621
Short name T1038
Test name
Test status
Simulation time 28002443081 ps
CPU time 35.12 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:13:52 PM PDT 24
Peak memory 200920 kb
Host smart-7aa014c5-c236-45fc-ad1b-35ae160ac83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34948621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.34948621
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1010435292
Short name T1011
Test name
Test status
Simulation time 13024194844 ps
CPU time 30.02 seconds
Started Apr 04 02:13:17 PM PDT 24
Finished Apr 04 02:13:47 PM PDT 24
Peak memory 200792 kb
Host smart-87f0e1c8-6415-47ff-887b-dadca856b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010435292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1010435292
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4176626872
Short name T1131
Test name
Test status
Simulation time 21208546977 ps
CPU time 24.94 seconds
Started Apr 04 02:13:16 PM PDT 24
Finished Apr 04 02:13:41 PM PDT 24
Peak memory 200772 kb
Host smart-fa5ddb77-e2cc-4e7a-accd-fb15c7b9117d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176626872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4176626872
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3713630824
Short name T535
Test name
Test status
Simulation time 33257446134 ps
CPU time 15.41 seconds
Started Apr 04 02:13:19 PM PDT 24
Finished Apr 04 02:13:35 PM PDT 24
Peak memory 200828 kb
Host smart-b0cf9dfd-f144-4764-8588-37f49de50dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713630824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3713630824
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3445223936
Short name T169
Test name
Test status
Simulation time 110866323655 ps
CPU time 173.03 seconds
Started Apr 04 02:13:18 PM PDT 24
Finished Apr 04 02:16:11 PM PDT 24
Peak memory 200860 kb
Host smart-ee159946-faab-4df2-902f-db627d5dee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445223936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3445223936
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.493714899
Short name T409
Test name
Test status
Simulation time 81434300 ps
CPU time 0.54 seconds
Started Apr 04 02:07:10 PM PDT 24
Finished Apr 04 02:07:10 PM PDT 24
Peak memory 195728 kb
Host smart-8ae0f14f-7739-4611-86e6-f1b7b69ee3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493714899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.493714899
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.483210441
Short name T947
Test name
Test status
Simulation time 149548827062 ps
CPU time 170.79 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:10:01 PM PDT 24
Peak memory 200788 kb
Host smart-31af5a0c-eeee-4f7c-b52a-e936b754bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483210441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.483210441
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2156835569
Short name T453
Test name
Test status
Simulation time 18692145043 ps
CPU time 32.09 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:44 PM PDT 24
Peak memory 200880 kb
Host smart-e54663f4-eff0-4c84-95a1-81bfed48c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156835569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2156835569
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1705941759
Short name T598
Test name
Test status
Simulation time 31425053525 ps
CPU time 18.58 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:31 PM PDT 24
Peak memory 200728 kb
Host smart-064cfcce-d1eb-4833-88d5-9cb87da6e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705941759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1705941759
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3910675839
Short name T307
Test name
Test status
Simulation time 98156731918 ps
CPU time 35.63 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:49 PM PDT 24
Peak memory 198596 kb
Host smart-1741800c-2595-497a-8897-524454bf2517
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910675839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3910675839
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1281075901
Short name T579
Test name
Test status
Simulation time 69093854849 ps
CPU time 611.62 seconds
Started Apr 04 02:07:13 PM PDT 24
Finished Apr 04 02:17:25 PM PDT 24
Peak memory 200780 kb
Host smart-b22e3532-5ccd-41f8-9630-e61005b8e2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281075901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1281075901
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3711829555
Short name T639
Test name
Test status
Simulation time 8183474578 ps
CPU time 2.05 seconds
Started Apr 04 02:07:15 PM PDT 24
Finished Apr 04 02:07:17 PM PDT 24
Peak memory 199724 kb
Host smart-0f0492a1-70e2-4e47-90dc-f7499c63ea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711829555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3711829555
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.841726829
Short name T466
Test name
Test status
Simulation time 66205294561 ps
CPU time 108.61 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:09:04 PM PDT 24
Peak memory 200960 kb
Host smart-904bb1ce-ee16-4fbb-be27-c9b1b391b281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841726829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.841726829
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2419902245
Short name T440
Test name
Test status
Simulation time 16957077527 ps
CPU time 37.18 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:50 PM PDT 24
Peak memory 200812 kb
Host smart-0f6ceaf9-dfd9-4aaf-88f6-c17f47a6b0c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419902245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2419902245
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1884920967
Short name T17
Test name
Test status
Simulation time 4018509076 ps
CPU time 29.23 seconds
Started Apr 04 02:07:13 PM PDT 24
Finished Apr 04 02:07:43 PM PDT 24
Peak memory 198844 kb
Host smart-86d5e386-22a6-4392-b507-645653190460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884920967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1884920967
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.790765537
Short name T430
Test name
Test status
Simulation time 28975782357 ps
CPU time 42.48 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:56 PM PDT 24
Peak memory 200388 kb
Host smart-0270f382-5da1-4393-9878-a70bea7654a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790765537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.790765537
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2858384388
Short name T288
Test name
Test status
Simulation time 5892492176 ps
CPU time 10.6 seconds
Started Apr 04 02:07:16 PM PDT 24
Finished Apr 04 02:07:29 PM PDT 24
Peak memory 196716 kb
Host smart-fa1260bc-2c25-4cb8-988c-fec0404fed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858384388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2858384388
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1589802696
Short name T1134
Test name
Test status
Simulation time 692784164 ps
CPU time 3.09 seconds
Started Apr 04 02:07:10 PM PDT 24
Finished Apr 04 02:07:14 PM PDT 24
Peak memory 200488 kb
Host smart-5380f1ab-5c68-4dd1-b016-f252d40fa528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589802696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1589802696
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1784571206
Short name T631
Test name
Test status
Simulation time 477490514213 ps
CPU time 389.72 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:13:42 PM PDT 24
Peak memory 200856 kb
Host smart-3592f673-2da5-4b24-bfca-d237d8a467ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784571206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1784571206
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.533124357
Short name T277
Test name
Test status
Simulation time 70338604930 ps
CPU time 958.65 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:23:09 PM PDT 24
Peak memory 225616 kb
Host smart-09f4ce40-9986-4acc-acce-ff94dc10d4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533124357 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.533124357
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3127480151
Short name T969
Test name
Test status
Simulation time 383750523 ps
CPU time 1.81 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:07:13 PM PDT 24
Peak memory 199456 kb
Host smart-4786aac4-a013-43d8-a586-47d81f2e935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127480151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3127480151
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2191594857
Short name T271
Test name
Test status
Simulation time 80179225745 ps
CPU time 152.28 seconds
Started Apr 04 02:07:13 PM PDT 24
Finished Apr 04 02:09:46 PM PDT 24
Peak memory 200672 kb
Host smart-26f1dc90-b19c-4c9e-9b21-bf868ffccf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191594857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2191594857
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4040935041
Short name T1169
Test name
Test status
Simulation time 35989951208 ps
CPU time 45.21 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:14:16 PM PDT 24
Peak memory 200864 kb
Host smart-6a02640a-4389-4dc2-80c9-94ac7ddb103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040935041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4040935041
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2663107530
Short name T925
Test name
Test status
Simulation time 80966533629 ps
CPU time 128.74 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:15:39 PM PDT 24
Peak memory 200868 kb
Host smart-a8f38c07-b343-40e0-add2-e21ec0956e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663107530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2663107530
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.4134390852
Short name T1102
Test name
Test status
Simulation time 54990927645 ps
CPU time 87.06 seconds
Started Apr 04 02:13:29 PM PDT 24
Finished Apr 04 02:14:57 PM PDT 24
Peak memory 200724 kb
Host smart-5e82b8b7-f512-45f0-aabd-2d89470c0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134390852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.4134390852
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2711911408
Short name T1002
Test name
Test status
Simulation time 73606237790 ps
CPU time 64.31 seconds
Started Apr 04 02:13:28 PM PDT 24
Finished Apr 04 02:14:33 PM PDT 24
Peak memory 200816 kb
Host smart-1f054343-9abd-4e61-ab39-cad0777065e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711911408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2711911408
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3597466776
Short name T566
Test name
Test status
Simulation time 114738546810 ps
CPU time 405.3 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:20:16 PM PDT 24
Peak memory 200796 kb
Host smart-1e0ef531-6569-4d3c-b59b-5ebd9a2d3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597466776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3597466776
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3169049079
Short name T241
Test name
Test status
Simulation time 71444294607 ps
CPU time 34.1 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:14:05 PM PDT 24
Peak memory 200756 kb
Host smart-d1cb0553-00fa-4188-9c25-026e7cfd5486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169049079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3169049079
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.360122987
Short name T945
Test name
Test status
Simulation time 74108655542 ps
CPU time 17.44 seconds
Started Apr 04 02:13:29 PM PDT 24
Finished Apr 04 02:13:47 PM PDT 24
Peak memory 200340 kb
Host smart-fdc20708-aa7d-40db-add9-14b5d77055a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360122987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.360122987
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1318022231
Short name T158
Test name
Test status
Simulation time 114477486322 ps
CPU time 47.48 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:14:18 PM PDT 24
Peak memory 200848 kb
Host smart-d23c0c75-547c-4c72-b56c-f2c4e2258721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318022231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1318022231
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.639589238
Short name T1026
Test name
Test status
Simulation time 12954356 ps
CPU time 0.53 seconds
Started Apr 04 02:07:22 PM PDT 24
Finished Apr 04 02:07:23 PM PDT 24
Peak memory 196064 kb
Host smart-36ce807c-6b21-48ba-bc58-89d20748add5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639589238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.639589238
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.844323479
Short name T258
Test name
Test status
Simulation time 69205739084 ps
CPU time 30.99 seconds
Started Apr 04 02:07:15 PM PDT 24
Finished Apr 04 02:07:47 PM PDT 24
Peak memory 200840 kb
Host smart-3493a150-5037-45f1-9634-86f47a393c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844323479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.844323479
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.122833887
Short name T886
Test name
Test status
Simulation time 16454485889 ps
CPU time 17.37 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200760 kb
Host smart-8bba5e49-7cc2-4967-8cfa-f19fb1bfae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122833887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.122833887
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.966982485
Short name T896
Test name
Test status
Simulation time 148105679479 ps
CPU time 44.97 seconds
Started Apr 04 02:07:17 PM PDT 24
Finished Apr 04 02:08:04 PM PDT 24
Peak memory 200920 kb
Host smart-99a46ce9-f61e-4a34-955a-188148116259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966982485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.966982485
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1905029318
Short name T840
Test name
Test status
Simulation time 33150139253 ps
CPU time 29.43 seconds
Started Apr 04 02:07:12 PM PDT 24
Finished Apr 04 02:07:41 PM PDT 24
Peak memory 200872 kb
Host smart-69a7f7ee-1a4a-4cfb-aa21-09ca07533502
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905029318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1905029318
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1879621649
Short name T737
Test name
Test status
Simulation time 58004703421 ps
CPU time 438.17 seconds
Started Apr 04 02:07:24 PM PDT 24
Finished Apr 04 02:14:42 PM PDT 24
Peak memory 200888 kb
Host smart-ecee1f53-3024-4445-afba-da056eb08ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879621649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1879621649
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2737117296
Short name T24
Test name
Test status
Simulation time 7467930099 ps
CPU time 6.22 seconds
Started Apr 04 02:07:22 PM PDT 24
Finished Apr 04 02:07:29 PM PDT 24
Peak memory 200808 kb
Host smart-9f5eaa5a-ef31-4046-8f9b-e3488ee85e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737117296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2737117296
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3633720506
Short name T874
Test name
Test status
Simulation time 181771029983 ps
CPU time 156.77 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:09:52 PM PDT 24
Peak memory 209340 kb
Host smart-cda93df2-41e9-467f-8eec-c7eeb5a0aca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633720506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3633720506
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.3761676382
Short name T1136
Test name
Test status
Simulation time 18280496226 ps
CPU time 259.37 seconds
Started Apr 04 02:07:24 PM PDT 24
Finished Apr 04 02:11:44 PM PDT 24
Peak memory 200776 kb
Host smart-6fee301f-50e6-47a6-b3ed-88f83ef10167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761676382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3761676382
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3527266966
Short name T1040
Test name
Test status
Simulation time 2848560596 ps
CPU time 5.25 seconds
Started Apr 04 02:07:24 PM PDT 24
Finished Apr 04 02:07:30 PM PDT 24
Peak memory 198824 kb
Host smart-27b3a00f-9ad8-4edc-bc43-6244ed032e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527266966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3527266966
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2240700876
Short name T1107
Test name
Test status
Simulation time 32114306191 ps
CPU time 26.68 seconds
Started Apr 04 02:07:11 PM PDT 24
Finished Apr 04 02:07:38 PM PDT 24
Peak memory 200712 kb
Host smart-edaabf9e-a227-4dcb-abda-097ed4d145a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240700876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2240700876
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1794428211
Short name T376
Test name
Test status
Simulation time 2486866969 ps
CPU time 2.7 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:18 PM PDT 24
Peak memory 196932 kb
Host smart-91350f3c-a080-40b2-a838-2293e0486ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794428211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1794428211
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3342147
Short name T885
Test name
Test status
Simulation time 444885118 ps
CPU time 2.06 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:16 PM PDT 24
Peak memory 199488 kb
Host smart-68f59d73-af88-4b81-a1fc-dc2a66f9b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3342147
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1414504016
Short name T749
Test name
Test status
Simulation time 470523998226 ps
CPU time 2088 seconds
Started Apr 04 02:07:23 PM PDT 24
Finished Apr 04 02:42:12 PM PDT 24
Peak memory 209260 kb
Host smart-1b20ffd1-49e8-4723-9395-0752b651ca8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414504016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1414504016
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3326138637
Short name T753
Test name
Test status
Simulation time 42146446158 ps
CPU time 227.28 seconds
Started Apr 04 02:07:20 PM PDT 24
Finished Apr 04 02:11:08 PM PDT 24
Peak memory 209164 kb
Host smart-6e2c73f1-49de-4bee-a0a9-d8b9a4a73529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326138637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3326138637
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.720006796
Short name T663
Test name
Test status
Simulation time 712141732 ps
CPU time 2.28 seconds
Started Apr 04 02:07:14 PM PDT 24
Finished Apr 04 02:07:16 PM PDT 24
Peak memory 199412 kb
Host smart-82259792-1db4-43bc-b78f-95b418528e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720006796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.720006796
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.4157791823
Short name T740
Test name
Test status
Simulation time 144248712308 ps
CPU time 17.72 seconds
Started Apr 04 02:07:16 PM PDT 24
Finished Apr 04 02:07:36 PM PDT 24
Peak memory 200796 kb
Host smart-506c2c49-2f2b-40c4-b985-de08e835538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157791823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.4157791823
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1529668161
Short name T940
Test name
Test status
Simulation time 47969457110 ps
CPU time 77.83 seconds
Started Apr 04 02:13:29 PM PDT 24
Finished Apr 04 02:14:48 PM PDT 24
Peak memory 200828 kb
Host smart-86bca315-0194-43c9-9f38-f82fa7de73f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529668161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1529668161
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1470093374
Short name T1126
Test name
Test status
Simulation time 211443763267 ps
CPU time 52.63 seconds
Started Apr 04 02:13:30 PM PDT 24
Finished Apr 04 02:14:23 PM PDT 24
Peak memory 200696 kb
Host smart-e28e892b-d00c-4671-9f2b-577cb39954bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470093374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1470093374
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3621662715
Short name T1087
Test name
Test status
Simulation time 17944412749 ps
CPU time 37.38 seconds
Started Apr 04 02:13:29 PM PDT 24
Finished Apr 04 02:14:07 PM PDT 24
Peak memory 200828 kb
Host smart-418b92ac-0f4a-4418-835b-4f32f7c9b79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621662715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3621662715
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4074556078
Short name T739
Test name
Test status
Simulation time 52010696447 ps
CPU time 77.98 seconds
Started Apr 04 02:13:42 PM PDT 24
Finished Apr 04 02:15:00 PM PDT 24
Peak memory 200736 kb
Host smart-959f1269-c3f5-4d68-8ad7-bc6bea339667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074556078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4074556078
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2725378030
Short name T643
Test name
Test status
Simulation time 88163053557 ps
CPU time 66.89 seconds
Started Apr 04 02:13:43 PM PDT 24
Finished Apr 04 02:14:50 PM PDT 24
Peak memory 200844 kb
Host smart-0090f835-93e4-4a50-b47d-73e9c45562de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725378030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2725378030
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3669060399
Short name T117
Test name
Test status
Simulation time 50211212156 ps
CPU time 54.44 seconds
Started Apr 04 02:13:40 PM PDT 24
Finished Apr 04 02:14:35 PM PDT 24
Peak memory 200888 kb
Host smart-73b654cf-f87f-4d2c-928f-acb75781aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669060399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3669060399
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3760082527
Short name T854
Test name
Test status
Simulation time 31827027436 ps
CPU time 57.17 seconds
Started Apr 04 02:13:42 PM PDT 24
Finished Apr 04 02:14:40 PM PDT 24
Peak memory 200904 kb
Host smart-9880d586-9fb7-4454-8db4-57a189bed56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760082527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3760082527
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3537861977
Short name T1005
Test name
Test status
Simulation time 75162574 ps
CPU time 0.55 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:07:35 PM PDT 24
Peak memory 196164 kb
Host smart-d9ba40fd-871b-46f1-a7b8-5f27265d3917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537861977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3537861977
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1249793735
Short name T1118
Test name
Test status
Simulation time 133186210415 ps
CPU time 23.42 seconds
Started Apr 04 02:07:22 PM PDT 24
Finished Apr 04 02:07:45 PM PDT 24
Peak memory 200808 kb
Host smart-8926abcb-5f64-4813-ac01-2c7c656582fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249793735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1249793735
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3809316260
Short name T1014
Test name
Test status
Simulation time 22382007216 ps
CPU time 39.4 seconds
Started Apr 04 02:07:21 PM PDT 24
Finished Apr 04 02:08:01 PM PDT 24
Peak memory 200904 kb
Host smart-e28f417d-dd2d-45ad-a592-eac0be704b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809316260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3809316260
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.1629960169
Short name T555
Test name
Test status
Simulation time 56468287311 ps
CPU time 24.74 seconds
Started Apr 04 02:07:25 PM PDT 24
Finished Apr 04 02:07:50 PM PDT 24
Peak memory 200888 kb
Host smart-8684be82-aa61-4546-aa8e-096e942655c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629960169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1629960169
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1854100470
Short name T813
Test name
Test status
Simulation time 87166695009 ps
CPU time 258.12 seconds
Started Apr 04 02:07:35 PM PDT 24
Finished Apr 04 02:11:54 PM PDT 24
Peak memory 200704 kb
Host smart-a6ff817f-9b12-485e-875f-2e61787e757c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854100470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1854100470
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3280503944
Short name T368
Test name
Test status
Simulation time 12482077780 ps
CPU time 5.41 seconds
Started Apr 04 02:07:23 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200672 kb
Host smart-8c283d86-fc5c-4709-b990-674a6e05e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280503944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3280503944
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1779285852
Short name T1117
Test name
Test status
Simulation time 10301751426 ps
CPU time 8.12 seconds
Started Apr 04 02:07:22 PM PDT 24
Finished Apr 04 02:07:30 PM PDT 24
Peak memory 196892 kb
Host smart-17a56eb2-f46b-437f-80e5-5a3ab9d1a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779285852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1779285852
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2750456395
Short name T1047
Test name
Test status
Simulation time 5827165330 ps
CPU time 167.16 seconds
Started Apr 04 02:07:36 PM PDT 24
Finished Apr 04 02:10:24 PM PDT 24
Peak memory 200804 kb
Host smart-3b7ca019-8519-40cf-9545-423593dc8da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750456395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2750456395
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1320018392
Short name T776
Test name
Test status
Simulation time 7474140458 ps
CPU time 61.58 seconds
Started Apr 04 02:07:24 PM PDT 24
Finished Apr 04 02:08:27 PM PDT 24
Peak memory 200040 kb
Host smart-a86a369c-771a-4d48-a883-c7fe876b66d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320018392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1320018392
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2086529471
Short name T605
Test name
Test status
Simulation time 39240966825 ps
CPU time 34.93 seconds
Started Apr 04 02:07:25 PM PDT 24
Finished Apr 04 02:08:00 PM PDT 24
Peak memory 199580 kb
Host smart-1a719d45-493d-4c07-803a-d106ec773400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086529471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2086529471
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.400176787
Short name T352
Test name
Test status
Simulation time 844607956 ps
CPU time 0.96 seconds
Started Apr 04 02:07:25 PM PDT 24
Finished Apr 04 02:07:26 PM PDT 24
Peak memory 196240 kb
Host smart-3887b7f2-1592-4e7e-8674-92730ab60e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400176787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.400176787
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1652288403
Short name T534
Test name
Test status
Simulation time 732137490 ps
CPU time 1.42 seconds
Started Apr 04 02:07:24 PM PDT 24
Finished Apr 04 02:07:26 PM PDT 24
Peak memory 199028 kb
Host smart-81235232-90c3-477e-bbf5-87f221f49129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652288403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1652288403
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2141591629
Short name T155
Test name
Test status
Simulation time 93260451981 ps
CPU time 32.39 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 200824 kb
Host smart-59545640-ae4e-49c8-bef2-d9ef5d2a838f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141591629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2141591629
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1712137788
Short name T283
Test name
Test status
Simulation time 1181231175 ps
CPU time 2.28 seconds
Started Apr 04 02:07:22 PM PDT 24
Finished Apr 04 02:07:24 PM PDT 24
Peak memory 198984 kb
Host smart-1ca87589-90c5-4bcb-97eb-0e9e14e82029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712137788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1712137788
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3360057578
Short name T604
Test name
Test status
Simulation time 81025986451 ps
CPU time 75.86 seconds
Started Apr 04 02:07:25 PM PDT 24
Finished Apr 04 02:08:41 PM PDT 24
Peak memory 200876 kb
Host smart-729eea00-c125-4af8-bda8-46f4c75fcbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360057578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3360057578
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.496117918
Short name T719
Test name
Test status
Simulation time 95800566271 ps
CPU time 14.51 seconds
Started Apr 04 02:13:44 PM PDT 24
Finished Apr 04 02:13:59 PM PDT 24
Peak memory 200888 kb
Host smart-550ebbd0-f850-46f3-8b64-a9408b84bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496117918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.496117918
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2115633588
Short name T974
Test name
Test status
Simulation time 114505982206 ps
CPU time 43.58 seconds
Started Apr 04 02:13:43 PM PDT 24
Finished Apr 04 02:14:26 PM PDT 24
Peak memory 200860 kb
Host smart-7b1530b2-7b4a-48a9-9f8e-66dafee60095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115633588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2115633588
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4288451684
Short name T817
Test name
Test status
Simulation time 26650827102 ps
CPU time 67.42 seconds
Started Apr 04 02:13:42 PM PDT 24
Finished Apr 04 02:14:49 PM PDT 24
Peak memory 200828 kb
Host smart-55c98fc8-b8d9-4936-ab2a-62f719a017ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288451684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4288451684
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3767189766
Short name T714
Test name
Test status
Simulation time 175793653370 ps
CPU time 70.5 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:15:04 PM PDT 24
Peak memory 200856 kb
Host smart-1092bef5-2d0d-45ed-8a62-d7c7e9856fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767189766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3767189766
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1431928675
Short name T768
Test name
Test status
Simulation time 232968148700 ps
CPU time 43.88 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:37 PM PDT 24
Peak memory 200836 kb
Host smart-fe552e41-96fe-4391-aac7-694cf4ecb1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431928675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1431928675
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2479648208
Short name T748
Test name
Test status
Simulation time 131145019204 ps
CPU time 15.8 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:14:10 PM PDT 24
Peak memory 200880 kb
Host smart-ed000652-0ab8-4a06-8c30-fc4b52a98018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479648208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2479648208
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2767004602
Short name T588
Test name
Test status
Simulation time 30355879341 ps
CPU time 51.94 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:45 PM PDT 24
Peak memory 200764 kb
Host smart-df5496e4-4603-4d9b-af19-7084f26027ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767004602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2767004602
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3356617484
Short name T225
Test name
Test status
Simulation time 42256479993 ps
CPU time 18.1 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:14:13 PM PDT 24
Peak memory 200876 kb
Host smart-ae8666f4-5ab1-4d41-bad6-b9dce51cb421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356617484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3356617484
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.147258521
Short name T650
Test name
Test status
Simulation time 49375893462 ps
CPU time 25.27 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:18 PM PDT 24
Peak memory 200744 kb
Host smart-a704e17c-c072-49e2-a2a4-265468f2c577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147258521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.147258521
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1652483027
Short name T686
Test name
Test status
Simulation time 15104846690 ps
CPU time 23.06 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:16 PM PDT 24
Peak memory 200488 kb
Host smart-981d91d4-4c00-49be-bc53-2d56a1d3451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652483027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1652483027
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2974525336
Short name T380
Test name
Test status
Simulation time 46711812 ps
CPU time 0.56 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:07:35 PM PDT 24
Peak memory 196244 kb
Host smart-88fb8dba-c936-4b02-90d1-8e5827a048fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974525336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2974525336
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3236819320
Short name T610
Test name
Test status
Simulation time 230518729272 ps
CPU time 77.64 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:08:52 PM PDT 24
Peak memory 200856 kb
Host smart-243d5ec6-d53f-43a9-a3fc-052f8ed43cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236819320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3236819320
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1268944942
Short name T595
Test name
Test status
Simulation time 21856853516 ps
CPU time 19.48 seconds
Started Apr 04 02:07:35 PM PDT 24
Finished Apr 04 02:07:55 PM PDT 24
Peak memory 200708 kb
Host smart-da11aebd-d96e-4cab-bcbb-341e9806cc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268944942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1268944942
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1806164959
Short name T110
Test name
Test status
Simulation time 59493527980 ps
CPU time 35.25 seconds
Started Apr 04 02:07:36 PM PDT 24
Finished Apr 04 02:08:11 PM PDT 24
Peak memory 200720 kb
Host smart-26861fdb-acd6-44a0-96c7-956734b51e76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806164959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1806164959
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3072896672
Short name T101
Test name
Test status
Simulation time 185358219268 ps
CPU time 368.81 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:13:44 PM PDT 24
Peak memory 200780 kb
Host smart-475dc347-4ef3-4bff-8347-1af17a491fc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072896672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3072896672
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3888106975
Short name T936
Test name
Test status
Simulation time 5333022792 ps
CPU time 13.7 seconds
Started Apr 04 02:07:35 PM PDT 24
Finished Apr 04 02:07:49 PM PDT 24
Peak memory 200660 kb
Host smart-f089f0f0-e2fb-444c-b34e-2d3caed9be03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888106975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3888106975
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.1965005549
Short name T958
Test name
Test status
Simulation time 86845256714 ps
CPU time 79.12 seconds
Started Apr 04 02:07:36 PM PDT 24
Finished Apr 04 02:08:55 PM PDT 24
Peak memory 200552 kb
Host smart-04b894f9-a878-4bf8-93dd-b92d02872d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965005549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1965005549
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.439012993
Short name T252
Test name
Test status
Simulation time 13738041833 ps
CPU time 666.56 seconds
Started Apr 04 02:07:37 PM PDT 24
Finished Apr 04 02:18:44 PM PDT 24
Peak memory 200856 kb
Host smart-427ee420-1845-440b-a096-37c934aef210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439012993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.439012993
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.743483030
Short name T1129
Test name
Test status
Simulation time 2715276778 ps
CPU time 22.5 seconds
Started Apr 04 02:07:37 PM PDT 24
Finished Apr 04 02:08:00 PM PDT 24
Peak memory 199136 kb
Host smart-f5771eda-b749-4cf2-9e35-36ebdd068e82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743483030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.743483030
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1575668505
Short name T63
Test name
Test status
Simulation time 8609437915 ps
CPU time 4.95 seconds
Started Apr 04 02:07:37 PM PDT 24
Finished Apr 04 02:07:42 PM PDT 24
Peak memory 200892 kb
Host smart-ca731d70-3168-4410-a15a-9831b48dfad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575668505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1575668505
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2559419158
Short name T853
Test name
Test status
Simulation time 2922342715 ps
CPU time 1.69 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:07:36 PM PDT 24
Peak memory 196908 kb
Host smart-32c55dfb-e8c9-4dc8-8217-e1a72a7945cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559419158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2559419158
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2697187804
Short name T1122
Test name
Test status
Simulation time 6053789937 ps
CPU time 16.26 seconds
Started Apr 04 02:07:37 PM PDT 24
Finished Apr 04 02:07:53 PM PDT 24
Peak memory 200652 kb
Host smart-090d3e04-a85d-48c7-b7bf-8fa808ed8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697187804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2697187804
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2807165560
Short name T542
Test name
Test status
Simulation time 237135147635 ps
CPU time 114.15 seconds
Started Apr 04 02:07:33 PM PDT 24
Finished Apr 04 02:09:28 PM PDT 24
Peak memory 200860 kb
Host smart-4784ec47-93bb-4b57-b5d9-4b1b7bf79f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807165560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2807165560
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3203477630
Short name T53
Test name
Test status
Simulation time 218869476570 ps
CPU time 681.62 seconds
Started Apr 04 02:07:33 PM PDT 24
Finished Apr 04 02:18:55 PM PDT 24
Peak memory 217452 kb
Host smart-aa04a6df-062a-43cc-818e-d14b2f500389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203477630 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3203477630
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.631296817
Short name T705
Test name
Test status
Simulation time 1712679668 ps
CPU time 1.96 seconds
Started Apr 04 02:07:36 PM PDT 24
Finished Apr 04 02:07:39 PM PDT 24
Peak memory 199172 kb
Host smart-a362a507-bdd7-4edb-bddf-6daf4ff0b3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631296817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.631296817
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2992407627
Short name T1163
Test name
Test status
Simulation time 41347218758 ps
CPU time 77.58 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:08:52 PM PDT 24
Peak memory 200896 kb
Host smart-8c3e1d65-c9ea-43b4-a5ab-d78e9ebe27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992407627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2992407627
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.62043982
Short name T304
Test name
Test status
Simulation time 29301234290 ps
CPU time 23.13 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:14:18 PM PDT 24
Peak memory 200840 kb
Host smart-544e966a-57fe-4e06-9427-09496717d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62043982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.62043982
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2233310018
Short name T647
Test name
Test status
Simulation time 13901741992 ps
CPU time 22.86 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:16 PM PDT 24
Peak memory 200912 kb
Host smart-9657c91e-9090-4c93-be00-efd2e9c9b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233310018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2233310018
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1018799171
Short name T205
Test name
Test status
Simulation time 71564546532 ps
CPU time 35.9 seconds
Started Apr 04 02:13:54 PM PDT 24
Finished Apr 04 02:14:31 PM PDT 24
Peak memory 200784 kb
Host smart-47eb0a07-d68e-4371-9db6-44c9df98f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018799171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1018799171
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2099227933
Short name T293
Test name
Test status
Simulation time 18767332679 ps
CPU time 16.57 seconds
Started Apr 04 02:13:55 PM PDT 24
Finished Apr 04 02:14:12 PM PDT 24
Peak memory 200732 kb
Host smart-2d16a02d-6691-48a0-903d-fb7d6b3a3fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099227933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2099227933
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3538568031
Short name T233
Test name
Test status
Simulation time 67384904161 ps
CPU time 26.44 seconds
Started Apr 04 02:13:51 PM PDT 24
Finished Apr 04 02:14:17 PM PDT 24
Peak memory 200792 kb
Host smart-777d7d5d-7799-42a1-8553-269c33bec2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538568031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3538568031
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.651424734
Short name T434
Test name
Test status
Simulation time 11043932846 ps
CPU time 18.09 seconds
Started Apr 04 02:13:53 PM PDT 24
Finished Apr 04 02:14:11 PM PDT 24
Peak memory 200796 kb
Host smart-53bd1e03-46ac-4c11-b806-fdaad6d58327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651424734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.651424734
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4146393951
Short name T829
Test name
Test status
Simulation time 53705162056 ps
CPU time 24.29 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:14:32 PM PDT 24
Peak memory 200868 kb
Host smart-af342f88-f05a-4be9-b2ee-b4ce27ad716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146393951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4146393951
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3148947299
Short name T333
Test name
Test status
Simulation time 53126661 ps
CPU time 0.53 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:07:48 PM PDT 24
Peak memory 195676 kb
Host smart-3b7c8096-f300-4580-b809-1c3b584a86ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148947299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3148947299
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3404535462
Short name T860
Test name
Test status
Simulation time 39529664959 ps
CPU time 41 seconds
Started Apr 04 02:07:39 PM PDT 24
Finished Apr 04 02:08:20 PM PDT 24
Peak memory 200836 kb
Host smart-a46a00d8-9399-4509-a885-1b5494172971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404535462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3404535462
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1400162437
Short name T797
Test name
Test status
Simulation time 21777846677 ps
CPU time 30.96 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:08:18 PM PDT 24
Peak memory 199948 kb
Host smart-d918c10c-269d-467a-b977-ed84eb661243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400162437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1400162437
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1296543289
Short name T187
Test name
Test status
Simulation time 108846338023 ps
CPU time 46.16 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:08:33 PM PDT 24
Peak memory 200688 kb
Host smart-1a621c1b-612a-4274-985d-70b2ea1ace75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296543289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1296543289
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3866672941
Short name T450
Test name
Test status
Simulation time 50224384651 ps
CPU time 20.14 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 199968 kb
Host smart-c3c1bbe2-8ded-4c4e-a607-a6ad4786e040
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866672941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3866672941
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3784561475
Short name T300
Test name
Test status
Simulation time 127258050449 ps
CPU time 705.27 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:19:34 PM PDT 24
Peak memory 200868 kb
Host smart-fd0b07c4-dc52-4589-a329-50a41ad7b657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784561475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3784561475
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1384470433
Short name T576
Test name
Test status
Simulation time 12801952467 ps
CPU time 10.29 seconds
Started Apr 04 02:07:43 PM PDT 24
Finished Apr 04 02:07:53 PM PDT 24
Peak memory 200768 kb
Host smart-30887351-355c-4de3-b43d-969f966fefff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384470433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1384470433
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4142914932
Short name T62
Test name
Test status
Simulation time 17218300582 ps
CPU time 15.61 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:08:03 PM PDT 24
Peak memory 197460 kb
Host smart-a4c59e93-580a-41fc-9bf9-50a378f70fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142914932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4142914932
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2145482527
Short name T932
Test name
Test status
Simulation time 14463054744 ps
CPU time 801.67 seconds
Started Apr 04 02:07:47 PM PDT 24
Finished Apr 04 02:21:09 PM PDT 24
Peak memory 200904 kb
Host smart-8cd84bb0-a4f9-40e0-a89a-eb424705a161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2145482527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2145482527
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.4035622131
Short name T433
Test name
Test status
Simulation time 6028662864 ps
CPU time 50.41 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:08:38 PM PDT 24
Peak memory 200112 kb
Host smart-95053d45-8ead-48cf-b3e8-7c57cb53dc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035622131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4035622131
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.365631160
Short name T562
Test name
Test status
Simulation time 32503870930 ps
CPU time 63.83 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:08:51 PM PDT 24
Peak memory 200836 kb
Host smart-9a166615-55de-4925-b395-33acdf908134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365631160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.365631160
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.699637244
Short name T692
Test name
Test status
Simulation time 4519292118 ps
CPU time 8.45 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:07:56 PM PDT 24
Peak memory 196896 kb
Host smart-da6741d4-a99d-4853-b274-9e345262da5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699637244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.699637244
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2577910944
Short name T421
Test name
Test status
Simulation time 563257969 ps
CPU time 2.46 seconds
Started Apr 04 02:07:34 PM PDT 24
Finished Apr 04 02:07:37 PM PDT 24
Peak memory 200360 kb
Host smart-01ea7ed2-d216-4459-bf3a-a028fc0a6ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577910944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2577910944
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1388928263
Short name T680
Test name
Test status
Simulation time 227395958638 ps
CPU time 441.74 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:15:09 PM PDT 24
Peak memory 200796 kb
Host smart-14752065-e882-499b-9bdf-244c08c52446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388928263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1388928263
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.597200016
Short name T393
Test name
Test status
Simulation time 290525680820 ps
CPU time 916.31 seconds
Started Apr 04 02:07:49 PM PDT 24
Finished Apr 04 02:23:06 PM PDT 24
Peak memory 225688 kb
Host smart-a9de2e67-9277-4fa4-a86d-44a970812bf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597200016 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.597200016
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3252113079
Short name T957
Test name
Test status
Simulation time 1969293960 ps
CPU time 1.82 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:07:49 PM PDT 24
Peak memory 199236 kb
Host smart-66ab69e9-7d97-4299-9032-52d699ceeed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252113079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3252113079
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2459681652
Short name T729
Test name
Test status
Simulation time 53049773676 ps
CPU time 20.35 seconds
Started Apr 04 02:07:39 PM PDT 24
Finished Apr 04 02:08:00 PM PDT 24
Peak memory 200812 kb
Host smart-105622c3-a758-4327-b95d-8a6afc468bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459681652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2459681652
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2694528406
Short name T1177
Test name
Test status
Simulation time 145030345971 ps
CPU time 225.95 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:17:54 PM PDT 24
Peak memory 200776 kb
Host smart-ee5781ea-4088-4150-b3b0-e6bea46e9755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694528406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2694528406
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1976646550
Short name T956
Test name
Test status
Simulation time 249417142225 ps
CPU time 453.78 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:21:42 PM PDT 24
Peak memory 200900 kb
Host smart-b57c8ddb-2740-4720-a998-4cac015612c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976646550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1976646550
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.16998796
Short name T223
Test name
Test status
Simulation time 46140699443 ps
CPU time 135.01 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:16:23 PM PDT 24
Peak memory 200840 kb
Host smart-45a63838-d9e5-4479-99be-c24529a28c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16998796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.16998796
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1844085711
Short name T189
Test name
Test status
Simulation time 39758420906 ps
CPU time 16.94 seconds
Started Apr 04 02:14:09 PM PDT 24
Finished Apr 04 02:14:26 PM PDT 24
Peak memory 200900 kb
Host smart-4c00b481-dded-4da3-b1b7-0c441c4020de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844085711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1844085711
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.278990882
Short name T119
Test name
Test status
Simulation time 16877063964 ps
CPU time 23.03 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:14:30 PM PDT 24
Peak memory 200644 kb
Host smart-c548a3fb-2f37-4373-81b0-81c27b0e05ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278990882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.278990882
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3149518236
Short name T884
Test name
Test status
Simulation time 136440489732 ps
CPU time 59.82 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:15:06 PM PDT 24
Peak memory 200772 kb
Host smart-57066536-ba53-4f63-ade9-ff520549b5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149518236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3149518236
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.359240934
Short name T138
Test name
Test status
Simulation time 28016770652 ps
CPU time 13.34 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:14:21 PM PDT 24
Peak memory 200756 kb
Host smart-499d91a8-84a5-4a75-af12-7c118309e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359240934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.359240934
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2363852834
Short name T28
Test name
Test status
Simulation time 13395210 ps
CPU time 0.57 seconds
Started Apr 04 02:08:00 PM PDT 24
Finished Apr 04 02:08:01 PM PDT 24
Peak memory 195176 kb
Host smart-ab4cf734-85e0-450b-9210-e3db671c348b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363852834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2363852834
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3265593130
Short name T1094
Test name
Test status
Simulation time 45000356482 ps
CPU time 98.21 seconds
Started Apr 04 02:07:51 PM PDT 24
Finished Apr 04 02:09:29 PM PDT 24
Peak memory 200784 kb
Host smart-6d0aaa12-19d5-466c-abd8-c04c4980740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265593130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3265593130
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2420545997
Short name T39
Test name
Test status
Simulation time 85306721080 ps
CPU time 37.23 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:08:24 PM PDT 24
Peak memory 200896 kb
Host smart-a2fbd5ae-e102-48a3-b6a1-af972820d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420545997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2420545997
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.1507460059
Short name T558
Test name
Test status
Simulation time 54835247757 ps
CPU time 96.48 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:09:24 PM PDT 24
Peak memory 200936 kb
Host smart-556ba08b-ae09-48b5-9f2d-22c81a244611
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507460059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1507460059
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.667238037
Short name T898
Test name
Test status
Simulation time 104844545316 ps
CPU time 662.04 seconds
Started Apr 04 02:07:44 PM PDT 24
Finished Apr 04 02:18:49 PM PDT 24
Peak memory 200800 kb
Host smart-f84756e1-194d-43f0-a2a6-1ccd9ddd1fc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=667238037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.667238037
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2353045929
Short name T342
Test name
Test status
Simulation time 1765995096 ps
CPU time 3.32 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:07:51 PM PDT 24
Peak memory 196852 kb
Host smart-5c045e34-c644-4d04-8afd-068583daf973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353045929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2353045929
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3051773076
Short name T260
Test name
Test status
Simulation time 26891307578 ps
CPU time 24.34 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:08:13 PM PDT 24
Peak memory 199648 kb
Host smart-025eff92-e6bc-4c99-9941-c4dfa078fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051773076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3051773076
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1014720744
Short name T965
Test name
Test status
Simulation time 12000755249 ps
CPU time 170.15 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:10:38 PM PDT 24
Peak memory 200672 kb
Host smart-087bf6af-8fd8-4100-a75d-0eceeaee8fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014720744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1014720744
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4236400578
Short name T638
Test name
Test status
Simulation time 4459043085 ps
CPU time 37.85 seconds
Started Apr 04 02:07:47 PM PDT 24
Finished Apr 04 02:08:25 PM PDT 24
Peak memory 199124 kb
Host smart-6a173673-4c14-45a3-ab90-e14a16f8f507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236400578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4236400578
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2322071042
Short name T1091
Test name
Test status
Simulation time 51335524147 ps
CPU time 7.55 seconds
Started Apr 04 02:07:47 PM PDT 24
Finished Apr 04 02:07:55 PM PDT 24
Peak memory 200668 kb
Host smart-52046ef2-cc6a-4183-ba50-656cd46cbd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322071042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2322071042
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3997290900
Short name T565
Test name
Test status
Simulation time 2575264215 ps
CPU time 1 seconds
Started Apr 04 02:07:46 PM PDT 24
Finished Apr 04 02:07:49 PM PDT 24
Peak memory 196796 kb
Host smart-9551913c-ab38-4f5b-b82f-e27d8a46595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997290900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3997290900
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2002196504
Short name T765
Test name
Test status
Simulation time 5557691971 ps
CPU time 13.92 seconds
Started Apr 04 02:07:50 PM PDT 24
Finished Apr 04 02:08:04 PM PDT 24
Peak memory 200584 kb
Host smart-2c76a419-421b-4811-90df-931c328c989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002196504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2002196504
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3750854064
Short name T838
Test name
Test status
Simulation time 325702447337 ps
CPU time 525.72 seconds
Started Apr 04 02:08:01 PM PDT 24
Finished Apr 04 02:16:47 PM PDT 24
Peak memory 200564 kb
Host smart-ba41f333-b022-4f57-9c8e-c95cca3587ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750854064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3750854064
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1421952967
Short name T309
Test name
Test status
Simulation time 41887144669 ps
CPU time 217.59 seconds
Started Apr 04 02:07:45 PM PDT 24
Finished Apr 04 02:11:25 PM PDT 24
Peak memory 216860 kb
Host smart-40220100-d77a-465e-9e8a-fc9e6eca9872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421952967 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1421952967
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4116617933
Short name T1114
Test name
Test status
Simulation time 6176118130 ps
CPU time 25.25 seconds
Started Apr 04 02:07:51 PM PDT 24
Finished Apr 04 02:08:16 PM PDT 24
Peak memory 200692 kb
Host smart-5d8812b3-c4c8-421e-8d2c-d7c83c54fb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116617933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4116617933
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.879824693
Short name T966
Test name
Test status
Simulation time 73323563991 ps
CPU time 15.23 seconds
Started Apr 04 02:07:50 PM PDT 24
Finished Apr 04 02:08:06 PM PDT 24
Peak memory 200568 kb
Host smart-ce9082f5-ee55-4cbb-9efa-b05829fffc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879824693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.879824693
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.850611218
Short name T8
Test name
Test status
Simulation time 69753175654 ps
CPU time 28.86 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:14:35 PM PDT 24
Peak memory 200740 kb
Host smart-98d95f18-4657-4527-b707-8a45ac2ec4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850611218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.850611218
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2641567154
Short name T670
Test name
Test status
Simulation time 136065287696 ps
CPU time 40.09 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:14:48 PM PDT 24
Peak memory 200836 kb
Host smart-19628732-254d-46cc-9033-f28096b22e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641567154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2641567154
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3222700493
Short name T15
Test name
Test status
Simulation time 23715985521 ps
CPU time 16.73 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:14:25 PM PDT 24
Peak memory 200752 kb
Host smart-e461825f-fd6b-4bec-9c15-3b5ff653236f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222700493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3222700493
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1020734934
Short name T1075
Test name
Test status
Simulation time 38947832329 ps
CPU time 52.12 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:15:00 PM PDT 24
Peak memory 200832 kb
Host smart-0ce71adf-aeda-4401-9343-a0b587e8129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020734934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1020734934
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.162523503
Short name T612
Test name
Test status
Simulation time 32594434440 ps
CPU time 104.03 seconds
Started Apr 04 02:14:06 PM PDT 24
Finished Apr 04 02:15:51 PM PDT 24
Peak memory 200848 kb
Host smart-ea1a744c-a5e3-4dbd-8b97-091a4c8bab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162523503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.162523503
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3071675837
Short name T1151
Test name
Test status
Simulation time 12218880309 ps
CPU time 17.75 seconds
Started Apr 04 02:14:08 PM PDT 24
Finished Apr 04 02:14:25 PM PDT 24
Peak memory 200812 kb
Host smart-3aaece63-9e0b-4be9-99d9-ab7fd2861fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071675837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3071675837
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2105098041
Short name T532
Test name
Test status
Simulation time 7061410174 ps
CPU time 12.44 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:14:20 PM PDT 24
Peak memory 200700 kb
Host smart-802062b8-6962-4e7b-b446-96a528ceec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105098041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2105098041
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2472404175
Short name T214
Test name
Test status
Simulation time 91392010316 ps
CPU time 40.13 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:14:47 PM PDT 24
Peak memory 200712 kb
Host smart-d3ec6d94-de6a-4f9b-acc0-410afae174b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472404175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2472404175
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.43994147
Short name T1058
Test name
Test status
Simulation time 80357940 ps
CPU time 0.61 seconds
Started Apr 04 02:08:00 PM PDT 24
Finished Apr 04 02:08:01 PM PDT 24
Peak memory 195572 kb
Host smart-b18f0173-0490-49a7-a1cf-26153c493d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43994147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.43994147
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3445100206
Short name T834
Test name
Test status
Simulation time 282859463778 ps
CPU time 36.72 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:08:33 PM PDT 24
Peak memory 200736 kb
Host smart-42c35c4b-ddbc-4e7e-a547-fc25f74e0123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445100206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3445100206
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1424803506
Short name T481
Test name
Test status
Simulation time 26362837942 ps
CPU time 9.92 seconds
Started Apr 04 02:07:55 PM PDT 24
Finished Apr 04 02:08:05 PM PDT 24
Peak memory 200580 kb
Host smart-fe6fe8da-965c-4408-be2b-3b1cb17bc36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424803506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1424803506
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.210830401
Short name T836
Test name
Test status
Simulation time 123900611373 ps
CPU time 46.85 seconds
Started Apr 04 02:07:55 PM PDT 24
Finished Apr 04 02:08:42 PM PDT 24
Peak memory 200828 kb
Host smart-cc3e194f-765d-473a-84b2-552ef1938636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210830401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.210830401
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.522949523
Short name T425
Test name
Test status
Simulation time 25753409089 ps
CPU time 60.86 seconds
Started Apr 04 02:07:55 PM PDT 24
Finished Apr 04 02:08:57 PM PDT 24
Peak memory 200820 kb
Host smart-e4751eda-b4ad-4205-9e59-e1e2db3c7746
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522949523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.522949523
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2288526449
Short name T417
Test name
Test status
Simulation time 142792653808 ps
CPU time 1121.31 seconds
Started Apr 04 02:08:00 PM PDT 24
Finished Apr 04 02:26:42 PM PDT 24
Peak memory 200772 kb
Host smart-32cae3fb-3f16-4da8-ac57-e1d23953deaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2288526449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2288526449
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3850729572
Short name T672
Test name
Test status
Simulation time 63133424 ps
CPU time 0.97 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:07:57 PM PDT 24
Peak memory 198512 kb
Host smart-ac651054-870b-4fdc-9d39-eb8319939c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850729572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3850729572
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1978726291
Short name T743
Test name
Test status
Simulation time 195923700493 ps
CPU time 40.62 seconds
Started Apr 04 02:07:55 PM PDT 24
Finished Apr 04 02:08:36 PM PDT 24
Peak memory 200960 kb
Host smart-ca652000-c747-4f3a-bef7-6f6d56366289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978726291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1978726291
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.4110998581
Short name T1083
Test name
Test status
Simulation time 18807257398 ps
CPU time 750.89 seconds
Started Apr 04 02:08:01 PM PDT 24
Finished Apr 04 02:20:32 PM PDT 24
Peak memory 200508 kb
Host smart-58a8349e-eab5-4ab4-8647-e4b15774b56c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110998581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4110998581
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1579304812
Short name T587
Test name
Test status
Simulation time 5857301521 ps
CPU time 43.84 seconds
Started Apr 04 02:07:54 PM PDT 24
Finished Apr 04 02:08:39 PM PDT 24
Peak memory 198996 kb
Host smart-46e447ef-ab80-4d7f-9dc7-dc0c80188af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579304812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1579304812
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2166904169
Short name T381
Test name
Test status
Simulation time 98332409467 ps
CPU time 153.24 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:10:30 PM PDT 24
Peak memory 200772 kb
Host smart-c8c842f1-3295-4b91-be6b-5dcb436ace4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166904169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2166904169
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.4013669386
Short name T361
Test name
Test status
Simulation time 1640154833 ps
CPU time 1.19 seconds
Started Apr 04 02:07:54 PM PDT 24
Finished Apr 04 02:07:56 PM PDT 24
Peak memory 196240 kb
Host smart-2c0c9c2f-7e57-494c-b043-e2a8cf5df065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013669386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.4013669386
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1211003524
Short name T364
Test name
Test status
Simulation time 726240552 ps
CPU time 1.57 seconds
Started Apr 04 02:08:00 PM PDT 24
Finished Apr 04 02:08:01 PM PDT 24
Peak memory 199136 kb
Host smart-4cc2cc62-42da-40b6-a661-33e06f64f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211003524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1211003524
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2612638031
Short name T791
Test name
Test status
Simulation time 15922646388 ps
CPU time 368.99 seconds
Started Apr 04 02:08:00 PM PDT 24
Finished Apr 04 02:14:09 PM PDT 24
Peak memory 216376 kb
Host smart-c7ff4c5c-3b52-437c-8824-bea9c59efaec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612638031 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2612638031
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3436628134
Short name T655
Test name
Test status
Simulation time 7496544559 ps
CPU time 5.8 seconds
Started Apr 04 02:07:57 PM PDT 24
Finished Apr 04 02:08:03 PM PDT 24
Peak memory 200740 kb
Host smart-c8f80536-caf0-4a34-b871-9ce8f952152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436628134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3436628134
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2087056965
Short name T1109
Test name
Test status
Simulation time 26572343048 ps
CPU time 23.64 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:08:20 PM PDT 24
Peak memory 200860 kb
Host smart-638c06b2-2feb-464b-a28d-29ac498759b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087056965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2087056965
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.163857643
Short name T586
Test name
Test status
Simulation time 18625088049 ps
CPU time 9.89 seconds
Started Apr 04 02:14:07 PM PDT 24
Finished Apr 04 02:14:17 PM PDT 24
Peak memory 200884 kb
Host smart-bd450a2b-8e12-4884-a515-5e07eb133941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163857643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.163857643
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1420500534
Short name T46
Test name
Test status
Simulation time 52769539490 ps
CPU time 21.6 seconds
Started Apr 04 02:14:21 PM PDT 24
Finished Apr 04 02:14:43 PM PDT 24
Peak memory 200828 kb
Host smart-7a8ca052-6e48-4f56-8f37-a517663fcce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420500534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1420500534
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.871684822
Short name T793
Test name
Test status
Simulation time 85295802325 ps
CPU time 69.7 seconds
Started Apr 04 02:14:18 PM PDT 24
Finished Apr 04 02:15:28 PM PDT 24
Peak memory 200920 kb
Host smart-739cfe8a-569e-4bfd-9ea2-581ffa6b6b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871684822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.871684822
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3021040930
Short name T471
Test name
Test status
Simulation time 48291835555 ps
CPU time 88.87 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:15:49 PM PDT 24
Peak memory 200868 kb
Host smart-e3d27234-c159-4c65-8a54-a9a9b8a3a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021040930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3021040930
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.865984031
Short name T547
Test name
Test status
Simulation time 55850232620 ps
CPU time 28.17 seconds
Started Apr 04 02:14:19 PM PDT 24
Finished Apr 04 02:14:48 PM PDT 24
Peak memory 200900 kb
Host smart-7ac2f320-d9ed-41da-a9fc-bed6750b2bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865984031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.865984031
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3650787120
Short name T244
Test name
Test status
Simulation time 61172056428 ps
CPU time 25.12 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:14:46 PM PDT 24
Peak memory 200732 kb
Host smart-3a42bd44-d026-4b06-88c3-2c9e3b0b1aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650787120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3650787120
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3585425340
Short name T780
Test name
Test status
Simulation time 45650392489 ps
CPU time 77.86 seconds
Started Apr 04 02:14:18 PM PDT 24
Finished Apr 04 02:15:36 PM PDT 24
Peak memory 200900 kb
Host smart-309b931d-d903-426f-96f6-f6b5b8d09fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585425340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3585425340
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.248836390
Short name T490
Test name
Test status
Simulation time 207124485807 ps
CPU time 25.42 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:14:45 PM PDT 24
Peak memory 200800 kb
Host smart-5e45ef2a-787c-4953-8778-f85c012373e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248836390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.248836390
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3351631641
Short name T194
Test name
Test status
Simulation time 19465577192 ps
CPU time 35.58 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:14:56 PM PDT 24
Peak memory 200912 kb
Host smart-95075ca4-c791-446f-a1b8-40eafccaa525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351631641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3351631641
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.797292535
Short name T573
Test name
Test status
Simulation time 191135161578 ps
CPU time 72.03 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:15:32 PM PDT 24
Peak memory 200920 kb
Host smart-cf3f22fd-c1ae-41b6-8764-5c6fb2352d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797292535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.797292535
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.262082949
Short name T935
Test name
Test status
Simulation time 34791327 ps
CPU time 0.54 seconds
Started Apr 04 02:06:22 PM PDT 24
Finished Apr 04 02:06:23 PM PDT 24
Peak memory 195144 kb
Host smart-a52c31c5-d78d-4ec9-bb4e-13fdfc9d312a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262082949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.262082949
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.558351177
Short name T920
Test name
Test status
Simulation time 71496274137 ps
CPU time 56.39 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:06:59 PM PDT 24
Peak memory 200852 kb
Host smart-6f263e15-0b1c-414c-a401-3ad8430e7239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558351177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.558351177
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3367207658
Short name T955
Test name
Test status
Simulation time 72017699630 ps
CPU time 65.72 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:07:09 PM PDT 24
Peak memory 200752 kb
Host smart-6ccf81f8-099d-4744-8c51-c5c20ebf4c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367207658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3367207658
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3630418797
Short name T858
Test name
Test status
Simulation time 115279237309 ps
CPU time 22.38 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:06:24 PM PDT 24
Peak memory 199328 kb
Host smart-abfd410d-dee6-4917-9499-ed63c6d6f3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630418797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3630418797
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1715580612
Short name T750
Test name
Test status
Simulation time 12225549840 ps
CPU time 7.21 seconds
Started Apr 04 02:06:03 PM PDT 24
Finished Apr 04 02:06:10 PM PDT 24
Peak memory 200816 kb
Host smart-461cb914-12b3-4c37-aaa7-410a2a91cb8b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715580612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1715580612
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.282366339
Short name T1149
Test name
Test status
Simulation time 81368443635 ps
CPU time 647.53 seconds
Started Apr 04 02:06:13 PM PDT 24
Finished Apr 04 02:17:01 PM PDT 24
Peak memory 200888 kb
Host smart-3a05cd5c-437d-4410-9897-fd516bd4a921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282366339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.282366339
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1724653380
Short name T354
Test name
Test status
Simulation time 2410000467 ps
CPU time 2.51 seconds
Started Apr 04 02:06:04 PM PDT 24
Finished Apr 04 02:06:07 PM PDT 24
Peak memory 197216 kb
Host smart-78c1f867-afcf-42f9-96a9-2f9312fe7202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724653380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1724653380
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2607000689
Short name T448
Test name
Test status
Simulation time 118665100857 ps
CPU time 179.01 seconds
Started Apr 04 02:06:06 PM PDT 24
Finished Apr 04 02:09:05 PM PDT 24
Peak memory 201060 kb
Host smart-22ab1516-ab38-4a8f-b661-d6ada73f3bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607000689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2607000689
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1344745627
Short name T746
Test name
Test status
Simulation time 6573163646 ps
CPU time 412.53 seconds
Started Apr 04 02:06:11 PM PDT 24
Finished Apr 04 02:13:03 PM PDT 24
Peak memory 200848 kb
Host smart-c7d61b49-8cb0-4195-b5f7-a2c0e8e5fc11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1344745627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1344745627
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3885737451
Short name T1171
Test name
Test status
Simulation time 2553205616 ps
CPU time 4.84 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:06:07 PM PDT 24
Peak memory 199976 kb
Host smart-eeacc1fd-3610-4b88-80d4-8561bd3e072e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885737451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3885737451
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1795497955
Short name T616
Test name
Test status
Simulation time 137868360102 ps
CPU time 13.82 seconds
Started Apr 04 02:06:09 PM PDT 24
Finished Apr 04 02:06:23 PM PDT 24
Peak memory 199948 kb
Host smart-ae6486fd-060d-43ff-932f-2619a20efa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795497955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1795497955
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3270418440
Short name T1100
Test name
Test status
Simulation time 37012879069 ps
CPU time 4.7 seconds
Started Apr 04 02:06:04 PM PDT 24
Finished Apr 04 02:06:09 PM PDT 24
Peak memory 196884 kb
Host smart-23f8e30f-5243-4b9e-85cf-939da5734dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270418440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3270418440
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3742362656
Short name T91
Test name
Test status
Simulation time 241663990 ps
CPU time 0.76 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:06:15 PM PDT 24
Peak memory 219040 kb
Host smart-4efe48fd-2d8a-4aee-b35f-fae2a33fd557
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742362656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3742362656
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1194359524
Short name T801
Test name
Test status
Simulation time 5978321149 ps
CPU time 8.48 seconds
Started Apr 04 02:06:02 PM PDT 24
Finished Apr 04 02:06:11 PM PDT 24
Peak memory 200540 kb
Host smart-6e60211a-b615-48b1-b90e-6efbfd6a1394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194359524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1194359524
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.334665511
Short name T529
Test name
Test status
Simulation time 464214374830 ps
CPU time 338.45 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:11:58 PM PDT 24
Peak memory 200844 kb
Host smart-979f7344-58d9-4db6-95c7-de846acfb04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334665511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.334665511
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.82058900
Short name T939
Test name
Test status
Simulation time 189373680025 ps
CPU time 333.34 seconds
Started Apr 04 02:06:24 PM PDT 24
Finished Apr 04 02:11:57 PM PDT 24
Peak memory 225380 kb
Host smart-571643fd-ae2e-425b-b472-706301b8ccea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82058900 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.82058900
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.505190538
Short name T1034
Test name
Test status
Simulation time 1435236028 ps
CPU time 1.82 seconds
Started Apr 04 02:06:04 PM PDT 24
Finished Apr 04 02:06:06 PM PDT 24
Peak memory 199516 kb
Host smart-7bb8c64b-ba2e-459b-ba9b-de620f511443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505190538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.505190538
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2110175452
Short name T818
Test name
Test status
Simulation time 30744271698 ps
CPU time 28.44 seconds
Started Apr 04 02:06:04 PM PDT 24
Finished Apr 04 02:06:33 PM PDT 24
Peak memory 200928 kb
Host smart-912543fa-1762-48e4-ba3d-d06ff2eeee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110175452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2110175452
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.4257332061
Short name T733
Test name
Test status
Simulation time 31249486 ps
CPU time 0.53 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 196120 kb
Host smart-ab2255aa-461f-4d7c-8bcf-ce7956fe2052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257332061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.4257332061
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1558153316
Short name T274
Test name
Test status
Simulation time 106094490604 ps
CPU time 96.95 seconds
Started Apr 04 02:07:55 PM PDT 24
Finished Apr 04 02:09:32 PM PDT 24
Peak memory 200832 kb
Host smart-943e95cb-dc08-467e-9f6c-34b6d3546009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558153316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1558153316
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.656803903
Short name T752
Test name
Test status
Simulation time 75809194662 ps
CPU time 137.34 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 200800 kb
Host smart-e3153034-a382-4323-b2d9-14117b2f2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656803903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.656803903
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3240410668
Short name T193
Test name
Test status
Simulation time 39647322658 ps
CPU time 31.82 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:08:28 PM PDT 24
Peak memory 200868 kb
Host smart-86c983ec-df0d-4ab9-9e0f-071a1d353b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240410668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3240410668
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.468921423
Short name T882
Test name
Test status
Simulation time 100850310731 ps
CPU time 152.39 seconds
Started Apr 04 02:08:04 PM PDT 24
Finished Apr 04 02:10:36 PM PDT 24
Peak memory 196924 kb
Host smart-1fffc2e1-76e9-4c3d-9373-915df726de4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468921423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.468921423
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1907553918
Short name T648
Test name
Test status
Simulation time 118621827483 ps
CPU time 355.28 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:14:02 PM PDT 24
Peak memory 200716 kb
Host smart-3518167b-1b6d-41eb-9b84-bde22e9ade86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907553918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1907553918
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1635071476
Short name T821
Test name
Test status
Simulation time 132307376 ps
CPU time 0.65 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 196644 kb
Host smart-7950a2eb-0d2b-4fc5-b496-5a75d5d9193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635071476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1635071476
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3896301313
Short name T918
Test name
Test status
Simulation time 128722861123 ps
CPU time 57.63 seconds
Started Apr 04 02:08:04 PM PDT 24
Finished Apr 04 02:09:02 PM PDT 24
Peak memory 200656 kb
Host smart-17b5fabf-5b90-44bb-9c5b-a1d97646a391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896301313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3896301313
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3563517255
Short name T487
Test name
Test status
Simulation time 13418294608 ps
CPU time 654.62 seconds
Started Apr 04 02:08:05 PM PDT 24
Finished Apr 04 02:19:00 PM PDT 24
Peak memory 200832 kb
Host smart-37ed11f5-9256-48e0-82f6-98a8c2e90bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563517255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3563517255
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.821152751
Short name T609
Test name
Test status
Simulation time 3697820186 ps
CPU time 7.04 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:08:03 PM PDT 24
Peak memory 198912 kb
Host smart-ef6e641d-2496-495d-8abd-4d27080483c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821152751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.821152751
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3222776230
Short name T828
Test name
Test status
Simulation time 23975441962 ps
CPU time 41.38 seconds
Started Apr 04 02:08:05 PM PDT 24
Finished Apr 04 02:08:47 PM PDT 24
Peak memory 200708 kb
Host smart-55f42adf-94a6-4d1f-8252-2fefb3c4bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222776230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3222776230
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.48030515
Short name T811
Test name
Test status
Simulation time 45898147075 ps
CPU time 34.76 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:08:41 PM PDT 24
Peak memory 196888 kb
Host smart-68ef50a7-106b-4a8a-971d-6bda7ca81fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48030515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.48030515
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1362122883
Short name T908
Test name
Test status
Simulation time 6061742117 ps
CPU time 9.31 seconds
Started Apr 04 02:07:56 PM PDT 24
Finished Apr 04 02:08:06 PM PDT 24
Peak memory 200856 kb
Host smart-c9d80cf4-5ad2-4158-898a-95f64390894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362122883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1362122883
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1750284885
Short name T934
Test name
Test status
Simulation time 498582553426 ps
CPU time 637.54 seconds
Started Apr 04 02:08:07 PM PDT 24
Finished Apr 04 02:18:45 PM PDT 24
Peak memory 217340 kb
Host smart-a9fc664f-fd56-4e61-8aee-9ef4c1ab378f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750284885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1750284885
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2140431773
Short name T1179
Test name
Test status
Simulation time 803664307 ps
CPU time 1.57 seconds
Started Apr 04 02:08:05 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 199400 kb
Host smart-4a3dd297-dfef-4b9f-ab82-e42a54f9f6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140431773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2140431773
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3008727931
Short name T1054
Test name
Test status
Simulation time 139172403916 ps
CPU time 71.19 seconds
Started Apr 04 02:07:54 PM PDT 24
Finished Apr 04 02:09:05 PM PDT 24
Peak memory 200876 kb
Host smart-805388c9-5e72-4e69-bb71-d53cdf4b3fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008727931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3008727931
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.691772055
Short name T181
Test name
Test status
Simulation time 175242478657 ps
CPU time 47.1 seconds
Started Apr 04 02:14:18 PM PDT 24
Finished Apr 04 02:15:05 PM PDT 24
Peak memory 200792 kb
Host smart-1d5a2f6d-95da-439c-9c53-db9fcf3bd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691772055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.691772055
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2839082881
Short name T305
Test name
Test status
Simulation time 115813944007 ps
CPU time 102.52 seconds
Started Apr 04 02:14:18 PM PDT 24
Finished Apr 04 02:16:01 PM PDT 24
Peak memory 200860 kb
Host smart-de7bbb24-d089-43a0-ba31-96d9bf6cc423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839082881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2839082881
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2924089222
Short name T1141
Test name
Test status
Simulation time 34248723062 ps
CPU time 18.89 seconds
Started Apr 04 02:14:20 PM PDT 24
Finished Apr 04 02:14:39 PM PDT 24
Peak memory 200816 kb
Host smart-0738b4ab-2a52-4543-bb21-b6cef5d71b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924089222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2924089222
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1270598201
Short name T1097
Test name
Test status
Simulation time 137826842439 ps
CPU time 46.69 seconds
Started Apr 04 02:14:18 PM PDT 24
Finished Apr 04 02:15:05 PM PDT 24
Peak memory 200800 kb
Host smart-a7ddd4b4-2f7c-4e79-beb0-339f88d35602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270598201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1270598201
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3078677476
Short name T679
Test name
Test status
Simulation time 30079321472 ps
CPU time 49.98 seconds
Started Apr 04 02:14:19 PM PDT 24
Finished Apr 04 02:15:09 PM PDT 24
Peak memory 200816 kb
Host smart-0b92ae4d-9e33-4d52-af98-e3440e988a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078677476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3078677476
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.75139270
Short name T206
Test name
Test status
Simulation time 14920554551 ps
CPU time 15.94 seconds
Started Apr 04 02:14:31 PM PDT 24
Finished Apr 04 02:14:47 PM PDT 24
Peak memory 200456 kb
Host smart-71e78774-3061-4c5f-9cfc-d81fa0a5eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75139270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.75139270
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4185520007
Short name T988
Test name
Test status
Simulation time 146405090133 ps
CPU time 177.29 seconds
Started Apr 04 02:14:30 PM PDT 24
Finished Apr 04 02:17:27 PM PDT 24
Peak memory 200828 kb
Host smart-72f7134e-b283-49d3-a974-9555edbcf75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185520007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4185520007
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.214435183
Short name T524
Test name
Test status
Simulation time 132324324173 ps
CPU time 83.52 seconds
Started Apr 04 02:14:36 PM PDT 24
Finished Apr 04 02:16:00 PM PDT 24
Peak memory 200816 kb
Host smart-48b7c5e7-c66a-4e31-9f8c-3a828a8007ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214435183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.214435183
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3198363703
Short name T984
Test name
Test status
Simulation time 111656224935 ps
CPU time 63.86 seconds
Started Apr 04 02:14:31 PM PDT 24
Finished Apr 04 02:15:35 PM PDT 24
Peak memory 200796 kb
Host smart-5448319b-321a-4093-aeb6-4ced30a06178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198363703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3198363703
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2990608953
Short name T125
Test name
Test status
Simulation time 193919607061 ps
CPU time 110.99 seconds
Started Apr 04 02:14:34 PM PDT 24
Finished Apr 04 02:16:25 PM PDT 24
Peak memory 200712 kb
Host smart-07cd7fc2-954f-4d64-94cd-c982bf4039ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990608953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2990608953
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1170744043
Short name T708
Test name
Test status
Simulation time 37768454 ps
CPU time 0.53 seconds
Started Apr 04 02:08:20 PM PDT 24
Finished Apr 04 02:08:21 PM PDT 24
Peak memory 195680 kb
Host smart-e545d84f-ac12-4004-a309-efdbcd803668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170744043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1170744043
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1941940378
Short name T891
Test name
Test status
Simulation time 88678912079 ps
CPU time 102.4 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:09:48 PM PDT 24
Peak memory 200868 kb
Host smart-4f599ece-a676-488d-8af1-2091e7092a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941940378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1941940378
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3280580541
Short name T1165
Test name
Test status
Simulation time 172779313905 ps
CPU time 308.76 seconds
Started Apr 04 02:08:04 PM PDT 24
Finished Apr 04 02:13:12 PM PDT 24
Peak memory 200744 kb
Host smart-45768fa5-1c65-43b7-ad52-d234e020b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280580541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3280580541
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2242031541
Short name T13
Test name
Test status
Simulation time 202116265891 ps
CPU time 122.23 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:10:08 PM PDT 24
Peak memory 200844 kb
Host smart-a85856a8-19f3-4ad5-b494-e2f261ec88eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242031541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2242031541
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3018573157
Short name T499
Test name
Test status
Simulation time 9464689020 ps
CPU time 14.66 seconds
Started Apr 04 02:08:07 PM PDT 24
Finished Apr 04 02:08:22 PM PDT 24
Peak memory 197052 kb
Host smart-8b6c164d-8238-4666-a5f4-54e6e56db972
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018573157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3018573157
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1336299465
Short name T382
Test name
Test status
Simulation time 169123612398 ps
CPU time 1941.15 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:40:37 PM PDT 24
Peak memory 200904 kb
Host smart-a7b7723c-b0e2-42d7-b6e6-f993e3658dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1336299465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1336299465
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2289021333
Short name T340
Test name
Test status
Simulation time 11194989037 ps
CPU time 6.29 seconds
Started Apr 04 02:08:17 PM PDT 24
Finished Apr 04 02:08:23 PM PDT 24
Peak memory 199528 kb
Host smart-0fb7cc91-2e2f-401a-8fdb-26977a23f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289021333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2289021333
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.3049080178
Short name T976
Test name
Test status
Simulation time 163456618154 ps
CPU time 138.16 seconds
Started Apr 04 02:08:12 PM PDT 24
Finished Apr 04 02:10:30 PM PDT 24
Peak memory 200368 kb
Host smart-70c2feec-b532-47a8-a753-9b28a5dc1f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049080178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3049080178
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.3175009435
Short name T377
Test name
Test status
Simulation time 16028101902 ps
CPU time 481.44 seconds
Started Apr 04 02:08:18 PM PDT 24
Finished Apr 04 02:16:20 PM PDT 24
Peak memory 200836 kb
Host smart-15882585-e1b7-4db8-9517-eee55c835848
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175009435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3175009435
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3230323324
Short name T554
Test name
Test status
Simulation time 3710359401 ps
CPU time 33.87 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:08:40 PM PDT 24
Peak memory 198936 kb
Host smart-026aa595-8a6b-45bc-a763-cea80eb07456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230323324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3230323324
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4271073277
Short name T782
Test name
Test status
Simulation time 47155409903 ps
CPU time 83.52 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:09:39 PM PDT 24
Peak memory 200880 kb
Host smart-5bc76e5b-b1e3-4aaa-b570-11dedc94175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271073277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4271073277
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3762408525
Short name T787
Test name
Test status
Simulation time 23727708333 ps
CPU time 15.66 seconds
Started Apr 04 02:08:05 PM PDT 24
Finished Apr 04 02:08:21 PM PDT 24
Peak memory 197180 kb
Host smart-7f8d6e6f-3560-40db-8918-eae2d181fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762408525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3762408525
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.803229581
Short name T479
Test name
Test status
Simulation time 347807229 ps
CPU time 0.92 seconds
Started Apr 04 02:08:06 PM PDT 24
Finished Apr 04 02:08:07 PM PDT 24
Peak memory 199256 kb
Host smart-b023a3ca-e1e0-4af3-98ee-240eecdee205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803229581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.803229581
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2176091608
Short name T640
Test name
Test status
Simulation time 392628776904 ps
CPU time 72.14 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:09:28 PM PDT 24
Peak memory 200844 kb
Host smart-03e5947b-2879-471f-ae18-24f852c48b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176091608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2176091608
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2047788921
Short name T919
Test name
Test status
Simulation time 1233229604 ps
CPU time 1.26 seconds
Started Apr 04 02:08:19 PM PDT 24
Finished Apr 04 02:08:21 PM PDT 24
Peak memory 198948 kb
Host smart-318d2783-2f4a-4e9d-ad84-048d2cb28667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047788921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2047788921
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3672825464
Short name T458
Test name
Test status
Simulation time 45591102946 ps
CPU time 90.03 seconds
Started Apr 04 02:08:07 PM PDT 24
Finished Apr 04 02:09:37 PM PDT 24
Peak memory 200884 kb
Host smart-dc895ee9-8f90-4031-a778-3bf55e09b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672825464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3672825464
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.849065462
Short name T992
Test name
Test status
Simulation time 13754979098 ps
CPU time 23.54 seconds
Started Apr 04 02:14:36 PM PDT 24
Finished Apr 04 02:15:00 PM PDT 24
Peak memory 200820 kb
Host smart-0f82987f-2e8a-453c-a61d-3529e7994602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849065462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.849065462
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3054637881
Short name T975
Test name
Test status
Simulation time 102226215154 ps
CPU time 44.98 seconds
Started Apr 04 02:14:34 PM PDT 24
Finished Apr 04 02:15:20 PM PDT 24
Peak memory 200848 kb
Host smart-a6369ffe-9bd0-46e6-8c2e-c98eb901e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054637881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3054637881
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1394695965
Short name T1025
Test name
Test status
Simulation time 66628483528 ps
CPU time 92.28 seconds
Started Apr 04 02:14:30 PM PDT 24
Finished Apr 04 02:16:02 PM PDT 24
Peak memory 200872 kb
Host smart-5abd7044-d8b0-45af-ac27-70c233932135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394695965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1394695965
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4109908456
Short name T510
Test name
Test status
Simulation time 175006648463 ps
CPU time 116.6 seconds
Started Apr 04 02:14:35 PM PDT 24
Finished Apr 04 02:16:32 PM PDT 24
Peak memory 200888 kb
Host smart-b8dbe188-96df-4aeb-be75-4a47265abd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109908456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4109908456
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2257110946
Short name T276
Test name
Test status
Simulation time 9173100885 ps
CPU time 4.48 seconds
Started Apr 04 02:14:33 PM PDT 24
Finished Apr 04 02:14:38 PM PDT 24
Peak memory 200076 kb
Host smart-bd94015f-1a81-4247-afd9-d7a322c406fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257110946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2257110946
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1059313318
Short name T911
Test name
Test status
Simulation time 56637285066 ps
CPU time 26.27 seconds
Started Apr 04 02:14:32 PM PDT 24
Finished Apr 04 02:14:58 PM PDT 24
Peak memory 200828 kb
Host smart-afd75f00-fb39-4409-9c95-4c4b841413e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059313318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1059313318
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2241943824
Short name T843
Test name
Test status
Simulation time 113622663372 ps
CPU time 76 seconds
Started Apr 04 02:14:35 PM PDT 24
Finished Apr 04 02:15:52 PM PDT 24
Peak memory 200896 kb
Host smart-401b92f1-365a-4d72-a5f8-844a58fdec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241943824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2241943824
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4202031168
Short name T174
Test name
Test status
Simulation time 72521807482 ps
CPU time 28.59 seconds
Started Apr 04 02:14:34 PM PDT 24
Finished Apr 04 02:15:03 PM PDT 24
Peak memory 200804 kb
Host smart-365c4c51-aacd-4995-85c2-6ca26c729b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202031168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4202031168
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1466704016
Short name T812
Test name
Test status
Simulation time 20613267607 ps
CPU time 22.79 seconds
Started Apr 04 02:14:33 PM PDT 24
Finished Apr 04 02:14:56 PM PDT 24
Peak memory 201004 kb
Host smart-601d68ac-70d6-44a5-9303-d1d051e164bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466704016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1466704016
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.4046279863
Short name T328
Test name
Test status
Simulation time 21099901 ps
CPU time 0.54 seconds
Started Apr 04 02:08:18 PM PDT 24
Finished Apr 04 02:08:19 PM PDT 24
Peak memory 196184 kb
Host smart-40de6e13-311d-4660-840e-21d0d25b0b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046279863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.4046279863
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1083633415
Short name T446
Test name
Test status
Simulation time 80760877547 ps
CPU time 66.36 seconds
Started Apr 04 02:08:15 PM PDT 24
Finished Apr 04 02:09:22 PM PDT 24
Peak memory 200832 kb
Host smart-39672c0a-0835-44f8-9261-9e469810fc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083633415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1083633415
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4137634912
Short name T449
Test name
Test status
Simulation time 55906366388 ps
CPU time 89.45 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:09:46 PM PDT 24
Peak memory 200692 kb
Host smart-c78866b8-5a9f-4dea-ac6d-c15144384ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137634912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4137634912
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.114868597
Short name T546
Test name
Test status
Simulation time 110987388156 ps
CPU time 44.58 seconds
Started Apr 04 02:08:20 PM PDT 24
Finished Apr 04 02:09:05 PM PDT 24
Peak memory 200888 kb
Host smart-1218c80d-120f-44ac-b9f8-2c180b623277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114868597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.114868597
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2076826957
Short name T70
Test name
Test status
Simulation time 5258696459 ps
CPU time 1.91 seconds
Started Apr 04 02:08:19 PM PDT 24
Finished Apr 04 02:08:21 PM PDT 24
Peak memory 196756 kb
Host smart-887a2ada-3828-45eb-8a09-7a0f25c0d90f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076826957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2076826957
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1622693079
Short name T792
Test name
Test status
Simulation time 99636124007 ps
CPU time 784.31 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:21:20 PM PDT 24
Peak memory 200704 kb
Host smart-cc30244f-986e-403a-ae32-79e2a32e4c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622693079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1622693079
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3985981187
Short name T804
Test name
Test status
Simulation time 5176336857 ps
CPU time 11.76 seconds
Started Apr 04 02:08:19 PM PDT 24
Finished Apr 04 02:08:31 PM PDT 24
Peak memory 200560 kb
Host smart-7cf4f290-c9ca-4eed-829e-c4bad1484438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985981187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3985981187
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1401870748
Short name T1142
Test name
Test status
Simulation time 60211054316 ps
CPU time 126.91 seconds
Started Apr 04 02:08:21 PM PDT 24
Finished Apr 04 02:10:28 PM PDT 24
Peak memory 201064 kb
Host smart-fcb1d1e9-2a1a-430d-bb05-8584e7c04dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401870748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1401870748
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3577328545
Short name T1167
Test name
Test status
Simulation time 16603665390 ps
CPU time 485.61 seconds
Started Apr 04 02:08:18 PM PDT 24
Finished Apr 04 02:16:24 PM PDT 24
Peak memory 200812 kb
Host smart-a6cb54c4-9307-4a43-85ec-e6f6c3bc7ae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3577328545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3577328545
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3341669379
Short name T952
Test name
Test status
Simulation time 5951752881 ps
CPU time 57.28 seconds
Started Apr 04 02:08:15 PM PDT 24
Finished Apr 04 02:09:12 PM PDT 24
Peak memory 199020 kb
Host smart-598d7483-5846-4558-8063-d0b2bb1e472d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341669379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3341669379
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.961024374
Short name T1042
Test name
Test status
Simulation time 108589702477 ps
CPU time 73.37 seconds
Started Apr 04 02:08:17 PM PDT 24
Finished Apr 04 02:09:30 PM PDT 24
Peak memory 200888 kb
Host smart-3e043d6d-6c0f-4ac6-ab12-0c9e0419ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961024374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.961024374
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1073260051
Short name T889
Test name
Test status
Simulation time 35945637326 ps
CPU time 33.29 seconds
Started Apr 04 02:08:21 PM PDT 24
Finished Apr 04 02:08:54 PM PDT 24
Peak memory 196876 kb
Host smart-7141dda6-8302-4cc0-9928-ce7d22869a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073260051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1073260051
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3911454708
Short name T549
Test name
Test status
Simulation time 847211236 ps
CPU time 3.18 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:08:19 PM PDT 24
Peak memory 199660 kb
Host smart-e2ce7a00-f1fc-4ce0-b550-ffe7277f8c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911454708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3911454708
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1187142150
Short name T1071
Test name
Test status
Simulation time 201482032346 ps
CPU time 302.88 seconds
Started Apr 04 02:08:19 PM PDT 24
Finished Apr 04 02:13:22 PM PDT 24
Peak memory 200836 kb
Host smart-15ae13b8-4fcd-41f7-8a1f-247618a8d354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187142150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1187142150
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.134083622
Short name T568
Test name
Test status
Simulation time 80876668959 ps
CPU time 1006.02 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:25:03 PM PDT 24
Peak memory 225744 kb
Host smart-03989289-ece3-4f25-b29b-7da9aad80f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134083622 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.134083622
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.787034068
Short name T584
Test name
Test status
Simulation time 828364199 ps
CPU time 1.21 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:08:17 PM PDT 24
Peak memory 199044 kb
Host smart-2101ce1d-e49a-4ef9-bf88-7f742569ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787034068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.787034068
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3419050569
Short name T519
Test name
Test status
Simulation time 80259757729 ps
CPU time 76.21 seconds
Started Apr 04 02:08:17 PM PDT 24
Finished Apr 04 02:09:33 PM PDT 24
Peak memory 200860 kb
Host smart-a21442df-a6ed-4d5f-a7fb-e8e960af100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419050569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3419050569
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3639191866
Short name T196
Test name
Test status
Simulation time 256959806716 ps
CPU time 362.54 seconds
Started Apr 04 02:14:35 PM PDT 24
Finished Apr 04 02:20:38 PM PDT 24
Peak memory 200788 kb
Host smart-25a6a49e-32b0-47df-b6aa-5366c45f491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639191866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3639191866
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3499819333
Short name T928
Test name
Test status
Simulation time 105998724762 ps
CPU time 34.97 seconds
Started Apr 04 02:14:30 PM PDT 24
Finished Apr 04 02:15:05 PM PDT 24
Peak memory 200708 kb
Host smart-38b1fd7d-09cc-4e4c-bf1e-94c1e3fd0625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499819333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3499819333
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3992188696
Short name T1081
Test name
Test status
Simulation time 59545855539 ps
CPU time 99.79 seconds
Started Apr 04 02:14:30 PM PDT 24
Finished Apr 04 02:16:10 PM PDT 24
Peak memory 200844 kb
Host smart-39321e0b-5bfa-499f-a5d2-878b26cc0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992188696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3992188696
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.217954733
Short name T651
Test name
Test status
Simulation time 22489747166 ps
CPU time 40.1 seconds
Started Apr 04 02:14:35 PM PDT 24
Finished Apr 04 02:15:15 PM PDT 24
Peak memory 200792 kb
Host smart-6b5c3814-c7d5-46a1-982e-a13bd183e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217954733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.217954733
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3098331555
Short name T224
Test name
Test status
Simulation time 21868914836 ps
CPU time 33.23 seconds
Started Apr 04 02:14:36 PM PDT 24
Finished Apr 04 02:15:09 PM PDT 24
Peak memory 200896 kb
Host smart-15240c21-d185-4d7e-b0a7-7094696a1333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098331555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3098331555
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3708758565
Short name T862
Test name
Test status
Simulation time 19938570682 ps
CPU time 42.77 seconds
Started Apr 04 02:14:46 PM PDT 24
Finished Apr 04 02:15:29 PM PDT 24
Peak memory 200824 kb
Host smart-b218bd7c-c3ee-40b7-9a82-f98636e21155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708758565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3708758565
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2560901379
Short name T1104
Test name
Test status
Simulation time 25608010946 ps
CPU time 39.16 seconds
Started Apr 04 02:14:41 PM PDT 24
Finished Apr 04 02:15:21 PM PDT 24
Peak memory 200876 kb
Host smart-0ec90689-9d17-41dd-ae0f-41a694311f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560901379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2560901379
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2553695739
Short name T942
Test name
Test status
Simulation time 110216009535 ps
CPU time 41.38 seconds
Started Apr 04 02:14:42 PM PDT 24
Finished Apr 04 02:15:23 PM PDT 24
Peak memory 200732 kb
Host smart-3b594e5a-1816-466c-8147-2f39aa75e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553695739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2553695739
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.821990650
Short name T1125
Test name
Test status
Simulation time 43783680221 ps
CPU time 37.95 seconds
Started Apr 04 02:14:47 PM PDT 24
Finished Apr 04 02:15:25 PM PDT 24
Peak memory 200800 kb
Host smart-0898e5e7-b8c8-4e44-9758-6425d8fe064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821990650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.821990650
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1199259513
Short name T913
Test name
Test status
Simulation time 117519262424 ps
CPU time 22.08 seconds
Started Apr 04 02:14:41 PM PDT 24
Finished Apr 04 02:15:03 PM PDT 24
Peak memory 200800 kb
Host smart-f115e37c-87f5-41fc-a489-cc807fb68045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199259513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1199259513
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.792963713
Short name T623
Test name
Test status
Simulation time 14587222 ps
CPU time 0.55 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:28 PM PDT 24
Peak memory 196248 kb
Host smart-dcbe2220-e0ac-4264-9d1d-add248bcd11a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792963713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.792963713
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.700539210
Short name T497
Test name
Test status
Simulation time 120305232557 ps
CPU time 239.44 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:12:16 PM PDT 24
Peak memory 200860 kb
Host smart-a150a053-d337-4a30-9f51-cabbad734651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700539210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.700539210
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3121707669
Short name T394
Test name
Test status
Simulation time 15370639076 ps
CPU time 28.79 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:08:44 PM PDT 24
Peak memory 200908 kb
Host smart-f036609c-9a59-472d-8b07-4a0e09e8a70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121707669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3121707669
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3351180725
Short name T1145
Test name
Test status
Simulation time 184851232125 ps
CPU time 458.82 seconds
Started Apr 04 02:08:21 PM PDT 24
Finished Apr 04 02:16:00 PM PDT 24
Peak memory 200876 kb
Host smart-c2bce91a-e8bb-4704-8197-69e194b0caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351180725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3351180725
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1328272291
Short name T994
Test name
Test status
Simulation time 13006724962 ps
CPU time 23.31 seconds
Started Apr 04 02:08:29 PM PDT 24
Finished Apr 04 02:08:52 PM PDT 24
Peak memory 199332 kb
Host smart-5da08a1d-85e2-4914-af05-7aa82603c19f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328272291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1328272291
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2647569224
Short name T445
Test name
Test status
Simulation time 199165727139 ps
CPU time 315.31 seconds
Started Apr 04 02:08:26 PM PDT 24
Finished Apr 04 02:13:42 PM PDT 24
Peak memory 200860 kb
Host smart-e35cd950-5b54-49fb-8c53-23d7b26af329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647569224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2647569224
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1292949836
Short name T949
Test name
Test status
Simulation time 10434747385 ps
CPU time 7.02 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:34 PM PDT 24
Peak memory 200592 kb
Host smart-6578b879-7bb8-4968-84bf-23fe3f7349fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292949836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1292949836
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1794696082
Short name T264
Test name
Test status
Simulation time 169089019755 ps
CPU time 62.08 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:09:29 PM PDT 24
Peak memory 208944 kb
Host smart-672354f2-b3c4-4380-831b-f03517068043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794696082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1794696082
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1112355943
Short name T1016
Test name
Test status
Simulation time 22296348345 ps
CPU time 166.48 seconds
Started Apr 04 02:08:28 PM PDT 24
Finished Apr 04 02:11:14 PM PDT 24
Peak memory 200844 kb
Host smart-6fac8628-5603-4b30-a18e-c054e1ea154b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112355943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1112355943
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.19685140
Short name T1022
Test name
Test status
Simulation time 6399614449 ps
CPU time 9.22 seconds
Started Apr 04 02:08:21 PM PDT 24
Finished Apr 04 02:08:30 PM PDT 24
Peak memory 199032 kb
Host smart-466bec28-93de-4b3c-b7fa-fd6d5413797d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19685140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.19685140
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.247575634
Short name T845
Test name
Test status
Simulation time 200784173982 ps
CPU time 355.08 seconds
Started Apr 04 02:08:29 PM PDT 24
Finished Apr 04 02:14:24 PM PDT 24
Peak memory 200844 kb
Host smart-b58ea0da-a591-4327-bf01-470acf2b6abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247575634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.247575634
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3572644118
Short name T991
Test name
Test status
Simulation time 1872862423 ps
CPU time 1.35 seconds
Started Apr 04 02:08:28 PM PDT 24
Finished Apr 04 02:08:30 PM PDT 24
Peak memory 196308 kb
Host smart-20e59e2b-8522-44f5-8b33-23732811def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572644118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3572644118
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2569445876
Short name T778
Test name
Test status
Simulation time 275672424 ps
CPU time 0.91 seconds
Started Apr 04 02:08:16 PM PDT 24
Finished Apr 04 02:08:17 PM PDT 24
Peak memory 199220 kb
Host smart-f8155a4d-40e5-46b9-9b59-5dde5483da66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569445876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2569445876
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2204578729
Short name T644
Test name
Test status
Simulation time 834864594 ps
CPU time 2.88 seconds
Started Apr 04 02:08:26 PM PDT 24
Finished Apr 04 02:08:29 PM PDT 24
Peak memory 199324 kb
Host smart-678709b5-3b91-43cd-846d-ae32b985fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204578729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2204578729
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1615673341
Short name T601
Test name
Test status
Simulation time 34436838723 ps
CPU time 16.27 seconds
Started Apr 04 02:08:18 PM PDT 24
Finished Apr 04 02:08:35 PM PDT 24
Peak memory 200832 kb
Host smart-602dc002-4375-4fd5-b815-3edfc8519fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615673341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1615673341
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1764378686
Short name T982
Test name
Test status
Simulation time 18998784666 ps
CPU time 19.07 seconds
Started Apr 04 02:14:43 PM PDT 24
Finished Apr 04 02:15:02 PM PDT 24
Peak memory 200908 kb
Host smart-1a56d9e8-fe6a-4e3b-81f9-5ec48313e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764378686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1764378686
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2715749984
Short name T671
Test name
Test status
Simulation time 16226408792 ps
CPU time 26.16 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:15:21 PM PDT 24
Peak memory 200668 kb
Host smart-22ff359b-eeb6-402c-82fb-b0e6ee908cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715749984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2715749984
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.791132635
Short name T219
Test name
Test status
Simulation time 30343707053 ps
CPU time 47.14 seconds
Started Apr 04 02:14:57 PM PDT 24
Finished Apr 04 02:15:44 PM PDT 24
Peak memory 200948 kb
Host smart-50dc479a-a424-4758-81b2-7bb2ff80d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791132635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.791132635
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1735732656
Short name T1051
Test name
Test status
Simulation time 48804907886 ps
CPU time 166.33 seconds
Started Apr 04 02:14:56 PM PDT 24
Finished Apr 04 02:17:42 PM PDT 24
Peak memory 200836 kb
Host smart-1d71f8a1-bd62-4758-b779-3fabfedc404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735732656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1735732656
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3758795465
Short name T153
Test name
Test status
Simulation time 81210637373 ps
CPU time 48.67 seconds
Started Apr 04 02:14:54 PM PDT 24
Finished Apr 04 02:15:43 PM PDT 24
Peak memory 200468 kb
Host smart-273973b5-4182-4af0-9954-26171875351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758795465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3758795465
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.924788871
Short name T1006
Test name
Test status
Simulation time 130992316757 ps
CPU time 62.15 seconds
Started Apr 04 02:14:53 PM PDT 24
Finished Apr 04 02:15:56 PM PDT 24
Peak memory 200840 kb
Host smart-61c5d573-5927-4bde-97a4-ff31f5fc556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924788871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.924788871
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4279360743
Short name T427
Test name
Test status
Simulation time 97855752 ps
CPU time 0.55 seconds
Started Apr 04 02:08:36 PM PDT 24
Finished Apr 04 02:08:37 PM PDT 24
Peak memory 196220 kb
Host smart-51dffdb6-2b9d-429a-bfdc-49d6899ab792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279360743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4279360743
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3401245351
Short name T915
Test name
Test status
Simulation time 182877820796 ps
CPU time 194.4 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:11:42 PM PDT 24
Peak memory 200776 kb
Host smart-7bfe2a02-4099-48c7-bf9e-e1d3055c3230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401245351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3401245351
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2377411379
Short name T754
Test name
Test status
Simulation time 10429557963 ps
CPU time 17.97 seconds
Started Apr 04 02:08:28 PM PDT 24
Finished Apr 04 02:08:46 PM PDT 24
Peak memory 200888 kb
Host smart-71f639e4-5d73-418c-b486-cdccaad552b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377411379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2377411379
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.623268691
Short name T617
Test name
Test status
Simulation time 85976252311 ps
CPU time 142.36 seconds
Started Apr 04 02:08:28 PM PDT 24
Finished Apr 04 02:10:50 PM PDT 24
Peak memory 200652 kb
Host smart-cdafb1f0-f123-4b8a-b574-1e8ee957570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623268691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.623268691
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2864517992
Short name T14
Test name
Test status
Simulation time 29834966080 ps
CPU time 41.58 seconds
Started Apr 04 02:08:32 PM PDT 24
Finished Apr 04 02:09:14 PM PDT 24
Peak memory 200764 kb
Host smart-6562ba48-90c7-4e88-9a07-4bbb4c66ce65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864517992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2864517992
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2133672946
Short name T989
Test name
Test status
Simulation time 93301232277 ps
CPU time 514.28 seconds
Started Apr 04 02:08:30 PM PDT 24
Finished Apr 04 02:17:05 PM PDT 24
Peak memory 200876 kb
Host smart-458296af-68e1-48f3-a3ba-e97b93f0e7f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133672946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2133672946
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.2822644496
Short name T65
Test name
Test status
Simulation time 8031462168 ps
CPU time 12.77 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:40 PM PDT 24
Peak memory 199936 kb
Host smart-09b3b139-c4cb-4764-a795-3befcc26dccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822644496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2822644496
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2264669987
Short name T929
Test name
Test status
Simulation time 158524608729 ps
CPU time 74.31 seconds
Started Apr 04 02:08:32 PM PDT 24
Finished Apr 04 02:09:46 PM PDT 24
Peak memory 200640 kb
Host smart-44efaa47-69e9-4cb6-8890-4db6e5f81d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264669987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2264669987
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2884886678
Short name T1029
Test name
Test status
Simulation time 8917111096 ps
CPU time 106.37 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 200904 kb
Host smart-4d78461b-3651-4c35-a160-55f712dbecdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884886678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2884886678
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2927262086
Short name T365
Test name
Test status
Simulation time 8338401652 ps
CPU time 4.52 seconds
Started Apr 04 02:08:30 PM PDT 24
Finished Apr 04 02:08:34 PM PDT 24
Peak memory 198732 kb
Host smart-c529133d-a89d-473c-b447-f36273242904
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927262086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2927262086
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1920678105
Short name T924
Test name
Test status
Simulation time 36687494669 ps
CPU time 18.38 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:46 PM PDT 24
Peak memory 200884 kb
Host smart-fbdc72fa-66c4-4012-87b0-fd0792bd8df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920678105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1920678105
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2758387985
Short name T800
Test name
Test status
Simulation time 51455035152 ps
CPU time 74.78 seconds
Started Apr 04 02:08:30 PM PDT 24
Finished Apr 04 02:09:44 PM PDT 24
Peak memory 196288 kb
Host smart-9123123e-ea87-40cb-9eb3-6bc35d5375d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758387985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2758387985
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.397846824
Short name T504
Test name
Test status
Simulation time 488443316 ps
CPU time 1.58 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:28 PM PDT 24
Peak memory 199560 kb
Host smart-5dafb83d-01cb-4353-bc70-87c633d47d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397846824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.397846824
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2524633493
Short name T575
Test name
Test status
Simulation time 102484769834 ps
CPU time 112.37 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:10:30 PM PDT 24
Peak memory 200916 kb
Host smart-3a909879-c5c0-4b29-a8f9-fe2433b46ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524633493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2524633493
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2456576084
Short name T922
Test name
Test status
Simulation time 134246614593 ps
CPU time 589.31 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:18:27 PM PDT 24
Peak memory 217472 kb
Host smart-fedb5bcb-afa2-4cb7-8162-0c9636a9dc31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456576084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2456576084
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1445742425
Short name T329
Test name
Test status
Simulation time 1387221312 ps
CPU time 1.88 seconds
Started Apr 04 02:08:27 PM PDT 24
Finished Apr 04 02:08:29 PM PDT 24
Peak memory 199852 kb
Host smart-c9a2b77e-3144-41cc-81b1-182694cde140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445742425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1445742425
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2567330039
Short name T561
Test name
Test status
Simulation time 95622440814 ps
CPU time 174.01 seconds
Started Apr 04 02:08:26 PM PDT 24
Finished Apr 04 02:11:20 PM PDT 24
Peak memory 200860 kb
Host smart-a5c02de1-4dd6-4be9-8954-d4798772ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567330039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2567330039
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.433730842
Short name T521
Test name
Test status
Simulation time 144740113049 ps
CPU time 68.27 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:16:03 PM PDT 24
Peak memory 200788 kb
Host smart-e4e492a3-1967-4c48-a255-3e50da12c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433730842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.433730842
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1832236507
Short name T401
Test name
Test status
Simulation time 15242769876 ps
CPU time 23.22 seconds
Started Apr 04 02:14:56 PM PDT 24
Finished Apr 04 02:15:20 PM PDT 24
Peak memory 200852 kb
Host smart-02d3d627-0e35-43da-b371-a3a2cc0fa164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832236507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1832236507
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3297656885
Short name T188
Test name
Test status
Simulation time 139097811122 ps
CPU time 227.82 seconds
Started Apr 04 02:14:58 PM PDT 24
Finished Apr 04 02:18:46 PM PDT 24
Peak memory 200916 kb
Host smart-0c3d689d-30d5-405e-97a2-50ded1b3927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297656885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3297656885
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3290010399
Short name T930
Test name
Test status
Simulation time 18805931077 ps
CPU time 40.25 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:15:36 PM PDT 24
Peak memory 200952 kb
Host smart-3b4690cd-0a33-4f33-9fb1-07d38d2538eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290010399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3290010399
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.742877157
Short name T707
Test name
Test status
Simulation time 122728930989 ps
CPU time 46.04 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:15:41 PM PDT 24
Peak memory 200664 kb
Host smart-e3daf0d0-55f4-4b22-bdec-75d21262cded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742877157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.742877157
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3898188856
Short name T530
Test name
Test status
Simulation time 27462883657 ps
CPU time 6.22 seconds
Started Apr 04 02:14:54 PM PDT 24
Finished Apr 04 02:15:01 PM PDT 24
Peak memory 200652 kb
Host smart-6d1715af-f8c0-42da-a1f6-5d694fbfe480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898188856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3898188856
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.517733436
Short name T209
Test name
Test status
Simulation time 288679048744 ps
CPU time 38.12 seconds
Started Apr 04 02:14:56 PM PDT 24
Finished Apr 04 02:15:34 PM PDT 24
Peak memory 200884 kb
Host smart-02dd48b0-04a0-4deb-a8b8-39105853f930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517733436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.517733436
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3278372757
Short name T757
Test name
Test status
Simulation time 20294589656 ps
CPU time 18.44 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:15:14 PM PDT 24
Peak memory 200872 kb
Host smart-c9055b6c-8c98-4175-b4ef-ec38cfcc38fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278372757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3278372757
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.4076599088
Short name T528
Test name
Test status
Simulation time 68584282395 ps
CPU time 27.95 seconds
Started Apr 04 02:14:56 PM PDT 24
Finished Apr 04 02:15:24 PM PDT 24
Peak memory 200924 kb
Host smart-c9123552-6f67-4b3b-9469-e1d68b4ed002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076599088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4076599088
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4210387748
Short name T909
Test name
Test status
Simulation time 20833570 ps
CPU time 0.52 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:08:37 PM PDT 24
Peak memory 196128 kb
Host smart-b0be2b14-188d-48dc-a248-017e63cec65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210387748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4210387748
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3376103034
Short name T541
Test name
Test status
Simulation time 275107732860 ps
CPU time 60.38 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:09:39 PM PDT 24
Peak memory 200872 kb
Host smart-780bd2cc-a958-4f76-853b-5ac1882b2532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376103034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3376103034
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3236419352
Short name T152
Test name
Test status
Simulation time 25506210389 ps
CPU time 44.28 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:09:21 PM PDT 24
Peak memory 200712 kb
Host smart-ecab2ca5-83d6-49fa-b727-f8f305a512c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236419352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3236419352
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.819380719
Short name T560
Test name
Test status
Simulation time 83060845218 ps
CPU time 21.61 seconds
Started Apr 04 02:08:39 PM PDT 24
Finished Apr 04 02:09:01 PM PDT 24
Peak memory 200824 kb
Host smart-7e781e20-ef46-4d00-a312-9b841600b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819380719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.819380719
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2251479952
Short name T620
Test name
Test status
Simulation time 68483235207 ps
CPU time 119.3 seconds
Started Apr 04 02:08:36 PM PDT 24
Finished Apr 04 02:10:36 PM PDT 24
Peak memory 200816 kb
Host smart-5760bfd7-47be-495c-8438-c377eb3f2b36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251479952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2251479952
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.117135399
Short name T676
Test name
Test status
Simulation time 79910724803 ps
CPU time 457.47 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:16:15 PM PDT 24
Peak memory 200828 kb
Host smart-241c6d6d-6548-4ecc-8d54-125b844edf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=117135399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.117135399
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.113296677
Short name T855
Test name
Test status
Simulation time 7261992146 ps
CPU time 23.73 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:09:02 PM PDT 24
Peak memory 200780 kb
Host smart-f956ba70-cd22-4a64-bee3-e0f939d3b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113296677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.113296677
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3415011521
Short name T894
Test name
Test status
Simulation time 37515771342 ps
CPU time 32.56 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:09:11 PM PDT 24
Peak memory 200988 kb
Host smart-4ea25457-af48-4f5f-ab2b-73fd825859bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415011521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3415011521
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.1876697175
Short name T395
Test name
Test status
Simulation time 17448686716 ps
CPU time 756.13 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:21:13 PM PDT 24
Peak memory 200832 kb
Host smart-3fc6cc19-a6bf-4aa0-98a9-366f673cd9a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876697175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1876697175
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1793154825
Short name T1159
Test name
Test status
Simulation time 7682712400 ps
CPU time 17.35 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:08:55 PM PDT 24
Peak memory 198932 kb
Host smart-e7b5f749-9016-46ea-863c-024927464c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793154825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1793154825
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1040403249
Short name T415
Test name
Test status
Simulation time 39719890639 ps
CPU time 85.65 seconds
Started Apr 04 02:08:36 PM PDT 24
Finished Apr 04 02:10:02 PM PDT 24
Peak memory 200880 kb
Host smart-78d528de-8ebb-40a3-bb62-da488170032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040403249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1040403249
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3820311871
Short name T713
Test name
Test status
Simulation time 708276908 ps
CPU time 1.73 seconds
Started Apr 04 02:08:39 PM PDT 24
Finished Apr 04 02:08:41 PM PDT 24
Peak memory 196260 kb
Host smart-eacdfafb-7a03-43df-a315-bbd0d950f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820311871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3820311871
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2861041584
Short name T998
Test name
Test status
Simulation time 5890801043 ps
CPU time 12.58 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:08:50 PM PDT 24
Peak memory 200648 kb
Host smart-785344b0-028d-4481-a70b-c2e09b1cddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861041584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2861041584
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3931141965
Short name T1060
Test name
Test status
Simulation time 276253175830 ps
CPU time 78.87 seconds
Started Apr 04 02:08:41 PM PDT 24
Finished Apr 04 02:10:00 PM PDT 24
Peak memory 201196 kb
Host smart-4127a3d5-544d-48e0-b371-b08c2947dcb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931141965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3931141965
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3467786547
Short name T432
Test name
Test status
Simulation time 1852103700 ps
CPU time 4.02 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:08:42 PM PDT 24
Peak memory 199404 kb
Host smart-6e5e2972-c8b4-4d37-8fdf-1730e40bae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467786547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3467786547
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2656428547
Short name T910
Test name
Test status
Simulation time 60955554993 ps
CPU time 54.75 seconds
Started Apr 04 02:08:37 PM PDT 24
Finished Apr 04 02:09:32 PM PDT 24
Peak memory 200804 kb
Host smart-aa29a03b-0da1-4604-b576-8eca258a1e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656428547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2656428547
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.93829557
Short name T316
Test name
Test status
Simulation time 236092613289 ps
CPU time 408.28 seconds
Started Apr 04 02:14:55 PM PDT 24
Finished Apr 04 02:21:43 PM PDT 24
Peak memory 200296 kb
Host smart-e115bf3e-3256-4893-9a02-91715b2caa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93829557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.93829557
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.626693314
Short name T302
Test name
Test status
Simulation time 80583054090 ps
CPU time 260.9 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:19:31 PM PDT 24
Peak memory 200836 kb
Host smart-630e7750-5925-48b9-a969-fdf32eeebda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626693314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.626693314
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2016643062
Short name T923
Test name
Test status
Simulation time 8255658660 ps
CPU time 14.16 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:15:25 PM PDT 24
Peak memory 200480 kb
Host smart-d066ee1d-3c26-4678-9225-d1de7334bcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016643062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2016643062
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3503752487
Short name T921
Test name
Test status
Simulation time 157424499926 ps
CPU time 20.16 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:15:32 PM PDT 24
Peak memory 200916 kb
Host smart-7bcbd46f-4429-4dbc-a6cb-62cc54d40a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503752487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3503752487
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3017958049
Short name T109
Test name
Test status
Simulation time 67944253831 ps
CPU time 28.69 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:38 PM PDT 24
Peak memory 200756 kb
Host smart-576fdfe5-4fe0-4e6b-be84-b829fd87f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017958049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3017958049
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.805333493
Short name T1178
Test name
Test status
Simulation time 30133320285 ps
CPU time 45.29 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:55 PM PDT 24
Peak memory 200828 kb
Host smart-63fec637-95cc-4fca-9c27-fa395fa677ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805333493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.805333493
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3717607579
Short name T1116
Test name
Test status
Simulation time 8592196083 ps
CPU time 13.91 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:15:26 PM PDT 24
Peak memory 200596 kb
Host smart-b304a043-ed5b-4446-926a-7adbf048f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717607579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3717607579
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2691923508
Short name T816
Test name
Test status
Simulation time 21773743357 ps
CPU time 14.07 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:15:25 PM PDT 24
Peak memory 200764 kb
Host smart-f9fc7276-2989-49b2-9747-63169af428cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691923508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2691923508
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1331963950
Short name T993
Test name
Test status
Simulation time 19200065953 ps
CPU time 12.4 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:22 PM PDT 24
Peak memory 200700 kb
Host smart-d83e036f-14ea-4a4c-86fd-7e015fe79ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331963950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1331963950
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1576170994
Short name T456
Test name
Test status
Simulation time 13953746 ps
CPU time 0.57 seconds
Started Apr 04 02:08:52 PM PDT 24
Finished Apr 04 02:08:53 PM PDT 24
Peak memory 196148 kb
Host smart-3530c1ad-9aeb-4239-afc3-85ca9a632108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576170994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1576170994
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.205161682
Short name T997
Test name
Test status
Simulation time 86878820933 ps
CPU time 39.92 seconds
Started Apr 04 02:08:39 PM PDT 24
Finished Apr 04 02:09:19 PM PDT 24
Peak memory 200876 kb
Host smart-325b6b92-6537-46b6-94af-6158cd4bc3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205161682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.205161682
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1515417315
Short name T798
Test name
Test status
Simulation time 81421620179 ps
CPU time 32.79 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:09:11 PM PDT 24
Peak memory 200808 kb
Host smart-080ee5ed-45db-4776-9c3d-99d427b1474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515417315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1515417315
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.4238950092
Short name T953
Test name
Test status
Simulation time 27713450780 ps
CPU time 39.63 seconds
Started Apr 04 02:08:49 PM PDT 24
Finished Apr 04 02:09:29 PM PDT 24
Peak memory 200872 kb
Host smart-c7de4b2f-559e-4735-9c10-be22ea663e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238950092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.4238950092
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.70452836
Short name T359
Test name
Test status
Simulation time 22775296194 ps
CPU time 37.85 seconds
Started Apr 04 02:08:49 PM PDT 24
Finished Apr 04 02:09:27 PM PDT 24
Peak memory 200136 kb
Host smart-8e370de1-7275-46a7-adcc-c9ad4c16a68a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70452836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.70452836
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.754227917
Short name T760
Test name
Test status
Simulation time 170921217413 ps
CPU time 825.76 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:22:36 PM PDT 24
Peak memory 200816 kb
Host smart-12de6f57-e16d-41a3-a1aa-34d092a77c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754227917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.754227917
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3874743835
Short name T518
Test name
Test status
Simulation time 11176567655 ps
CPU time 8 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:08:58 PM PDT 24
Peak memory 199600 kb
Host smart-5904cfa3-e296-451f-bd26-2023781fa39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874743835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3874743835
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.458689196
Short name T775
Test name
Test status
Simulation time 17135506629 ps
CPU time 31 seconds
Started Apr 04 02:08:49 PM PDT 24
Finished Apr 04 02:09:20 PM PDT 24
Peak memory 200948 kb
Host smart-b53e3a2d-39f5-4c39-9b8d-2cdfbf65a0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458689196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.458689196
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3414846122
Short name T5
Test name
Test status
Simulation time 13907895885 ps
CPU time 671.96 seconds
Started Apr 04 02:08:53 PM PDT 24
Finished Apr 04 02:20:05 PM PDT 24
Peak memory 200916 kb
Host smart-d2a53aef-3973-4a7d-83bf-112072078255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414846122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3414846122
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4284250143
Short name T1148
Test name
Test status
Simulation time 6897440200 ps
CPU time 65.82 seconds
Started Apr 04 02:08:54 PM PDT 24
Finished Apr 04 02:10:01 PM PDT 24
Peak memory 200120 kb
Host smart-db318b47-da8b-44d5-b127-397f2ea623a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284250143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4284250143
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3587631784
Short name T723
Test name
Test status
Simulation time 30306403335 ps
CPU time 14.15 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:09:04 PM PDT 24
Peak memory 200740 kb
Host smart-10053c20-56e5-434d-98df-bf560f1080e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587631784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3587631784
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.147040061
Short name T688
Test name
Test status
Simulation time 33096512830 ps
CPU time 21.7 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:09:12 PM PDT 24
Peak memory 196856 kb
Host smart-e8cfdfea-fe05-497e-a844-5b78066c95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147040061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.147040061
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2249956379
Short name T262
Test name
Test status
Simulation time 103276510 ps
CPU time 0.96 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:08:40 PM PDT 24
Peak memory 199152 kb
Host smart-f1341ec3-9ade-4ebf-b321-cdd8913c0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249956379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2249956379
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2354861687
Short name T37
Test name
Test status
Simulation time 65276357647 ps
CPU time 991 seconds
Started Apr 04 02:08:51 PM PDT 24
Finished Apr 04 02:25:22 PM PDT 24
Peak memory 217288 kb
Host smart-377274ed-f11b-4289-a978-245ab1462fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354861687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2354861687
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.872293473
Short name T1049
Test name
Test status
Simulation time 1211868422 ps
CPU time 3.63 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:08:54 PM PDT 24
Peak memory 200384 kb
Host smart-f9ffe60c-fcef-458e-b84e-e65c7665d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872293473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.872293473
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1189807337
Short name T291
Test name
Test status
Simulation time 54180082817 ps
CPU time 201.83 seconds
Started Apr 04 02:08:38 PM PDT 24
Finished Apr 04 02:12:00 PM PDT 24
Peak memory 200852 kb
Host smart-db561e78-b0ae-475c-ae4a-380d1ffccee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189807337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1189807337
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2861842111
Short name T1127
Test name
Test status
Simulation time 73576861194 ps
CPU time 16.85 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:15:28 PM PDT 24
Peak memory 200840 kb
Host smart-4847dd66-e06e-4fa3-a68f-c629927e69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861842111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2861842111
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3074641141
Short name T865
Test name
Test status
Simulation time 31701877775 ps
CPU time 69.36 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:16:21 PM PDT 24
Peak memory 200832 kb
Host smart-8ab2cf8f-898e-49e5-8899-6a47750ca0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074641141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3074641141
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.649760167
Short name T201
Test name
Test status
Simulation time 72664723483 ps
CPU time 34.72 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:15:45 PM PDT 24
Peak memory 200824 kb
Host smart-6068eab3-2f6f-4e91-a7dd-c51a0717497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649760167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.649760167
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1123569574
Short name T136
Test name
Test status
Simulation time 38662556287 ps
CPU time 65.53 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:16:17 PM PDT 24
Peak memory 200856 kb
Host smart-545cfc65-5705-4774-ae8b-ef6d5c2feaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123569574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1123569574
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.82430146
Short name T166
Test name
Test status
Simulation time 18615482029 ps
CPU time 34.42 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:44 PM PDT 24
Peak memory 200808 kb
Host smart-7c1d0930-2ae3-4051-80db-297de79fe349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82430146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.82430146
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3307503840
Short name T171
Test name
Test status
Simulation time 23203603151 ps
CPU time 20.07 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:15:31 PM PDT 24
Peak memory 200816 kb
Host smart-10539931-93f8-43dc-ba30-b23a75d33adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307503840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3307503840
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2969957313
Short name T129
Test name
Test status
Simulation time 18600956462 ps
CPU time 29.72 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:39 PM PDT 24
Peak memory 200796 kb
Host smart-ba844aaf-a727-4dd4-8be8-360ba06f997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969957313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2969957313
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3960181459
Short name T131
Test name
Test status
Simulation time 308102721094 ps
CPU time 198.61 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:18:30 PM PDT 24
Peak memory 200892 kb
Host smart-49e142f9-e45a-4365-ac4b-6b29ea7f7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960181459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3960181459
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4247248282
Short name T1021
Test name
Test status
Simulation time 15255289011 ps
CPU time 33.04 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:42 PM PDT 24
Peak memory 200876 kb
Host smart-729bd315-b623-4d8e-800f-d12dc89f3aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247248282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4247248282
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2927701512
Short name T657
Test name
Test status
Simulation time 12999842 ps
CPU time 0.54 seconds
Started Apr 04 02:09:08 PM PDT 24
Finished Apr 04 02:09:09 PM PDT 24
Peak memory 196152 kb
Host smart-a7a92704-2a95-43d0-89bb-3d52124cc9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927701512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2927701512
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3338174259
Short name T141
Test name
Test status
Simulation time 127735295706 ps
CPU time 60.65 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:09:51 PM PDT 24
Peak memory 200744 kb
Host smart-098c9a16-3eec-4573-b60f-71b3bf47748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338174259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3338174259
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2628946740
Short name T147
Test name
Test status
Simulation time 143288169616 ps
CPU time 93.31 seconds
Started Apr 04 02:08:48 PM PDT 24
Finished Apr 04 02:10:22 PM PDT 24
Peak memory 200760 kb
Host smart-1637df4b-411d-40db-a642-1d0560d121ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628946740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2628946740
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2457926282
Short name T180
Test name
Test status
Simulation time 114228703709 ps
CPU time 215.29 seconds
Started Apr 04 02:08:53 PM PDT 24
Finished Apr 04 02:12:28 PM PDT 24
Peak memory 200912 kb
Host smart-50e21879-df12-4571-9dc3-100afcbaf823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457926282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2457926282
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3577393040
Short name T363
Test name
Test status
Simulation time 289909223885 ps
CPU time 389.48 seconds
Started Apr 04 02:08:49 PM PDT 24
Finished Apr 04 02:15:18 PM PDT 24
Peak memory 197912 kb
Host smart-3b43270b-dcc8-437f-af17-6713a5d00d16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577393040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3577393040
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2475572293
Short name T556
Test name
Test status
Simulation time 81605974508 ps
CPU time 239.78 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:13:06 PM PDT 24
Peak memory 200844 kb
Host smart-06ecb165-c08c-4990-a6f8-d3805388f782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2475572293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2475572293
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2208538637
Short name T1000
Test name
Test status
Simulation time 9742373282 ps
CPU time 7.25 seconds
Started Apr 04 02:08:53 PM PDT 24
Finished Apr 04 02:09:01 PM PDT 24
Peak memory 200720 kb
Host smart-9dd84ba7-7329-4e10-8474-516375aa4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208538637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2208538637
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3642291259
Short name T569
Test name
Test status
Simulation time 119818630085 ps
CPU time 53.87 seconds
Started Apr 04 02:08:48 PM PDT 24
Finished Apr 04 02:09:43 PM PDT 24
Peak memory 200496 kb
Host smart-15de7e1d-48ba-4095-9103-31f049663dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642291259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3642291259
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2450359907
Short name T1175
Test name
Test status
Simulation time 4044406009 ps
CPU time 198.01 seconds
Started Apr 04 02:08:52 PM PDT 24
Finished Apr 04 02:12:11 PM PDT 24
Peak memory 200812 kb
Host smart-77a62d2c-6325-49c4-a2cc-c5a18b06188c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450359907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2450359907
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.970100546
Short name T856
Test name
Test status
Simulation time 3601654550 ps
CPU time 14.46 seconds
Started Apr 04 02:08:48 PM PDT 24
Finished Apr 04 02:09:03 PM PDT 24
Peak memory 198660 kb
Host smart-27baa242-a87e-45c8-a8d7-4c41056cf2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970100546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.970100546
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.4103588771
Short name T1031
Test name
Test status
Simulation time 17461233825 ps
CPU time 14.86 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:09:05 PM PDT 24
Peak memory 200688 kb
Host smart-0a33fb7a-6e5f-42b0-84d6-85fec73f17d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103588771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4103588771
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3440092675
Short name T803
Test name
Test status
Simulation time 6851345344 ps
CPU time 2.38 seconds
Started Apr 04 02:08:49 PM PDT 24
Finished Apr 04 02:08:51 PM PDT 24
Peak memory 196944 kb
Host smart-b28f2865-478f-472c-b0d8-34771c3174fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440092675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3440092675
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.4032012796
Short name T1108
Test name
Test status
Simulation time 5755384180 ps
CPU time 8.61 seconds
Started Apr 04 02:08:51 PM PDT 24
Finished Apr 04 02:09:00 PM PDT 24
Peak memory 200032 kb
Host smart-a1a6b23e-716d-4759-a73a-68fcf29f7df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032012796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.4032012796
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3477311222
Short name T114
Test name
Test status
Simulation time 55941516842 ps
CPU time 52.96 seconds
Started Apr 04 02:09:05 PM PDT 24
Finished Apr 04 02:09:58 PM PDT 24
Peak memory 200868 kb
Host smart-1b1da452-2cf8-4905-acf8-0bd46cc6a69a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477311222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3477311222
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.886554935
Short name T204
Test name
Test status
Simulation time 114159541393 ps
CPU time 268.4 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:13:35 PM PDT 24
Peak memory 226464 kb
Host smart-87536990-ce21-4d2e-b31d-47b5035d1b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886554935 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.886554935
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3299782480
Short name T266
Test name
Test status
Simulation time 933770467 ps
CPU time 2.03 seconds
Started Apr 04 02:08:50 PM PDT 24
Finished Apr 04 02:08:52 PM PDT 24
Peak memory 199668 kb
Host smart-e17f23f5-27a9-4cc6-ae85-360d36df1d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299782480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3299782480
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.74556912
Short name T548
Test name
Test status
Simulation time 63846048487 ps
CPU time 30.47 seconds
Started Apr 04 02:08:43 PM PDT 24
Finished Apr 04 02:09:14 PM PDT 24
Peak memory 200800 kb
Host smart-5cc2fdb8-fdc1-4786-801c-499b4a62d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74556912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.74556912
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.207500560
Short name T210
Test name
Test status
Simulation time 152472201061 ps
CPU time 18.19 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:15:30 PM PDT 24
Peak memory 200784 kb
Host smart-d41a65c6-b166-478b-9ba3-7ee10a1af982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207500560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.207500560
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.366692518
Short name T833
Test name
Test status
Simulation time 102154361218 ps
CPU time 164.88 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:17:55 PM PDT 24
Peak memory 200880 kb
Host smart-3053c7f9-7cd1-439e-8015-e5bc77cdbdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366692518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.366692518
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3348692860
Short name T1067
Test name
Test status
Simulation time 108823193148 ps
CPU time 165.88 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:17:57 PM PDT 24
Peak memory 200908 kb
Host smart-1b26bf43-7a7f-406a-8165-820f14e626a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348692860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3348692860
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1879694672
Short name T237
Test name
Test status
Simulation time 45491857171 ps
CPU time 65.6 seconds
Started Apr 04 02:15:13 PM PDT 24
Finished Apr 04 02:16:18 PM PDT 24
Peak memory 200816 kb
Host smart-8ba67bb8-0997-4d8f-b54d-cc7869b8213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879694672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1879694672
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3750007544
Short name T810
Test name
Test status
Simulation time 20999593243 ps
CPU time 18.45 seconds
Started Apr 04 02:15:12 PM PDT 24
Finished Apr 04 02:15:30 PM PDT 24
Peak memory 200852 kb
Host smart-6e245ecc-8bbb-49c2-9b71-2052e5da24d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750007544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3750007544
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.590003334
Short name T967
Test name
Test status
Simulation time 29609478515 ps
CPU time 24.91 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:15:36 PM PDT 24
Peak memory 200336 kb
Host smart-c384ecdb-5b52-4fc4-bb59-8a568f126779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590003334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.590003334
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3761051551
Short name T1113
Test name
Test status
Simulation time 111238153801 ps
CPU time 54.12 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:16:03 PM PDT 24
Peak memory 200904 kb
Host smart-07e6bde8-e371-4d4d-81c7-251491cd382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761051551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3761051551
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2380792392
Short name T419
Test name
Test status
Simulation time 18822390710 ps
CPU time 17.66 seconds
Started Apr 04 02:15:11 PM PDT 24
Finished Apr 04 02:15:29 PM PDT 24
Peak memory 200848 kb
Host smart-9c07ca32-5d72-4572-ad7d-ee1223d057bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380792392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2380792392
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3457885120
Short name T990
Test name
Test status
Simulation time 251165073164 ps
CPU time 44.4 seconds
Started Apr 04 02:15:09 PM PDT 24
Finished Apr 04 02:15:54 PM PDT 24
Peak memory 200908 kb
Host smart-89cc170c-f7f7-43af-aed5-54236fc5a647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457885120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3457885120
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.581538335
Short name T665
Test name
Test status
Simulation time 12546038 ps
CPU time 0.57 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:07 PM PDT 24
Peak memory 196192 kb
Host smart-4d51cf7c-0b74-4040-ba84-d94ad387f58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581538335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.581538335
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2801150425
Short name T526
Test name
Test status
Simulation time 7643225960 ps
CPU time 13.24 seconds
Started Apr 04 02:09:07 PM PDT 24
Finished Apr 04 02:09:21 PM PDT 24
Peak memory 200856 kb
Host smart-90791da2-9e60-4c4a-a908-f0ab7b16d7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801150425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2801150425
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3456436896
Short name T144
Test name
Test status
Simulation time 205944368504 ps
CPU time 319.16 seconds
Started Apr 04 02:09:07 PM PDT 24
Finished Apr 04 02:14:26 PM PDT 24
Peak memory 200696 kb
Host smart-570ccb8a-350e-45be-82fa-22eb374d8ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456436896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3456436896
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1538647432
Short name T213
Test name
Test status
Simulation time 97447969100 ps
CPU time 125.27 seconds
Started Apr 04 02:09:08 PM PDT 24
Finished Apr 04 02:11:13 PM PDT 24
Peak memory 200856 kb
Host smart-f1cfce93-2193-4848-862b-ea651ebab722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538647432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1538647432
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.60486511
Short name T720
Test name
Test status
Simulation time 20898904164 ps
CPU time 37.9 seconds
Started Apr 04 02:09:08 PM PDT 24
Finished Apr 04 02:09:46 PM PDT 24
Peak memory 200792 kb
Host smart-c5b43e6d-0b08-4133-9765-302cf9824b43
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60486511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.60486511
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2419838387
Short name T999
Test name
Test status
Simulation time 150183634008 ps
CPU time 203.04 seconds
Started Apr 04 02:09:08 PM PDT 24
Finished Apr 04 02:12:31 PM PDT 24
Peak memory 200836 kb
Host smart-437a18db-078c-43a0-9d21-3e419c2dabc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419838387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2419838387
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4176723623
Short name T375
Test name
Test status
Simulation time 9668689525 ps
CPU time 9.74 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:15 PM PDT 24
Peak memory 199556 kb
Host smart-262e74ba-3773-44ba-b805-4aa751d75734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176723623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4176723623
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.3106141924
Short name T326
Test name
Test status
Simulation time 1845645750 ps
CPU time 41.56 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:47 PM PDT 24
Peak memory 200744 kb
Host smart-4b0c278b-618e-4cbf-983b-7b5faabe1279
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106141924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3106141924
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3657360679
Short name T312
Test name
Test status
Simulation time 5777999832 ps
CPU time 26.45 seconds
Started Apr 04 02:09:10 PM PDT 24
Finished Apr 04 02:09:36 PM PDT 24
Peak memory 199968 kb
Host smart-10684d57-88e6-4057-9315-5a5062af305b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657360679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3657360679
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.899686045
Short name T959
Test name
Test status
Simulation time 127639266686 ps
CPU time 88.86 seconds
Started Apr 04 02:09:05 PM PDT 24
Finished Apr 04 02:10:34 PM PDT 24
Peak memory 200820 kb
Host smart-0a418fc8-707d-4667-977b-5379cbf83f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899686045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.899686045
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1282375930
Short name T345
Test name
Test status
Simulation time 6197880599 ps
CPU time 3.26 seconds
Started Apr 04 02:09:07 PM PDT 24
Finished Apr 04 02:09:11 PM PDT 24
Peak memory 197088 kb
Host smart-c70a6b0c-a76e-4826-bfe7-b7e6951812e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282375930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1282375930
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3315961814
Short name T1103
Test name
Test status
Simulation time 432805674 ps
CPU time 1.83 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:08 PM PDT 24
Peak memory 199532 kb
Host smart-50449e03-28e5-47bf-9817-ea1bc8d26793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315961814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3315961814
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4199124600
Short name T1173
Test name
Test status
Simulation time 342062947053 ps
CPU time 47.64 seconds
Started Apr 04 02:09:08 PM PDT 24
Finished Apr 04 02:09:55 PM PDT 24
Peak memory 200804 kb
Host smart-2712636c-82d7-4fff-9d90-e05b4dd65b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199124600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4199124600
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1298754105
Short name T435
Test name
Test status
Simulation time 12373413553 ps
CPU time 150.16 seconds
Started Apr 04 02:09:05 PM PDT 24
Finished Apr 04 02:11:36 PM PDT 24
Peak memory 200948 kb
Host smart-552ffcb8-ac69-458a-9c9b-bf0d706e902d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298754105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1298754105
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3460496926
Short name T868
Test name
Test status
Simulation time 4530126938 ps
CPU time 2.22 seconds
Started Apr 04 02:09:04 PM PDT 24
Finished Apr 04 02:09:07 PM PDT 24
Peak memory 199944 kb
Host smart-7278cb72-c7b2-4422-9014-fd263670cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460496926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3460496926
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2612627155
Short name T1105
Test name
Test status
Simulation time 119839968486 ps
CPU time 242.08 seconds
Started Apr 04 02:09:05 PM PDT 24
Finished Apr 04 02:13:07 PM PDT 24
Peak memory 200816 kb
Host smart-19bf7d47-130d-4000-a0cc-8c72c45aec9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612627155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2612627155
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2542205241
Short name T248
Test name
Test status
Simulation time 107767338302 ps
CPU time 90.28 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:16:41 PM PDT 24
Peak memory 200884 kb
Host smart-1edf72e0-de54-4d4d-84d2-4aacb79ff99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542205241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2542205241
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1107088672
Short name T231
Test name
Test status
Simulation time 80062171867 ps
CPU time 293.38 seconds
Started Apr 04 02:15:10 PM PDT 24
Finished Apr 04 02:20:04 PM PDT 24
Peak memory 200832 kb
Host smart-c2b41ddb-9acc-4118-bee3-53780ca48161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107088672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1107088672
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2230834934
Short name T182
Test name
Test status
Simulation time 4835767645 ps
CPU time 11.03 seconds
Started Apr 04 02:15:27 PM PDT 24
Finished Apr 04 02:15:38 PM PDT 24
Peak memory 200840 kb
Host smart-5c024897-3836-4330-8823-2d7bde5cddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230834934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2230834934
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3530234804
Short name T179
Test name
Test status
Simulation time 84484489921 ps
CPU time 33.34 seconds
Started Apr 04 02:15:29 PM PDT 24
Finished Apr 04 02:16:02 PM PDT 24
Peak memory 200756 kb
Host smart-ad06a424-5ecd-4361-90a7-22f2dea6dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530234804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3530234804
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1989766326
Short name T727
Test name
Test status
Simulation time 50631083047 ps
CPU time 19.07 seconds
Started Apr 04 02:15:27 PM PDT 24
Finished Apr 04 02:15:46 PM PDT 24
Peak memory 200892 kb
Host smart-64434845-f842-4797-8005-696bcac53089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989766326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1989766326
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2894030133
Short name T660
Test name
Test status
Simulation time 23965900137 ps
CPU time 23.05 seconds
Started Apr 04 02:15:26 PM PDT 24
Finished Apr 04 02:15:49 PM PDT 24
Peak memory 200868 kb
Host smart-659ee10d-48f6-4d29-a8cf-fdadafeec699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894030133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2894030133
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1807360215
Short name T807
Test name
Test status
Simulation time 12344417893 ps
CPU time 42.48 seconds
Started Apr 04 02:15:28 PM PDT 24
Finished Apr 04 02:16:11 PM PDT 24
Peak memory 200784 kb
Host smart-a965e75d-bac4-48b1-ac4e-634e88f9f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807360215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1807360215
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.921948089
Short name T892
Test name
Test status
Simulation time 90864786374 ps
CPU time 16.95 seconds
Started Apr 04 02:15:25 PM PDT 24
Finished Apr 04 02:15:42 PM PDT 24
Peak memory 200804 kb
Host smart-717789e4-3ba3-4671-beec-d483515aa783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921948089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.921948089
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.24766647
Short name T581
Test name
Test status
Simulation time 22873253 ps
CPU time 0.54 seconds
Started Apr 04 02:09:18 PM PDT 24
Finished Apr 04 02:09:19 PM PDT 24
Peak memory 196212 kb
Host smart-d09501f2-2812-45b9-b4f5-172ea957f086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24766647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.24766647
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1633511051
Short name T678
Test name
Test status
Simulation time 71054271752 ps
CPU time 20.92 seconds
Started Apr 04 02:09:07 PM PDT 24
Finished Apr 04 02:09:29 PM PDT 24
Peak memory 200700 kb
Host smart-f5c5aa77-c307-4cf9-ba07-5693d0136510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633511051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1633511051
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2483942278
Short name T69
Test name
Test status
Simulation time 62066400530 ps
CPU time 53.74 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:10:00 PM PDT 24
Peak memory 200844 kb
Host smart-4c954055-9b2b-4576-86ab-aa47ba3e9031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483942278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2483942278
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1221691973
Short name T1147
Test name
Test status
Simulation time 105536719487 ps
CPU time 65.37 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:10:11 PM PDT 24
Peak memory 200916 kb
Host smart-54205d86-77b1-4d8f-b171-16974b3c887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221691973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1221691973
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1386752316
Short name T1112
Test name
Test status
Simulation time 16389497677 ps
CPU time 6.68 seconds
Started Apr 04 02:09:10 PM PDT 24
Finished Apr 04 02:09:16 PM PDT 24
Peak memory 200812 kb
Host smart-496bdfdc-157a-46fd-ad2e-b667b4392e59
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386752316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1386752316
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.374392540
Short name T600
Test name
Test status
Simulation time 73897971102 ps
CPU time 323.18 seconds
Started Apr 04 02:09:20 PM PDT 24
Finished Apr 04 02:14:44 PM PDT 24
Peak memory 200936 kb
Host smart-9e3945a2-9f0e-4145-a28a-d8993da7ba62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374392540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.374392540
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.410787509
Short name T621
Test name
Test status
Simulation time 305342281 ps
CPU time 0.76 seconds
Started Apr 04 02:09:17 PM PDT 24
Finished Apr 04 02:09:18 PM PDT 24
Peak memory 197728 kb
Host smart-f6f26a0e-775d-41d5-8c4e-94246062ce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410787509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.410787509
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1500623033
Short name T779
Test name
Test status
Simulation time 49420402716 ps
CPU time 102.97 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:10:49 PM PDT 24
Peak memory 201040 kb
Host smart-bf580fb8-6778-4a50-9841-caf9de6d7f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500623033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1500623033
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2056277908
Short name T691
Test name
Test status
Simulation time 28646505707 ps
CPU time 438.45 seconds
Started Apr 04 02:09:17 PM PDT 24
Finished Apr 04 02:16:36 PM PDT 24
Peak memory 200900 kb
Host smart-cc81a0b6-0500-4e1f-8716-98ccb3a5b2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056277908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2056277908
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1680365869
Short name T927
Test name
Test status
Simulation time 2089123044 ps
CPU time 5.83 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:12 PM PDT 24
Peak memory 198888 kb
Host smart-6ec4b6cc-18e0-41a0-856a-8ade8fa446a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680365869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1680365869
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.496035876
Short name T132
Test name
Test status
Simulation time 45886653350 ps
CPU time 79.9 seconds
Started Apr 04 02:09:18 PM PDT 24
Finished Apr 04 02:10:38 PM PDT 24
Peak memory 200812 kb
Host smart-e6d56ccd-5d8a-4da7-b005-944c925b1bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496035876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.496035876
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2874833751
Short name T501
Test name
Test status
Simulation time 526081288 ps
CPU time 1.09 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:20 PM PDT 24
Peak memory 196548 kb
Host smart-33003d7b-1469-4ef9-884f-2829f09a4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874833751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2874833751
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2247575877
Short name T784
Test name
Test status
Simulation time 6033910955 ps
CPU time 10.98 seconds
Started Apr 04 02:09:06 PM PDT 24
Finished Apr 04 02:09:17 PM PDT 24
Peak memory 200632 kb
Host smart-f7409038-b32f-43d7-9341-75624f606ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247575877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2247575877
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3749056700
Short name T878
Test name
Test status
Simulation time 82734809724 ps
CPU time 332.78 seconds
Started Apr 04 02:09:22 PM PDT 24
Finished Apr 04 02:14:55 PM PDT 24
Peak memory 200928 kb
Host smart-8054fae1-8eaa-4477-a083-624e0f410e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749056700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3749056700
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3617892418
Short name T626
Test name
Test status
Simulation time 915850384 ps
CPU time 3.07 seconds
Started Apr 04 02:09:18 PM PDT 24
Finished Apr 04 02:09:21 PM PDT 24
Peak memory 200552 kb
Host smart-16eeb1d7-488d-43b2-9f61-1e2e9b364e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617892418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3617892418
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3850241053
Short name T1166
Test name
Test status
Simulation time 206685153046 ps
CPU time 110.35 seconds
Started Apr 04 02:09:05 PM PDT 24
Finished Apr 04 02:10:55 PM PDT 24
Peak memory 200892 kb
Host smart-3ecedc69-9c89-4a5d-aa40-cd7fcc53d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850241053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3850241053
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.53859430
Short name T685
Test name
Test status
Simulation time 19274643133 ps
CPU time 42.48 seconds
Started Apr 04 02:15:25 PM PDT 24
Finished Apr 04 02:16:08 PM PDT 24
Peak memory 200752 kb
Host smart-e85ae7d7-d003-4ea6-a6fd-4dff1f76ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53859430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.53859430
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1169443572
Short name T66
Test name
Test status
Simulation time 97636164561 ps
CPU time 162.61 seconds
Started Apr 04 02:15:26 PM PDT 24
Finished Apr 04 02:18:08 PM PDT 24
Peak memory 200916 kb
Host smart-b835b031-f934-415a-9a28-67681c826d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169443572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1169443572
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.369991766
Short name T191
Test name
Test status
Simulation time 68206795850 ps
CPU time 158.74 seconds
Started Apr 04 02:15:28 PM PDT 24
Finished Apr 04 02:18:07 PM PDT 24
Peak memory 200844 kb
Host smart-d2eb2ec3-4adf-45aa-8006-999ecf622ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369991766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.369991766
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3467280154
Short name T559
Test name
Test status
Simulation time 52736459189 ps
CPU time 22.46 seconds
Started Apr 04 02:15:25 PM PDT 24
Finished Apr 04 02:15:47 PM PDT 24
Peak memory 200888 kb
Host smart-8937a580-42ea-4f93-8533-9dc250db3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467280154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3467280154
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3163343680
Short name T611
Test name
Test status
Simulation time 99439204537 ps
CPU time 80.31 seconds
Started Apr 04 02:15:26 PM PDT 24
Finished Apr 04 02:16:46 PM PDT 24
Peak memory 200888 kb
Host smart-4ee96ea9-9669-4ce9-9e36-b69707852e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163343680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3163343680
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3948545913
Short name T1041
Test name
Test status
Simulation time 46269009683 ps
CPU time 110.62 seconds
Started Apr 04 02:15:25 PM PDT 24
Finished Apr 04 02:17:16 PM PDT 24
Peak memory 200888 kb
Host smart-791dc7c6-cce3-472f-8916-4044356c7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948545913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3948545913
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.891557032
Short name T493
Test name
Test status
Simulation time 169844252624 ps
CPU time 340.09 seconds
Started Apr 04 02:15:26 PM PDT 24
Finished Apr 04 02:21:07 PM PDT 24
Peak memory 200852 kb
Host smart-7d0c79d3-efd3-477a-9295-842084ff1cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891557032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.891557032
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.551702282
Short name T324
Test name
Test status
Simulation time 14508255063 ps
CPU time 25.83 seconds
Started Apr 04 02:15:31 PM PDT 24
Finished Apr 04 02:15:57 PM PDT 24
Peak memory 200860 kb
Host smart-bb1bf5ec-0421-479f-a1de-c800c00f325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551702282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.551702282
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.174393569
Short name T177
Test name
Test status
Simulation time 23679266342 ps
CPU time 39.96 seconds
Started Apr 04 02:15:27 PM PDT 24
Finished Apr 04 02:16:07 PM PDT 24
Peak memory 200688 kb
Host smart-ce6994e0-2c63-4388-80fc-2ddb0673aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174393569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.174393569
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.752784007
Short name T236
Test name
Test status
Simulation time 22073022547 ps
CPU time 29.43 seconds
Started Apr 04 02:15:28 PM PDT 24
Finished Apr 04 02:15:58 PM PDT 24
Peak memory 200788 kb
Host smart-204b2af1-ed6c-4417-b4f3-00b10a3a09f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752784007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.752784007
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3096319947
Short name T744
Test name
Test status
Simulation time 15502485 ps
CPU time 0.56 seconds
Started Apr 04 02:06:18 PM PDT 24
Finished Apr 04 02:06:19 PM PDT 24
Peak memory 196212 kb
Host smart-5992653b-38ed-45d1-bd70-76256044f577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096319947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3096319947
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2373139667
Short name T582
Test name
Test status
Simulation time 132837989725 ps
CPU time 155.51 seconds
Started Apr 04 02:06:13 PM PDT 24
Finished Apr 04 02:08:49 PM PDT 24
Peak memory 200904 kb
Host smart-c75c9ea5-50dc-42bb-acf4-f6f282d89569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373139667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2373139667
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.417502978
Short name T1007
Test name
Test status
Simulation time 285021891802 ps
CPU time 35.37 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:06:54 PM PDT 24
Peak memory 200780 kb
Host smart-fc13133a-1fec-4970-a2a6-d7737af0db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417502978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.417502978
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2159028430
Short name T774
Test name
Test status
Simulation time 44252308713 ps
CPU time 75.4 seconds
Started Apr 04 02:06:18 PM PDT 24
Finished Apr 04 02:07:34 PM PDT 24
Peak memory 200868 kb
Host smart-66169d6f-3390-46e6-bd76-c96435f59758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159028430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2159028430
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3861109665
Short name T538
Test name
Test status
Simulation time 26844903377 ps
CPU time 3.29 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:06:23 PM PDT 24
Peak memory 198544 kb
Host smart-4642e7aa-cd6f-4840-959e-1a35e07a9f0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861109665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3861109665
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.394388483
Short name T295
Test name
Test status
Simulation time 76358753818 ps
CPU time 369.06 seconds
Started Apr 04 02:06:21 PM PDT 24
Finished Apr 04 02:12:30 PM PDT 24
Peak memory 200716 kb
Host smart-433918d6-0227-4b4d-bcbf-c17b48d27f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=394388483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.394388483
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.236395478
Short name T399
Test name
Test status
Simulation time 4430261216 ps
CPU time 4.48 seconds
Started Apr 04 02:06:16 PM PDT 24
Finished Apr 04 02:06:21 PM PDT 24
Peak memory 197028 kb
Host smart-14d81550-4fe9-465f-904d-257a96ed5c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236395478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.236395478
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3848777293
Short name T1152
Test name
Test status
Simulation time 33369232959 ps
CPU time 57.68 seconds
Started Apr 04 02:06:17 PM PDT 24
Finished Apr 04 02:07:15 PM PDT 24
Peak memory 201064 kb
Host smart-9cd07784-0d2c-4485-ae26-33142d2dcc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848777293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3848777293
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1858305594
Short name T693
Test name
Test status
Simulation time 12567378337 ps
CPU time 212 seconds
Started Apr 04 02:06:20 PM PDT 24
Finished Apr 04 02:09:53 PM PDT 24
Peak memory 200712 kb
Host smart-d48e4434-b0e9-4d39-a2b3-4bd0f8b7012d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858305594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1858305594
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1845421117
Short name T347
Test name
Test status
Simulation time 3715820592 ps
CPU time 16.49 seconds
Started Apr 04 02:06:18 PM PDT 24
Finished Apr 04 02:06:35 PM PDT 24
Peak memory 199056 kb
Host smart-c56d932a-4920-46b9-b2a0-67ca308dda1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845421117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1845421117
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2775089602
Short name T799
Test name
Test status
Simulation time 44114961345 ps
CPU time 73.18 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200760 kb
Host smart-b042397f-f6a5-456c-a789-634e8bd5f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775089602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2775089602
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.198055726
Short name T625
Test name
Test status
Simulation time 42846470269 ps
CPU time 68.19 seconds
Started Apr 04 02:06:18 PM PDT 24
Finished Apr 04 02:07:27 PM PDT 24
Peak memory 196600 kb
Host smart-58bbeb8f-310d-41d1-8ecc-189513c3fcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198055726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.198055726
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1837262508
Short name T90
Test name
Test status
Simulation time 269675714 ps
CPU time 0.83 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:06:16 PM PDT 24
Peak memory 218840 kb
Host smart-28de4042-0b81-4513-8188-444417bc4adf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837262508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1837262508
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3722938653
Short name T674
Test name
Test status
Simulation time 410999423 ps
CPU time 1.75 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:06:22 PM PDT 24
Peak memory 200348 kb
Host smart-a532f678-77c5-49c8-91b8-dc49f2c91e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722938653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3722938653
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3622066556
Short name T802
Test name
Test status
Simulation time 36585049284 ps
CPU time 355 seconds
Started Apr 04 02:06:21 PM PDT 24
Finished Apr 04 02:12:16 PM PDT 24
Peak memory 217552 kb
Host smart-7654deeb-0ff0-4a34-9589-7ce434bde491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622066556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3622066556
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2805733373
Short name T344
Test name
Test status
Simulation time 2298292966 ps
CPU time 2.35 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:06:22 PM PDT 24
Peak memory 199304 kb
Host smart-ceca0372-b1c2-4232-abcc-8553460091aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805733373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2805733373
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2356773536
Short name T864
Test name
Test status
Simulation time 24643687735 ps
CPU time 36.2 seconds
Started Apr 04 02:06:22 PM PDT 24
Finished Apr 04 02:06:59 PM PDT 24
Peak memory 200840 kb
Host smart-2a4c9157-79bf-491c-b28a-de486b33f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356773536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2356773536
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3481054027
Short name T1056
Test name
Test status
Simulation time 25958625 ps
CPU time 0.54 seconds
Started Apr 04 02:09:18 PM PDT 24
Finished Apr 04 02:09:19 PM PDT 24
Peak memory 196088 kb
Host smart-b5aac677-6219-45ee-8e49-65454eaae82b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481054027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3481054027
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1275987153
Short name T461
Test name
Test status
Simulation time 84209533539 ps
CPU time 36.86 seconds
Started Apr 04 02:09:20 PM PDT 24
Finished Apr 04 02:09:57 PM PDT 24
Peak memory 200776 kb
Host smart-cdcf079a-7bf9-46ca-854c-d73bd74bdc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275987153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1275987153
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3234028829
Short name T901
Test name
Test status
Simulation time 47648482377 ps
CPU time 38.78 seconds
Started Apr 04 02:09:18 PM PDT 24
Finished Apr 04 02:09:57 PM PDT 24
Peak memory 200328 kb
Host smart-b8c9f67a-2b5c-4e02-93aa-72a6f786d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234028829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3234028829
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3177583060
Short name T315
Test name
Test status
Simulation time 11914620208 ps
CPU time 11.58 seconds
Started Apr 04 02:09:23 PM PDT 24
Finished Apr 04 02:09:35 PM PDT 24
Peak memory 200816 kb
Host smart-189d33cd-acf3-4d7c-8d9f-bc983fb17804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177583060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3177583060
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3576385915
Short name T759
Test name
Test status
Simulation time 56752803103 ps
CPU time 14.66 seconds
Started Apr 04 02:09:20 PM PDT 24
Finished Apr 04 02:09:35 PM PDT 24
Peak memory 200764 kb
Host smart-1a50ee87-5a20-4d5b-8727-89233ef7d832
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576385915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3576385915
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1161008641
Short name T332
Test name
Test status
Simulation time 94605231453 ps
CPU time 289.34 seconds
Started Apr 04 02:09:20 PM PDT 24
Finished Apr 04 02:14:09 PM PDT 24
Peak memory 200852 kb
Host smart-cf02c3af-96f1-493a-a054-bb0663f4f4e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1161008641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1161008641
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1508689697
Short name T387
Test name
Test status
Simulation time 6776744112 ps
CPU time 16.83 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:36 PM PDT 24
Peak memory 199772 kb
Host smart-7b441381-2a9b-487f-b281-3023019aaa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508689697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1508689697
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.548339639
Short name T689
Test name
Test status
Simulation time 14804282907 ps
CPU time 26.17 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:45 PM PDT 24
Peak memory 198676 kb
Host smart-6043e81d-4f6a-43ae-862a-2c73ab0f540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548339639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.548339639
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.934438092
Short name T917
Test name
Test status
Simulation time 23107500400 ps
CPU time 1013.25 seconds
Started Apr 04 02:09:21 PM PDT 24
Finished Apr 04 02:26:14 PM PDT 24
Peak memory 200868 kb
Host smart-eb34b984-cb16-4ba5-88bf-28b3f14619c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934438092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.934438092
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.818476158
Short name T346
Test name
Test status
Simulation time 2893957237 ps
CPU time 1.93 seconds
Started Apr 04 02:09:21 PM PDT 24
Finished Apr 04 02:09:23 PM PDT 24
Peak memory 199044 kb
Host smart-9070da01-7903-47af-bad7-57793a2216e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818476158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.818476158
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.442101753
Short name T279
Test name
Test status
Simulation time 38937362002 ps
CPU time 19.62 seconds
Started Apr 04 02:09:22 PM PDT 24
Finished Apr 04 02:09:42 PM PDT 24
Peak memory 200164 kb
Host smart-db354eac-6014-4949-801f-30c2b3c85de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442101753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.442101753
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1380388675
Short name T392
Test name
Test status
Simulation time 44119093286 ps
CPU time 6.35 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:26 PM PDT 24
Peak memory 196764 kb
Host smart-42e7f537-7aac-4ae0-ad2b-d411ab9040b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380388675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1380388675
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3949930897
Short name T372
Test name
Test status
Simulation time 5325829634 ps
CPU time 9.01 seconds
Started Apr 04 02:09:21 PM PDT 24
Finished Apr 04 02:09:31 PM PDT 24
Peak memory 200620 kb
Host smart-97f050a0-d35a-4a1d-8ef9-f784c01195d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949930897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3949930897
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.653795307
Short name T603
Test name
Test status
Simulation time 209302355243 ps
CPU time 1382.74 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:32:22 PM PDT 24
Peak memory 200908 kb
Host smart-8b6fd0e4-19aa-4f7f-b318-8c1a3ae815d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653795307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.653795307
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3522854078
Short name T1099
Test name
Test status
Simulation time 171004536676 ps
CPU time 437.18 seconds
Started Apr 04 02:09:21 PM PDT 24
Finished Apr 04 02:16:38 PM PDT 24
Peak memory 217376 kb
Host smart-81c550cb-a0f5-4afd-b4de-888c71816dd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522854078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3522854078
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1531052029
Short name T11
Test name
Test status
Simulation time 1127638898 ps
CPU time 1.87 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:21 PM PDT 24
Peak memory 199420 kb
Host smart-e98cdc0e-bde6-44f7-8b26-f732df7e2912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531052029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1531052029
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.295380722
Short name T467
Test name
Test status
Simulation time 105258300238 ps
CPU time 57.06 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:10:16 PM PDT 24
Peak memory 200808 kb
Host smart-934051ef-b427-416f-9b5f-4fe563a0cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295380722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.295380722
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4230419330
Short name T336
Test name
Test status
Simulation time 38678398 ps
CPU time 0.52 seconds
Started Apr 04 02:09:30 PM PDT 24
Finished Apr 04 02:09:31 PM PDT 24
Peak memory 195572 kb
Host smart-c19754ac-4685-4348-b4c5-0dd29301409f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230419330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4230419330
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4131221153
Short name T627
Test name
Test status
Simulation time 74830299329 ps
CPU time 165.02 seconds
Started Apr 04 02:09:23 PM PDT 24
Finished Apr 04 02:12:09 PM PDT 24
Peak memory 200876 kb
Host smart-4336f277-cb51-4061-8933-fe7c310fb86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131221153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4131221153
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.810640197
Short name T4
Test name
Test status
Simulation time 25745715846 ps
CPU time 44.73 seconds
Started Apr 04 02:09:23 PM PDT 24
Finished Apr 04 02:10:08 PM PDT 24
Peak memory 200900 kb
Host smart-9d349f3c-70fe-4ad5-82ac-9b6791cf845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810640197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.810640197
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3221321569
Short name T128
Test name
Test status
Simulation time 32730623993 ps
CPU time 54.21 seconds
Started Apr 04 02:09:23 PM PDT 24
Finished Apr 04 02:10:18 PM PDT 24
Peak memory 200824 kb
Host smart-97c82476-53cb-4024-acd4-5264aa111d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221321569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3221321569
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.828977299
Short name T1020
Test name
Test status
Simulation time 56391766646 ps
CPU time 7.83 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:40 PM PDT 24
Peak memory 200144 kb
Host smart-269e99c4-06e0-472c-8a94-806750f55cb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828977299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.828977299
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.730370349
Short name T666
Test name
Test status
Simulation time 115714261433 ps
CPU time 568.16 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:18:59 PM PDT 24
Peak memory 200852 kb
Host smart-f34d8dcc-620b-4389-bc68-a9596ad3c4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=730370349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.730370349
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3643930388
Short name T362
Test name
Test status
Simulation time 5921965721 ps
CPU time 5.41 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:38 PM PDT 24
Peak memory 199840 kb
Host smart-ec056658-6ad6-401b-9fcc-8e8296e5e95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643930388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3643930388
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3414966843
Short name T543
Test name
Test status
Simulation time 97530211176 ps
CPU time 173.36 seconds
Started Apr 04 02:09:30 PM PDT 24
Finished Apr 04 02:12:24 PM PDT 24
Peak memory 216548 kb
Host smart-1e0486e3-aab1-4fbd-b9e7-65d2b972f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414966843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3414966843
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4125026129
Short name T257
Test name
Test status
Simulation time 20152113926 ps
CPU time 256.77 seconds
Started Apr 04 02:09:32 PM PDT 24
Finished Apr 04 02:13:49 PM PDT 24
Peak memory 200868 kb
Host smart-5e6f21a9-4f8f-4c3a-a7ba-02a7f81a7f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125026129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4125026129
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1451406177
Short name T755
Test name
Test status
Simulation time 1772647248 ps
CPU time 6.13 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:38 PM PDT 24
Peak memory 198960 kb
Host smart-23b1f3b0-4fb8-4d19-b4b0-8702f773ce50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451406177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1451406177
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1215025339
Short name T1003
Test name
Test status
Simulation time 81474509681 ps
CPU time 159.06 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:12:11 PM PDT 24
Peak memory 200924 kb
Host smart-d3eb2877-afa5-42eb-90de-7db7bd1ab38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215025339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1215025339
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3576578732
Short name T358
Test name
Test status
Simulation time 38812919444 ps
CPU time 14.58 seconds
Started Apr 04 02:09:36 PM PDT 24
Finished Apr 04 02:09:51 PM PDT 24
Peak memory 196892 kb
Host smart-547152fd-de31-4034-991e-8c637b22aaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576578732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3576578732
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2122954089
Short name T861
Test name
Test status
Simulation time 102185262 ps
CPU time 0.88 seconds
Started Apr 04 02:09:19 PM PDT 24
Finished Apr 04 02:09:20 PM PDT 24
Peak memory 197904 kb
Host smart-62420e0c-c5a1-4df8-9160-c733c0a67316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122954089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2122954089
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.3071664509
Short name T690
Test name
Test status
Simulation time 170106879162 ps
CPU time 85.65 seconds
Started Apr 04 02:09:36 PM PDT 24
Finished Apr 04 02:11:02 PM PDT 24
Peak memory 200892 kb
Host smart-270845f4-0a71-4bae-a53f-13a2bc8c490d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071664509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.3071664509
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2465210802
Short name T1176
Test name
Test status
Simulation time 24881190547 ps
CPU time 610.28 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:19:43 PM PDT 24
Peak memory 216940 kb
Host smart-93e22aa3-ed04-4f9d-98a5-620ad573ca2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465210802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2465210802
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1787561904
Short name T296
Test name
Test status
Simulation time 737362490 ps
CPU time 4.14 seconds
Started Apr 04 02:09:29 PM PDT 24
Finished Apr 04 02:09:33 PM PDT 24
Peak memory 200540 kb
Host smart-f49e7c1f-d23b-4252-9d44-520a51dd07ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787561904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1787561904
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2108841319
Short name T319
Test name
Test status
Simulation time 19908830619 ps
CPU time 6.58 seconds
Started Apr 04 02:09:20 PM PDT 24
Finished Apr 04 02:09:27 PM PDT 24
Peak memory 198624 kb
Host smart-1a9d9555-80e8-4a4c-9924-9d999cd55556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108841319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2108841319
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1380038040
Short name T758
Test name
Test status
Simulation time 14139627 ps
CPU time 0.54 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:09:44 PM PDT 24
Peak memory 196132 kb
Host smart-f348a442-470f-46f4-8c05-a57c27aac8a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380038040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1380038040
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1196825448
Short name T585
Test name
Test status
Simulation time 17316408338 ps
CPU time 32.95 seconds
Started Apr 04 02:09:33 PM PDT 24
Finished Apr 04 02:10:06 PM PDT 24
Peak memory 200760 kb
Host smart-e9eb2f92-072f-47e9-81df-1f73a4c48a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196825448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1196825448
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3934767132
Short name T457
Test name
Test status
Simulation time 23837683620 ps
CPU time 40.78 seconds
Started Apr 04 02:09:33 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 200636 kb
Host smart-d5e507fb-4ae7-4a91-b06b-bee0a995e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934767132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3934767132
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.25401417
Short name T944
Test name
Test status
Simulation time 29981008596 ps
CPU time 57.76 seconds
Started Apr 04 02:09:32 PM PDT 24
Finished Apr 04 02:10:31 PM PDT 24
Peak memory 200800 kb
Host smart-4d5236c5-1d7c-483f-b1a1-7ef02a75d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25401417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.25401417
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.4030155141
Short name T475
Test name
Test status
Simulation time 5672064079 ps
CPU time 7.04 seconds
Started Apr 04 02:09:30 PM PDT 24
Finished Apr 04 02:09:38 PM PDT 24
Peak memory 199364 kb
Host smart-5d590c14-8d95-4012-ad2b-ecbc91a13729
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030155141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.4030155141
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.61541799
Short name T1085
Test name
Test status
Simulation time 228527483000 ps
CPU time 438.04 seconds
Started Apr 04 02:09:46 PM PDT 24
Finished Apr 04 02:17:04 PM PDT 24
Peak memory 200708 kb
Host smart-f35652d4-8d4c-4f1d-b480-e2c21803273e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61541799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.61541799
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.600345708
Short name T406
Test name
Test status
Simulation time 3003593504 ps
CPU time 2.61 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:35 PM PDT 24
Peak memory 199172 kb
Host smart-a2a5b98f-5618-4baf-8b32-da905467b2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600345708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.600345708
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1564449599
Short name T1035
Test name
Test status
Simulation time 55171776660 ps
CPU time 21.72 seconds
Started Apr 04 02:09:32 PM PDT 24
Finished Apr 04 02:09:54 PM PDT 24
Peak memory 199132 kb
Host smart-3d291ece-4756-4817-83bc-e5e5def32ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564449599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1564449599
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.4200825610
Short name T789
Test name
Test status
Simulation time 20330964898 ps
CPU time 287.35 seconds
Started Apr 04 02:10:00 PM PDT 24
Finished Apr 04 02:14:47 PM PDT 24
Peak memory 200828 kb
Host smart-dc2e283e-cb6e-45a8-9826-3037a6a0d4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200825610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4200825610
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1597923944
Short name T715
Test name
Test status
Simulation time 6068799809 ps
CPU time 4.42 seconds
Started Apr 04 02:09:30 PM PDT 24
Finished Apr 04 02:09:35 PM PDT 24
Peak memory 199844 kb
Host smart-d72007c7-17df-4a8b-8350-8bbeedf43730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597923944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1597923944
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2223621305
Short name T1063
Test name
Test status
Simulation time 25671614481 ps
CPU time 21.06 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:53 PM PDT 24
Peak memory 200468 kb
Host smart-2344d0c6-df8c-47de-a1b2-64b6c31a6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223621305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2223621305
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.236856942
Short name T403
Test name
Test status
Simulation time 3450557347 ps
CPU time 5.85 seconds
Started Apr 04 02:09:36 PM PDT 24
Finished Apr 04 02:09:42 PM PDT 24
Peak memory 196888 kb
Host smart-b618f6bd-4c45-4496-b813-309f8d29b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236856942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.236856942
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3409808734
Short name T624
Test name
Test status
Simulation time 5381189706 ps
CPU time 19.67 seconds
Started Apr 04 02:09:32 PM PDT 24
Finished Apr 04 02:09:53 PM PDT 24
Peak memory 200020 kb
Host smart-324b24fa-5ef1-461d-a866-4db00a21f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409808734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3409808734
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2157188666
Short name T102
Test name
Test status
Simulation time 195239191099 ps
CPU time 351.36 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:15:36 PM PDT 24
Peak memory 200860 kb
Host smart-8a5e58f4-0628-40c4-8f14-6676abc9855d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157188666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2157188666
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3146399955
Short name T781
Test name
Test status
Simulation time 9699270642 ps
CPU time 93.6 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:11:18 PM PDT 24
Peak memory 217008 kb
Host smart-1ada9abc-93f4-46cd-b34d-fb3ee18e897b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146399955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3146399955
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3407659562
Short name T254
Test name
Test status
Simulation time 7323550640 ps
CPU time 12.11 seconds
Started Apr 04 02:09:31 PM PDT 24
Finished Apr 04 02:09:44 PM PDT 24
Peak memory 200660 kb
Host smart-7ebfc807-e788-4972-8b77-5132bdf51643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407659562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3407659562
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1497913689
Short name T64
Test name
Test status
Simulation time 54054875221 ps
CPU time 16.59 seconds
Started Apr 04 02:09:30 PM PDT 24
Finished Apr 04 02:09:47 PM PDT 24
Peak memory 200764 kb
Host smart-8ab79dad-af76-4403-b411-0cf155f99d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497913689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1497913689
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3028469669
Short name T795
Test name
Test status
Simulation time 36512668 ps
CPU time 0.56 seconds
Started Apr 04 02:09:53 PM PDT 24
Finished Apr 04 02:09:54 PM PDT 24
Peak memory 196200 kb
Host smart-c68c27f0-9ff0-4d1e-bd55-6e79c1fa2b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028469669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3028469669
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1395228582
Short name T983
Test name
Test status
Simulation time 24699384722 ps
CPU time 43.95 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:10:29 PM PDT 24
Peak memory 200872 kb
Host smart-7585e1fc-d62d-4823-929e-30e6e98616e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395228582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1395228582
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.490789309
Short name T1001
Test name
Test status
Simulation time 18951707259 ps
CPU time 29.39 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 200852 kb
Host smart-54d5f276-0d9b-4aba-a2ec-409cae9106bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490789309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.490789309
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3538296432
Short name T1106
Test name
Test status
Simulation time 7828695073 ps
CPU time 7.5 seconds
Started Apr 04 02:10:00 PM PDT 24
Finished Apr 04 02:10:07 PM PDT 24
Peak memory 200884 kb
Host smart-679939e2-03f2-4738-bb2f-ac2fbe212435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538296432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3538296432
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3369089280
Short name T22
Test name
Test status
Simulation time 83328030572 ps
CPU time 44.8 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:10:30 PM PDT 24
Peak memory 199904 kb
Host smart-7558d474-9eb6-4e5b-8a10-e615c8f81790
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369089280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3369089280
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1346555663
Short name T857
Test name
Test status
Simulation time 107117600830 ps
CPU time 801.09 seconds
Started Apr 04 02:09:54 PM PDT 24
Finished Apr 04 02:23:15 PM PDT 24
Peak memory 200916 kb
Host smart-efeed214-8465-4b06-a93a-7dd64b5abdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346555663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1346555663
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4263284862
Short name T551
Test name
Test status
Simulation time 1851788922 ps
CPU time 3.89 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:09:49 PM PDT 24
Peak memory 199004 kb
Host smart-e886823a-aea2-44a7-9414-ba0507a2b7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263284862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4263284862
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.349385567
Short name T289
Test name
Test status
Simulation time 82379829803 ps
CPU time 165.7 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:12:29 PM PDT 24
Peak memory 209472 kb
Host smart-225d9b2f-2ffc-4dd7-bc5a-a2f1dcb822de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349385567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.349385567
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1319175663
Short name T1074
Test name
Test status
Simulation time 15448068132 ps
CPU time 871.96 seconds
Started Apr 04 02:09:55 PM PDT 24
Finished Apr 04 02:24:27 PM PDT 24
Peak memory 200824 kb
Host smart-b4119d59-be8e-4b43-b6e0-23ed4a92731e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319175663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1319175663
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3042500855
Short name T42
Test name
Test status
Simulation time 1575369569 ps
CPU time 2.91 seconds
Started Apr 04 02:09:54 PM PDT 24
Finished Apr 04 02:09:57 PM PDT 24
Peak memory 197804 kb
Host smart-6714e7d2-a70a-468a-98df-1d21f458c7ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042500855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3042500855
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1881737087
Short name T404
Test name
Test status
Simulation time 23672224902 ps
CPU time 43.24 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:10:27 PM PDT 24
Peak memory 200808 kb
Host smart-2d85eec3-1c32-400b-b59e-4823a9c8b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881737087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1881737087
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3472593643
Short name T751
Test name
Test status
Simulation time 50284785518 ps
CPU time 33.7 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:10:18 PM PDT 24
Peak memory 196660 kb
Host smart-35473518-e935-46b5-8469-5d9f79da7858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472593643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3472593643
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3503693465
Short name T492
Test name
Test status
Simulation time 933765525 ps
CPU time 2.47 seconds
Started Apr 04 02:09:46 PM PDT 24
Finished Apr 04 02:09:49 PM PDT 24
Peak memory 199356 kb
Host smart-c864bb6a-54ee-41ac-aa84-1a7a377c8bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503693465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3503693465
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.14229127
Short name T460
Test name
Test status
Simulation time 43402413016 ps
CPU time 30.37 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:10:15 PM PDT 24
Peak memory 200808 kb
Host smart-42376d3b-97e8-4ff2-a1e9-74effcc81125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.14229127
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3690208068
Short name T310
Test name
Test status
Simulation time 54009984318 ps
CPU time 688.85 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:21:13 PM PDT 24
Peak memory 225776 kb
Host smart-4a028bab-5ab0-48de-9d83-bc9ab352dcc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690208068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3690208068
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2054950102
Short name T796
Test name
Test status
Simulation time 6405745856 ps
CPU time 13.2 seconds
Started Apr 04 02:09:54 PM PDT 24
Finished Apr 04 02:10:07 PM PDT 24
Peak memory 199844 kb
Host smart-27f174dd-f294-4fef-b535-1ea0cdc2044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054950102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2054950102
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3060393496
Short name T977
Test name
Test status
Simulation time 297905512916 ps
CPU time 36.93 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:10:22 PM PDT 24
Peak memory 200876 kb
Host smart-a20c93d5-90cd-4751-bc1f-1e666a29dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060393496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3060393496
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1355431752
Short name T766
Test name
Test status
Simulation time 14238600 ps
CPU time 0.55 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:09:57 PM PDT 24
Peak memory 196196 kb
Host smart-79eaeac4-4324-4d96-88e8-332ced9dc88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355431752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1355431752
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2870793711
Short name T68
Test name
Test status
Simulation time 90015487160 ps
CPU time 137.9 seconds
Started Apr 04 02:09:46 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 200868 kb
Host smart-e00ca90f-4455-4fd3-9685-ff31bbd290b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870793711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2870793711
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.970470017
Short name T294
Test name
Test status
Simulation time 53788697327 ps
CPU time 21.83 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:19 PM PDT 24
Peak memory 200860 kb
Host smart-42130688-ef32-4c0f-8840-ef1db3b6dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970470017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.970470017
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1331254201
Short name T273
Test name
Test status
Simulation time 162733727024 ps
CPU time 73.71 seconds
Started Apr 04 02:10:01 PM PDT 24
Finished Apr 04 02:11:15 PM PDT 24
Peak memory 200828 kb
Host smart-0809212e-657b-4822-a630-fa5b5dfd6cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331254201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1331254201
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3095126864
Short name T653
Test name
Test status
Simulation time 20646765404 ps
CPU time 36.03 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:33 PM PDT 24
Peak memory 200728 kb
Host smart-56f477a0-ca01-4d16-ba27-b0da76aa4b78
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095126864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3095126864
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3414628129
Short name T1095
Test name
Test status
Simulation time 123630397712 ps
CPU time 886.36 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:24:43 PM PDT 24
Peak memory 200836 kb
Host smart-73fb29fc-8934-4ffb-bcdb-889bb5bca323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414628129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3414628129
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.905581883
Short name T1059
Test name
Test status
Simulation time 205267414 ps
CPU time 0.95 seconds
Started Apr 04 02:09:55 PM PDT 24
Finished Apr 04 02:09:56 PM PDT 24
Peak memory 198084 kb
Host smart-386e26b2-6a9e-4262-9049-42b758b3cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905581883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.905581883
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2385778811
Short name T267
Test name
Test status
Simulation time 50229652819 ps
CPU time 28.63 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:26 PM PDT 24
Peak memory 201060 kb
Host smart-bfbc1a07-1437-41ac-b065-940b44d091ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385778811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2385778811
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1454954416
Short name T724
Test name
Test status
Simulation time 8280873904 ps
CPU time 99.75 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:11:37 PM PDT 24
Peak memory 200956 kb
Host smart-9d306ffb-3e90-48db-a188-f63f07c78b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1454954416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1454954416
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1203544367
Short name T1023
Test name
Test status
Simulation time 6377494982 ps
CPU time 53.57 seconds
Started Apr 04 02:09:58 PM PDT 24
Finished Apr 04 02:10:51 PM PDT 24
Peak memory 199476 kb
Host smart-6927394d-edb1-4795-82ee-a8a936bea5b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203544367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1203544367
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1227149459
Short name T163
Test name
Test status
Simulation time 108014244390 ps
CPU time 404.58 seconds
Started Apr 04 02:09:56 PM PDT 24
Finished Apr 04 02:16:40 PM PDT 24
Peak memory 200876 kb
Host smart-32c599e7-31fe-46cc-b4a4-954ca1e5739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227149459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1227149459
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1243229790
Short name T370
Test name
Test status
Simulation time 29455487259 ps
CPU time 45.14 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:42 PM PDT 24
Peak memory 196912 kb
Host smart-026fa8f2-f73d-45e8-98d8-a49e594840db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243229790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1243229790
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3068527518
Short name T374
Test name
Test status
Simulation time 943990062 ps
CPU time 2.65 seconds
Started Apr 04 02:09:44 PM PDT 24
Finished Apr 04 02:09:47 PM PDT 24
Peak memory 199532 kb
Host smart-30e87c66-6738-416f-b272-45d483d9e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068527518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3068527518
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3391069254
Short name T468
Test name
Test status
Simulation time 644744642620 ps
CPU time 1269.28 seconds
Started Apr 04 02:09:56 PM PDT 24
Finished Apr 04 02:31:06 PM PDT 24
Peak memory 225736 kb
Host smart-bbf657c6-c9df-40d0-8439-ef7c78b82ccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391069254 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3391069254
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.664016606
Short name T794
Test name
Test status
Simulation time 1754491336 ps
CPU time 1.81 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:09:59 PM PDT 24
Peak memory 200496 kb
Host smart-24c59aaa-141e-40c3-922e-c230b0d1ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664016606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.664016606
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1933001690
Short name T839
Test name
Test status
Simulation time 65414868493 ps
CPU time 73.92 seconds
Started Apr 04 02:09:45 PM PDT 24
Finished Apr 04 02:10:59 PM PDT 24
Peak memory 200844 kb
Host smart-0baa5bd2-43de-4b80-a8f5-ed07127ee603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933001690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1933001690
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.618213952
Short name T1019
Test name
Test status
Simulation time 21772338 ps
CPU time 0.53 seconds
Started Apr 04 02:10:14 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 195692 kb
Host smart-69fa8c66-4e2e-49fb-b719-0a66dceb397f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618213952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.618213952
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.180005390
Short name T699
Test name
Test status
Simulation time 204154297477 ps
CPU time 119.93 seconds
Started Apr 04 02:09:58 PM PDT 24
Finished Apr 04 02:11:58 PM PDT 24
Peak memory 200928 kb
Host smart-7cee6ce6-efdf-49c6-bbff-4eaf6fbde3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180005390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.180005390
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2718519701
Short name T115
Test name
Test status
Simulation time 15150449090 ps
CPU time 21.87 seconds
Started Apr 04 02:10:04 PM PDT 24
Finished Apr 04 02:10:26 PM PDT 24
Peak memory 200856 kb
Host smart-297bb960-ca28-412d-9c11-bd9b52b8e5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718519701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2718519701
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2868940019
Short name T320
Test name
Test status
Simulation time 34212712578 ps
CPU time 15.07 seconds
Started Apr 04 02:10:04 PM PDT 24
Finished Apr 04 02:10:19 PM PDT 24
Peak memory 200804 kb
Host smart-54cbdf84-f30b-450b-83f2-d3e9d6c07005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868940019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2868940019
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.823097654
Short name T1158
Test name
Test status
Simulation time 181764548852 ps
CPU time 81.02 seconds
Started Apr 04 02:09:59 PM PDT 24
Finished Apr 04 02:11:20 PM PDT 24
Peak memory 200688 kb
Host smart-45f959c7-9cf2-4915-aa6e-4a6a2f74879b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823097654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.823097654
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.4067434310
Short name T831
Test name
Test status
Simulation time 46258316373 ps
CPU time 234.16 seconds
Started Apr 04 02:10:10 PM PDT 24
Finished Apr 04 02:14:05 PM PDT 24
Peak memory 200800 kb
Host smart-2ac58f95-c960-4662-9a5c-bf7fdc859390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067434310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4067434310
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1126359179
Short name T681
Test name
Test status
Simulation time 490535331 ps
CPU time 0.77 seconds
Started Apr 04 02:10:13 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 196756 kb
Host smart-0acc6c04-8a62-45ed-8ad5-3dd232ca70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126359179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1126359179
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.55305625
Short name T1146
Test name
Test status
Simulation time 94438386611 ps
CPU time 18.65 seconds
Started Apr 04 02:09:56 PM PDT 24
Finished Apr 04 02:10:15 PM PDT 24
Peak memory 197932 kb
Host smart-478d8a16-99c0-4994-9a3e-008bae9cf06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55305625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.55305625
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1372528196
Short name T1050
Test name
Test status
Simulation time 22443178352 ps
CPU time 313.73 seconds
Started Apr 04 02:10:15 PM PDT 24
Finished Apr 04 02:15:29 PM PDT 24
Peak memory 200888 kb
Host smart-d714a8c5-1eed-4539-b027-d3e93960df78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372528196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1372528196
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2204523880
Short name T903
Test name
Test status
Simulation time 5946960355 ps
CPU time 26.02 seconds
Started Apr 04 02:09:56 PM PDT 24
Finished Apr 04 02:10:22 PM PDT 24
Peak memory 199332 kb
Host smart-58a25a17-84de-4c64-8a8a-e0a6a90b0d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204523880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2204523880
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.815392334
Short name T483
Test name
Test status
Simulation time 75585159318 ps
CPU time 59.55 seconds
Started Apr 04 02:10:14 PM PDT 24
Finished Apr 04 02:11:14 PM PDT 24
Peak memory 200804 kb
Host smart-deab0c9f-2dd8-479e-b4e1-006d4990d03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815392334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.815392334
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.4224841000
Short name T505
Test name
Test status
Simulation time 34125552542 ps
CPU time 51.37 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:49 PM PDT 24
Peak memory 196892 kb
Host smart-06b5b3e5-4544-48f6-8a09-59fefe2138bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224841000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.4224841000
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2082105865
Short name T286
Test name
Test status
Simulation time 667430809 ps
CPU time 3.4 seconds
Started Apr 04 02:09:56 PM PDT 24
Finished Apr 04 02:09:59 PM PDT 24
Peak memory 200800 kb
Host smart-34af83b7-9b7b-47f1-bd56-836e67fe78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082105865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2082105865
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.4268202509
Short name T814
Test name
Test status
Simulation time 652194740072 ps
CPU time 315.67 seconds
Started Apr 04 02:10:12 PM PDT 24
Finished Apr 04 02:15:28 PM PDT 24
Peak memory 200804 kb
Host smart-5e3d0859-758a-45ab-906f-5f58a84ebcad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268202509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.4268202509
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4027522872
Short name T907
Test name
Test status
Simulation time 6838371488 ps
CPU time 19.88 seconds
Started Apr 04 02:10:13 PM PDT 24
Finished Apr 04 02:10:33 PM PDT 24
Peak memory 200624 kb
Host smart-3f78e7fe-ad0f-47f7-85f7-2825a049fec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027522872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4027522872
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.665960485
Short name T522
Test name
Test status
Simulation time 96333327223 ps
CPU time 45.16 seconds
Started Apr 04 02:09:57 PM PDT 24
Finished Apr 04 02:10:42 PM PDT 24
Peak memory 200796 kb
Host smart-135c677a-938c-4dcd-9df8-a7db501eb20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665960485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.665960485
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3189963923
Short name T1066
Test name
Test status
Simulation time 35357148 ps
CPU time 0.54 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:10:27 PM PDT 24
Peak memory 195620 kb
Host smart-b626cadc-699e-4c82-818d-561681b0cc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189963923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3189963923
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.550586685
Short name T531
Test name
Test status
Simulation time 129800164082 ps
CPU time 188.75 seconds
Started Apr 04 02:10:10 PM PDT 24
Finished Apr 04 02:13:19 PM PDT 24
Peak memory 200836 kb
Host smart-3ad62cc9-d539-43ab-946f-1eef56d328aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550586685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.550586685
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2717878941
Short name T1079
Test name
Test status
Simulation time 53164889784 ps
CPU time 26.16 seconds
Started Apr 04 02:10:13 PM PDT 24
Finished Apr 04 02:10:39 PM PDT 24
Peak memory 200900 kb
Host smart-6798ad88-6408-4ead-b3d0-61e671a741f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717878941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2717878941
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.4029745532
Short name T436
Test name
Test status
Simulation time 108785502358 ps
CPU time 214.02 seconds
Started Apr 04 02:10:13 PM PDT 24
Finished Apr 04 02:13:47 PM PDT 24
Peak memory 200880 kb
Host smart-1c3a81e7-6a39-459c-95d5-3df8d6d0d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029745532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.4029745532
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3640125264
Short name T850
Test name
Test status
Simulation time 36904605650 ps
CPU time 62.66 seconds
Started Apr 04 02:10:10 PM PDT 24
Finished Apr 04 02:11:13 PM PDT 24
Peak memory 200804 kb
Host smart-753fd6ec-e56b-41b6-9fc6-eab7b7ed7cea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640125264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3640125264
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1803122556
Short name T964
Test name
Test status
Simulation time 40744679199 ps
CPU time 293.17 seconds
Started Apr 04 02:10:25 PM PDT 24
Finished Apr 04 02:15:19 PM PDT 24
Peak memory 200884 kb
Host smart-f31a98b2-eb5a-4354-945b-83da47b612cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803122556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1803122556
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3035960302
Short name T700
Test name
Test status
Simulation time 1336483675 ps
CPU time 1.29 seconds
Started Apr 04 02:10:12 PM PDT 24
Finished Apr 04 02:10:13 PM PDT 24
Peak memory 199280 kb
Host smart-5814db60-1ccb-401d-8f18-3ad6156c62d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035960302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3035960302
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.1914107703
Short name T477
Test name
Test status
Simulation time 12981840304 ps
CPU time 14.53 seconds
Started Apr 04 02:10:13 PM PDT 24
Finished Apr 04 02:10:28 PM PDT 24
Peak memory 197256 kb
Host smart-611b249d-79d6-4c52-8296-e2e63ed025e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914107703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1914107703
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3361984767
Short name T578
Test name
Test status
Simulation time 18637526901 ps
CPU time 875.81 seconds
Started Apr 04 02:10:25 PM PDT 24
Finished Apr 04 02:25:01 PM PDT 24
Peak memory 200904 kb
Host smart-64207b90-2255-4a3b-8852-9ae9ca66a8bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361984767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3361984767
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1826116848
Short name T912
Test name
Test status
Simulation time 3652481384 ps
CPU time 26.69 seconds
Started Apr 04 02:10:11 PM PDT 24
Finished Apr 04 02:10:38 PM PDT 24
Peak memory 198916 kb
Host smart-2d493e87-087a-41c3-8ea9-906de5113851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826116848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1826116848
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1047222064
Short name T441
Test name
Test status
Simulation time 154905137457 ps
CPU time 213.82 seconds
Started Apr 04 02:10:14 PM PDT 24
Finished Apr 04 02:13:48 PM PDT 24
Peak memory 200932 kb
Host smart-f1615612-834b-48bc-b8a2-d16b00ec0f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047222064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1047222064
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1083446334
Short name T785
Test name
Test status
Simulation time 2679410344 ps
CPU time 4.11 seconds
Started Apr 04 02:10:11 PM PDT 24
Finished Apr 04 02:10:16 PM PDT 24
Peak memory 196900 kb
Host smart-09de8874-a539-457a-9736-dde4ecd2242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083446334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1083446334
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4023580220
Short name T256
Test name
Test status
Simulation time 510618349 ps
CPU time 1.5 seconds
Started Apr 04 02:10:12 PM PDT 24
Finished Apr 04 02:10:14 PM PDT 24
Peak memory 199504 kb
Host smart-0865fcca-1dc5-4ab2-84fd-8b683f6078d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023580220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4023580220
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.303332168
Short name T846
Test name
Test status
Simulation time 92098192440 ps
CPU time 541.62 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:19:31 PM PDT 24
Peak memory 200852 kb
Host smart-281cf26a-a4ae-4d5d-aa7b-c054e35d6e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303332168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.303332168
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1252556373
Short name T1110
Test name
Test status
Simulation time 731136871 ps
CPU time 1.87 seconds
Started Apr 04 02:10:11 PM PDT 24
Finished Apr 04 02:10:13 PM PDT 24
Peak memory 199976 kb
Host smart-a24f18cb-0b64-4d29-b78a-e45e8c823e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252556373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1252556373
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1989407382
Short name T652
Test name
Test status
Simulation time 25966594238 ps
CPU time 15.29 seconds
Started Apr 04 02:10:14 PM PDT 24
Finished Apr 04 02:10:29 PM PDT 24
Peak memory 200892 kb
Host smart-8aba4050-41d7-4fcb-8569-1d15b3ce4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989407382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1989407382
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2104078049
Short name T564
Test name
Test status
Simulation time 20975068 ps
CPU time 0.55 seconds
Started Apr 04 02:10:33 PM PDT 24
Finished Apr 04 02:10:34 PM PDT 24
Peak memory 195992 kb
Host smart-041e6d9f-21c0-42e3-8d4d-20518e6b0283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104078049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2104078049
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.16691323
Short name T67
Test name
Test status
Simulation time 25635919401 ps
CPU time 56.63 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:23 PM PDT 24
Peak memory 200764 kb
Host smart-d7a376f1-75f0-4870-9e1b-7b90e90be5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16691323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.16691323
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3117694481
Short name T322
Test name
Test status
Simulation time 85438576435 ps
CPU time 70.58 seconds
Started Apr 04 02:10:25 PM PDT 24
Finished Apr 04 02:11:36 PM PDT 24
Peak memory 200848 kb
Host smart-15cfe67c-a193-457f-8649-cfdec9dd292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117694481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3117694481
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3879977208
Short name T1143
Test name
Test status
Simulation time 96472397767 ps
CPU time 51.9 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:18 PM PDT 24
Peak memory 200916 kb
Host smart-0d450d84-93fb-4187-aa9b-7cc6250518ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879977208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3879977208
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.3100870462
Short name T756
Test name
Test status
Simulation time 20475218147 ps
CPU time 8.45 seconds
Started Apr 04 02:10:24 PM PDT 24
Finished Apr 04 02:10:33 PM PDT 24
Peak memory 200768 kb
Host smart-53a6226a-3187-4869-b728-1eec710eefea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100870462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3100870462
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3350895024
Short name T1069
Test name
Test status
Simulation time 283321459052 ps
CPU time 138.46 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:12:47 PM PDT 24
Peak memory 200756 kb
Host smart-88dc9b77-2e77-4b97-8f68-0281aecb0426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350895024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3350895024
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.399887603
Short name T1062
Test name
Test status
Simulation time 183087071 ps
CPU time 0.98 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:10:27 PM PDT 24
Peak memory 196764 kb
Host smart-53a31bd5-59c1-4c0a-9488-3d55cba2335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399887603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.399887603
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1047109290
Short name T411
Test name
Test status
Simulation time 237601381302 ps
CPU time 149.95 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:12:56 PM PDT 24
Peak memory 199952 kb
Host smart-88e3af5c-99fa-4690-adb8-8f4f58de7c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047109290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1047109290
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2796893940
Short name T946
Test name
Test status
Simulation time 7875789271 ps
CPU time 319.62 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:15:46 PM PDT 24
Peak memory 200812 kb
Host smart-9e9b85f5-de13-4063-882f-a9d20c9a7a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796893940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2796893940
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2496578244
Short name T1043
Test name
Test status
Simulation time 4986209581 ps
CPU time 40.1 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:06 PM PDT 24
Peak memory 200188 kb
Host smart-ebbc6411-edc0-4c50-bebc-7db79b2f681a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2496578244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2496578244
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3849914817
Short name T668
Test name
Test status
Simulation time 202762616574 ps
CPU time 353.46 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:16:23 PM PDT 24
Peak memory 200892 kb
Host smart-8e483b81-173a-4cb2-a103-f687d47e62a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849914817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3849914817
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3214292297
Short name T537
Test name
Test status
Simulation time 3210686898 ps
CPU time 3.02 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:10:29 PM PDT 24
Peak memory 196828 kb
Host smart-4110997d-842c-4901-b30d-9c435e0f97c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214292297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3214292297
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2782002861
Short name T673
Test name
Test status
Simulation time 252703625 ps
CPU time 1.25 seconds
Started Apr 04 02:10:24 PM PDT 24
Finished Apr 04 02:10:26 PM PDT 24
Peak memory 199460 kb
Host smart-61d14e91-15a6-41cd-a95e-205567971599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782002861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2782002861
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1418750320
Short name T572
Test name
Test status
Simulation time 70629010055 ps
CPU time 258.43 seconds
Started Apr 04 02:10:27 PM PDT 24
Finished Apr 04 02:14:46 PM PDT 24
Peak memory 200888 kb
Host smart-317819e0-b241-4fd5-ab0b-acef8bace9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418750320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1418750320
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.539916070
Short name T725
Test name
Test status
Simulation time 108680903708 ps
CPU time 530.74 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:19:20 PM PDT 24
Peak memory 213352 kb
Host smart-53ea8b94-1870-4057-8f3b-e224d535686f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539916070 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.539916070
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2530291551
Short name T859
Test name
Test status
Simulation time 765800429 ps
CPU time 3.61 seconds
Started Apr 04 02:10:25 PM PDT 24
Finished Apr 04 02:10:29 PM PDT 24
Peak memory 199028 kb
Host smart-45358e05-d431-4d42-a46a-eb9b570464a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530291551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2530291551
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2272115414
Short name T893
Test name
Test status
Simulation time 33977387290 ps
CPU time 66.81 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:33 PM PDT 24
Peak memory 200880 kb
Host smart-ff058bfd-f73e-437c-bab3-006536b2f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272115414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2272115414
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3695528595
Short name T525
Test name
Test status
Simulation time 31886620 ps
CPU time 0.56 seconds
Started Apr 04 02:10:28 PM PDT 24
Finished Apr 04 02:10:29 PM PDT 24
Peak memory 196240 kb
Host smart-45171491-a362-4fe3-b225-79741617a060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695528595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3695528595
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2829447437
Short name T356
Test name
Test status
Simulation time 98706669004 ps
CPU time 161.38 seconds
Started Apr 04 02:10:33 PM PDT 24
Finished Apr 04 02:13:15 PM PDT 24
Peak memory 200728 kb
Host smart-d08e8857-c5ae-45a3-98a8-901a190f45a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829447437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2829447437
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1165759041
Short name T698
Test name
Test status
Simulation time 188604796053 ps
CPU time 132.82 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:12:42 PM PDT 24
Peak memory 200856 kb
Host smart-70d506cd-3f9b-4a01-a0db-665b4c2a1083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165759041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1165759041
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3840210120
Short name T41
Test name
Test status
Simulation time 284149310311 ps
CPU time 129.97 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:12:37 PM PDT 24
Peak memory 200796 kb
Host smart-7be67790-ba42-4288-b36f-8ba209a00260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840210120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3840210120
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.492171773
Short name T508
Test name
Test status
Simulation time 4022564284 ps
CPU time 6.04 seconds
Started Apr 04 02:10:33 PM PDT 24
Finished Apr 04 02:10:40 PM PDT 24
Peak memory 197340 kb
Host smart-b4884ab5-0b0d-4522-9d13-9c2aa9ddef45
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492171773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.492171773
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.37196029
Short name T391
Test name
Test status
Simulation time 118498160081 ps
CPU time 402.36 seconds
Started Apr 04 02:10:33 PM PDT 24
Finished Apr 04 02:17:15 PM PDT 24
Peak memory 200768 kb
Host smart-19ca3b0d-cd7f-4fa3-a5c7-1cae3538069c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37196029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.37196029
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.632644260
Short name T594
Test name
Test status
Simulation time 3484037556 ps
CPU time 1.26 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:10:30 PM PDT 24
Peak memory 197992 kb
Host smart-a6b3c836-4fd6-4cc2-9de7-ae4bb93335f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632644260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.632644260
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1298765660
Short name T500
Test name
Test status
Simulation time 90381980782 ps
CPU time 9.26 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:10:38 PM PDT 24
Peak memory 200844 kb
Host smart-ad37bc8c-ab7d-4750-873d-8662c885b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298765660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1298765660
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3724706975
Short name T1088
Test name
Test status
Simulation time 9670084004 ps
CPU time 138.82 seconds
Started Apr 04 02:10:32 PM PDT 24
Finished Apr 04 02:12:51 PM PDT 24
Peak memory 200704 kb
Host smart-4489cae1-9bc3-46ad-823d-eb23590f3f6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3724706975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3724706975
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2414249225
Short name T1084
Test name
Test status
Simulation time 7916364511 ps
CPU time 72.72 seconds
Started Apr 04 02:10:27 PM PDT 24
Finished Apr 04 02:11:40 PM PDT 24
Peak memory 200088 kb
Host smart-71987072-b983-45c0-8697-7cb0e1a6461c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414249225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2414249225
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.680512531
Short name T628
Test name
Test status
Simulation time 99105324401 ps
CPU time 40.79 seconds
Started Apr 04 02:10:29 PM PDT 24
Finished Apr 04 02:11:10 PM PDT 24
Peak memory 200840 kb
Host smart-c52916ec-3a5b-4cc2-b017-9a020dbb7f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680512531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.680512531
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3713250308
Short name T847
Test name
Test status
Simulation time 45745959651 ps
CPU time 71.92 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:38 PM PDT 24
Peak memory 196508 kb
Host smart-03bc1d46-3e03-49a9-bd7c-ed73b084500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713250308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3713250308
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3084971694
Short name T414
Test name
Test status
Simulation time 451639262 ps
CPU time 1.2 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:10:28 PM PDT 24
Peak memory 199612 kb
Host smart-43e1989b-71d9-49cb-9ecd-1f351a66f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084971694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3084971694
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3220561291
Short name T486
Test name
Test status
Simulation time 141310267272 ps
CPU time 63.91 seconds
Started Apr 04 02:10:32 PM PDT 24
Finished Apr 04 02:11:36 PM PDT 24
Peak memory 200704 kb
Host smart-50d024e9-b5b4-4f08-88f9-5165c41ca413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220561291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3220561291
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.237115083
Short name T162
Test name
Test status
Simulation time 49507520186 ps
CPU time 1016.6 seconds
Started Apr 04 02:10:34 PM PDT 24
Finished Apr 04 02:27:31 PM PDT 24
Peak memory 229080 kb
Host smart-a1592384-7c53-4540-ac29-f35a6297df57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237115083 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.237115083
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3775575614
Short name T495
Test name
Test status
Simulation time 1047926527 ps
CPU time 2.26 seconds
Started Apr 04 02:10:32 PM PDT 24
Finished Apr 04 02:10:35 PM PDT 24
Peak memory 199312 kb
Host smart-a472ea61-d742-4544-b80d-9c3af67be3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775575614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3775575614
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.608154459
Short name T444
Test name
Test status
Simulation time 114213041021 ps
CPU time 79.29 seconds
Started Apr 04 02:10:25 PM PDT 24
Finished Apr 04 02:11:45 PM PDT 24
Peak memory 200852 kb
Host smart-d4fcb074-9930-4fad-90d5-5c3980d194a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608154459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.608154459
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.665100251
Short name T515
Test name
Test status
Simulation time 25662999 ps
CPU time 0.54 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:10:38 PM PDT 24
Peak memory 195680 kb
Host smart-b3f9edad-6984-4a53-abc9-443ac26d6b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665100251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.665100251
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2952956811
Short name T463
Test name
Test status
Simulation time 59858320040 ps
CPU time 45.81 seconds
Started Apr 04 02:10:28 PM PDT 24
Finished Apr 04 02:11:14 PM PDT 24
Peak memory 200672 kb
Host smart-0d51b1bc-dc6a-44d2-b80a-64043a85be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952956811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2952956811
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2897417508
Short name T545
Test name
Test status
Simulation time 41941900878 ps
CPU time 17.43 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:10:55 PM PDT 24
Peak memory 200904 kb
Host smart-4626c321-78a6-4e3a-a95d-17376f06e635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897417508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2897417508
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.3334901790
Short name T788
Test name
Test status
Simulation time 271998494271 ps
CPU time 379.11 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:16:56 PM PDT 24
Peak memory 198140 kb
Host smart-ec5bb59a-aa8d-4f3e-ada5-afd5e7990a0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334901790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3334901790
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3874911592
Short name T348
Test name
Test status
Simulation time 245597822003 ps
CPU time 263.21 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:15:01 PM PDT 24
Peak memory 200776 kb
Host smart-895f12ce-2b8e-4d14-af69-9a18d3e5156f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874911592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3874911592
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.306466550
Short name T550
Test name
Test status
Simulation time 5268226099 ps
CPU time 3.48 seconds
Started Apr 04 02:10:38 PM PDT 24
Finished Apr 04 02:10:42 PM PDT 24
Peak memory 200380 kb
Host smart-ed16c4a4-3956-429f-be47-1363d6377adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306466550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.306466550
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.2448503225
Short name T1132
Test name
Test status
Simulation time 74119783965 ps
CPU time 69.45 seconds
Started Apr 04 02:10:41 PM PDT 24
Finished Apr 04 02:11:51 PM PDT 24
Peak memory 200320 kb
Host smart-d67b0511-81b8-4b82-9107-11bd1739837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448503225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2448503225
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2278055144
Short name T265
Test name
Test status
Simulation time 12862125675 ps
CPU time 486.59 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:18:44 PM PDT 24
Peak memory 200896 kb
Host smart-e3b5c3da-b12c-4611-9b3a-3c4eb9f0678b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2278055144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2278055144
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4056346097
Short name T1096
Test name
Test status
Simulation time 7530256536 ps
CPU time 12.2 seconds
Started Apr 04 02:10:38 PM PDT 24
Finished Apr 04 02:10:51 PM PDT 24
Peak memory 199968 kb
Host smart-b13abda7-40b8-4bb7-93e2-f36d778d4245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056346097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4056346097
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1826416710
Short name T596
Test name
Test status
Simulation time 67691475714 ps
CPU time 26.11 seconds
Started Apr 04 02:10:36 PM PDT 24
Finished Apr 04 02:11:02 PM PDT 24
Peak memory 200132 kb
Host smart-0c644ef4-feab-42e0-9f55-a92d77497ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826416710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1826416710
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3428723096
Short name T7
Test name
Test status
Simulation time 2105718631 ps
CPU time 2.28 seconds
Started Apr 04 02:10:38 PM PDT 24
Finished Apr 04 02:10:41 PM PDT 24
Peak memory 196272 kb
Host smart-12000632-798a-4de3-be20-4bf7b37638c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428723096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3428723096
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3040167893
Short name T732
Test name
Test status
Simulation time 138680803 ps
CPU time 0.89 seconds
Started Apr 04 02:10:32 PM PDT 24
Finished Apr 04 02:10:33 PM PDT 24
Peak memory 199936 kb
Host smart-a334620f-b311-4aa4-b862-b31f77d002c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040167893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3040167893
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1532563212
Short name T809
Test name
Test status
Simulation time 315143626280 ps
CPU time 724.37 seconds
Started Apr 04 02:10:42 PM PDT 24
Finished Apr 04 02:22:47 PM PDT 24
Peak memory 200700 kb
Host smart-d9152c31-c5cc-4e59-886d-578da51583d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532563212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1532563212
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1025364284
Short name T385
Test name
Test status
Simulation time 1005451262 ps
CPU time 1.65 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:10:39 PM PDT 24
Peak memory 199344 kb
Host smart-fa80825d-9608-4883-a46f-f3a9ccea195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025364284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1025364284
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1326576727
Short name T512
Test name
Test status
Simulation time 91001766906 ps
CPU time 68.08 seconds
Started Apr 04 02:10:26 PM PDT 24
Finished Apr 04 02:11:35 PM PDT 24
Peak memory 200784 kb
Host smart-0f0a8316-d659-4524-9ac1-d6decb6ba775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326576727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1326576727
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3345612770
Short name T941
Test name
Test status
Simulation time 34340727 ps
CPU time 0.56 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:06:27 PM PDT 24
Peak memory 196196 kb
Host smart-59ace53b-7e4c-443f-b14c-4e31c63f2c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345612770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3345612770
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2354550529
Short name T269
Test name
Test status
Simulation time 51128209095 ps
CPU time 77.97 seconds
Started Apr 04 02:06:20 PM PDT 24
Finished Apr 04 02:07:39 PM PDT 24
Peak memory 200892 kb
Host smart-babf84bc-25db-446a-a67a-0400d8602e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354550529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2354550529
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4176316486
Short name T428
Test name
Test status
Simulation time 28611624847 ps
CPU time 45.03 seconds
Started Apr 04 02:06:15 PM PDT 24
Finished Apr 04 02:07:00 PM PDT 24
Peak memory 200496 kb
Host smart-839dfa3c-3219-4c04-b247-1423f2f3ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176316486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4176316486
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.100222236
Short name T156
Test name
Test status
Simulation time 159588649625 ps
CPU time 275.53 seconds
Started Apr 04 02:06:22 PM PDT 24
Finished Apr 04 02:10:58 PM PDT 24
Peak memory 200824 kb
Host smart-7f9f2355-ed41-4c3b-9cdb-e8ea352d1821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100222236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.100222236
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1459576255
Short name T464
Test name
Test status
Simulation time 240443453469 ps
CPU time 204.22 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:09:44 PM PDT 24
Peak memory 199948 kb
Host smart-bd941f5b-9976-4fc9-b3a3-0a55e3dc50c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459576255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1459576255
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1210638549
Short name T1082
Test name
Test status
Simulation time 138467858220 ps
CPU time 1360.03 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:29:08 PM PDT 24
Peak memory 200780 kb
Host smart-7e03ca64-55a9-49f9-b143-ddec646c4e4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1210638549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1210638549
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.238346713
Short name T822
Test name
Test status
Simulation time 6619636056 ps
CPU time 12.8 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:06:28 PM PDT 24
Peak memory 197224 kb
Host smart-06abc9a6-0aca-4b9d-98d2-90101bdba1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238346713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.238346713
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1902839446
Short name T971
Test name
Test status
Simulation time 129345287108 ps
CPU time 39.41 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:06:54 PM PDT 24
Peak memory 199588 kb
Host smart-fb4ab8ee-99de-4f59-a25a-0c5c64a244dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902839446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1902839446
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2125653655
Short name T379
Test name
Test status
Simulation time 6735424274 ps
CPU time 195.99 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:09:36 PM PDT 24
Peak memory 200860 kb
Host smart-b7558370-4236-4125-8955-456583ba70f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2125653655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2125653655
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2088931216
Short name T635
Test name
Test status
Simulation time 4146795499 ps
CPU time 8.17 seconds
Started Apr 04 02:06:15 PM PDT 24
Finished Apr 04 02:06:23 PM PDT 24
Peak memory 198920 kb
Host smart-f48ea5cc-7549-4e0a-8cfd-372442bcaae6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088931216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2088931216
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1065470469
Short name T44
Test name
Test status
Simulation time 26692872742 ps
CPU time 21.47 seconds
Started Apr 04 02:06:15 PM PDT 24
Finished Apr 04 02:06:37 PM PDT 24
Peak memory 200876 kb
Host smart-41ca6505-dd2f-4c01-9251-e160ce8a1e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065470469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1065470469
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1064034123
Short name T978
Test name
Test status
Simulation time 3615051560 ps
CPU time 6.34 seconds
Started Apr 04 02:06:23 PM PDT 24
Finished Apr 04 02:06:30 PM PDT 24
Peak memory 196792 kb
Host smart-bc327a96-77a2-487e-a969-bfc9f5c3ae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064034123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1064034123
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2523162648
Short name T31
Test name
Test status
Simulation time 234488795 ps
CPU time 0.86 seconds
Started Apr 04 02:06:30 PM PDT 24
Finished Apr 04 02:06:31 PM PDT 24
Peak memory 218948 kb
Host smart-6a8c9844-8a43-4a8d-bfe1-bf5b3131a0a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523162648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2523162648
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.659951208
Short name T808
Test name
Test status
Simulation time 496802151 ps
CPU time 1.25 seconds
Started Apr 04 02:06:22 PM PDT 24
Finished Apr 04 02:06:24 PM PDT 24
Peak memory 200096 kb
Host smart-c64a5bc5-7598-4894-bca0-a66ffbc880f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659951208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.659951208
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2539323519
Short name T872
Test name
Test status
Simulation time 94699847689 ps
CPU time 558.23 seconds
Started Apr 04 02:06:28 PM PDT 24
Finished Apr 04 02:15:47 PM PDT 24
Peak memory 200860 kb
Host smart-f9cbebef-3504-4854-b2a4-bf99a3e83509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539323519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2539323519
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1999354842
Short name T1133
Test name
Test status
Simulation time 177733406576 ps
CPU time 714.88 seconds
Started Apr 04 02:06:25 PM PDT 24
Finished Apr 04 02:18:20 PM PDT 24
Peak memory 217508 kb
Host smart-9cb33f91-c3a7-43f6-bcd1-57ff95aca69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999354842 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1999354842
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1143489998
Short name T423
Test name
Test status
Simulation time 497022780 ps
CPU time 1.48 seconds
Started Apr 04 02:06:14 PM PDT 24
Finished Apr 04 02:06:16 PM PDT 24
Peak memory 199520 kb
Host smart-2a4885b8-03b5-4352-8482-831982fe8ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143489998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1143489998
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.896612040
Short name T599
Test name
Test status
Simulation time 180509826271 ps
CPU time 190.27 seconds
Started Apr 04 02:06:19 PM PDT 24
Finished Apr 04 02:09:29 PM PDT 24
Peak memory 200728 kb
Host smart-04425ee3-9e10-41ec-a4d0-5c8f49ccc256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896612040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.896612040
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4272608819
Short name T452
Test name
Test status
Simulation time 14688828 ps
CPU time 0.54 seconds
Started Apr 04 02:10:55 PM PDT 24
Finished Apr 04 02:10:56 PM PDT 24
Peak memory 196196 kb
Host smart-a6d8a1c8-ab3f-4ceb-ab19-86e1c518872c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272608819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4272608819
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.94023826
Short name T772
Test name
Test status
Simulation time 177780359953 ps
CPU time 47.17 seconds
Started Apr 04 02:10:40 PM PDT 24
Finished Apr 04 02:11:28 PM PDT 24
Peak memory 200784 kb
Host smart-4abcf1cc-a2c7-42eb-8824-fc4daa79e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94023826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.94023826
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2121365638
Short name T48
Test name
Test status
Simulation time 114980496429 ps
CPU time 251.87 seconds
Started Apr 04 02:10:41 PM PDT 24
Finished Apr 04 02:14:54 PM PDT 24
Peak memory 200616 kb
Host smart-24187e39-657b-4b07-8b64-3eaeb674982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121365638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2121365638
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1877351064
Short name T950
Test name
Test status
Simulation time 348226355214 ps
CPU time 46.34 seconds
Started Apr 04 02:10:39 PM PDT 24
Finished Apr 04 02:11:26 PM PDT 24
Peak memory 200892 kb
Host smart-13f221ff-ee60-494b-ae23-e8c3a07fab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877351064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1877351064
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.382147735
Short name T343
Test name
Test status
Simulation time 12195253217 ps
CPU time 12.44 seconds
Started Apr 04 02:10:39 PM PDT 24
Finished Apr 04 02:10:52 PM PDT 24
Peak memory 200864 kb
Host smart-cc6e5404-1bb7-4e53-8309-91922327fc1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382147735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.382147735
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_loopback.297005490
Short name T880
Test name
Test status
Simulation time 11640095365 ps
CPU time 9.06 seconds
Started Apr 04 02:10:46 PM PDT 24
Finished Apr 04 02:10:55 PM PDT 24
Peak memory 200732 kb
Host smart-bdb48aa2-30d6-43ff-8244-9b12d0e7e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297005490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.297005490
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.390505159
Short name T1123
Test name
Test status
Simulation time 83368397231 ps
CPU time 37.57 seconds
Started Apr 04 02:10:46 PM PDT 24
Finished Apr 04 02:11:24 PM PDT 24
Peak memory 201016 kb
Host smart-ea6be1a7-82e5-4a19-ab93-97c866e91c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390505159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.390505159
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.152566742
Short name T484
Test name
Test status
Simulation time 18821834501 ps
CPU time 487.67 seconds
Started Apr 04 02:10:46 PM PDT 24
Finished Apr 04 02:18:54 PM PDT 24
Peak memory 200772 kb
Host smart-91a95e07-0307-4dc3-8970-3e6e4ec30ce7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152566742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.152566742
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3530691516
Short name T1137
Test name
Test status
Simulation time 3995729131 ps
CPU time 8.69 seconds
Started Apr 04 02:10:38 PM PDT 24
Finished Apr 04 02:10:47 PM PDT 24
Peak memory 199652 kb
Host smart-57dbe687-0aca-4dde-912a-f0962aaeed01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530691516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3530691516
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.997566808
Short name T870
Test name
Test status
Simulation time 107627124066 ps
CPU time 88.57 seconds
Started Apr 04 02:10:58 PM PDT 24
Finished Apr 04 02:12:27 PM PDT 24
Peak memory 200780 kb
Host smart-7ad7e450-3fd7-4764-936d-e0a94f9eef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997566808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.997566808
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.400882098
Short name T701
Test name
Test status
Simulation time 37155427199 ps
CPU time 9.76 seconds
Started Apr 04 02:10:46 PM PDT 24
Finished Apr 04 02:10:56 PM PDT 24
Peak memory 196564 kb
Host smart-bb955a8e-993d-4adb-9d82-632230e4ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400882098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.400882098
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1549790728
Short name T474
Test name
Test status
Simulation time 491255063 ps
CPU time 2.88 seconds
Started Apr 04 02:10:42 PM PDT 24
Finished Apr 04 02:10:46 PM PDT 24
Peak memory 199304 kb
Host smart-f47fc5fd-9a1c-47b5-81fb-f426ff0e294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549790728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1549790728
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.540119108
Short name T1080
Test name
Test status
Simulation time 215915405567 ps
CPU time 100.1 seconds
Started Apr 04 02:10:37 PM PDT 24
Finished Apr 04 02:12:18 PM PDT 24
Peak memory 201052 kb
Host smart-56da0e00-097e-458d-9568-a8e3e2994721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540119108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.540119108
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2330298315
Short name T764
Test name
Test status
Simulation time 329124274977 ps
CPU time 582.1 seconds
Started Apr 04 02:10:40 PM PDT 24
Finished Apr 04 02:20:22 PM PDT 24
Peak memory 225752 kb
Host smart-09d46837-4661-4841-832e-c0b59ae1c40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330298315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2330298315
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2389011178
Short name T629
Test name
Test status
Simulation time 617968937 ps
CPU time 2.16 seconds
Started Apr 04 02:10:42 PM PDT 24
Finished Apr 04 02:10:45 PM PDT 24
Peak memory 199384 kb
Host smart-9a4b81fd-5ee7-497d-b083-4d069525ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389011178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2389011178
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.468262223
Short name T769
Test name
Test status
Simulation time 23289350568 ps
CPU time 12.13 seconds
Started Apr 04 02:10:39 PM PDT 24
Finished Apr 04 02:10:52 PM PDT 24
Peak memory 200768 kb
Host smart-f302930b-5ee1-40dd-940a-28eb3f05e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468262223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.468262223
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1204907349
Short name T443
Test name
Test status
Simulation time 36393149 ps
CPU time 0.54 seconds
Started Apr 04 02:11:01 PM PDT 24
Finished Apr 04 02:11:02 PM PDT 24
Peak memory 196212 kb
Host smart-59e3aa87-94b4-4177-b383-fdfc7ddf5210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204907349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1204907349
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2648810881
Short name T711
Test name
Test status
Simulation time 99703738774 ps
CPU time 38.28 seconds
Started Apr 04 02:10:54 PM PDT 24
Finished Apr 04 02:11:33 PM PDT 24
Peak memory 200880 kb
Host smart-aea1f226-f859-4ca3-b348-c564c2c9bb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648810881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2648810881
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2958424737
Short name T251
Test name
Test status
Simulation time 115202928632 ps
CPU time 58.06 seconds
Started Apr 04 02:10:54 PM PDT 24
Finished Apr 04 02:11:53 PM PDT 24
Peak memory 200896 kb
Host smart-f285d529-175d-4d46-8d25-5edabc0340c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958424737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2958424737
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2962149768
Short name T1168
Test name
Test status
Simulation time 141586516034 ps
CPU time 220.31 seconds
Started Apr 04 02:10:51 PM PDT 24
Finished Apr 04 02:14:32 PM PDT 24
Peak memory 200824 kb
Host smart-b0a95487-ca90-41d0-a69d-4f9731e68b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962149768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2962149768
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1705106785
Short name T249
Test name
Test status
Simulation time 303122632015 ps
CPU time 977.61 seconds
Started Apr 04 02:10:58 PM PDT 24
Finished Apr 04 02:27:17 PM PDT 24
Peak memory 200880 kb
Host smart-ce490ae3-4e87-4411-9145-9e74ed68c3bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705106785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1705106785
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4226576623
Short name T418
Test name
Test status
Simulation time 68671758493 ps
CPU time 74.64 seconds
Started Apr 04 02:10:56 PM PDT 24
Finished Apr 04 02:12:12 PM PDT 24
Peak memory 200776 kb
Host smart-e9ffcf27-57b0-429a-ae46-115e11c84b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226576623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4226576623
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1017857303
Short name T478
Test name
Test status
Simulation time 8613157809 ps
CPU time 5 seconds
Started Apr 04 02:10:50 PM PDT 24
Finished Apr 04 02:10:56 PM PDT 24
Peak memory 200440 kb
Host smart-d9e7d23b-2c67-46e0-b5f9-68929557bc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017857303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1017857303
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1672290585
Short name T507
Test name
Test status
Simulation time 132456043310 ps
CPU time 77.58 seconds
Started Apr 04 02:10:55 PM PDT 24
Finished Apr 04 02:12:12 PM PDT 24
Peak memory 200968 kb
Host smart-c9325edc-a375-4e89-aed8-c3e61e600b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672290585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1672290585
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2317078432
Short name T645
Test name
Test status
Simulation time 31397686972 ps
CPU time 1513.71 seconds
Started Apr 04 02:10:55 PM PDT 24
Finished Apr 04 02:36:09 PM PDT 24
Peak memory 200920 kb
Host smart-7c37b69b-fc73-46fd-b1fd-9ac0de0fabe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317078432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2317078432
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3610395439
Short name T422
Test name
Test status
Simulation time 1397287475 ps
CPU time 1.89 seconds
Started Apr 04 02:10:54 PM PDT 24
Finished Apr 04 02:10:57 PM PDT 24
Peak memory 198912 kb
Host smart-cc2e0b78-cdc5-4781-8d95-904c3db4346c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610395439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3610395439
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.979907890
Short name T606
Test name
Test status
Simulation time 70487293814 ps
CPU time 124.88 seconds
Started Apr 04 02:10:48 PM PDT 24
Finished Apr 04 02:12:53 PM PDT 24
Peak memory 200744 kb
Host smart-8f8af957-0720-4382-99df-709c6faa4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979907890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.979907890
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2830151266
Short name T687
Test name
Test status
Simulation time 3524287953 ps
CPU time 3.29 seconds
Started Apr 04 02:10:50 PM PDT 24
Finished Apr 04 02:10:54 PM PDT 24
Peak memory 196916 kb
Host smart-524561d7-0fa7-49f8-a022-12dda27b2f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830151266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2830151266
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2920054752
Short name T881
Test name
Test status
Simulation time 681164426 ps
CPU time 1.46 seconds
Started Apr 04 02:10:51 PM PDT 24
Finished Apr 04 02:10:53 PM PDT 24
Peak memory 200268 kb
Host smart-aa797ad9-4d9c-4c0f-abd4-1b5114810a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920054752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2920054752
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2656399592
Short name T986
Test name
Test status
Simulation time 77555111451 ps
CPU time 34.74 seconds
Started Apr 04 02:10:55 PM PDT 24
Finished Apr 04 02:11:31 PM PDT 24
Peak memory 200840 kb
Host smart-abc8ffb7-cf7a-468c-a9fe-e3016f332230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656399592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2656399592
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.551858527
Short name T716
Test name
Test status
Simulation time 59527996659 ps
CPU time 961.9 seconds
Started Apr 04 02:10:50 PM PDT 24
Finished Apr 04 02:26:52 PM PDT 24
Peak memory 217540 kb
Host smart-a742a624-a8bd-4534-a46d-f8fec50bf7be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551858527 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.551858527
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.953570293
Short name T413
Test name
Test status
Simulation time 1264107069 ps
CPU time 3.09 seconds
Started Apr 04 02:10:55 PM PDT 24
Finished Apr 04 02:10:59 PM PDT 24
Peak memory 199672 kb
Host smart-e3a59390-843f-44dc-863a-b6c63069b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953570293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.953570293
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3896499725
Short name T303
Test name
Test status
Simulation time 25252257852 ps
CPU time 41.91 seconds
Started Apr 04 02:10:50 PM PDT 24
Finished Apr 04 02:11:32 PM PDT 24
Peak memory 200796 kb
Host smart-b328bda2-78e7-4212-b387-534d0e0c41e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896499725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3896499725
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.4140404682
Short name T1048
Test name
Test status
Simulation time 22775062 ps
CPU time 0.55 seconds
Started Apr 04 02:11:10 PM PDT 24
Finished Apr 04 02:11:11 PM PDT 24
Peak memory 195620 kb
Host smart-37c70963-3598-41eb-965d-3104e20ef03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140404682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.4140404682
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2784320875
Short name T904
Test name
Test status
Simulation time 49809367851 ps
CPU time 23.36 seconds
Started Apr 04 02:11:10 PM PDT 24
Finished Apr 04 02:11:34 PM PDT 24
Peak memory 200872 kb
Host smart-2da5a3a3-b675-48c4-97b6-10dcc3e1a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784320875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2784320875
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.811936841
Short name T473
Test name
Test status
Simulation time 145736912404 ps
CPU time 208.13 seconds
Started Apr 04 02:11:03 PM PDT 24
Finished Apr 04 02:14:32 PM PDT 24
Peak memory 200868 kb
Host smart-bdeb9972-7253-409c-84c5-c59f3a0ce690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811936841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.811936841
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1354174718
Short name T229
Test name
Test status
Simulation time 118198091335 ps
CPU time 124.74 seconds
Started Apr 04 02:11:01 PM PDT 24
Finished Apr 04 02:13:07 PM PDT 24
Peak memory 200864 kb
Host smart-235e25b3-09a3-4179-9818-af1025e3ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354174718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1354174718
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2529575995
Short name T731
Test name
Test status
Simulation time 172061661305 ps
CPU time 112.33 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:12:54 PM PDT 24
Peak memory 200848 kb
Host smart-afb4ed10-7a8f-4d29-a173-17c41f1f31e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529575995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2529575995
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2098121807
Short name T270
Test name
Test status
Simulation time 28762781302 ps
CPU time 49.89 seconds
Started Apr 04 02:11:03 PM PDT 24
Finished Apr 04 02:11:53 PM PDT 24
Peak memory 200796 kb
Host smart-47f625c2-6fde-45c0-a8b8-e4337403d92a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2098121807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2098121807
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1294885559
Short name T353
Test name
Test status
Simulation time 12972840454 ps
CPU time 14.74 seconds
Started Apr 04 02:11:03 PM PDT 24
Finished Apr 04 02:11:17 PM PDT 24
Peak memory 200792 kb
Host smart-4a1eb4b8-6878-4e84-b005-69d5b65362e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294885559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1294885559
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1030252840
Short name T1128
Test name
Test status
Simulation time 227232026571 ps
CPU time 135.48 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:13:17 PM PDT 24
Peak memory 201064 kb
Host smart-12b46dc6-f852-470d-96ef-ecc03ab838d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030252840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1030252840
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.573380027
Short name T820
Test name
Test status
Simulation time 11919697366 ps
CPU time 673.75 seconds
Started Apr 04 02:11:04 PM PDT 24
Finished Apr 04 02:22:18 PM PDT 24
Peak memory 200660 kb
Host smart-43362b68-845c-4c65-82ca-c01c7dbc871e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573380027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.573380027
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.952365745
Short name T722
Test name
Test status
Simulation time 2984293191 ps
CPU time 5.37 seconds
Started Apr 04 02:11:10 PM PDT 24
Finished Apr 04 02:11:15 PM PDT 24
Peak memory 199760 kb
Host smart-82a753e1-0c38-428d-8445-87ab586b028c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952365745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.952365745
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3875260744
Short name T848
Test name
Test status
Simulation time 34610817211 ps
CPU time 69.39 seconds
Started Apr 04 02:11:04 PM PDT 24
Finished Apr 04 02:12:14 PM PDT 24
Peak memory 200932 kb
Host smart-9b9d5f04-a942-4412-aa3a-a48cb6c5154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875260744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3875260744
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4150120807
Short name T275
Test name
Test status
Simulation time 36045129697 ps
CPU time 61.01 seconds
Started Apr 04 02:11:05 PM PDT 24
Finished Apr 04 02:12:06 PM PDT 24
Peak memory 196448 kb
Host smart-4b2803cb-a346-4b4f-9ccb-981b488eb3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150120807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4150120807
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2344531561
Short name T100
Test name
Test status
Simulation time 5906544820 ps
CPU time 13.35 seconds
Started Apr 04 02:11:01 PM PDT 24
Finished Apr 04 02:11:15 PM PDT 24
Peak memory 200340 kb
Host smart-6fb5c76b-0946-43ec-b716-92513528436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344531561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2344531561
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3280801596
Short name T618
Test name
Test status
Simulation time 95933447594 ps
CPU time 1637.98 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:38:21 PM PDT 24
Peak memory 209272 kb
Host smart-18602747-5c90-4e14-85a5-29e5ce4c32fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280801596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3280801596
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2280480620
Short name T438
Test name
Test status
Simulation time 13261984222 ps
CPU time 17.84 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:11:20 PM PDT 24
Peak memory 200800 kb
Host smart-1c9fe2f7-29ee-4b26-a91f-4fecf274ad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280480620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2280480620
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.430817764
Short name T608
Test name
Test status
Simulation time 106297110829 ps
CPU time 48.74 seconds
Started Apr 04 02:11:03 PM PDT 24
Finished Apr 04 02:11:52 PM PDT 24
Peak memory 200800 kb
Host smart-18d2076d-78bc-4ac4-8539-cb9a39b3818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430817764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.430817764
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2088780156
Short name T527
Test name
Test status
Simulation time 42108025 ps
CPU time 0.55 seconds
Started Apr 04 02:11:25 PM PDT 24
Finished Apr 04 02:11:26 PM PDT 24
Peak memory 196096 kb
Host smart-3ba7f9bf-191a-4d1a-a10e-78c0f9f48d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088780156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2088780156
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3722648086
Short name T593
Test name
Test status
Simulation time 44564773441 ps
CPU time 28.72 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:11:31 PM PDT 24
Peak memory 200636 kb
Host smart-9572bc1b-1798-4215-8b34-8b4b37c4b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722648086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3722648086
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2365317250
Short name T116
Test name
Test status
Simulation time 158794812866 ps
CPU time 277.86 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:15:40 PM PDT 24
Peak memory 200796 kb
Host smart-524363ba-14d3-4a04-af3e-fdbace65277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365317250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2365317250
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3137833990
Short name T203
Test name
Test status
Simulation time 117544312359 ps
CPU time 86.28 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:12:29 PM PDT 24
Peak memory 200880 kb
Host smart-fc2536c1-c022-48ff-b663-516eb2484557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137833990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3137833990
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3524440250
Short name T867
Test name
Test status
Simulation time 21262147186 ps
CPU time 7.32 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:11:09 PM PDT 24
Peak memory 198924 kb
Host smart-3479058e-bc91-4a1b-a618-3f5452e44216
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524440250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3524440250
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.541332542
Short name T1064
Test name
Test status
Simulation time 91206172259 ps
CPU time 581.34 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:21:10 PM PDT 24
Peak memory 200884 kb
Host smart-8ba19a7c-a545-445e-89ac-0442aea68376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541332542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.541332542
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1039744540
Short name T429
Test name
Test status
Simulation time 363796022 ps
CPU time 0.59 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:26 PM PDT 24
Peak memory 196496 kb
Host smart-8bc6085c-8fa7-4d61-ac59-094dde499327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039744540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1039744540
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.897407605
Short name T712
Test name
Test status
Simulation time 76507684803 ps
CPU time 66.26 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:12:08 PM PDT 24
Peak memory 201072 kb
Host smart-1f20b206-39d3-48ca-8a4c-52e46a63aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897407605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.897407605
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2256278298
Short name T879
Test name
Test status
Simulation time 9562478968 ps
CPU time 130.6 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:13:37 PM PDT 24
Peak memory 200892 kb
Host smart-b20d383e-8592-4261-b6ff-1e45ff159414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256278298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2256278298
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1229830805
Short name T18
Test name
Test status
Simulation time 7246014482 ps
CPU time 60.83 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:12:03 PM PDT 24
Peak memory 200736 kb
Host smart-e1aa624f-fae5-48c1-b642-75cd2940217a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229830805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1229830805
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1684002051
Short name T574
Test name
Test status
Simulation time 36261989293 ps
CPU time 14.85 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:41 PM PDT 24
Peak memory 200816 kb
Host smart-6ed99000-de2f-4b10-b2a1-a57acb688ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684002051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1684002051
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3837033077
Short name T619
Test name
Test status
Simulation time 4709033264 ps
CPU time 4.56 seconds
Started Apr 04 02:11:10 PM PDT 24
Finished Apr 04 02:11:15 PM PDT 24
Peak memory 197048 kb
Host smart-c726cb50-d169-4cbe-a0a6-fecc08954d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837033077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3837033077
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1571036641
Short name T280
Test name
Test status
Simulation time 712851062 ps
CPU time 2.56 seconds
Started Apr 04 02:11:02 PM PDT 24
Finished Apr 04 02:11:05 PM PDT 24
Peak memory 199592 kb
Host smart-ab52565f-ff5b-40a0-9f93-9127f30885e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571036641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1571036641
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2052707979
Short name T298
Test name
Test status
Simulation time 224714720096 ps
CPU time 530.97 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:20:18 PM PDT 24
Peak memory 217444 kb
Host smart-26ccd213-4a77-40be-bc80-328cad0bb468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052707979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2052707979
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.697121727
Short name T684
Test name
Test status
Simulation time 2715804086 ps
CPU time 1.88 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:11:29 PM PDT 24
Peak memory 199908 kb
Host smart-29740148-faa0-4b30-a5a0-1a4480e44201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697121727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.697121727
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1073893379
Short name T297
Test name
Test status
Simulation time 44786354116 ps
CPU time 28.24 seconds
Started Apr 04 02:11:01 PM PDT 24
Finished Apr 04 02:11:30 PM PDT 24
Peak memory 200868 kb
Host smart-af795e51-416b-4ec3-88e3-561d34b58296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073893379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1073893379
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2716422913
Short name T514
Test name
Test status
Simulation time 18468859 ps
CPU time 0.57 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:29 PM PDT 24
Peak memory 196212 kb
Host smart-e142c1bf-f9e5-4f43-997a-bfc9a0ee77b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716422913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2716422913
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1368139071
Short name T954
Test name
Test status
Simulation time 12548474688 ps
CPU time 12.17 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:11:40 PM PDT 24
Peak memory 200896 kb
Host smart-920f28af-00ee-43d4-922e-a6ccce5b4015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368139071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1368139071
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2791969796
Short name T1070
Test name
Test status
Simulation time 96163828383 ps
CPU time 168.74 seconds
Started Apr 04 02:11:29 PM PDT 24
Finished Apr 04 02:14:18 PM PDT 24
Peak memory 200920 kb
Host smart-9abf5e0e-cd36-401d-8831-5f32fd23f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791969796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2791969796
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1203211262
Short name T105
Test name
Test status
Simulation time 40965125930 ps
CPU time 68.47 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:12:35 PM PDT 24
Peak memory 200844 kb
Host smart-d1043f48-5c3b-49e1-a9be-d8c2b33729ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203211262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1203211262
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3815021946
Short name T1010
Test name
Test status
Simulation time 50668824142 ps
CPU time 73.74 seconds
Started Apr 04 02:11:31 PM PDT 24
Finished Apr 04 02:12:45 PM PDT 24
Peak memory 200800 kb
Host smart-86018e56-b7b4-4f0f-8406-07501eff245f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815021946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3815021946
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4141347347
Short name T706
Test name
Test status
Simulation time 163769174207 ps
CPU time 628.32 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:21:55 PM PDT 24
Peak memory 200892 kb
Host smart-6c9d7f1a-750b-41ae-92fa-e61f390101a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141347347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4141347347
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3888253605
Short name T45
Test name
Test status
Simulation time 1431832975 ps
CPU time 1.59 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:30 PM PDT 24
Peak memory 196528 kb
Host smart-36511b6f-3202-4d98-9660-02cde8f41163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888253605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3888253605
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2890163906
Short name T451
Test name
Test status
Simulation time 28710148591 ps
CPU time 20.56 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:46 PM PDT 24
Peak memory 199284 kb
Host smart-38417e55-731c-406f-8dc7-6b98ba1101c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890163906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2890163906
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.373388790
Short name T987
Test name
Test status
Simulation time 19950193069 ps
CPU time 412.13 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:18:20 PM PDT 24
Peak memory 200904 kb
Host smart-9e04a9b4-2d90-4271-a3c5-1a1d08f5ce97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=373388790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.373388790
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.415247624
Short name T1078
Test name
Test status
Simulation time 4517697868 ps
CPU time 40.27 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:12:07 PM PDT 24
Peak memory 199056 kb
Host smart-304a87b1-bb08-4247-9614-00b6c00c1bc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415247624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.415247624
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1461943242
Short name T996
Test name
Test status
Simulation time 29897559060 ps
CPU time 46.97 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:12:15 PM PDT 24
Peak memory 200660 kb
Host smart-5191cbd9-2685-4fcc-a9db-340a88a27d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461943242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1461943242
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.4271070700
Short name T786
Test name
Test status
Simulation time 3927980393 ps
CPU time 2.21 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:31 PM PDT 24
Peak memory 196896 kb
Host smart-cca76a9a-a4d8-440d-8d7d-af3e72edee8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271070700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4271070700
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3447254759
Short name T675
Test name
Test status
Simulation time 11054500377 ps
CPU time 19.45 seconds
Started Apr 04 02:11:29 PM PDT 24
Finished Apr 04 02:11:48 PM PDT 24
Peak memory 200656 kb
Host smart-162b0758-c124-4013-8448-f7840d0e2c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447254759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3447254759
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1888948110
Short name T654
Test name
Test status
Simulation time 441111825404 ps
CPU time 802.74 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:24:49 PM PDT 24
Peak memory 200884 kb
Host smart-61e105c9-0042-4ffc-912d-13a100913786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888948110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1888948110
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.753514791
Short name T973
Test name
Test status
Simulation time 610073594780 ps
CPU time 452.28 seconds
Started Apr 04 02:11:29 PM PDT 24
Finished Apr 04 02:19:01 PM PDT 24
Peak memory 215576 kb
Host smart-ed485c06-a4fd-4287-be9f-84c7c924ff69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753514791 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.753514791
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3732946533
Short name T960
Test name
Test status
Simulation time 7439595536 ps
CPU time 10.66 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:39 PM PDT 24
Peak memory 200108 kb
Host smart-f0abaa18-4b1c-49f6-a9e7-4c9ea86555d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732946533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3732946533
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3857032444
Short name T282
Test name
Test status
Simulation time 95438525246 ps
CPU time 121.32 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:13:28 PM PDT 24
Peak memory 200812 kb
Host smart-67a660db-e941-4384-bd3d-21b9695155e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857032444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3857032444
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3383909714
Short name T567
Test name
Test status
Simulation time 12237231 ps
CPU time 0.55 seconds
Started Apr 04 02:11:39 PM PDT 24
Finished Apr 04 02:11:40 PM PDT 24
Peak memory 196216 kb
Host smart-d2fa2deb-5e0e-4beb-ab09-2057b4beeab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383909714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3383909714
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1058876052
Short name T369
Test name
Test status
Simulation time 12663832170 ps
CPU time 18.72 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:45 PM PDT 24
Peak memory 200596 kb
Host smart-c89cb344-1c26-455d-913d-6d7bb94f8cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058876052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1058876052
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2856106009
Short name T938
Test name
Test status
Simulation time 16523196136 ps
CPU time 25.41 seconds
Started Apr 04 02:11:27 PM PDT 24
Finished Apr 04 02:11:53 PM PDT 24
Peak memory 200632 kb
Host smart-f28dc97c-442d-4735-86dd-be6f3a125a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856106009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2856106009
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3589212257
Short name T1086
Test name
Test status
Simulation time 4923499602 ps
CPU time 8.29 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:34 PM PDT 24
Peak memory 200220 kb
Host smart-f00e5353-db53-4bdf-8bac-223ffa519bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589212257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3589212257
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3165623622
Short name T426
Test name
Test status
Simulation time 19949568078 ps
CPU time 10.53 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:39 PM PDT 24
Peak memory 200364 kb
Host smart-77217757-fe27-4a80-a890-95be27349c0c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165623622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3165623622
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2388905831
Short name T832
Test name
Test status
Simulation time 102114078552 ps
CPU time 496.34 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:19:57 PM PDT 24
Peak memory 200800 kb
Host smart-afc16ed5-d625-4c40-9917-486a2b5077f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388905831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2388905831
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1381610799
Short name T469
Test name
Test status
Simulation time 8840591001 ps
CPU time 9.71 seconds
Started Apr 04 02:11:40 PM PDT 24
Finished Apr 04 02:11:50 PM PDT 24
Peak memory 200888 kb
Host smart-e2ac4470-54e9-4323-8240-4d1515017099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381610799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1381610799
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2688571002
Short name T888
Test name
Test status
Simulation time 38879592719 ps
CPU time 64.05 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:12:30 PM PDT 24
Peak memory 199960 kb
Host smart-08188f56-5e6a-4661-bc02-7b6263041319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688571002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2688571002
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.887807089
Short name T661
Test name
Test status
Simulation time 23613664355 ps
CPU time 449.97 seconds
Started Apr 04 02:11:39 PM PDT 24
Finished Apr 04 02:19:09 PM PDT 24
Peak memory 200904 kb
Host smart-e85ac43c-c01c-4163-8ee3-b24bbf6b68d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887807089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.887807089
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2847806418
Short name T488
Test name
Test status
Simulation time 5379728759 ps
CPU time 21.07 seconds
Started Apr 04 02:11:26 PM PDT 24
Finished Apr 04 02:11:47 PM PDT 24
Peak memory 199060 kb
Host smart-66d3d5ba-fc8f-4797-9fb8-4ad049be8b5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847806418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2847806418
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1097816568
Short name T337
Test name
Test status
Simulation time 1859498417 ps
CPU time 1.88 seconds
Started Apr 04 02:11:39 PM PDT 24
Finished Apr 04 02:11:41 PM PDT 24
Peak memory 196192 kb
Host smart-7e57982c-98e1-46c4-bc1b-ff13049453de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097816568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1097816568
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.674343015
Short name T602
Test name
Test status
Simulation time 6207654900 ps
CPU time 19.56 seconds
Started Apr 04 02:11:28 PM PDT 24
Finished Apr 04 02:11:47 PM PDT 24
Peak memory 200824 kb
Host smart-830dd9b2-a34f-4645-ba6b-95b460d0f0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674343015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.674343015
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.205749652
Short name T431
Test name
Test status
Simulation time 88445658386 ps
CPU time 54.37 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:12:35 PM PDT 24
Peak memory 200752 kb
Host smart-0279d7cb-7385-4f38-a2cd-fddaaaa0e3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205749652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.205749652
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2998212181
Short name T963
Test name
Test status
Simulation time 20036249071 ps
CPU time 213.37 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:15:14 PM PDT 24
Peak memory 216312 kb
Host smart-7e89315c-5fc0-4b62-a7f8-5885ef584bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998212181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2998212181
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1746488545
Short name T334
Test name
Test status
Simulation time 875676226 ps
CPU time 3.68 seconds
Started Apr 04 02:11:40 PM PDT 24
Finished Apr 04 02:11:44 PM PDT 24
Peak memory 200760 kb
Host smart-7fb51968-62d6-408c-979c-298f3497ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746488545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1746488545
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_alert_test.2982980504
Short name T89
Test name
Test status
Simulation time 33203834 ps
CPU time 0.54 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:11:44 PM PDT 24
Peak memory 196128 kb
Host smart-0bec4886-8110-4635-8993-d4bff49bba2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982980504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2982980504
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.231524650
Short name T122
Test name
Test status
Simulation time 81071145105 ps
CPU time 116.63 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:13:39 PM PDT 24
Peak memory 200896 kb
Host smart-74df6027-4220-4894-98ba-e9645f42103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231524650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.231524650
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.278109988
Short name T150
Test name
Test status
Simulation time 127137519506 ps
CPU time 87.61 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:13:08 PM PDT 24
Peak memory 200848 kb
Host smart-18d6df88-26e2-426d-a6f2-72961f2bc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278109988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.278109988
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.539910172
Short name T1162
Test name
Test status
Simulation time 250495189062 ps
CPU time 35.16 seconds
Started Apr 04 02:11:47 PM PDT 24
Finished Apr 04 02:12:22 PM PDT 24
Peak memory 200644 kb
Host smart-7f2cdace-9dd1-410a-a0b5-0b6a7d776b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539910172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.539910172
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.116485560
Short name T1012
Test name
Test status
Simulation time 10976058189 ps
CPU time 7.82 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:11:50 PM PDT 24
Peak memory 200312 kb
Host smart-dff7c9ec-276d-4643-8f76-726a5f2d075c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116485560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.116485560
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2451971176
Short name T1101
Test name
Test status
Simulation time 66069412813 ps
CPU time 678.33 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:23:01 PM PDT 24
Peak memory 200876 kb
Host smart-3c5324d6-8a04-4091-86f7-a1d5f88b703f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451971176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2451971176
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4096489210
Short name T763
Test name
Test status
Simulation time 6743814425 ps
CPU time 4.2 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:11:45 PM PDT 24
Peak memory 199552 kb
Host smart-e763e4ce-63e6-428a-b785-fffdb343bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096489210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4096489210
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.909363087
Short name T1130
Test name
Test status
Simulation time 94283673405 ps
CPU time 144.31 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:14:06 PM PDT 24
Peak memory 201124 kb
Host smart-4a199e97-44bf-4a28-8998-d7dce3b49dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909363087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.909363087
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.4264409480
Short name T261
Test name
Test status
Simulation time 9613755196 ps
CPU time 480.78 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:19:44 PM PDT 24
Peak memory 200864 kb
Host smart-95176933-02ed-4510-bd27-01e02fcbe100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264409480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.4264409480
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2508752666
Short name T1009
Test name
Test status
Simulation time 5079431408 ps
CPU time 20 seconds
Started Apr 04 02:11:41 PM PDT 24
Finished Apr 04 02:12:01 PM PDT 24
Peak memory 199980 kb
Host smart-0e6ec0fc-7eaa-4832-8819-9e9b6ce303d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508752666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2508752666
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3876962492
Short name T165
Test name
Test status
Simulation time 117213293930 ps
CPU time 32.98 seconds
Started Apr 04 02:11:40 PM PDT 24
Finished Apr 04 02:12:13 PM PDT 24
Peak memory 200864 kb
Host smart-8094e4c6-984e-42c3-b021-5946ad8f3042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876962492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3876962492
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.889991011
Short name T871
Test name
Test status
Simulation time 4488420466 ps
CPU time 2.38 seconds
Started Apr 04 02:11:39 PM PDT 24
Finished Apr 04 02:11:42 PM PDT 24
Peak memory 197076 kb
Host smart-a544e382-8887-4746-9581-3682af9d0a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889991011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.889991011
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2734848678
Short name T408
Test name
Test status
Simulation time 5894705482 ps
CPU time 21.78 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 200668 kb
Host smart-db78bd15-9419-42f8-b8a2-7c82467a6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734848678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2734848678
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3602730311
Short name T704
Test name
Test status
Simulation time 132145294594 ps
CPU time 523.74 seconds
Started Apr 04 02:11:45 PM PDT 24
Finished Apr 04 02:20:29 PM PDT 24
Peak memory 217284 kb
Host smart-5af593d1-c0c3-4b35-831a-6c756f97d1c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602730311 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3602730311
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3629584700
Short name T360
Test name
Test status
Simulation time 1321990656 ps
CPU time 2.16 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:11:45 PM PDT 24
Peak memory 199788 kb
Host smart-e68a7e0f-61e2-44f0-9514-07c687aa088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629584700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3629584700
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3344699412
Short name T390
Test name
Test status
Simulation time 125863085918 ps
CPU time 37.45 seconds
Started Apr 04 02:11:47 PM PDT 24
Finished Apr 04 02:12:25 PM PDT 24
Peak memory 200820 kb
Host smart-bd24ffa7-81b2-4653-bbcf-0ebb01e078cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344699412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3344699412
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.994190684
Short name T26
Test name
Test status
Simulation time 17099016 ps
CPU time 0.54 seconds
Started Apr 04 02:11:58 PM PDT 24
Finished Apr 04 02:11:59 PM PDT 24
Peak memory 196212 kb
Host smart-44ad5baa-7364-4c36-bdda-d9968bb1189f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994190684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.994190684
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.888990428
Short name T823
Test name
Test status
Simulation time 56288821219 ps
CPU time 81.63 seconds
Started Apr 04 02:11:44 PM PDT 24
Finished Apr 04 02:13:06 PM PDT 24
Peak memory 200844 kb
Host smart-1bf4b34e-a0d6-45e4-b331-5b61320231c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888990428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.888990428
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1928075887
Short name T168
Test name
Test status
Simulation time 30335467158 ps
CPU time 12.55 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:11:56 PM PDT 24
Peak memory 200816 kb
Host smart-fecd661e-40e3-4160-86e6-6beb35bc38ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928075887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1928075887
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.494483205
Short name T221
Test name
Test status
Simulation time 204187359710 ps
CPU time 169.59 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:14:32 PM PDT 24
Peak memory 200832 kb
Host smart-2ac555bf-7651-4222-bfdf-975d6b44656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494483205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.494483205
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1626973393
Short name T1170
Test name
Test status
Simulation time 24440935011 ps
CPU time 27.9 seconds
Started Apr 04 02:11:43 PM PDT 24
Finished Apr 04 02:12:11 PM PDT 24
Peak memory 200688 kb
Host smart-e5d75aa1-fe9e-4a8f-8c95-314200b9e605
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626973393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1626973393
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2456109455
Short name T1018
Test name
Test status
Simulation time 95202249021 ps
CPU time 611.01 seconds
Started Apr 04 02:11:51 PM PDT 24
Finished Apr 04 02:22:02 PM PDT 24
Peak memory 200776 kb
Host smart-92a4403a-a89a-439a-8ea5-9aa347a24687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456109455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2456109455
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3537478022
Short name T9
Test name
Test status
Simulation time 4558656224 ps
CPU time 2.58 seconds
Started Apr 04 02:11:51 PM PDT 24
Finished Apr 04 02:11:54 PM PDT 24
Peak memory 196860 kb
Host smart-0d9d6e92-577d-43a0-b1a6-c3e4f8d6d1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537478022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3537478022
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3750558383
Short name T367
Test name
Test status
Simulation time 28840304494 ps
CPU time 13.44 seconds
Started Apr 04 02:11:44 PM PDT 24
Finished Apr 04 02:11:58 PM PDT 24
Peak memory 198956 kb
Host smart-8b5a9398-e49a-44f0-85d0-c1bdf8662d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750558383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3750558383
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.4206359849
Short name T583
Test name
Test status
Simulation time 27773418291 ps
CPU time 1174.53 seconds
Started Apr 04 02:11:53 PM PDT 24
Finished Apr 04 02:31:28 PM PDT 24
Peak memory 200880 kb
Host smart-100c95af-3ca0-4bca-af7f-95da06cb26c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206359849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4206359849
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2302131752
Short name T717
Test name
Test status
Simulation time 7230813762 ps
CPU time 7.58 seconds
Started Apr 04 02:11:46 PM PDT 24
Finished Apr 04 02:11:54 PM PDT 24
Peak memory 199016 kb
Host smart-530be108-3b4a-4f5b-bb00-62b16e871224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302131752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2302131752
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3357441094
Short name T1098
Test name
Test status
Simulation time 56551538637 ps
CPU time 54.82 seconds
Started Apr 04 02:11:47 PM PDT 24
Finished Apr 04 02:12:41 PM PDT 24
Peak memory 200880 kb
Host smart-2fb559b6-e0e8-47d8-8019-bc3f6c6cec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357441094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3357441094
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.461331818
Short name T472
Test name
Test status
Simulation time 42393405523 ps
CPU time 28.22 seconds
Started Apr 04 02:11:47 PM PDT 24
Finished Apr 04 02:12:15 PM PDT 24
Peak memory 196888 kb
Host smart-8a63b33e-5854-4051-b6c0-3803fecda224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461331818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.461331818
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.213678017
Short name T533
Test name
Test status
Simulation time 739417634 ps
CPU time 1.28 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:11:43 PM PDT 24
Peak memory 200712 kb
Host smart-84455ccb-20af-4088-89d3-1af5294c1ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213678017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.213678017
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1699115514
Short name T815
Test name
Test status
Simulation time 107124254602 ps
CPU time 189.76 seconds
Started Apr 04 02:11:53 PM PDT 24
Finished Apr 04 02:15:03 PM PDT 24
Peak memory 200912 kb
Host smart-6c144409-c5b6-4f19-8647-fdda251670dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699115514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1699115514
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1344988680
Short name T709
Test name
Test status
Simulation time 230353165642 ps
CPU time 596.41 seconds
Started Apr 04 02:11:54 PM PDT 24
Finished Apr 04 02:21:50 PM PDT 24
Peak memory 225708 kb
Host smart-a29ab35f-a262-4fd6-baf3-54cbdf495082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344988680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1344988680
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3797677234
Short name T383
Test name
Test status
Simulation time 724053191 ps
CPU time 1.31 seconds
Started Apr 04 02:11:44 PM PDT 24
Finished Apr 04 02:11:45 PM PDT 24
Peak memory 199592 kb
Host smart-7d574d9e-f10e-4f04-b205-1e1b3a3e6902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797677234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3797677234
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1223780508
Short name T1092
Test name
Test status
Simulation time 62392154530 ps
CPU time 49.9 seconds
Started Apr 04 02:11:42 PM PDT 24
Finished Apr 04 02:12:32 PM PDT 24
Peak memory 200872 kb
Host smart-8dfc3014-26b3-4ea0-a882-01b96c90f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223780508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1223780508
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1602602405
Short name T664
Test name
Test status
Simulation time 14005593 ps
CPU time 0.55 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 196200 kb
Host smart-4d5d2bb7-ab1a-4e90-a0cd-081da5cf88aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602602405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1602602405
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2426691930
Short name T103
Test name
Test status
Simulation time 116303955468 ps
CPU time 197.19 seconds
Started Apr 04 02:11:54 PM PDT 24
Finished Apr 04 02:15:11 PM PDT 24
Peak memory 200812 kb
Host smart-1ad46a1b-cf65-4118-882d-4a495523bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426691930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2426691930
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1231529400
Short name T745
Test name
Test status
Simulation time 36875897403 ps
CPU time 31.87 seconds
Started Apr 04 02:11:50 PM PDT 24
Finished Apr 04 02:12:22 PM PDT 24
Peak memory 200872 kb
Host smart-1d16c302-fd91-45af-92b8-f6435a85b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231529400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1231529400
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1364175311
Short name T726
Test name
Test status
Simulation time 307742705922 ps
CPU time 92.89 seconds
Started Apr 04 02:11:51 PM PDT 24
Finished Apr 04 02:13:24 PM PDT 24
Peak memory 200800 kb
Host smart-95543a45-f647-4fa1-8330-0548cd580f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364175311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1364175311
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.584850439
Short name T634
Test name
Test status
Simulation time 44418031496 ps
CPU time 11.41 seconds
Started Apr 04 02:11:51 PM PDT 24
Finished Apr 04 02:12:02 PM PDT 24
Peak memory 200716 kb
Host smart-bcb3326d-eb08-4873-bf51-62b03988c597
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584850439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.584850439
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2901957357
Short name T906
Test name
Test status
Simulation time 30301041892 ps
CPU time 136.62 seconds
Started Apr 04 02:12:04 PM PDT 24
Finished Apr 04 02:14:21 PM PDT 24
Peak memory 200904 kb
Host smart-56aa38e2-4736-42c3-ac54-267f0acf743b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901957357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2901957357
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1898037950
Short name T1153
Test name
Test status
Simulation time 6091905575 ps
CPU time 4.33 seconds
Started Apr 04 02:12:02 PM PDT 24
Finished Apr 04 02:12:07 PM PDT 24
Peak memory 198628 kb
Host smart-91bc8845-4ea8-4363-abbc-a0e47d994f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898037950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1898037950
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1013697435
Short name T589
Test name
Test status
Simulation time 64842899343 ps
CPU time 31.18 seconds
Started Apr 04 02:11:51 PM PDT 24
Finished Apr 04 02:12:23 PM PDT 24
Peak memory 199792 kb
Host smart-c39c9b5e-f2be-4a7a-b33e-1725d7f9c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013697435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1013697435
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.1720464473
Short name T520
Test name
Test status
Simulation time 19185980671 ps
CPU time 487.25 seconds
Started Apr 04 02:12:04 PM PDT 24
Finished Apr 04 02:20:11 PM PDT 24
Peak memory 200864 kb
Host smart-8e04a954-0f1c-45a3-b1ae-c51977e387d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720464473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1720464473
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1078006460
Short name T398
Test name
Test status
Simulation time 1521021012 ps
CPU time 1.3 seconds
Started Apr 04 02:11:50 PM PDT 24
Finished Apr 04 02:11:52 PM PDT 24
Peak memory 199108 kb
Host smart-607d9587-29aa-4d75-9bfb-41e93123c3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078006460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1078006460
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1380643859
Short name T1090
Test name
Test status
Simulation time 78958929354 ps
CPU time 31.69 seconds
Started Apr 04 02:11:50 PM PDT 24
Finished Apr 04 02:12:22 PM PDT 24
Peak memory 200800 kb
Host smart-9d93a1ad-797f-4d9e-bbf0-a0080712d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380643859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1380643859
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1620879844
Short name T738
Test name
Test status
Simulation time 1137961808 ps
CPU time 1.5 seconds
Started Apr 04 02:11:50 PM PDT 24
Finished Apr 04 02:11:52 PM PDT 24
Peak memory 196204 kb
Host smart-ed0d0480-f80f-4478-acae-ab2b44071bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620879844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1620879844
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.748737969
Short name T389
Test name
Test status
Simulation time 6258243859 ps
CPU time 13.99 seconds
Started Apr 04 02:11:49 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 200036 kb
Host smart-352fcef7-b219-4dca-8157-85bd6181af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748737969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.748737969
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3864550810
Short name T642
Test name
Test status
Simulation time 448446936611 ps
CPU time 2026.54 seconds
Started Apr 04 02:12:01 PM PDT 24
Finished Apr 04 02:45:49 PM PDT 24
Peak memory 200872 kb
Host smart-84043b19-3922-43a8-8060-ce524dff6f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864550810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3864550810
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2374570762
Short name T19
Test name
Test status
Simulation time 79727223791 ps
CPU time 712.58 seconds
Started Apr 04 02:12:02 PM PDT 24
Finished Apr 04 02:23:55 PM PDT 24
Peak memory 225672 kb
Host smart-ee6b5039-7522-477e-a3c2-22016eed07a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374570762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2374570762
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2175880890
Short name T442
Test name
Test status
Simulation time 806877970 ps
CPU time 2.76 seconds
Started Apr 04 02:12:04 PM PDT 24
Finished Apr 04 02:12:07 PM PDT 24
Peak memory 200192 kb
Host smart-3aeeb854-b0ef-45bc-8026-f5216b2f71fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175880890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2175880890
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1490655813
Short name T951
Test name
Test status
Simulation time 18780774310 ps
CPU time 38.35 seconds
Started Apr 04 02:11:54 PM PDT 24
Finished Apr 04 02:12:32 PM PDT 24
Peak memory 200820 kb
Host smart-e9f3e2c8-ce3c-4fee-a853-a275a8372dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490655813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1490655813
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1801437446
Short name T465
Test name
Test status
Simulation time 32053606 ps
CPU time 0.52 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:12:17 PM PDT 24
Peak memory 195088 kb
Host smart-3ec26a41-9092-4dce-a7ca-664b094d7cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801437446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1801437446
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1445116469
Short name T761
Test name
Test status
Simulation time 31625938400 ps
CPU time 12.48 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:12:16 PM PDT 24
Peak memory 200860 kb
Host smart-36db24cb-dd3b-4d61-9a87-52ff2b305e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445116469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1445116469
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2109871237
Short name T806
Test name
Test status
Simulation time 265814583204 ps
CPU time 46.32 seconds
Started Apr 04 02:12:04 PM PDT 24
Finished Apr 04 02:12:51 PM PDT 24
Peak memory 200864 kb
Host smart-2964d2ae-9a5b-49ce-915d-5eace83613e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109871237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2109871237
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2109263291
Short name T841
Test name
Test status
Simulation time 179744376710 ps
CPU time 187.91 seconds
Started Apr 04 02:12:04 PM PDT 24
Finished Apr 04 02:15:12 PM PDT 24
Peak memory 200824 kb
Host smart-43731312-c383-40ab-a622-cb48fd67d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109263291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2109263291
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1086730950
Short name T1139
Test name
Test status
Simulation time 26860255458 ps
CPU time 43.25 seconds
Started Apr 04 02:12:07 PM PDT 24
Finished Apr 04 02:12:51 PM PDT 24
Peak memory 199804 kb
Host smart-04d56eca-6180-4931-82e3-7bc042e1d9a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086730950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1086730950
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2189458744
Short name T386
Test name
Test status
Simulation time 35769094981 ps
CPU time 210.16 seconds
Started Apr 04 02:12:17 PM PDT 24
Finished Apr 04 02:15:47 PM PDT 24
Peak memory 200844 kb
Host smart-614fc1a7-1d84-45c0-9e11-e1f02a9077ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189458744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2189458744
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.589462961
Short name T900
Test name
Test status
Simulation time 6934088971 ps
CPU time 15.12 seconds
Started Apr 04 02:12:17 PM PDT 24
Finished Apr 04 02:12:32 PM PDT 24
Peak memory 199116 kb
Host smart-bfe5fc0e-029c-41e3-85af-ffab367c4f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589462961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.589462961
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.3327135352
Short name T899
Test name
Test status
Simulation time 136705242898 ps
CPU time 86.64 seconds
Started Apr 04 02:12:07 PM PDT 24
Finished Apr 04 02:13:34 PM PDT 24
Peak memory 201068 kb
Host smart-3a8897f2-3fd3-461c-96d8-8e78c629eb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327135352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3327135352
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3837212203
Short name T40
Test name
Test status
Simulation time 8483291914 ps
CPU time 84.28 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:13:40 PM PDT 24
Peak memory 200816 kb
Host smart-35be4ba1-606b-4f01-89cf-91135b6b068d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837212203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3837212203
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4213119129
Short name T1120
Test name
Test status
Simulation time 4191238902 ps
CPU time 5.32 seconds
Started Apr 04 02:12:07 PM PDT 24
Finished Apr 04 02:12:13 PM PDT 24
Peak memory 200368 kb
Host smart-a35b2fdc-c432-48d8-ac6a-892b99e11694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213119129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4213119129
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2445949299
Short name T677
Test name
Test status
Simulation time 8015676310 ps
CPU time 14.46 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:12:17 PM PDT 24
Peak memory 200728 kb
Host smart-fb530532-6427-41da-9434-4b45887d713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445949299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2445949299
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2682606024
Short name T349
Test name
Test status
Simulation time 2952487949 ps
CPU time 5.18 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:12:09 PM PDT 24
Peak memory 197628 kb
Host smart-96964e3a-eab0-462e-a7bf-4e6ae706c6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682606024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2682606024
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2529619405
Short name T1061
Test name
Test status
Simulation time 629314454 ps
CPU time 3.33 seconds
Started Apr 04 02:12:01 PM PDT 24
Finished Apr 04 02:12:06 PM PDT 24
Peak memory 200292 kb
Host smart-d92c769d-584c-491c-aa05-cfb60fdf811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529619405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2529619405
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.4130667529
Short name T54
Test name
Test status
Simulation time 189594456849 ps
CPU time 525.51 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:21:01 PM PDT 24
Peak memory 217492 kb
Host smart-65c54362-8fed-45e9-9b9e-27254ef7997f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130667529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4130667529
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.997305523
Short name T897
Test name
Test status
Simulation time 226986837 ps
CPU time 1.18 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 198716 kb
Host smart-436d97bd-55c2-4819-8fe5-a7a97c1c4407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997305523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.997305523
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2180764520
Short name T614
Test name
Test status
Simulation time 26628782335 ps
CPU time 71.21 seconds
Started Apr 04 02:12:03 PM PDT 24
Finished Apr 04 02:13:15 PM PDT 24
Peak memory 200900 kb
Host smart-2590bb26-4373-4c0a-943b-31bc5023bbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180764520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2180764520
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1592407109
Short name T1157
Test name
Test status
Simulation time 11552704 ps
CPU time 0.55 seconds
Started Apr 04 02:06:31 PM PDT 24
Finished Apr 04 02:06:32 PM PDT 24
Peak memory 196208 kb
Host smart-825928b5-61f0-4d3d-b146-53439ea78c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592407109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1592407109
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.980127062
Short name T1154
Test name
Test status
Simulation time 78004553438 ps
CPU time 106.39 seconds
Started Apr 04 02:06:25 PM PDT 24
Finished Apr 04 02:08:11 PM PDT 24
Peak memory 200808 kb
Host smart-b441ed75-bbdd-44b5-9438-191e60b35c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980127062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.980127062
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.654460913
Short name T135
Test name
Test status
Simulation time 47113218186 ps
CPU time 21.91 seconds
Started Apr 04 02:06:25 PM PDT 24
Finished Apr 04 02:06:47 PM PDT 24
Peak memory 200832 kb
Host smart-bd4fc041-6109-4591-9ce3-e0202cce6bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654460913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.654460913
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.720287098
Short name T849
Test name
Test status
Simulation time 137955682150 ps
CPU time 30.85 seconds
Started Apr 04 02:06:32 PM PDT 24
Finished Apr 04 02:07:03 PM PDT 24
Peak memory 200900 kb
Host smart-095ae791-b20e-4e19-94ce-ddc444e4413c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720287098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.720287098
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3547230734
Short name T107
Test name
Test status
Simulation time 50734892013 ps
CPU time 81.69 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:07:48 PM PDT 24
Peak memory 200832 kb
Host smart-381295e2-d6f3-45e2-b4aa-38cdc3448d88
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547230734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3547230734
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.232188080
Short name T887
Test name
Test status
Simulation time 118667509920 ps
CPU time 100.09 seconds
Started Apr 04 02:06:33 PM PDT 24
Finished Apr 04 02:08:14 PM PDT 24
Peak memory 200768 kb
Host smart-a07424db-7d26-4bd5-8156-d209f737f70b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232188080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.232188080
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3646957231
Short name T330
Test name
Test status
Simulation time 4814164243 ps
CPU time 3.41 seconds
Started Apr 04 02:06:32 PM PDT 24
Finished Apr 04 02:06:36 PM PDT 24
Peak memory 198336 kb
Host smart-21f16461-f98b-4934-96c4-c8babc5650db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646957231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3646957231
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3095681492
Short name T47
Test name
Test status
Simulation time 72031526780 ps
CPU time 140.14 seconds
Started Apr 04 02:06:30 PM PDT 24
Finished Apr 04 02:08:50 PM PDT 24
Peak memory 209300 kb
Host smart-4586ede7-3d23-4098-8438-d4c6356d09e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095681492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3095681492
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3063124693
Short name T388
Test name
Test status
Simulation time 5184569612 ps
CPU time 199.08 seconds
Started Apr 04 02:06:31 PM PDT 24
Finished Apr 04 02:09:50 PM PDT 24
Peak memory 200932 kb
Host smart-685fc889-ce56-42a0-a624-36ade451748f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063124693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3063124693
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2358240250
Short name T762
Test name
Test status
Simulation time 4024591370 ps
CPU time 8.13 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:06:34 PM PDT 24
Peak memory 200384 kb
Host smart-38ce8041-4ab1-423c-a7d6-19ec1c5219fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358240250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2358240250
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1604001489
Short name T735
Test name
Test status
Simulation time 74814626764 ps
CPU time 68.62 seconds
Started Apr 04 02:06:31 PM PDT 24
Finished Apr 04 02:07:40 PM PDT 24
Peak memory 200932 kb
Host smart-e1d84456-db0a-498e-97fd-fe9a3cb03808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604001489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1604001489
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2073061482
Short name T378
Test name
Test status
Simulation time 706196300 ps
CPU time 1.65 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:06:28 PM PDT 24
Peak memory 196540 kb
Host smart-61de665c-2dd7-44d4-912b-b6d784df38c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073061482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2073061482
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3299204261
Short name T1030
Test name
Test status
Simulation time 454437233 ps
CPU time 1.23 seconds
Started Apr 04 02:06:25 PM PDT 24
Finished Apr 04 02:06:26 PM PDT 24
Peak memory 200152 kb
Host smart-84e1c112-0e5a-49ab-bfe0-697a8a861617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299204261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3299204261
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1967760946
Short name T1008
Test name
Test status
Simulation time 107358328394 ps
CPU time 684.17 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:17:52 PM PDT 24
Peak memory 209288 kb
Host smart-e60ce31c-e27c-4782-8572-1dbf39cb65e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967760946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1967760946
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1442803610
Short name T937
Test name
Test status
Simulation time 293904614808 ps
CPU time 1197.68 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:26:24 PM PDT 24
Peak memory 227544 kb
Host smart-333caf7f-b97d-42a5-9d03-c2fb439a5885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442803610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1442803610
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.4094556060
Short name T1052
Test name
Test status
Simulation time 738569780 ps
CPU time 2.03 seconds
Started Apr 04 02:06:28 PM PDT 24
Finished Apr 04 02:06:30 PM PDT 24
Peak memory 199276 kb
Host smart-5033a8cb-e384-4834-970c-5c42032d207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094556060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.4094556060
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1450855364
Short name T1115
Test name
Test status
Simulation time 19710381895 ps
CPU time 19.53 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:06:45 PM PDT 24
Peak memory 200828 kb
Host smart-624690a0-c66e-4381-8be8-9f7f0b7f9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450855364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1450855364
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.826517440
Short name T1174
Test name
Test status
Simulation time 26333565662 ps
CPU time 117.29 seconds
Started Apr 04 02:12:17 PM PDT 24
Finished Apr 04 02:14:15 PM PDT 24
Peak memory 200768 kb
Host smart-2bdcd8cf-6711-4da5-a34a-697d44eb514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826517440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.826517440
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2762353316
Short name T1057
Test name
Test status
Simulation time 158157736842 ps
CPU time 290.22 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:17:06 PM PDT 24
Peak memory 216700 kb
Host smart-59a2f0ff-e458-4920-b656-0b5416332171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762353316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2762353316
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4028327910
Short name T314
Test name
Test status
Simulation time 25757384452 ps
CPU time 12.14 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:12:27 PM PDT 24
Peak memory 200800 kb
Host smart-b47469eb-52b0-4b46-8183-8a2fc345120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028327910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4028327910
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4099377761
Short name T35
Test name
Test status
Simulation time 41991957620 ps
CPU time 522.06 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:20:58 PM PDT 24
Peak memory 229776 kb
Host smart-6ef48b02-1514-4eb0-8550-35b54cc5164b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099377761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4099377761
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.686190597
Short name T877
Test name
Test status
Simulation time 14755660681 ps
CPU time 8.01 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:12:24 PM PDT 24
Peak memory 200924 kb
Host smart-d0f1a306-39e6-4616-93ee-01c382595124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686190597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.686190597
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1499998598
Short name T1156
Test name
Test status
Simulation time 124721557738 ps
CPU time 348.09 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:18:05 PM PDT 24
Peak memory 217640 kb
Host smart-280a2ed4-8979-432f-b694-b0851c6b7716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499998598 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1499998598
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.279285467
Short name T948
Test name
Test status
Simulation time 19222008061 ps
CPU time 33.02 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:12:49 PM PDT 24
Peak memory 200772 kb
Host smart-b944e577-eee0-48b4-9e5b-06a8502f5464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279285467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.279285467
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3647440981
Short name T1037
Test name
Test status
Simulation time 37062395008 ps
CPU time 390.52 seconds
Started Apr 04 02:12:19 PM PDT 24
Finished Apr 04 02:18:50 PM PDT 24
Peak memory 214288 kb
Host smart-fd223b8a-4f67-45a0-9baa-89967eec293a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647440981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3647440981
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1955364838
Short name T186
Test name
Test status
Simulation time 8768500978 ps
CPU time 8.86 seconds
Started Apr 04 02:12:19 PM PDT 24
Finished Apr 04 02:12:28 PM PDT 24
Peak memory 200676 kb
Host smart-a599e1a4-92c0-48ed-9798-92f5c320194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955364838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1955364838
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1023639304
Short name T790
Test name
Test status
Simulation time 213604325481 ps
CPU time 234.45 seconds
Started Apr 04 02:12:17 PM PDT 24
Finished Apr 04 02:16:12 PM PDT 24
Peak memory 217376 kb
Host smart-8c8f676e-8668-47b6-9914-bf750c0e94a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023639304 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1023639304
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3224767239
Short name T175
Test name
Test status
Simulation time 51931726145 ps
CPU time 24.3 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:12:41 PM PDT 24
Peak memory 200652 kb
Host smart-975f37e9-8a4e-4c6b-977e-ad31c3d0c37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224767239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3224767239
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.880944063
Short name T25
Test name
Test status
Simulation time 4827478269 ps
CPU time 75.22 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:13:30 PM PDT 24
Peak memory 216580 kb
Host smart-2720af0d-7419-4ff4-ad10-0e201ba82613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880944063 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.880944063
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.897502971
Short name T325
Test name
Test status
Simulation time 85009874647 ps
CPU time 57.36 seconds
Started Apr 04 02:12:15 PM PDT 24
Finished Apr 04 02:13:13 PM PDT 24
Peak memory 200564 kb
Host smart-ea2fe5ea-39f3-40f5-afe3-825c6f0ef5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897502971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.897502971
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1718448009
Short name T93
Test name
Test status
Simulation time 91219151076 ps
CPU time 673.8 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:23:31 PM PDT 24
Peak memory 217532 kb
Host smart-e71fd0f9-5261-47ad-9cac-d8fa252d4ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718448009 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1718448009
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.4150349189
Short name T1032
Test name
Test status
Simulation time 150573103999 ps
CPU time 65.04 seconds
Started Apr 04 02:12:20 PM PDT 24
Finished Apr 04 02:13:25 PM PDT 24
Peak memory 200828 kb
Host smart-d20c8b5b-c0eb-4a7c-98b1-9fce964ee382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150349189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.4150349189
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1538336844
Short name T905
Test name
Test status
Simulation time 258954083655 ps
CPU time 813.83 seconds
Started Apr 04 02:12:14 PM PDT 24
Finished Apr 04 02:25:48 PM PDT 24
Peak memory 216292 kb
Host smart-b125730e-77ce-4a8e-b8c4-f8194e8f9c95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538336844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1538336844
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3769768443
Short name T1033
Test name
Test status
Simulation time 15188591782 ps
CPU time 26.15 seconds
Started Apr 04 02:12:16 PM PDT 24
Finished Apr 04 02:12:43 PM PDT 24
Peak memory 200572 kb
Host smart-261da09e-dd3d-4aca-91ae-dfdc98aa31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769768443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3769768443
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1689074398
Short name T197
Test name
Test status
Simulation time 92114922758 ps
CPU time 43.9 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:13:11 PM PDT 24
Peak memory 200832 kb
Host smart-84ee90a3-ebf6-4fd3-b28c-e48913577a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689074398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1689074398
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2370250037
Short name T968
Test name
Test status
Simulation time 314509659729 ps
CPU time 457.44 seconds
Started Apr 04 02:12:26 PM PDT 24
Finished Apr 04 02:20:04 PM PDT 24
Peak memory 217392 kb
Host smart-c033e5a5-ec38-4cf7-8280-3892efdccb79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370250037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2370250037
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1769112202
Short name T1045
Test name
Test status
Simulation time 11123925 ps
CPU time 0.53 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:06:39 PM PDT 24
Peak memory 195140 kb
Host smart-cbd7dc2e-a9a6-4b4d-8292-63c3f6144f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769112202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1769112202
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3294856180
Short name T702
Test name
Test status
Simulation time 9758400124 ps
CPU time 16.19 seconds
Started Apr 04 02:06:29 PM PDT 24
Finished Apr 04 02:06:46 PM PDT 24
Peak memory 200600 kb
Host smart-f449255e-509b-43ea-9549-88868753da8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294856180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3294856180
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1364139315
Short name T284
Test name
Test status
Simulation time 25971589735 ps
CPU time 39.62 seconds
Started Apr 04 02:06:30 PM PDT 24
Finished Apr 04 02:07:10 PM PDT 24
Peak memory 200956 kb
Host smart-9e6b0813-c830-429a-ac0b-bba06d5066b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364139315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1364139315
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2126685674
Short name T106
Test name
Test status
Simulation time 99073025739 ps
CPU time 142.86 seconds
Started Apr 04 02:06:28 PM PDT 24
Finished Apr 04 02:08:51 PM PDT 24
Peak memory 200732 kb
Host smart-551976c1-a0cb-42d4-b23c-53de360d7bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126685674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2126685674
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.4280988640
Short name T1017
Test name
Test status
Simulation time 278399535178 ps
CPU time 337.25 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:12:04 PM PDT 24
Peak memory 200680 kb
Host smart-06278c72-4ef6-4e3f-9166-97a29404a84d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280988640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4280988640
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4149766106
Short name T341
Test name
Test status
Simulation time 224895375051 ps
CPU time 95.46 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:08:16 PM PDT 24
Peak memory 200860 kb
Host smart-276698dd-e65c-455e-8906-097d6e76bfe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149766106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4149766106
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3722480791
Short name T622
Test name
Test status
Simulation time 4283118040 ps
CPU time 2.88 seconds
Started Apr 04 02:06:29 PM PDT 24
Finished Apr 04 02:06:32 PM PDT 24
Peak memory 199204 kb
Host smart-0518e74b-95a9-4336-8965-b1f29a34a768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722480791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3722480791
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2360454339
Short name T931
Test name
Test status
Simulation time 125752112747 ps
CPU time 40.35 seconds
Started Apr 04 02:06:29 PM PDT 24
Finished Apr 04 02:07:09 PM PDT 24
Peak memory 198584 kb
Host smart-4e0cd81b-17c3-4325-8dce-531ae6327315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360454339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2360454339
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.906422874
Short name T1155
Test name
Test status
Simulation time 14169533900 ps
CPU time 799.52 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:20:00 PM PDT 24
Peak memory 200844 kb
Host smart-d528bf5c-fb73-4f50-ba04-4c2b675c21be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906422874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.906422874
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3014926259
Short name T516
Test name
Test status
Simulation time 3132167122 ps
CPU time 8.53 seconds
Started Apr 04 02:06:28 PM PDT 24
Finished Apr 04 02:06:37 PM PDT 24
Peak memory 198788 kb
Host smart-6a44bc64-f239-4e30-8751-b89e37a57bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3014926259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3014926259
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.3205035438
Short name T139
Test name
Test status
Simulation time 14728230208 ps
CPU time 11.95 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:06:39 PM PDT 24
Peak memory 200388 kb
Host smart-7342a5db-50a8-4bba-93ba-142f563e76b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205035438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3205035438
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2258071916
Short name T916
Test name
Test status
Simulation time 47458879545 ps
CPU time 35.61 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:07:02 PM PDT 24
Peak memory 196612 kb
Host smart-59a1c9b6-e77d-4b10-802f-17199012883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258071916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2258071916
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4085173121
Short name T1076
Test name
Test status
Simulation time 756675693 ps
CPU time 1.72 seconds
Started Apr 04 02:06:27 PM PDT 24
Finished Apr 04 02:06:29 PM PDT 24
Peak memory 200744 kb
Host smart-cec32fc5-3e62-4a15-bb86-0ef01d496a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085173121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4085173121
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2435468121
Short name T615
Test name
Test status
Simulation time 256711216789 ps
CPU time 94.67 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:08:14 PM PDT 24
Peak memory 200884 kb
Host smart-4e619b5e-01d5-4066-8b06-b1f2fc130074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435468121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2435468121
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.174298648
Short name T1150
Test name
Test status
Simulation time 40146803161 ps
CPU time 452.03 seconds
Started Apr 04 02:06:44 PM PDT 24
Finished Apr 04 02:14:16 PM PDT 24
Peak memory 216428 kb
Host smart-545f4d3f-d821-4c36-930d-63cac33186dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174298648 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.174298648
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3852618026
Short name T852
Test name
Test status
Simulation time 583093819 ps
CPU time 2.58 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:06:42 PM PDT 24
Peak memory 199532 kb
Host smart-2aea01b8-f291-479f-83a4-f7d2b9d91b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852618026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3852618026
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.870543266
Short name T662
Test name
Test status
Simulation time 23039788146 ps
CPU time 19.57 seconds
Started Apr 04 02:06:26 PM PDT 24
Finished Apr 04 02:06:46 PM PDT 24
Peak memory 200820 kb
Host smart-8bb19837-a766-49c6-92f1-3e8b361bae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870543266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.870543266
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.589462832
Short name T1093
Test name
Test status
Simulation time 92355999886 ps
CPU time 299.92 seconds
Started Apr 04 02:12:31 PM PDT 24
Finished Apr 04 02:17:32 PM PDT 24
Peak memory 209176 kb
Host smart-7c82f5dd-6370-4603-89c3-457fd8c92cf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589462832 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.589462832
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4282393239
Short name T667
Test name
Test status
Simulation time 67624869456 ps
CPU time 107.66 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:14:16 PM PDT 24
Peak memory 200884 kb
Host smart-161de65c-5da0-4df5-88ac-39c3552edc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282393239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4282393239
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1054327167
Short name T50
Test name
Test status
Simulation time 112484986863 ps
CPU time 2026.38 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:46:14 PM PDT 24
Peak memory 233852 kb
Host smart-7e024906-2cd9-4f7a-9d50-927016a8df05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054327167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1054327167
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1419500163
Short name T137
Test name
Test status
Simulation time 70983059493 ps
CPU time 60.35 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:13:28 PM PDT 24
Peak memory 200816 kb
Host smart-bac63b87-b91e-4827-9f19-e74861c04d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419500163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1419500163
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3052681945
Short name T1138
Test name
Test status
Simulation time 116364305443 ps
CPU time 751.92 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:24:59 PM PDT 24
Peak memory 232468 kb
Host smart-02653618-cb92-48fc-8d8e-e624680d0259
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052681945 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3052681945
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3507231663
Short name T734
Test name
Test status
Simulation time 41112300868 ps
CPU time 24.67 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:12:53 PM PDT 24
Peak memory 200924 kb
Host smart-a57bec0e-54ee-4f9f-855f-071c0fe0b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507231663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3507231663
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.286250211
Short name T94
Test name
Test status
Simulation time 56993243276 ps
CPU time 487.8 seconds
Started Apr 04 02:12:29 PM PDT 24
Finished Apr 04 02:20:38 PM PDT 24
Peak memory 217352 kb
Host smart-88693c6b-6ada-4c3e-8375-42238ad78615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286250211 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.286250211
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3094007238
Short name T38
Test name
Test status
Simulation time 108380275872 ps
CPU time 170.9 seconds
Started Apr 04 02:12:26 PM PDT 24
Finished Apr 04 02:15:17 PM PDT 24
Peak memory 200780 kb
Host smart-db339ac2-0ac9-4290-8a73-55e726a9b36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094007238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3094007238
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1043668056
Short name T1161
Test name
Test status
Simulation time 591056480950 ps
CPU time 629.68 seconds
Started Apr 04 02:12:29 PM PDT 24
Finished Apr 04 02:22:59 PM PDT 24
Peak memory 225620 kb
Host smart-5d89f19d-5a36-498f-a0d0-b809e04ad492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043668056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1043668056
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.478991795
Short name T933
Test name
Test status
Simulation time 15067389847 ps
CPU time 33.04 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:13:01 PM PDT 24
Peak memory 200800 kb
Host smart-5e80dbb2-1298-4c20-8bf8-dc302b36009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478991795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.478991795
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2934871540
Short name T506
Test name
Test status
Simulation time 46914550253 ps
CPU time 503.61 seconds
Started Apr 04 02:12:30 PM PDT 24
Finished Apr 04 02:20:53 PM PDT 24
Peak memory 217140 kb
Host smart-b40a77f6-a9c6-4089-ba29-50519c009cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934871540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2934871540
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1075951166
Short name T1135
Test name
Test status
Simulation time 32783896621 ps
CPU time 16.29 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:12:45 PM PDT 24
Peak memory 200872 kb
Host smart-e55ef9a6-eab8-4746-a632-5d6a804e7fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075951166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1075951166
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4203987731
Short name T95
Test name
Test status
Simulation time 29661054038 ps
CPU time 334.9 seconds
Started Apr 04 02:12:26 PM PDT 24
Finished Apr 04 02:18:01 PM PDT 24
Peak memory 209240 kb
Host smart-bda69728-e927-49ed-a0d0-b03cc3536065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203987731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4203987731
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2755665713
Short name T536
Test name
Test status
Simulation time 149397864694 ps
CPU time 17.45 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:12:46 PM PDT 24
Peak memory 200656 kb
Host smart-dccb7cfe-e43e-4f4a-8d55-e324aebe16c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755665713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2755665713
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.860220779
Short name T1055
Test name
Test status
Simulation time 26357451165 ps
CPU time 1026.46 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:29:34 PM PDT 24
Peak memory 217440 kb
Host smart-d1e176c5-d429-43be-b1ea-4b56054ab653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860220779 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.860220779
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3169864695
Short name T99
Test name
Test status
Simulation time 9728818614 ps
CPU time 18.47 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:12:47 PM PDT 24
Peak memory 200852 kb
Host smart-07f372b1-f93c-4f31-958a-caa05234ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169864695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3169864695
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.3520937996
Short name T402
Test name
Test status
Simulation time 92374030485 ps
CPU time 843.45 seconds
Started Apr 04 02:12:26 PM PDT 24
Finished Apr 04 02:26:30 PM PDT 24
Peak memory 214140 kb
Host smart-e1d87168-c262-456c-b5d5-1653bb973c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520937996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.3520937996
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1317591301
Short name T371
Test name
Test status
Simulation time 32592008 ps
CPU time 0.56 seconds
Started Apr 04 02:06:42 PM PDT 24
Finished Apr 04 02:06:43 PM PDT 24
Peak memory 195200 kb
Host smart-dce4637d-aaab-4069-8185-926cb0a58286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317591301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1317591301
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3943832957
Short name T124
Test name
Test status
Simulation time 77398764385 ps
CPU time 29.54 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:07:08 PM PDT 24
Peak memory 200756 kb
Host smart-68490b12-b814-4641-9d00-39f478af2fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943832957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3943832957
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.114049209
Short name T447
Test name
Test status
Simulation time 29044324068 ps
CPU time 48.22 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200888 kb
Host smart-808ce1a3-7d6b-435a-87f6-dbd880dba03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114049209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.114049209
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.4086143381
Short name T873
Test name
Test status
Simulation time 318171420354 ps
CPU time 130.88 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:08:51 PM PDT 24
Peak memory 198128 kb
Host smart-313e23a4-84a0-4bef-b17d-e6b5ad9d902b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086143381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4086143381
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3981876153
Short name T710
Test name
Test status
Simulation time 111939339674 ps
CPU time 489.95 seconds
Started Apr 04 02:06:37 PM PDT 24
Finished Apr 04 02:14:48 PM PDT 24
Peak memory 200760 kb
Host smart-a678e99d-62fa-434e-887b-c75d5ae584e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981876153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3981876153
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3618876720
Short name T339
Test name
Test status
Simulation time 3470802279 ps
CPU time 7.55 seconds
Started Apr 04 02:06:37 PM PDT 24
Finished Apr 04 02:06:45 PM PDT 24
Peak memory 199812 kb
Host smart-af416fd1-c313-43ab-a3de-22be31cb669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618876720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3618876720
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.1051824766
Short name T292
Test name
Test status
Simulation time 55968380556 ps
CPU time 18.04 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:06:57 PM PDT 24
Peak memory 199228 kb
Host smart-a81e1898-dd5c-4b89-bfde-7b1ec0a6a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051824766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1051824766
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.12615850
Short name T482
Test name
Test status
Simulation time 11785348756 ps
CPU time 43.52 seconds
Started Apr 04 02:06:44 PM PDT 24
Finished Apr 04 02:07:28 PM PDT 24
Peak memory 200728 kb
Host smart-1ed33b53-ebe7-4ee8-8bc7-3628be6d5cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12615850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.12615850
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2178349937
Short name T311
Test name
Test status
Simulation time 2839470066 ps
CPU time 8.29 seconds
Started Apr 04 02:06:36 PM PDT 24
Finished Apr 04 02:06:45 PM PDT 24
Peak memory 198856 kb
Host smart-0dd23a6b-425a-4c14-8fe0-f9056bc35c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178349937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2178349937
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1261501967
Short name T659
Test name
Test status
Simulation time 20762047248 ps
CPU time 20.16 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:06:59 PM PDT 24
Peak memory 200900 kb
Host smart-46eea91a-f273-4edb-9a9f-08bb2c060c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261501967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1261501967
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1793534285
Short name T773
Test name
Test status
Simulation time 37376227546 ps
CPU time 13.84 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:07:05 PM PDT 24
Peak memory 196692 kb
Host smart-af8642eb-2102-41aa-b536-128812a9f20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793534285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1793534285
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1533375157
Short name T513
Test name
Test status
Simulation time 892004786 ps
CPU time 4.8 seconds
Started Apr 04 02:06:45 PM PDT 24
Finished Apr 04 02:06:50 PM PDT 24
Peak memory 199744 kb
Host smart-085b52b4-66df-477f-a355-b71085fa3184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533375157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1533375157
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1765494420
Short name T323
Test name
Test status
Simulation time 378469404999 ps
CPU time 116.43 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:08:37 PM PDT 24
Peak memory 209312 kb
Host smart-ae76cf78-6941-42d5-9468-beae6ba48460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765494420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1765494420
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2714846141
Short name T649
Test name
Test status
Simulation time 186833489425 ps
CPU time 582.48 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:16:21 PM PDT 24
Peak memory 225612 kb
Host smart-7c7f61ea-0889-458b-ac2f-ef8fa742fde2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714846141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2714846141
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2395241643
Short name T591
Test name
Test status
Simulation time 8019883587 ps
CPU time 11.38 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:06:50 PM PDT 24
Peak memory 200872 kb
Host smart-dccfa219-fb05-4da8-a008-5cb27407e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395241643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2395241643
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.4068875370
Short name T767
Test name
Test status
Simulation time 30941445474 ps
CPU time 54.07 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:07:32 PM PDT 24
Peak memory 200864 kb
Host smart-62c25674-c93c-4b97-8b26-0d0f22e69176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068875370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4068875370
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1876695620
Short name T357
Test name
Test status
Simulation time 105411828630 ps
CPU time 151.36 seconds
Started Apr 04 02:12:28 PM PDT 24
Finished Apr 04 02:15:00 PM PDT 24
Peak memory 200880 kb
Host smart-6574bc38-05c8-48ea-a31f-dc516e092e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876695620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1876695620
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.678040719
Short name T227
Test name
Test status
Simulation time 82191788956 ps
CPU time 1371.44 seconds
Started Apr 04 02:12:31 PM PDT 24
Finished Apr 04 02:35:23 PM PDT 24
Peak memory 217344 kb
Host smart-964c74de-2a6c-43d2-9d55-e2d436c68cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678040719 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.678040719
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3459667248
Short name T178
Test name
Test status
Simulation time 60713731795 ps
CPU time 30.9 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:12:59 PM PDT 24
Peak memory 200840 kb
Host smart-3a28436e-cfda-41d8-b032-7d73d1dcc03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459667248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3459667248
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.341066803
Short name T1065
Test name
Test status
Simulation time 20526664762 ps
CPU time 254.97 seconds
Started Apr 04 02:12:27 PM PDT 24
Finished Apr 04 02:16:42 PM PDT 24
Peak memory 217536 kb
Host smart-a095b245-e7f7-4984-99ea-f1ad2860d7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341066803 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.341066803
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1006912810
Short name T321
Test name
Test status
Simulation time 109013802434 ps
CPU time 123.88 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:14:44 PM PDT 24
Peak memory 200868 kb
Host smart-4e593446-10bd-43ad-9057-c6538118582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006912810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1006912810
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.141720956
Short name T826
Test name
Test status
Simulation time 32371381886 ps
CPU time 304.62 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:17:44 PM PDT 24
Peak memory 217592 kb
Host smart-e45c9151-f6df-4571-81bf-7e8a6f9a449c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141720956 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.141720956
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3506116687
Short name T511
Test name
Test status
Simulation time 132847929546 ps
CPU time 102.02 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:14:23 PM PDT 24
Peak memory 200656 kb
Host smart-db09208c-1737-4a5d-b316-3282b6918478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506116687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3506116687
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.164697537
Short name T890
Test name
Test status
Simulation time 10097090494 ps
CPU time 112.23 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:14:33 PM PDT 24
Peak memory 200984 kb
Host smart-797a88ce-6647-42e8-a6f8-f2386a96fbee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164697537 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.164697537
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3833165177
Short name T1164
Test name
Test status
Simulation time 19334626198 ps
CPU time 35.99 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:13:16 PM PDT 24
Peak memory 200780 kb
Host smart-4aca39b5-464e-47fe-a817-cd13d9ca3151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833165177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3833165177
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3917287425
Short name T824
Test name
Test status
Simulation time 128011128253 ps
CPU time 325.27 seconds
Started Apr 04 02:12:41 PM PDT 24
Finished Apr 04 02:18:09 PM PDT 24
Peak memory 217580 kb
Host smart-5a6fcb9a-6d37-45ab-893d-bcea9b27d8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917287425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3917287425
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.521294700
Short name T199
Test name
Test status
Simulation time 23727058241 ps
CPU time 73.16 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:13:54 PM PDT 24
Peak memory 200876 kb
Host smart-605b72e6-b549-4e9e-a6c0-0d8127b7a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521294700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.521294700
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1009100802
Short name T979
Test name
Test status
Simulation time 43006908992 ps
CPU time 36.66 seconds
Started Apr 04 02:12:40 PM PDT 24
Finished Apr 04 02:13:19 PM PDT 24
Peak memory 200832 kb
Host smart-da43eecf-20a6-49b2-b793-a60db19a5430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009100802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1009100802
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4293084075
Short name T36
Test name
Test status
Simulation time 34632101205 ps
CPU time 555.21 seconds
Started Apr 04 02:12:40 PM PDT 24
Finished Apr 04 02:21:58 PM PDT 24
Peak memory 210788 kb
Host smart-1fd3029c-cf3f-4a73-bdeb-29fee060e69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293084075 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4293084075
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.648076251
Short name T416
Test name
Test status
Simulation time 111676486315 ps
CPU time 176.06 seconds
Started Apr 04 02:12:40 PM PDT 24
Finished Apr 04 02:15:38 PM PDT 24
Peak memory 200916 kb
Host smart-51a3c2f9-a3e2-46a0-a9e8-92b1149a37f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648076251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.648076251
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.871183569
Short name T299
Test name
Test status
Simulation time 85482822324 ps
CPU time 835.79 seconds
Started Apr 04 02:12:38 PM PDT 24
Finished Apr 04 02:26:35 PM PDT 24
Peak memory 225660 kb
Host smart-2ff61c69-0a5c-44fc-84ae-fa1ca116321d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871183569 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.871183569
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1742084248
Short name T1053
Test name
Test status
Simulation time 171494670853 ps
CPU time 46.07 seconds
Started Apr 04 02:12:40 PM PDT 24
Finished Apr 04 02:13:27 PM PDT 24
Peak memory 200652 kb
Host smart-36431abb-fe11-4640-a1dc-7a7cc0f7c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742084248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1742084248
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1999048666
Short name T876
Test name
Test status
Simulation time 102078529144 ps
CPU time 656.86 seconds
Started Apr 04 02:12:38 PM PDT 24
Finished Apr 04 02:23:36 PM PDT 24
Peak memory 225540 kb
Host smart-45acf083-4f01-4ec0-8d46-550ad63f4eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999048666 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1999048666
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3278672044
Short name T577
Test name
Test status
Simulation time 7416554847 ps
CPU time 18.06 seconds
Started Apr 04 02:12:40 PM PDT 24
Finished Apr 04 02:12:59 PM PDT 24
Peak memory 200812 kb
Host smart-24bfd391-7722-4480-a8eb-83ed34d2f84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278672044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3278672044
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.31306185
Short name T981
Test name
Test status
Simulation time 22641395681 ps
CPU time 252.62 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:16:52 PM PDT 24
Peak memory 212032 kb
Host smart-ced56aac-b342-43d4-95c3-52b0e717d842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31306185 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.31306185
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4086237613
Short name T420
Test name
Test status
Simulation time 44809827 ps
CPU time 0.56 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:06:50 PM PDT 24
Peak memory 196156 kb
Host smart-423f972c-a388-4375-a118-dba5e5fd1d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086237613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4086237613
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3352247694
Short name T397
Test name
Test status
Simulation time 76031740149 ps
CPU time 26.16 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:07:04 PM PDT 24
Peak memory 200780 kb
Host smart-b9c05321-a270-497b-830f-6d5d4323f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352247694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3352247694
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1667776306
Short name T641
Test name
Test status
Simulation time 74535157000 ps
CPU time 72.39 seconds
Started Apr 04 02:06:37 PM PDT 24
Finished Apr 04 02:07:49 PM PDT 24
Peak memory 200956 kb
Host smart-e229593e-dbbc-4acb-a30c-b1fdf5374514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667776306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1667776306
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1196722004
Short name T183
Test name
Test status
Simulation time 12515395688 ps
CPU time 23.87 seconds
Started Apr 04 02:06:44 PM PDT 24
Finished Apr 04 02:07:08 PM PDT 24
Peak memory 200732 kb
Host smart-4ea95d77-4b26-44e3-bdcd-9634bd14293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196722004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1196722004
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1232288098
Short name T563
Test name
Test status
Simulation time 14198577753 ps
CPU time 23.12 seconds
Started Apr 04 02:06:36 PM PDT 24
Finished Apr 04 02:06:59 PM PDT 24
Peak memory 198084 kb
Host smart-fa6ce680-570e-4aef-942b-00cbbf57571c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232288098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1232288098
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1351149230
Short name T253
Test name
Test status
Simulation time 178701628499 ps
CPU time 1353.19 seconds
Started Apr 04 02:06:36 PM PDT 24
Finished Apr 04 02:29:10 PM PDT 24
Peak memory 200896 kb
Host smart-6880b034-776d-40df-ad14-25598a4e785e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351149230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1351149230
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2871084320
Short name T470
Test name
Test status
Simulation time 6419166501 ps
CPU time 14.88 seconds
Started Apr 04 02:06:43 PM PDT 24
Finished Apr 04 02:06:58 PM PDT 24
Peak memory 199652 kb
Host smart-e4627a48-9414-4472-9322-2ad1e2f7c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871084320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2871084320
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1568471502
Short name T485
Test name
Test status
Simulation time 73182076621 ps
CPU time 41.05 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:07:32 PM PDT 24
Peak memory 200868 kb
Host smart-e9492923-7fa7-46ee-b36b-31b2191f82c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568471502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1568471502
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3107103923
Short name T1036
Test name
Test status
Simulation time 14201871565 ps
CPU time 176.9 seconds
Started Apr 04 02:06:44 PM PDT 24
Finished Apr 04 02:09:40 PM PDT 24
Peak memory 200768 kb
Host smart-2da2464d-f725-4168-aaf1-bd5c95d54c86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107103923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3107103923
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3841512517
Short name T914
Test name
Test status
Simulation time 4932776929 ps
CPU time 8.85 seconds
Started Apr 04 02:06:45 PM PDT 24
Finished Apr 04 02:06:53 PM PDT 24
Peak memory 200100 kb
Host smart-65423d66-f6bb-4ace-8bd2-095b120b5f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841512517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3841512517
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3918583975
Short name T412
Test name
Test status
Simulation time 37964130721 ps
CPU time 21.63 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:07:13 PM PDT 24
Peak memory 200740 kb
Host smart-c4f0e5d0-6e6b-46d6-8497-f0271899a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918583975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3918583975
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.944507300
Short name T1004
Test name
Test status
Simulation time 680042446 ps
CPU time 1.69 seconds
Started Apr 04 02:06:43 PM PDT 24
Finished Apr 04 02:06:44 PM PDT 24
Peak memory 196264 kb
Host smart-d7258717-56d6-4d52-bd40-40f317cb7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944507300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.944507300
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2367124466
Short name T844
Test name
Test status
Simulation time 6245245476 ps
CPU time 9.24 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:06:48 PM PDT 24
Peak memory 200824 kb
Host smart-efa7c35c-2cd5-4157-bc35-0f962f991d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367124466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2367124466
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1507069868
Short name T255
Test name
Test status
Simulation time 176667351659 ps
CPU time 223.17 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:10:22 PM PDT 24
Peak memory 200804 kb
Host smart-d87da3fc-e252-46a3-889d-46bcbd625165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507069868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1507069868
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.496079492
Short name T962
Test name
Test status
Simulation time 25183670548 ps
CPU time 278.52 seconds
Started Apr 04 02:06:39 PM PDT 24
Finished Apr 04 02:11:19 PM PDT 24
Peak memory 216528 kb
Host smart-7dbcdc61-d81f-4908-be95-43c7631e1543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496079492 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.496079492
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3361474325
Short name T405
Test name
Test status
Simulation time 1184455656 ps
CPU time 1.68 seconds
Started Apr 04 02:06:43 PM PDT 24
Finished Apr 04 02:06:44 PM PDT 24
Peak memory 199876 kb
Host smart-928e5a2e-cfe0-4719-9121-088076c9c83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361474325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3361474325
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3953491473
Short name T410
Test name
Test status
Simulation time 41832132232 ps
CPU time 81.14 seconds
Started Apr 04 02:06:38 PM PDT 24
Finished Apr 04 02:07:59 PM PDT 24
Peak memory 200712 kb
Host smart-00b14ad6-b1fe-48ad-ad62-22d6f4e00ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953491473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3953491473
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2618127184
Short name T437
Test name
Test status
Simulation time 12895331577 ps
CPU time 21.61 seconds
Started Apr 04 02:12:45 PM PDT 24
Finished Apr 04 02:13:07 PM PDT 24
Peak memory 200824 kb
Host smart-0212561f-4601-40cf-8ed9-f0834f62a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618127184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2618127184
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2055951478
Short name T496
Test name
Test status
Simulation time 743252955407 ps
CPU time 553.32 seconds
Started Apr 04 02:12:41 PM PDT 24
Finished Apr 04 02:21:57 PM PDT 24
Peak memory 225736 kb
Host smart-d25eeb79-72be-4963-8da7-eed6210f18d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055951478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2055951478
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3550036708
Short name T146
Test name
Test status
Simulation time 129705546096 ps
CPU time 56.36 seconds
Started Apr 04 02:12:39 PM PDT 24
Finished Apr 04 02:13:37 PM PDT 24
Peak memory 200800 kb
Host smart-7b88774e-3f2a-484f-9b3c-35da3ec543a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550036708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3550036708
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3543574973
Short name T902
Test name
Test status
Simulation time 69872726708 ps
CPU time 944.39 seconds
Started Apr 04 02:12:52 PM PDT 24
Finished Apr 04 02:28:36 PM PDT 24
Peak memory 217352 kb
Host smart-1ac7c0a2-08ee-49ac-abab-00ec1f061eb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543574973 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3543574973
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3922212504
Short name T173
Test name
Test status
Simulation time 34862395371 ps
CPU time 16.82 seconds
Started Apr 04 02:12:51 PM PDT 24
Finished Apr 04 02:13:08 PM PDT 24
Peak memory 200868 kb
Host smart-7e00ef03-cb84-406e-bd99-aca3e68286fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922212504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3922212504
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.4016259353
Short name T3
Test name
Test status
Simulation time 19917710286 ps
CPU time 283.49 seconds
Started Apr 04 02:12:51 PM PDT 24
Finished Apr 04 02:17:35 PM PDT 24
Peak memory 212224 kb
Host smart-384bbca4-b2e1-4034-a5cd-668278f13524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016259353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4016259353
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2349113722
Short name T985
Test name
Test status
Simulation time 103834810875 ps
CPU time 129.14 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:15:02 PM PDT 24
Peak memory 200744 kb
Host smart-a20411fd-31af-4519-8416-232c16a48601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349113722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2349113722
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.79446316
Short name T771
Test name
Test status
Simulation time 76374120357 ps
CPU time 204.3 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:16:17 PM PDT 24
Peak memory 217496 kb
Host smart-7aac170d-f55a-4b62-b871-7fa7ba00449f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79446316 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.79446316
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3164306467
Short name T819
Test name
Test status
Simulation time 76374498398 ps
CPU time 234.81 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:16:48 PM PDT 24
Peak memory 200712 kb
Host smart-61cb9d81-dc6e-4f70-bb66-c510255c1594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164306467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3164306467
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1379704961
Short name T741
Test name
Test status
Simulation time 34574389019 ps
CPU time 465.15 seconds
Started Apr 04 02:12:51 PM PDT 24
Finished Apr 04 02:20:36 PM PDT 24
Peak memory 217168 kb
Host smart-c0c23e1e-1283-42af-a1a4-bb17caafb11d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379704961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1379704961
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1370654432
Short name T455
Test name
Test status
Simulation time 31684786757 ps
CPU time 13.22 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:13:06 PM PDT 24
Peak memory 200740 kb
Host smart-c1e063b6-4518-4117-b48d-47121bb59982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370654432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1370654432
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3875948815
Short name T805
Test name
Test status
Simulation time 162358578209 ps
CPU time 1138.56 seconds
Started Apr 04 02:12:52 PM PDT 24
Finished Apr 04 02:31:50 PM PDT 24
Peak memory 225640 kb
Host smart-70418557-2353-4a6b-8978-048ce0b0285f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875948815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3875948815
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3094893003
Short name T637
Test name
Test status
Simulation time 13106778715 ps
CPU time 12.98 seconds
Started Apr 04 02:12:54 PM PDT 24
Finished Apr 04 02:13:07 PM PDT 24
Peak memory 200776 kb
Host smart-2947e190-98cf-4c41-a114-c2da9c4e0eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094893003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3094893003
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1227850738
Short name T52
Test name
Test status
Simulation time 170520484848 ps
CPU time 1218.28 seconds
Started Apr 04 02:12:52 PM PDT 24
Finished Apr 04 02:33:10 PM PDT 24
Peak memory 232452 kb
Host smart-4eb6eb72-fabe-42b5-9fc0-bcf87cf65b33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227850738 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1227850738
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.187796675
Short name T462
Test name
Test status
Simulation time 141659462296 ps
CPU time 219.8 seconds
Started Apr 04 02:12:51 PM PDT 24
Finished Apr 04 02:16:31 PM PDT 24
Peak memory 200852 kb
Host smart-beb05a0c-e0d9-4835-9e87-f42bc4c557f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187796675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.187796675
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3484200404
Short name T190
Test name
Test status
Simulation time 219758291712 ps
CPU time 628.43 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:23:22 PM PDT 24
Peak memory 230660 kb
Host smart-a4d23fcd-c667-47bb-948c-5caa07b18b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484200404 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3484200404
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2117969245
Short name T1140
Test name
Test status
Simulation time 344232019404 ps
CPU time 28.31 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:13:21 PM PDT 24
Peak memory 200868 kb
Host smart-147368a3-ec9e-49bf-834b-b96860cfc501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117969245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2117969245
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2176346545
Short name T721
Test name
Test status
Simulation time 39484726885 ps
CPU time 465.25 seconds
Started Apr 04 02:12:54 PM PDT 24
Finished Apr 04 02:20:39 PM PDT 24
Peak memory 217592 kb
Host smart-6bc0a6de-723b-434a-a73f-dec76fa3a718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176346545 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2176346545
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3967418207
Short name T1013
Test name
Test status
Simulation time 273935997589 ps
CPU time 74.94 seconds
Started Apr 04 02:12:52 PM PDT 24
Finished Apr 04 02:14:07 PM PDT 24
Peak memory 200892 kb
Host smart-91cde058-9376-4aae-9ddc-504ae71cc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967418207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3967418207
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2878877336
Short name T98
Test name
Test status
Simulation time 300138115517 ps
CPU time 973.04 seconds
Started Apr 04 02:12:55 PM PDT 24
Finished Apr 04 02:29:08 PM PDT 24
Peak memory 233656 kb
Host smart-7410e767-426d-4b3b-b577-45b54ec56899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878877336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2878877336
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.732436735
Short name T480
Test name
Test status
Simulation time 12140561 ps
CPU time 0.54 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:06:52 PM PDT 24
Peak memory 196120 kb
Host smart-1748d2b7-029a-4e9e-a256-35eadf473cb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732436735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.732436735
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.402151689
Short name T351
Test name
Test status
Simulation time 54461484191 ps
CPU time 20.05 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:07:10 PM PDT 24
Peak memory 198208 kb
Host smart-14aeb441-2f01-4bb4-bb82-59f99085f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402151689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.402151689
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1507623918
Short name T837
Test name
Test status
Simulation time 22570452790 ps
CPU time 14.23 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:07:04 PM PDT 24
Peak memory 200848 kb
Host smart-0d32c003-7a90-4ed2-a01d-9100ae949e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507623918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1507623918
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2160349969
Short name T827
Test name
Test status
Simulation time 37703870389 ps
CPU time 15.74 seconds
Started Apr 04 02:06:54 PM PDT 24
Finished Apr 04 02:07:09 PM PDT 24
Peak memory 200428 kb
Host smart-5edc6e43-5b86-4d99-9032-d3afa49373ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160349969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2160349969
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1570535252
Short name T396
Test name
Test status
Simulation time 76294807474 ps
CPU time 29.86 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:07:19 PM PDT 24
Peak memory 200780 kb
Host smart-486f5079-0ab8-4d8b-b428-a3594f530abd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570535252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1570535252
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.245912268
Short name T980
Test name
Test status
Simulation time 126519301872 ps
CPU time 999.4 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:23:30 PM PDT 24
Peak memory 200888 kb
Host smart-92def0b0-7f7a-4630-a78a-bdd16d296f6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245912268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.245912268
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3250676155
Short name T703
Test name
Test status
Simulation time 4703452964 ps
CPU time 3.62 seconds
Started Apr 04 02:06:48 PM PDT 24
Finished Apr 04 02:06:52 PM PDT 24
Peak memory 199968 kb
Host smart-cbbe7e83-2323-4ac9-bd21-d64dcd51880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250676155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3250676155
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3122492651
Short name T742
Test name
Test status
Simulation time 32750688239 ps
CPU time 11.99 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:07:03 PM PDT 24
Peak memory 200724 kb
Host smart-b377bb1f-30b9-4118-af27-d79999fb45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122492651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3122492651
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3374455429
Short name T424
Test name
Test status
Simulation time 10139850779 ps
CPU time 161.65 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:09:32 PM PDT 24
Peak memory 200808 kb
Host smart-08a5fa9e-9654-4dd3-8905-930196215336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374455429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3374455429
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.4000560126
Short name T1073
Test name
Test status
Simulation time 6155158528 ps
CPU time 5.11 seconds
Started Apr 04 02:06:52 PM PDT 24
Finished Apr 04 02:06:57 PM PDT 24
Peak memory 199008 kb
Host smart-07131e3e-0d6c-4c7f-81b4-c5b4cd51859f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000560126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4000560126
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3013550525
Short name T20
Test name
Test status
Simulation time 109433945471 ps
CPU time 170.84 seconds
Started Apr 04 02:06:51 PM PDT 24
Finished Apr 04 02:09:42 PM PDT 24
Peak memory 200752 kb
Host smart-a643b58b-8d0d-48e2-a0c9-c0476f43312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013550525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3013550525
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1387001054
Short name T476
Test name
Test status
Simulation time 3266355151 ps
CPU time 1.97 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:06:52 PM PDT 24
Peak memory 196680 kb
Host smart-ab3fa7d3-3e08-4704-9aee-08557bf05aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387001054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1387001054
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.304763517
Short name T830
Test name
Test status
Simulation time 81814002 ps
CPU time 0.82 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:06:50 PM PDT 24
Peak memory 197780 kb
Host smart-6fb3dfbc-f66d-4daa-a613-d43549d668cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304763517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.304763517
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1730632958
Short name T1111
Test name
Test status
Simulation time 330214419625 ps
CPU time 181.06 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:09:51 PM PDT 24
Peak memory 209388 kb
Host smart-69565616-8081-43ea-9d8d-a14b2f8b2b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730632958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1730632958
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1894321549
Short name T866
Test name
Test status
Simulation time 626451720539 ps
CPU time 421.81 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:13:51 PM PDT 24
Peak memory 217540 kb
Host smart-4da1f4e3-068e-4a6c-aeb5-9d0e7e7e9d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894321549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1894321549
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1242196229
Short name T373
Test name
Test status
Simulation time 6899088514 ps
CPU time 9.96 seconds
Started Apr 04 02:06:50 PM PDT 24
Finished Apr 04 02:07:00 PM PDT 24
Peak memory 200300 kb
Host smart-a5f38965-86db-4d92-9cf4-0d6ef67b057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242196229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1242196229
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.988887368
Short name T636
Test name
Test status
Simulation time 38191521616 ps
CPU time 15.15 seconds
Started Apr 04 02:06:49 PM PDT 24
Finished Apr 04 02:07:05 PM PDT 24
Peak memory 200876 kb
Host smart-857158fd-e68a-43f9-83ea-16cca205a94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988887368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.988887368
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2708061850
Short name T1027
Test name
Test status
Simulation time 99658270414 ps
CPU time 47.77 seconds
Started Apr 04 02:12:54 PM PDT 24
Finished Apr 04 02:13:41 PM PDT 24
Peak memory 200728 kb
Host smart-4a343f75-5d9f-4b0d-b3ea-2bec521cbb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708061850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2708061850
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3270677141
Short name T92
Test name
Test status
Simulation time 293614027474 ps
CPU time 290.15 seconds
Started Apr 04 02:12:55 PM PDT 24
Finished Apr 04 02:17:45 PM PDT 24
Peak memory 210520 kb
Host smart-a08322e2-09fa-4208-b2e4-39d4b6130467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270677141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3270677141
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2632861638
Short name T148
Test name
Test status
Simulation time 155705369868 ps
CPU time 94.29 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:14:28 PM PDT 24
Peak memory 200888 kb
Host smart-e095691f-4ce0-4913-ad24-7a1cfc1a2110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632861638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2632861638
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.672869147
Short name T683
Test name
Test status
Simulation time 36705826239 ps
CPU time 134.14 seconds
Started Apr 04 02:12:55 PM PDT 24
Finished Apr 04 02:15:09 PM PDT 24
Peak memory 216368 kb
Host smart-6771730d-c1ed-4c9b-af4a-31c2b9fcd110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672869147 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.672869147
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.934925153
Short name T592
Test name
Test status
Simulation time 42960344444 ps
CPU time 295.52 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:17:48 PM PDT 24
Peak memory 217388 kb
Host smart-a4f8e628-5c21-44c9-97d9-75ec3002010f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934925153 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.934925153
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2251426531
Short name T318
Test name
Test status
Simulation time 162112835671 ps
CPU time 40.17 seconds
Started Apr 04 02:12:53 PM PDT 24
Finished Apr 04 02:13:33 PM PDT 24
Peak memory 200828 kb
Host smart-3e380e6c-37bf-4d8e-beeb-fb3858efd141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251426531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2251426531
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3438637306
Short name T51
Test name
Test status
Simulation time 386648593883 ps
CPU time 502.15 seconds
Started Apr 04 02:12:54 PM PDT 24
Finished Apr 04 02:21:16 PM PDT 24
Peak memory 226560 kb
Host smart-651f4ef9-6713-4ebd-a78f-e8c36ff88e87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438637306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3438637306
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.803551873
Short name T895
Test name
Test status
Simulation time 14473801835 ps
CPU time 18.89 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:13:22 PM PDT 24
Peak memory 200768 kb
Host smart-319e106f-df2c-4391-a2f2-90d7aa040093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803551873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.803551873
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3822621243
Short name T1046
Test name
Test status
Simulation time 155486684793 ps
CPU time 17.66 seconds
Started Apr 04 02:13:08 PM PDT 24
Finished Apr 04 02:13:26 PM PDT 24
Peak memory 200864 kb
Host smart-0dd1bc5a-69b0-4eba-9603-ac08ea2e6808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822621243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3822621243
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2973867987
Short name T308
Test name
Test status
Simulation time 11652854466 ps
CPU time 134.77 seconds
Started Apr 04 02:13:04 PM PDT 24
Finished Apr 04 02:15:19 PM PDT 24
Peak memory 217124 kb
Host smart-3e6ccc62-75c5-4bb0-aeab-97b1d32f1261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973867987 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2973867987
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1230256226
Short name T961
Test name
Test status
Simulation time 83663036005 ps
CPU time 139.44 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:15:23 PM PDT 24
Peak memory 200820 kb
Host smart-c1173d0f-1207-4be7-9b8b-2106c7c3837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230256226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1230256226
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1363623618
Short name T384
Test name
Test status
Simulation time 24802390274 ps
CPU time 144.84 seconds
Started Apr 04 02:13:08 PM PDT 24
Finished Apr 04 02:15:33 PM PDT 24
Peak memory 217316 kb
Host smart-2cd0d1e9-f9e6-4f3f-b166-5ebddc5eb539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363623618 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1363623618
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3324139856
Short name T154
Test name
Test status
Simulation time 211916908450 ps
CPU time 23.41 seconds
Started Apr 04 02:13:02 PM PDT 24
Finished Apr 04 02:13:25 PM PDT 24
Peak memory 200888 kb
Host smart-236dd405-b84d-4aea-b4a5-6b2a588c476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324139856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3324139856
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.429640115
Short name T540
Test name
Test status
Simulation time 135177562863 ps
CPU time 673.23 seconds
Started Apr 04 02:13:04 PM PDT 24
Finished Apr 04 02:24:17 PM PDT 24
Peak memory 217552 kb
Host smart-5c63f399-7994-45a4-912c-3449f617f21f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429640115 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.429640115
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1924757372
Short name T220
Test name
Test status
Simulation time 111458664009 ps
CPU time 83.64 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:14:27 PM PDT 24
Peak memory 200784 kb
Host smart-37488613-61bf-4966-ace1-4668b7d87795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924757372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1924757372
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3426014690
Short name T212
Test name
Test status
Simulation time 227640516443 ps
CPU time 310.19 seconds
Started Apr 04 02:13:04 PM PDT 24
Finished Apr 04 02:18:15 PM PDT 24
Peak memory 215756 kb
Host smart-b2b68e54-7ebf-418b-b5c0-a85cdf51fe87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426014690 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3426014690
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2382216271
Short name T494
Test name
Test status
Simulation time 61657160948 ps
CPU time 189.13 seconds
Started Apr 04 02:13:03 PM PDT 24
Finished Apr 04 02:16:12 PM PDT 24
Peak memory 200836 kb
Host smart-e12fbb1d-0734-483f-97ee-5a423ca874cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382216271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2382216271
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.805033697
Short name T97
Test name
Test status
Simulation time 254957438282 ps
CPU time 756.1 seconds
Started Apr 04 02:13:04 PM PDT 24
Finished Apr 04 02:25:40 PM PDT 24
Peak memory 217496 kb
Host smart-5d9c956d-665b-4b0e-854a-0da330ca2ec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805033697 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.805033697
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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