Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	113838	1			T1	2		T2	36		T3	52
all_values[1]	113838	1			T1	2		T2	36		T3	52
all_values[2]	113838	1			T1	2		T2	36		T3	52
all_values[3]	113838	1			T1	2		T2	36		T3	52
all_values[4]	113838	1			T1	2		T2	36		T3	52
all_values[5]	113838	1			T1	2		T2	36		T3	52
all_values[6]	113838	1			T1	2		T2	36		T3	52
all_values[7]	113838	1			T1	2		T2	36		T3	52

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

454134

1

T1

16

T2

84

T3

226

auto[1]

456570

1

T2

204

T3

190

T4

102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

852032

1

T1

13

T2

285

T3

367

auto[1]

58672

1

T1

3

T2

3

T3

49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30254	1			T2	30		T3	10		T4	21
all_values[0]	auto[0]	auto[1]	27408	1			T1	2		T3	42		T4	12
all_values[0]	auto[1]	auto[0]	36658	1			T2	5		T4	2		T8	1
all_values[0]	auto[1]	auto[1]	19518	1			T2	1		T4	2		T8	2
all_values[1]	auto[0]	auto[0]	56894	1			T1	2		T2	6		T3	9
all_values[1]	auto[0]	auto[1]	1644	1			T21	1		T16	1		T15	23
all_values[1]	auto[1]	auto[0]	53616	1			T2	30		T3	43		T4	15
all_values[1]	auto[1]	auto[1]	1684	1			T20	11		T41	1		T12	16
all_values[2]	auto[0]	auto[0]	53683	1			T1	1		T2	33		T3	42
all_values[2]	auto[0]	auto[1]	2836	1			T1	1		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	54799	1			T2	1		T3	3		T4	21
all_values[2]	auto[1]	auto[1]	2520	1			T2	1		T3	4		T7	1
all_values[3]	auto[0]	auto[0]	56929	1			T1	2		T3	49		T4	26
all_values[3]	auto[0]	auto[1]	345	1			T12	1		T13	2		T16	3
all_values[3]	auto[1]	auto[0]	56218	1			T2	36		T3	3		T4	11
all_values[3]	auto[1]	auto[1]	346	1			T13	3		T19	3		T86	1
all_values[4]	auto[0]	auto[0]	54875	1			T1	2		T2	4		T3	12
all_values[4]	auto[0]	auto[1]	476	1			T12	1		T16	3		T113	3
all_values[4]	auto[1]	auto[0]	57982	1			T2	32		T3	40		T4	11
all_values[4]	auto[1]	auto[1]	505	1			T16	2		T15	6		T19	2
all_values[5]	auto[0]	auto[0]	57530	1			T1	2		T2	2		T3	45
all_values[5]	auto[0]	auto[1]	183	1			T85	1		T35	2		T118	2
all_values[5]	auto[1]	auto[0]	55954	1			T2	34		T3	7		T4	4
all_values[5]	auto[1]	auto[1]	171	1			T16	5		T19	3		T35	2
all_values[6]	auto[0]	auto[0]	54438	1			T1	2		T2	2		T3	7
all_values[6]	auto[0]	auto[1]	163	1			T16	4		T85	1		T35	1
all_values[6]	auto[1]	auto[0]	59015	1			T2	34		T3	45		T4	32
all_values[6]	auto[1]	auto[1]	222	1			T16	3		T118	2		T38	2
all_values[7]	auto[0]	auto[0]	56151	1			T1	2		T2	6		T3	7
all_values[7]	auto[0]	auto[1]	325	1			T22	1		T12	4		T16	5
all_values[7]	auto[1]	auto[0]	57036	1			T2	30		T3	45		T4	4
all_values[7]	auto[1]	auto[1]	326	1			T20	1		T16	2		T85	2