Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2323	1			T3	1		T4	2		T6	14
auto[BaudRate115200]	2033	1			T1	1		T3	1		T7	1
auto[BaudRate230400]	2003	1			T1	1		T3	1		T4	1
auto[BaudRate128Kbps]	1976	1			T5	1		T8	2		T9	1
auto[BaudRate256Kbps]	2161	1			T2	3		T3	1		T4	2
auto[BaudRate1Mbps]	1903	1			T2	1		T3	1		T4	2
auto[BaudRate1p5Mbps]	1438	1			T2	1		T3	1		T20	2

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1513	1			T18	9		T21	15		T14	88
freqs[25]	1605	1			T2	5		T11	18		T20	29
freqs[48]	817	1			T287	1		T300	2		T338	14
freqs[50]	680	1			T6	14		T339	1		T105	7
freqs[100]	1062	1			T1	2		T5	2		T26	12

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	246	1			T18	9		T21	2		T14	5
auto[BaudRate9600]	freqs[25]	252	1			T20	6		T42	2		T23	9
auto[BaudRate9600]	freqs[48]	131	1			T338	1		T340	1		T341	1
auto[BaudRate9600]	freqs[50]	144	1			T6	14		T339	1		T25	1
auto[BaudRate9600]	freqs[100]	153	1			T129	1		T342	12		T309	1
auto[BaudRate115200]	freqs[24]	195	1			T21	3		T14	12		T343	9
auto[BaudRate115200]	freqs[25]	261	1			T11	3		T20	2		T42	1
auto[BaudRate115200]	freqs[48]	117	1			T338	3		T308	4		T344	6
auto[BaudRate115200]	freqs[50]	108	1			T105	3		T25	1		T281	2
auto[BaudRate115200]	freqs[100]	136	1			T1	1		T26	6		T102	1
auto[BaudRate230400]	freqs[24]	237	1			T21	4		T14	19		T116	1
auto[BaudRate230400]	freqs[25]	198	1			T11	6		T20	5		T278	2
auto[BaudRate230400]	freqs[48]	108	1			T338	1		T341	1		T308	2
auto[BaudRate230400]	freqs[50]	72	1			T105	2		T281	2		T143	1
auto[BaudRate230400]	freqs[100]	179	1			T1	1		T5	1		T129	2
auto[BaudRate128Kbps]	freqs[24]	220	1			T21	1		T14	19		T116	1
auto[BaudRate128Kbps]	freqs[25]	232	1			T20	5		T42	2		T189	2
auto[BaudRate128Kbps]	freqs[48]	118	1			T338	4		T308	1		T344	8
auto[BaudRate128Kbps]	freqs[50]	86	1			T105	1		T281	2		T143	2
auto[BaudRate128Kbps]	freqs[100]	161	1			T5	1		T129	2		T102	1
auto[BaudRate256Kbps]	freqs[24]	216	1			T21	3		T14	12		T343	6
auto[BaudRate256Kbps]	freqs[25]	237	1			T2	3		T20	6		T189	2
auto[BaudRate256Kbps]	freqs[48]	100	1			T338	2		T341	1		T344	11
auto[BaudRate256Kbps]	freqs[50]	91	1			T281	3		T143	2		T332	1
auto[BaudRate256Kbps]	freqs[100]	157	1			T129	1		T342	3		T345	1
auto[BaudRate1Mbps]	freqs[24]	267	1			T21	2		T14	12		T116	2
auto[BaudRate1Mbps]	freqs[25]	292	1			T2	1		T11	9		T20	3
auto[BaudRate1Mbps]	freqs[48]	115	1			T300	1		T338	1		T340	1
auto[BaudRate1Mbps]	freqs[50]	90	1			T281	2		T332	2		T178	11
auto[BaudRate1Mbps]	freqs[100]	130	1			T26	3		T342	6		T345	1
auto[BaudRate1p5Mbps]	freqs[25]	133	1			T2	1		T20	2		T189	1
auto[BaudRate1p5Mbps]	freqs[48]	128	1			T287	1		T300	1		T338	2
auto[BaudRate1p5Mbps]	freqs[50]	89	1			T105	1		T143	2		T332	1
auto[BaudRate1p5Mbps]	freqs[100]	146	1			T26	3		T129	1		T342	9

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded