Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32571903	1			T2	38230		T3	148		T4	45
all_levels[1]	198305	1			T2	2542		T3	1		T4	12
all_levels[2]	2722	1			T2	2		T4	1		T8	1
all_levels[3]	1201	1			T7	1		T20	5		T43	1
all_levels[4]	799	1			T20	6		T42	2		T21	1
all_levels[5]	565	1			T20	7		T42	1		T125	1
all_levels[6]	445	1			T4	2		T20	3		T21	1
all_levels[7]	382	1			T20	2		T22	1		T14	3
all_levels[8]	304	1			T7	2		T20	1		T125	1
all_levels[9]	255	1			T22	1		T125	3		T14	3
all_levels[10]	207	1			T13	1		T14	4		T115	2
all_levels[11]	215	1			T20	1		T33	1		T13	1
all_levels[12]	172	1			T20	2		T22	1		T14	1
all_levels[13]	153	1			T20	1		T13	2		T115	1
all_levels[14]	159	1			T41	1		T22	1		T14	1
all_levels[15]	104	1			T125	1		T14	1		T115	2
all_levels[16]	117	1			T4	1		T13	1		T14	1
all_levels[17]	105	1			T7	1		T20	1		T14	2
all_levels[18]	104	1			T14	3		T116	1		T34	1
all_levels[19]	98	1			T13	1		T14	1		T34	1
all_levels[20]	94	1			T20	1		T22	1		T13	1
all_levels[21]	72	1			T4	1		T116	2		T35	1
all_levels[22]	66	1			T7	2		T126	1		T101	1
all_levels[23]	57	1			T35	1		T127	1		T128	1
all_levels[24]	65	1			T13	1		T129	1		T106	1
all_levels[25]	62	1			T7	1		T22	1		T61	1
all_levels[26]	57	1			T7	1		T41	1		T42	4
all_levels[27]	53	1			T20	1		T22	1		T13	1
all_levels[28]	46	1			T7	2		T19	1		T57	1
all_levels[29]	52	1			T41	1		T115	1		T57	1
all_levels[30]	34	1			T128	1		T130	1		T107	1
all_levels[31]	34	1			T22	1		T115	1		T129	1
all_levels[32]	37	1			T22	1		T13	1		T19	1
all_levels[33]	34	1			T20	1		T131	1		T132	2
all_levels[34]	38	1			T7	1		T8	1		T13	1
all_levels[35]	23	1			T133	1		T134	1		T135	1
all_levels[36]	37	1			T131	1		T136	1		T137	1
all_levels[37]	33	1			T14	1		T24	1		T98	2
all_levels[38]	16	1			T20	1		T35	1		T133	1
all_levels[39]	12	1			T138	2		T139	2		T140	1
all_levels[40]	19	1			T133	1		T141	1		T142	1
all_levels[41]	19	1			T20	1		T136	1		T137	1
all_levels[42]	20	1			T57	1		T131	1		T136	1
all_levels[43]	17	1			T14	1		T100	1		T143	1
all_levels[44]	10	1			T144	1		T145	1		T146	1
all_levels[45]	20	1			T20	1		T131	1		T136	1
all_levels[46]	11	1			T42	1		T61	1		T147	1
all_levels[47]	14	1			T115	1		T106	1		T148	1
all_levels[48]	10	1			T149	1		T150	1		T151	1
all_levels[49]	8	1			T115	1		T152	2		T153	1
all_levels[50]	18	1			T35	1		T137	1		T154	1
all_levels[51]	8	1			T131	1		T155	1		T154	3
all_levels[52]	6	1			T156	3		T157	1		T158	1
all_levels[53]	11	1			T131	1		T98	1		T159	1
all_levels[54]	9	1			T160	4		T51	1		T161	1
all_levels[55]	13	1			T162	1		T163	2		T164	1
all_levels[56]	4	1			T165	1		T166	1		T167	1
all_levels[57]	6	1			T168	1		T169	1		T170	1
all_levels[58]	6	1			T171	1		T172	1		T173	1
all_levels[59]	7	1			T151	1		T174	1		T175	1
all_levels[60]	7	1			T160	1		T176	1		T177	1
all_levels[61]	4	1			T178	1		T179	1		T141	1
all_levels[62]	12	1			T43	1		T164	1		T180	2
all_levels[63]	13	1			T98	1		T149	1		T181	2
all_levels[64]	123	1			T13	2		T14	1		T86	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32774954

1

T2

40774

T3

144

T4

58

auto[1]

4678

1

T3

5

T4

4

T6

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32567728	1			T2	38230		T3	143		T4	42
all_levels[0]	auto[1]	4175	1			T3	5		T4	3		T6	1
all_levels[1]	auto[0]	198211	1			T2	2542		T3	1		T4	12
all_levels[1]	auto[1]	94	1			T42	2		T116	1		T86	1
all_levels[2]	auto[0]	2701	1			T2	2		T4	1		T8	1
all_levels[2]	auto[1]	21	1			T182	1		T126	1		T181	3
all_levels[3]	auto[0]	1175	1			T7	1		T20	5		T43	1
all_levels[3]	auto[1]	26	1			T114	1		T105	2		T183	1
all_levels[4]	auto[0]	778	1			T20	6		T42	2		T21	1
all_levels[4]	auto[1]	21	1			T115	1		T116	1		T184	5
all_levels[5]	auto[0]	547	1			T20	7		T42	1		T125	1
all_levels[5]	auto[1]	18	1			T61	1		T185	1		T186	2
all_levels[6]	auto[0]	431	1			T4	1		T20	3		T21	1
all_levels[6]	auto[1]	14	1			T4	1		T126	1		T185	1
all_levels[7]	auto[0]	365	1			T20	2		T22	1		T14	3
all_levels[7]	auto[1]	17	1			T101	1		T38	3		T187	2
all_levels[8]	auto[0]	290	1			T7	2		T20	1		T125	1
all_levels[8]	auto[1]	14	1			T14	2		T143	1		T188	1
all_levels[9]	auto[0]	246	1			T22	1		T125	3		T14	3
all_levels[9]	auto[1]	9	1			T104	1		T189	2		T190	1
all_levels[10]	auto[0]	200	1			T13	1		T14	4		T115	2
all_levels[10]	auto[1]	7	1			T191	1		T192	1		T165	1
all_levels[11]	auto[0]	204	1			T20	1		T33	1		T13	1
all_levels[11]	auto[1]	11	1			T193	1		T194	1		T195	1
all_levels[12]	auto[0]	169	1			T20	2		T22	1		T14	1
all_levels[12]	auto[1]	3	1			T196	1		T197	1		T198	1
all_levels[13]	auto[0]	143	1			T20	1		T13	2		T115	1
all_levels[13]	auto[1]	10	1			T199	1		T138	1		T200	1
all_levels[14]	auto[0]	146	1			T41	1		T22	1		T14	1
all_levels[14]	auto[1]	13	1			T115	3		T185	1		T119	1
all_levels[15]	auto[0]	97	1			T125	1		T14	1		T115	2
all_levels[15]	auto[1]	7	1			T201	1		T185	1		T202	1
all_levels[16]	auto[0]	108	1			T4	1		T13	1		T14	1
all_levels[16]	auto[1]	9	1			T150	1		T203	2		T204	1
all_levels[17]	auto[0]	103	1			T7	1		T20	1		T14	2
all_levels[17]	auto[1]	2	1			T134	1		T197	1		-	-
all_levels[18]	auto[0]	97	1			T14	3		T116	1		T34	1
all_levels[18]	auto[1]	7	1			T51	1		T205	1		T206	1
all_levels[19]	auto[0]	91	1			T13	1		T14	1		T34	1
all_levels[19]	auto[1]	7	1			T207	2		T208	2		T209	2
all_levels[20]	auto[0]	80	1			T20	1		T22	1		T13	1
all_levels[20]	auto[1]	14	1			T189	1		T210	4		T138	1
all_levels[21]	auto[0]	59	1			T4	1		T116	1		T35	1
all_levels[21]	auto[1]	13	1			T116	1		T129	1		T193	4
all_levels[22]	auto[0]	63	1			T7	2		T126	1		T101	1
all_levels[22]	auto[1]	3	1			T211	1		T144	2		-	-
all_levels[23]	auto[0]	53	1			T35	1		T127	1		T128	1
all_levels[23]	auto[1]	4	1			T212	3		T213	1		-	-
all_levels[24]	auto[0]	56	1			T13	1		T129	1		T106	1
all_levels[24]	auto[1]	9	1			T214	1		T215	3		T216	4
all_levels[25]	auto[0]	54	1			T7	1		T22	1		T61	1
all_levels[25]	auto[1]	8	1			T143	2		T217	4		T218	1
all_levels[26]	auto[0]	46	1			T7	1		T41	1		T42	1
all_levels[26]	auto[1]	11	1			T42	3		T104	1		T219	3
all_levels[27]	auto[0]	46	1			T20	1		T22	1		T13	1
all_levels[27]	auto[1]	7	1			T220	1		T221	2		T222	1
all_levels[28]	auto[0]	40	1			T7	2		T19	1		T57	1
all_levels[28]	auto[1]	6	1			T223	2		T224	1		T225	2
all_levels[29]	auto[0]	44	1			T41	1		T115	1		T57	1
all_levels[29]	auto[1]	8	1			T226	4		T227	1		T228	2
all_levels[30]	auto[0]	31	1			T128	1		T130	1		T107	1
all_levels[30]	auto[1]	3	1			T229	1		T191	2		-	-
all_levels[31]	auto[0]	27	1			T22	1		T115	1		T129	1
all_levels[31]	auto[1]	7	1			T230	1		T231	1		T232	1
all_levels[32]	auto[0]	29	1			T22	1		T13	1		T19	1
all_levels[32]	auto[1]	8	1			T186	2		T233	1		T234	1
all_levels[33]	auto[0]	27	1			T20	1		T131	1		T132	1
all_levels[33]	auto[1]	7	1			T132	1		T235	1		T236	1
all_levels[34]	auto[0]	32	1			T7	1		T8	1		T13	1
all_levels[34]	auto[1]	6	1			T187	1		T237	1		T238	1
all_levels[35]	auto[0]	22	1			T133	1		T134	1		T135	1
all_levels[35]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[36]	auto[0]	33	1			T131	1		T136	1		T137	1
all_levels[36]	auto[1]	4	1			T240	1		T241	2		T242	1
all_levels[37]	auto[0]	28	1			T14	1		T24	1		T98	1
all_levels[37]	auto[1]	5	1			T98	1		T133	1		T190	2
all_levels[38]	auto[0]	14	1			T20	1		T35	1		T133	1
all_levels[38]	auto[1]	2	1			T243	2		-	-		-	-
all_levels[39]	auto[0]	10	1			T138	1		T139	1		T140	1
all_levels[39]	auto[1]	2	1			T138	1		T139	1		-	-
all_levels[40]	auto[0]	14	1			T133	1		T141	1		T142	1
all_levels[40]	auto[1]	5	1			T242	2		T244	3		-	-
all_levels[41]	auto[0]	17	1			T20	1		T136	1		T137	1
all_levels[41]	auto[1]	2	1			T245	1		T246	1		-	-
all_levels[42]	auto[0]	14	1			T57	1		T131	1		T136	1
all_levels[42]	auto[1]	6	1			T247	4		T165	1		T248	1
all_levels[43]	auto[0]	14	1			T14	1		T100	1		T143	1
all_levels[43]	auto[1]	3	1			T153	2		T249	1		-	-
all_levels[44]	auto[0]	10	1			T144	1		T145	1		T146	1
all_levels[45]	auto[0]	17	1			T20	1		T131	1		T136	1
all_levels[45]	auto[1]	3	1			T130	1		T250	1		T209	1
all_levels[46]	auto[0]	11	1			T42	1		T61	1		T147	1
all_levels[47]	auto[0]	13	1			T115	1		T106	1		T148	1
all_levels[47]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[48]	auto[0]	10	1			T149	1		T150	1		T151	1
all_levels[49]	auto[0]	7	1			T115	1		T152	1		T153	1
all_levels[49]	auto[1]	1	1			T152	1		-	-		-	-
all_levels[50]	auto[0]	17	1			T35	1		T137	1		T154	1
all_levels[50]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[51]	auto[0]	8	1			T131	1		T155	1		T154	3
all_levels[52]	auto[0]	4	1			T156	1		T157	1		T158	1
all_levels[52]	auto[1]	2	1			T156	2		-	-		-	-
all_levels[53]	auto[0]	11	1			T131	1		T98	1		T159	1
all_levels[54]	auto[0]	6	1			T160	1		T51	1		T161	1
all_levels[54]	auto[1]	3	1			T160	3		-	-		-	-
all_levels[55]	auto[0]	10	1			T162	1		T163	1		T164	1
all_levels[55]	auto[1]	3	1			T163	1		T253	2		-	-
all_levels[56]	auto[0]	4	1			T165	1		T166	1		T167	1
all_levels[57]	auto[0]	5	1			T168	1		T169	1		T170	1
all_levels[57]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[58]	auto[0]	6	1			T171	1		T172	1		T173	1
all_levels[59]	auto[0]	6	1			T151	1		T174	1		T175	1
all_levels[59]	auto[1]	1	1			T255	1		-	-		-	-
all_levels[60]	auto[0]	6	1			T160	1		T176	1		T177	1
all_levels[60]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[61]	auto[0]	4	1			T178	1		T179	1		T141	1
all_levels[62]	auto[0]	9	1			T43	1		T164	1		T180	1
all_levels[62]	auto[1]	3	1			T180	1		T257	1		T233	1
all_levels[63]	auto[0]	9	1			T98	1		T149	1		T181	1
all_levels[63]	auto[1]	4	1			T181	1		T180	1		T258	1
all_levels[64]	auto[0]	98	1			T13	2		T14	1		T86	2
all_levels[64]	auto[1]	25	1			T98	2		T259	1		T260	4