Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	113838	1			T1	2		T2	36		T3	52
all_pins[1]	113838	1			T1	2		T2	36		T3	52
all_pins[2]	113838	1			T1	2		T2	36		T3	52
all_pins[3]	113838	1			T1	2		T2	36		T3	52
all_pins[4]	113838	1			T1	2		T2	36		T3	52
all_pins[5]	113838	1			T1	2		T2	36		T3	52
all_pins[6]	113838	1			T1	2		T2	36		T3	52
all_pins[7]	113838	1			T1	2		T2	36		T3	52

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	884396	1			T1	16		T2	286		T3	412
values[0x1]	26308	1			T2	2		T3	4		T4	2
transitions[0x0=>0x1]	25030	1			T2	2		T3	4		T4	2
transitions[0x1=>0x0]	24610	1			T2	1		T3	4		T4	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	94253	1			T1	2		T2	35		T3	52
all_pins[0]	values[0x1]	19585	1			T2	1		T4	2		T8	2
all_pins[0]	transitions[0x0=>0x1]	18936	1			T2	1		T4	2		T8	2
all_pins[0]	transitions[0x1=>0x0]	1031	1			T20	11		T41	1		T13	3
all_pins[1]	values[0x0]	112158	1			T1	2		T2	36		T3	52
all_pins[1]	values[0x1]	1680	1			T20	11		T41	1		T12	16
all_pins[1]	transitions[0x0=>0x1]	1523	1			T20	11		T41	1		T12	16
all_pins[1]	transitions[0x1=>0x0]	2426	1			T2	1		T3	4		T7	1
all_pins[2]	values[0x0]	111255	1			T1	2		T2	35		T3	48
all_pins[2]	values[0x1]	2583	1			T2	1		T3	4		T7	1
all_pins[2]	transitions[0x0=>0x1]	2512	1			T2	1		T3	4		T7	1
all_pins[2]	transitions[0x1=>0x0]	275	1			T13	3		T19	2		T85	3
all_pins[3]	values[0x0]	113492	1			T1	2		T2	36		T3	52
all_pins[3]	values[0x1]	346	1			T13	3		T19	3		T86	1
all_pins[3]	transitions[0x0=>0x1]	293	1			T13	3		T19	1		T86	1
all_pins[3]	transitions[0x1=>0x0]	451	1			T16	2		T15	6		T85	2
all_pins[4]	values[0x0]	113334	1			T1	2		T2	36		T3	52
all_pins[4]	values[0x1]	504	1			T16	2		T15	6		T19	2
all_pins[4]	transitions[0x0=>0x1]	431	1			T15	5		T85	4		T35	3
all_pins[4]	transitions[0x1=>0x0]	162	1			T16	3		T19	1		T35	2
all_pins[5]	values[0x0]	113603	1			T1	2		T2	36		T3	52
all_pins[5]	values[0x1]	235	1			T16	5		T15	1		T19	3
all_pins[5]	transitions[0x0=>0x1]	177	1			T16	4		T15	1		T19	3
all_pins[5]	transitions[0x1=>0x0]	991	1			T20	3		T21	7		T12	2
all_pins[6]	values[0x0]	112789	1			T1	2		T2	36		T3	52
all_pins[6]	values[0x1]	1049	1			T20	3		T21	7		T12	2
all_pins[6]	transitions[0x0=>0x1]	994	1			T20	3		T21	7		T12	2
all_pins[6]	transitions[0x1=>0x0]	271	1			T20	1		T16	2		T85	2
all_pins[7]	values[0x0]	113512	1			T1	2		T2	36		T3	52
all_pins[7]	values[0x1]	326	1			T20	1		T16	2		T85	2
all_pins[7]	transitions[0x0=>0x1]	164	1			T20	1		T85	1		T35	1
all_pins[7]	transitions[0x1=>0x0]	19003	1			T4	2		T8	1		T9	38