Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7730959	1			T2	3646		T3	11		T4	26
all_levels[1]	1908188	1			T2	51		T3	113		T9	6429
all_levels[2]	278404	1			T2	54		T3	1		T7	1
all_levels[3]	274272	1			T2	47		T3	3		T9	4492
all_levels[4]	245245	1			T2	48		T3	1		T9	4461
all_levels[5]	213147	1			T2	49		T8	1		T9	4487
all_levels[6]	260326	1			T2	52		T3	1		T7	1
all_levels[7]	207519	1			T2	47		T9	4475		T20	8
all_levels[8]	300100	1			T2	51		T9	4457		T20	10
all_levels[9]	642346	1			T2	40		T3	2		T9	4459
all_levels[10]	231906	1			T2	52		T9	4488		T21	2
all_levels[11]	348242	1			T2	51		T9	4474		T263	5148
all_levels[12]	395516	1			T2	49		T9	4455		T20	39
all_levels[13]	434933	1			T2	43		T9	4489		T22	1
all_levels[14]	200072	1			T2	43		T7	1		T9	4492
all_levels[15]	186646	1			T2	45		T9	4486		T20	1
all_levels[16]	301529	1			T2	46		T7	1		T9	4482
all_levels[17]	185351	1			T2	50		T7	2		T9	4474
all_levels[18]	212428	1			T2	44		T9	4480		T263	5120
all_levels[19]	240142	1			T2	45		T4	2		T9	4475
all_levels[20]	245253	1			T2	48		T9	4475		T20	3
all_levels[21]	232013	1			T2	48		T9	4313		T20	5
all_levels[22]	245996	1			T2	53		T9	2366		T20	3
all_levels[23]	165853	1			T2	55		T9	2330		T20	9
all_levels[24]	479663	1			T2	44		T9	2360		T20	10
all_levels[25]	440696	1			T2	57		T4	3		T7	1
all_levels[26]	160806	1			T2	46		T4	1		T7	2
all_levels[27]	246506	1			T2	53		T9	21833		T20	6
all_levels[28]	238243	1			T2	47		T3	3		T9	1
all_levels[29]	430880	1			T2	47		T9	1		T41	3
all_levels[30]	153019	1			T2	51		T9	1		T263	5150
all_levels[31]	468408	1			T2	1819		T9	1		T21	4
all_levels[32]	14474584	1			T2	33853		T3	15		T4	34

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32774954

1

T2

40774

T3

144

T4

58

auto[1]

4237

1

T3

6

T4

8

T6

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7728641	1			T2	3646		T3	10		T4	21
all_levels[0]	auto[1]	2318	1			T3	1		T4	5		T6	1
all_levels[1]	auto[0]	1907865	1			T2	51		T3	111		T9	6429
all_levels[1]	auto[1]	323	1			T3	2		T42	4		T16	1
all_levels[2]	auto[0]	278366	1			T2	54		T3	1		T7	1
all_levels[2]	auto[1]	38	1			T8	3		T339	1		T189	1
all_levels[3]	auto[0]	274070	1			T2	47		T3	3		T9	4492
all_levels[3]	auto[1]	202	1			T14	1		T115	1		T60	3
all_levels[4]	auto[0]	245221	1			T2	48		T3	1		T9	4461
all_levels[4]	auto[1]	24	1			T163	1		T214	1		T347	3
all_levels[5]	auto[0]	213120	1			T2	49		T8	1		T9	4487
all_levels[5]	auto[1]	27	1			T98	2		T119	1		T344	1
all_levels[6]	auto[0]	260305	1			T2	52		T3	1		T7	1
all_levels[6]	auto[1]	21	1			T182	1		T61	1		T297	1
all_levels[7]	auto[0]	207378	1			T2	47		T9	4475		T20	8
all_levels[7]	auto[1]	141	1			T14	12		T61	1		T102	10
all_levels[8]	auto[0]	300079	1			T2	51		T9	4457		T20	10
all_levels[8]	auto[1]	21	1			T143	3		T138	1		T231	1
all_levels[9]	auto[0]	642317	1			T2	40		T3	2		T9	4459
all_levels[9]	auto[1]	29	1			T266	1		T348	2		T325	1
all_levels[10]	auto[0]	231879	1			T2	52		T9	4488		T21	2
all_levels[10]	auto[1]	27	1			T185	1		T190	1		T119	1
all_levels[11]	auto[0]	348227	1			T2	51		T9	4474		T263	5148
all_levels[11]	auto[1]	15	1			T61	1		T101	1		T143	1
all_levels[12]	auto[0]	395498	1			T2	49		T9	4455		T20	39
all_levels[12]	auto[1]	18	1			T306	1		T38	1		T186	2
all_levels[13]	auto[0]	434899	1			T2	43		T9	4489		T22	1
all_levels[13]	auto[1]	34	1			T86	1		T349	1		T149	1
all_levels[14]	auto[0]	200039	1			T2	43		T7	1		T9	4492
all_levels[14]	auto[1]	33	1			T125	1		T338	1		T341	3
all_levels[15]	auto[0]	186519	1			T2	45		T9	4486		T20	1
all_levels[15]	auto[1]	127	1			T346	2		T163	1		T283	13
all_levels[16]	auto[0]	301497	1			T2	46		T7	1		T9	4482
all_levels[16]	auto[1]	32	1			T85	1		T126	1		T259	2
all_levels[17]	auto[0]	185327	1			T2	50		T7	2		T9	4474
all_levels[17]	auto[1]	24	1			T288	1		T126	3		T184	1
all_levels[18]	auto[0]	212404	1			T2	44		T9	4480		T263	5120
all_levels[18]	auto[1]	24	1			T126	1		T280	2		T191	2
all_levels[19]	auto[0]	240108	1			T2	45		T4	2		T9	4475
all_levels[19]	auto[1]	34	1			T189	3		T341	2		T142	4
all_levels[20]	auto[0]	245235	1			T2	48		T9	4475		T20	3
all_levels[20]	auto[1]	18	1			T115	1		T46	2		T38	2
all_levels[21]	auto[0]	231983	1			T2	48		T9	4313		T20	5
all_levels[21]	auto[1]	30	1			T149	3		T350	1		T210	1
all_levels[22]	auto[0]	245978	1			T2	53		T9	2366		T20	3
all_levels[22]	auto[1]	18	1			T286	2		T184	1		T185	1
all_levels[23]	auto[0]	165834	1			T2	55		T9	2330		T20	9
all_levels[23]	auto[1]	19	1			T46	1		T201	1		T134	1
all_levels[24]	auto[0]	479649	1			T2	44		T9	2360		T20	10
all_levels[24]	auto[1]	14	1			T286	1		T351	1		T352	1
all_levels[25]	auto[0]	440680	1			T2	57		T4	2		T7	1
all_levels[25]	auto[1]	16	1			T4	1		T104	1		T330	2
all_levels[26]	auto[0]	160785	1			T2	46		T4	1		T7	2
all_levels[26]	auto[1]	21	1			T86	1		T134	1		T345	1
all_levels[27]	auto[0]	246490	1			T2	53		T9	21833		T20	6
all_levels[27]	auto[1]	16	1			T353	2		T152	3		T220	1
all_levels[28]	auto[0]	238226	1			T2	47		T3	2		T9	1
all_levels[28]	auto[1]	17	1			T3	1		T121	1		T269	1
all_levels[29]	auto[0]	430857	1			T2	47		T9	1		T41	3
all_levels[29]	auto[1]	23	1			T185	1		T138	1		T354	1
all_levels[30]	auto[0]	153003	1			T2	51		T9	1		T263	5150
all_levels[30]	auto[1]	16	1			T182	1		T355	1		T195	1
all_levels[31]	auto[0]	468398	1			T2	1819		T9	1		T21	4
all_levels[31]	auto[1]	10	1			T134	1		T280	1		T356	1
all_levels[32]	auto[0]	14474077	1			T2	33853		T3	13		T4	32
all_levels[32]	auto[1]	507	1			T3	2		T4	2		T8	2