Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	838	1			T16	11		T19	4		T85	7
all_values[1]	838	1			T16	11		T19	4		T85	7
all_values[2]	838	1			T16	11		T19	4		T85	7
all_values[3]	838	1			T16	11		T19	4		T85	7
all_values[4]	838	1			T16	11		T19	4		T85	7
all_values[5]	838	1			T16	11		T19	4		T85	7
all_values[6]	838	1			T16	11		T19	4		T85	7
all_values[7]	838	1			T16	11		T19	4		T85	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3614

1

T16

49

T19

14

T85

29

auto[1]

3090

1

T16

39

T19

18

T85

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T16

28

T19

11

T85

20

auto[1]

4231

1

T16

60

T19

21

T85

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3974

1

T16

47

T19

19

T85

33

auto[1]

2730

1

T16

41

T19

13

T85

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	265	1			T16	3		T19	2		T85	3
all_values[0]	auto[0]	auto[1]	auto[1]	241	1			T16	2		T19	2		T85	3
all_values[0]	auto[1]	auto[0]	auto[1]	189	1			T16	4		T85	1		T35	1
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T16	2		T35	3		T118	3
all_values[1]	auto[0]	auto[0]	auto[0]	268	1			T16	4		T19	1		T85	2
all_values[1]	auto[0]	auto[1]	auto[0]	221	1			T16	2		T19	1		T85	1
all_values[1]	auto[1]	auto[0]	auto[1]	199	1			T16	1		T19	1		T118	3
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T16	4		T19	1		T85	4
all_values[2]	auto[0]	auto[0]	auto[0]	179	1			T16	2		T19	2		T85	1
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T16	1		T118	1		T38	2
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T19	1		T85	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[1]	96	1			T16	1		T85	2		T35	1
all_values[2]	auto[1]	auto[0]	auto[1]	205	1			T16	3		T85	3		T35	2
all_values[2]	auto[1]	auto[1]	auto[1]	147	1			T16	4		T19	1		T35	2
all_values[3]	auto[0]	auto[0]	auto[0]	159	1			T16	5		T35	1		T118	2
all_values[3]	auto[0]	auto[0]	auto[1]	95	1			T16	1		T118	1		T39	1
all_values[3]	auto[0]	auto[1]	auto[0]	144	1			T16	1		T85	1		T35	2
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T19	1		T85	1		T38	1
all_values[3]	auto[1]	auto[0]	auto[1]	213	1			T16	4		T19	2		T85	3
all_values[3]	auto[1]	auto[1]	auto[1]	143	1			T19	1		T85	2		T35	1
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T16	2		T39	1		T124	4
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T16	3		T85	1		T118	2
all_values[4]	auto[0]	auto[1]	auto[0]	154	1			T16	1		T85	1		T35	3
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T19	1		T85	1		T35	2
all_values[4]	auto[1]	auto[0]	auto[1]	197	1			T16	3		T19	2		T85	3
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T16	2		T19	1		T85	1
all_values[5]	auto[0]	auto[0]	auto[0]	205	1			T16	1		T85	5		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	74	1			T118	2		T38	2		T39	2
all_values[5]	auto[0]	auto[1]	auto[0]	155	1			T16	3		T85	1		T35	1
all_values[5]	auto[0]	auto[1]	auto[1]	72	1			T16	1		T19	1		T35	2
all_values[5]	auto[1]	auto[0]	auto[1]	189	1			T16	1		T35	3		T118	1
all_values[5]	auto[1]	auto[1]	auto[1]	143	1			T16	5		T19	3		T85	1
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T16	2		T19	2		T85	2
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T16	1		T39	2		T124	1
all_values[6]	auto[0]	auto[1]	auto[0]	164	1			T16	2		T19	2		T85	3
all_values[6]	auto[0]	auto[1]	auto[1]	100	1			T16	1		T118	2		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	181	1			T16	2		T85	2		T35	1
all_values[6]	auto[1]	auto[1]	auto[1]	160	1			T16	3		T118	2		T38	1
all_values[7]	auto[0]	auto[0]	auto[0]	196	1			T16	1		T85	1		T35	2
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T16	3		T19	1		T85	2
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T16	2		T19	2		T85	1
all_values[7]	auto[0]	auto[1]	auto[1]	89	1			T16	2		T35	2		T39	1
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T16	2		T19	1		T35	1
all_values[7]	auto[1]	auto[1]	auto[1]	154	1			T16	1		T85	3		T35	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal