Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.28	99.27	97.95	100.00		98.80	100.00	99.64

Total test records in report: 1319

T1258	/workspace/coverage/cover_reg_top/13.uart_intr_test.2247202202	Apr 15 03:24:31 PM PDT 24	Apr 15 03:24:33 PM PDT 24	120877179 ps
T1259	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1440185128	Apr 15 03:24:43 PM PDT 24	Apr 15 03:24:44 PM PDT 24	63455308 ps
T1260	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3344860696	Apr 15 03:24:36 PM PDT 24	Apr 15 03:24:39 PM PDT 24	166527832 ps
T1261	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.115557174	Apr 15 03:24:39 PM PDT 24	Apr 15 03:24:40 PM PDT 24	73536470 ps
T1262	/workspace/coverage/cover_reg_top/12.uart_tl_errors.3007322432	Apr 15 03:24:33 PM PDT 24	Apr 15 03:24:37 PM PDT 24	101263387 ps
T1263	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3445432232	Apr 15 03:24:24 PM PDT 24	Apr 15 03:24:26 PM PDT 24	28737247 ps
T1264	/workspace/coverage/cover_reg_top/11.uart_intr_test.2481161743	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:36 PM PDT 24	15090672 ps
T1265	/workspace/coverage/cover_reg_top/0.uart_intr_test.58463107	Apr 15 03:24:14 PM PDT 24	Apr 15 03:24:15 PM PDT 24	17043956 ps
T1266	/workspace/coverage/cover_reg_top/47.uart_intr_test.2875973117	Apr 15 03:24:52 PM PDT 24	Apr 15 03:24:53 PM PDT 24	12611836 ps
T1267	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2337635211	Apr 15 03:24:16 PM PDT 24	Apr 15 03:24:18 PM PDT 24	49607785 ps
T1268	/workspace/coverage/cover_reg_top/7.uart_intr_test.225285502	Apr 15 03:24:35 PM PDT 24	Apr 15 03:24:37 PM PDT 24	20007366 ps
T1269	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2547824575	Apr 15 03:24:21 PM PDT 24	Apr 15 03:24:22 PM PDT 24	15428795 ps
T122	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1742461983	Apr 15 03:24:28 PM PDT 24	Apr 15 03:24:31 PM PDT 24	90205747 ps
T1270	/workspace/coverage/cover_reg_top/10.uart_csr_rw.158370064	Apr 15 03:24:31 PM PDT 24	Apr 15 03:24:33 PM PDT 24	12713101 ps
T1271	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3587319256	Apr 15 03:24:19 PM PDT 24	Apr 15 03:24:20 PM PDT 24	20563760 ps
T70	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3374996460	Apr 15 03:24:18 PM PDT 24	Apr 15 03:24:20 PM PDT 24	38707231 ps
T1272	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.38942668	Apr 15 03:24:38 PM PDT 24	Apr 15 03:24:40 PM PDT 24	55153989 ps
T1273	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2970795114	Apr 15 03:24:13 PM PDT 24	Apr 15 03:24:14 PM PDT 24	152289227 ps
T1274	/workspace/coverage/cover_reg_top/1.uart_tl_errors.4026669686	Apr 15 03:24:21 PM PDT 24	Apr 15 03:24:23 PM PDT 24	75436840 ps
T1275	/workspace/coverage/cover_reg_top/46.uart_intr_test.2254029612	Apr 15 03:24:50 PM PDT 24	Apr 15 03:24:51 PM PDT 24	16714890 ps
T1276	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.606037650	Apr 15 03:24:27 PM PDT 24	Apr 15 03:24:28 PM PDT 24	599542493 ps
T1277	/workspace/coverage/cover_reg_top/4.uart_intr_test.975116733	Apr 15 03:24:23 PM PDT 24	Apr 15 03:24:24 PM PDT 24	24878157 ps
T1278	/workspace/coverage/cover_reg_top/37.uart_intr_test.2473897283	Apr 15 03:24:53 PM PDT 24	Apr 15 03:24:54 PM PDT 24	12526678 ps
T1279	/workspace/coverage/cover_reg_top/39.uart_intr_test.2145540842	Apr 15 03:24:47 PM PDT 24	Apr 15 03:24:49 PM PDT 24	26031683 ps
T1280	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2999927005	Apr 15 03:24:45 PM PDT 24	Apr 15 03:24:47 PM PDT 24	67463301 ps
T1281	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3486427877	Apr 15 03:24:27 PM PDT 24	Apr 15 03:24:29 PM PDT 24	31756705 ps
T1282	/workspace/coverage/cover_reg_top/6.uart_tl_errors.479059174	Apr 15 03:24:27 PM PDT 24	Apr 15 03:24:29 PM PDT 24	46917983 ps
T1283	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3076837108	Apr 15 03:24:42 PM PDT 24	Apr 15 03:24:45 PM PDT 24	98081542 ps
T1284	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.177293781	Apr 15 03:24:18 PM PDT 24	Apr 15 03:24:20 PM PDT 24	341693195 ps
T1285	/workspace/coverage/cover_reg_top/2.uart_tl_errors.795559922	Apr 15 03:24:17 PM PDT 24	Apr 15 03:24:19 PM PDT 24	217644588 ps
T1286	/workspace/coverage/cover_reg_top/41.uart_intr_test.3844858978	Apr 15 03:24:49 PM PDT 24	Apr 15 03:24:50 PM PDT 24	13648573 ps
T1287	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4089755674	Apr 15 03:24:39 PM PDT 24	Apr 15 03:24:40 PM PDT 24	26750675 ps
T1288	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.378957308	Apr 15 03:24:15 PM PDT 24	Apr 15 03:24:17 PM PDT 24	16147000 ps
T1289	/workspace/coverage/cover_reg_top/11.uart_tl_errors.1090838099	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:37 PM PDT 24	437641021 ps
T1290	/workspace/coverage/cover_reg_top/23.uart_intr_test.1410953312	Apr 15 03:24:45 PM PDT 24	Apr 15 03:24:46 PM PDT 24	46863700 ps
T123	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3575189034	Apr 15 03:24:37 PM PDT 24	Apr 15 03:24:39 PM PDT 24	100516849 ps
T1291	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1411096454	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:36 PM PDT 24	59666278 ps
T1292	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.415335725	Apr 15 03:24:12 PM PDT 24	Apr 15 03:24:14 PM PDT 24	287054502 ps
T1293	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.973284569	Apr 15 03:24:30 PM PDT 24	Apr 15 03:24:32 PM PDT 24	28962613 ps
T1294	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3960555553	Apr 15 03:24:28 PM PDT 24	Apr 15 03:24:30 PM PDT 24	77486989 ps
T1295	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2551289900	Apr 15 03:24:22 PM PDT 24	Apr 15 03:24:24 PM PDT 24	30491991 ps
T1296	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3880964573	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:37 PM PDT 24	30605247 ps
T1297	/workspace/coverage/cover_reg_top/40.uart_intr_test.943900410	Apr 15 03:24:48 PM PDT 24	Apr 15 03:24:49 PM PDT 24	188038414 ps
T1298	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1675479029	Apr 15 03:24:57 PM PDT 24	Apr 15 03:24:58 PM PDT 24	137706158 ps
T1299	/workspace/coverage/cover_reg_top/0.uart_tl_errors.2132507331	Apr 15 03:24:15 PM PDT 24	Apr 15 03:24:17 PM PDT 24	52004273 ps
T1300	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1858689547	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:36 PM PDT 24	27731507 ps
T1301	/workspace/coverage/cover_reg_top/14.uart_csr_rw.2222591216	Apr 15 03:24:38 PM PDT 24	Apr 15 03:24:40 PM PDT 24	62035422 ps
T1302	/workspace/coverage/cover_reg_top/17.uart_tl_errors.3657223674	Apr 15 03:24:39 PM PDT 24	Apr 15 03:24:41 PM PDT 24	290323503 ps
T1303	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2418173713	Apr 15 03:24:13 PM PDT 24	Apr 15 03:24:16 PM PDT 24	177311790 ps
T1304	/workspace/coverage/cover_reg_top/2.uart_intr_test.1809386139	Apr 15 03:24:21 PM PDT 24	Apr 15 03:24:22 PM PDT 24	178341453 ps
T1305	/workspace/coverage/cover_reg_top/20.uart_intr_test.3790779769	Apr 15 03:24:47 PM PDT 24	Apr 15 03:24:48 PM PDT 24	55703679 ps
T71	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1439186826	Apr 15 03:24:28 PM PDT 24	Apr 15 03:24:30 PM PDT 24	128249675 ps
T1306	/workspace/coverage/cover_reg_top/17.uart_intr_test.460356195	Apr 15 03:24:37 PM PDT 24	Apr 15 03:24:39 PM PDT 24	46884450 ps
T1307	/workspace/coverage/cover_reg_top/2.uart_csr_rw.914021644	Apr 15 03:24:20 PM PDT 24	Apr 15 03:24:21 PM PDT 24	103992961 ps
T1308	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3828068904	Apr 15 03:24:25 PM PDT 24	Apr 15 03:24:27 PM PDT 24	91736373 ps
T72	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1953388136	Apr 15 03:24:20 PM PDT 24	Apr 15 03:24:23 PM PDT 24	566303201 ps
T1309	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.901856805	Apr 15 03:24:36 PM PDT 24	Apr 15 03:24:38 PM PDT 24	41520456 ps
T1310	/workspace/coverage/cover_reg_top/43.uart_intr_test.3145128540	Apr 15 03:24:53 PM PDT 24	Apr 15 03:24:54 PM PDT 24	25394530 ps
T1311	/workspace/coverage/cover_reg_top/44.uart_intr_test.2721569166	Apr 15 03:24:48 PM PDT 24	Apr 15 03:24:50 PM PDT 24	122451842 ps
T1312	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1883841530	Apr 15 03:24:38 PM PDT 24	Apr 15 03:24:40 PM PDT 24	17273269 ps
T1313	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.620482020	Apr 15 03:24:24 PM PDT 24	Apr 15 03:24:25 PM PDT 24	21623474 ps
T1314	/workspace/coverage/cover_reg_top/31.uart_intr_test.1184042118	Apr 15 03:24:49 PM PDT 24	Apr 15 03:24:50 PM PDT 24	51510617 ps
T73	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4041502425	Apr 15 03:24:19 PM PDT 24	Apr 15 03:24:21 PM PDT 24	58390814 ps
T1315	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3643937455	Apr 15 03:24:33 PM PDT 24	Apr 15 03:24:35 PM PDT 24	17888053 ps
T1316	/workspace/coverage/cover_reg_top/12.uart_csr_rw.1824478590	Apr 15 03:24:34 PM PDT 24	Apr 15 03:24:36 PM PDT 24	172120448 ps
T1317	/workspace/coverage/cover_reg_top/32.uart_intr_test.725653710	Apr 15 03:24:47 PM PDT 24	Apr 15 03:24:48 PM PDT 24	14358414 ps
T1318	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2804614318	Apr 15 03:24:24 PM PDT 24	Apr 15 03:24:25 PM PDT 24	323384804 ps
T1319	/workspace/coverage/cover_reg_top/22.uart_intr_test.1093804126	Apr 15 03:24:47 PM PDT 24	Apr 15 03:24:48 PM PDT 24	18846144 ps
T74	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4074864329	Apr 15 03:24:29 PM PDT 24	Apr 15 03:24:31 PM PDT 24	38074675 ps

Test location	/workspace/coverage/default/19.uart_long_xfer_wo_dly.3172023379
Short name	T2
Test name
Test status
Simulation time	122856900286 ps
CPU time	400.75 seconds
Started	Apr 15 02:52:01 PM PDT 24
Finished	Apr 15 02:58:43 PM PDT 24
Peak memory	200928 kb
Host	smart-91eb52f9-f898-4bb0-87ec-05022fcc166c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3172023379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3172023379
Directory	/workspace/19.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_stress_all_with_rand_reset.874610218
Short name	T14
Test name
Test status
Simulation time	384291350817 ps
CPU time	930.31 seconds
Started	Apr 15 02:51:21 PM PDT 24
Finished	Apr 15 03:06:53 PM PDT 24
Peak memory	225576 kb
Host	smart-e2560fdb-e065-4c22-8971-9e905342c66e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874610218 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.874610218
Directory	/workspace/3.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.uart_stress_all_with_rand_reset.2142833219
Short name	T35
Test name
Test status
Simulation time	89835368846 ps
CPU time	841.19 seconds
Started	Apr 15 02:52:49 PM PDT 24
Finished	Apr 15 03:06:51 PM PDT 24
Peak memory	217356 kb
Host	smart-5862fc80-ad80-46fd-a14f-0540e6abde3b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142833219 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.2142833219
Directory	/workspace/30.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/50.uart_stress_all_with_rand_reset.26711951
Short name	T20
Test name
Test status
Simulation time	213090963846 ps
CPU time	358.52 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 03:00:13 PM PDT 24
Peak memory	215192 kb
Host	smart-48e980f9-82e0-4ab6-a208-9bf122518ec4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26711951 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.26711951
Directory	/workspace/50.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.uart_stress_all.227128814
Short name	T128
Test name
Test status
Simulation time	242810377214 ps
CPU time	469.62 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 03:00:58 PM PDT 24
Peak memory	217388 kb
Host	smart-cac8ca2c-533f-474b-8756-e5c9e06090a5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227128814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.227128814
Directory	/workspace/33.uart_stress_all/latest

Test location	/workspace/coverage/default/27.uart_intr.9064827
Short name	T15
Test name
Test status
Simulation time	61515005899 ps
CPU time	20.34 seconds
Started	Apr 15 02:52:30 PM PDT 24
Finished	Apr 15 02:52:51 PM PDT 24
Peak memory	200784 kb
Host	smart-ff57314b-c4a5-4ded-b1b0-a803f14aa11d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9064827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.9064827
Directory	/workspace/27.uart_intr/latest

Test location	/workspace/coverage/default/52.uart_stress_all_with_rand_reset.2751567364
Short name	T34
Test name
Test status
Simulation time	340299442204 ps
CPU time	578.34 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 03:03:52 PM PDT 24
Peak memory	211876 kb
Host	smart-5764ae83-5cef-48d3-aef4-0389babf3ad3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751567364 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2751567364
Directory	/workspace/52.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_sec_cm.3012507309
Short name	T30
Test name
Test status
Simulation time	405766181 ps
CPU time	0.84 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 02:51:20 PM PDT 24
Peak memory	219036 kb
Host	smart-7e2490af-4eb5-4b21-940d-59123140f11b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012507309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3012507309
Directory	/workspace/4.uart_sec_cm/latest

Test location	/workspace/coverage/default/254.uart_fifo_reset.302532594
Short name	T42
Test name
Test status
Simulation time	149855971951 ps
CPU time	85.37 seconds
Started	Apr 15 02:55:43 PM PDT 24
Finished	Apr 15 02:57:09 PM PDT 24
Peak memory	200852 kb
Host	smart-a974ba85-2106-444d-835f-48c102bef28f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302532594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.302532594
Directory	/workspace/254.uart_fifo_reset/latest

Test location	/workspace/coverage/default/1.uart_stress_all.4036546841
Short name	T178
Test name
Test status
Simulation time	363547770615 ps
CPU time	375.12 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:57:32 PM PDT 24
Peak memory	201112 kb
Host	smart-8d87e770-ade5-4c82-8f84-5ee90dce5bdd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036546841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4036546841
Directory	/workspace/1.uart_stress_all/latest

Test location	/workspace/coverage/default/5.uart_stress_all.260334873
Short name	T271
Test name
Test status
Simulation time	194264961295 ps
CPU time	305.2 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:56:51 PM PDT 24
Peak memory	200832 kb
Host	smart-36e9bb8f-0736-4b9d-b3b7-6b06bf077271
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260334873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.260334873
Directory	/workspace/5.uart_stress_all/latest

Test location	/workspace/coverage/default/88.uart_stress_all_with_rand_reset.586806150
Short name	T19
Test name
Test status
Simulation time	144804827568 ps
CPU time	1765.18 seconds
Started	Apr 15 02:54:30 PM PDT 24
Finished	Apr 15 03:23:56 PM PDT 24
Peak memory	217752 kb
Host	smart-5a460b0d-fab3-4c49-a682-8b3ea8058212
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586806150 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.586806150
Directory	/workspace/88.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_stress_all.4139607990
Short name	T184
Test name
Test status
Simulation time	273341926771 ps
CPU time	227.14 seconds
Started	Apr 15 02:52:34 PM PDT 24
Finished	Apr 15 02:56:22 PM PDT 24
Peak memory	209484 kb
Host	smart-654c3829-968c-472f-a24f-dcbfe723792b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139607990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4139607990
Directory	/workspace/27.uart_stress_all/latest

Test location	/workspace/coverage/default/10.uart_stress_all.1195560793
Short name	T410
Test name
Test status
Simulation time	371345392035 ps
CPU time	347.45 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 02:57:44 PM PDT 24
Peak memory	200908 kb
Host	smart-5c016f49-e0ca-43d8-b157-56f43749c98f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195560793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1195560793
Directory	/workspace/10.uart_stress_all/latest

Test location	/workspace/coverage/default/86.uart_stress_all_with_rand_reset.84822842
Short name	T24
Test name
Test status
Simulation time	177526468407 ps
CPU time	489.73 seconds
Started	Apr 15 02:54:32 PM PDT 24
Finished	Apr 15 03:02:43 PM PDT 24
Peak memory	225756 kb
Host	smart-333521ae-d61f-4b7d-a9db-dd2a17fa9945
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84822842 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.84822842
Directory	/workspace/86.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3871908675
Short name	T91
Test name
Test status
Simulation time	1290675844 ps
CPU time	1.28 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	199528 kb
Host	smart-1f9629f0-099f-4e32-80d7-e0fe9958129c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871908675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3871908675
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/28.uart_fifo_overflow.3924788746
Short name	T131
Test name
Test status
Simulation time	136421693916 ps
CPU time	142.22 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:54:56 PM PDT 24
Peak memory	200872 kb
Host	smart-2b9f6449-c20b-40c3-892f-b40ced5ad81e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924788746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3924788746
Directory	/workspace/28.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_alert_test.256640566
Short name	T416
Test name
Test status
Simulation time	22385480 ps
CPU time	0.57 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	196228 kb
Host	smart-25240597-8f2d-49f6-adb2-b41a537606ee
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256640566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.256640566
Directory	/workspace/13.uart_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.1304560796
Short name	T66
Test name
Test status
Simulation time	55285706 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:16 PM PDT 24
Finished	Apr 15 03:24:17 PM PDT 24
Peak memory	195536 kb
Host	smart-f17f504f-1418-4802-b181-b8032932773f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304560796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1304560796
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/default/56.uart_stress_all_with_rand_reset.3749324138
Short name	T146
Test name
Test status
Simulation time	335112486255 ps
CPU time	1030.12 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 03:11:23 PM PDT 24
Peak memory	225868 kb
Host	smart-474d2395-a9eb-4273-b30d-9b4a274788d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749324138 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3749324138
Directory	/workspace/56.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_stress_all.1928903010
Short name	T119
Test name
Test status
Simulation time	339882058525 ps
CPU time	266.24 seconds
Started	Apr 15 02:52:04 PM PDT 24
Finished	Apr 15 02:56:31 PM PDT 24
Peak memory	200880 kb
Host	smart-4861a416-73b8-40a5-b9d2-0944091688fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928903010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1928903010
Directory	/workspace/19.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_fifo_full.2361800154
Short name	T290
Test name
Test status
Simulation time	178072794736 ps
CPU time	83.8 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:55:23 PM PDT 24
Peak memory	200912 kb
Host	smart-924e08cd-922c-410e-b994-a515a081a125
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361800154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2361800154
Directory	/workspace/47.uart_fifo_full/latest

Test location	/workspace/coverage/default/71.uart_stress_all_with_rand_reset.379263179
Short name	T299
Test name
Test status
Simulation time	64961806492 ps
CPU time	1111.37 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:13:00 PM PDT 24
Peak memory	217392 kb
Host	smart-b79f2497-d2f1-42a1-878c-c98e27c9eb31
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379263179 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.379263179
Directory	/workspace/71.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_fifo_reset.2908036090
Short name	T139
Test name
Test status
Simulation time	121029540600 ps
CPU time	119.26 seconds
Started	Apr 15 02:53:50 PM PDT 24
Finished	Apr 15 02:55:50 PM PDT 24
Peak memory	200892 kb
Host	smart-aa4871e7-8a0f-4b16-b1fa-81a049fe3cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908036090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2908036090
Directory	/workspace/45.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_stress_all.3528054207
Short name	T85
Test name
Test status
Simulation time	135408361774 ps
CPU time	231.75 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:56:12 PM PDT 24
Peak memory	209516 kb
Host	smart-d8316436-2784-42d9-8944-aa91ea245184
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528054207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3528054207
Directory	/workspace/22.uart_stress_all/latest

Test location	/workspace/coverage/default/193.uart_fifo_reset.2803533526
Short name	T149
Test name
Test status
Simulation time	114143960588 ps
CPU time	74.17 seconds
Started	Apr 15 02:55:18 PM PDT 24
Finished	Apr 15 02:56:33 PM PDT 24
Peak memory	200912 kb
Host	smart-515ab4c1-fd51-40ca-8930-bf531366bfc2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803533526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2803533526
Directory	/workspace/193.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_fifo_full.2478062919
Short name	T141
Test name
Test status
Simulation time	164146225627 ps
CPU time	187.51 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200880 kb
Host	smart-9bcb4593-e24f-408a-a292-fad774c4c9ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478062919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2478062919
Directory	/workspace/15.uart_fifo_full/latest

Test location	/workspace/coverage/default/40.uart_fifo_full.2030213718
Short name	T296
Test name
Test status
Simulation time	82432435805 ps
CPU time	9.95 seconds
Started	Apr 15 02:53:26 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	200924 kb
Host	smart-3ed44066-78e3-408b-8ed0-35ef809ca10e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030213718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2030213718
Directory	/workspace/40.uart_fifo_full/latest

Test location	/workspace/coverage/default/50.uart_fifo_reset.3281361122
Short name	T134
Test name
Test status
Simulation time	57199075455 ps
CPU time	36.17 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 02:54:49 PM PDT 24
Peak memory	200832 kb
Host	smart-efbb275f-a47a-46bf-866b-96bbc49db994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281361122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3281361122
Directory	/workspace/50.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_stress_all_with_rand_reset.2614928552
Short name	T256
Test name
Test status
Simulation time	116739566798 ps
CPU time	338.77 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:57:47 PM PDT 24
Peak memory	211076 kb
Host	smart-35a7f49d-a581-4fa2-a006-a81bda4a4280
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614928552 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2614928552
Directory	/workspace/18.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/270.uart_fifo_reset.2153971557
Short name	T231
Test name
Test status
Simulation time	133833430355 ps
CPU time	176.18 seconds
Started	Apr 15 02:55:54 PM PDT 24
Finished	Apr 15 02:58:51 PM PDT 24
Peak memory	200928 kb
Host	smart-4aeaa8b0-b9e4-4b4f-9d08-64d1fdaef942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153971557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2153971557
Directory	/workspace/270.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_fifo_reset.592776648
Short name	T233
Test name
Test status
Simulation time	180442680382 ps
CPU time	69.05 seconds
Started	Apr 15 02:54:25 PM PDT 24
Finished	Apr 15 02:55:35 PM PDT 24
Peak memory	200676 kb
Host	smart-5ba32cd8-0cbe-425c-a78d-a1732e278152
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592776648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.592776648
Directory	/workspace/69.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3575189034
Short name	T123
Test name
Test status
Simulation time	100516849 ps
CPU time	1.32 seconds
Started	Apr 15 03:24:37 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	199252 kb
Host	smart-1079688f-3a13-4d0c-9724-6796351abd0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575189034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3575189034
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/21.uart_fifo_full.3905684551
Short name	T136
Test name
Test status
Simulation time	79299306380 ps
CPU time	33.32 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:47 PM PDT 24
Peak memory	200840 kb
Host	smart-67968077-f6de-4f1d-b966-d3da8369cbd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905684551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3905684551
Directory	/workspace/21.uart_fifo_full/latest

Test location	/workspace/coverage/default/221.uart_fifo_reset.326131953
Short name	T101
Test name
Test status
Simulation time	72573420661 ps
CPU time	58.8 seconds
Started	Apr 15 02:55:30 PM PDT 24
Finished	Apr 15 02:56:29 PM PDT 24
Peak memory	200848 kb
Host	smart-bbf4d92d-f65f-4ba9-a16a-08dec1e50f9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326131953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.326131953
Directory	/workspace/221.uart_fifo_reset/latest

Test location	/workspace/coverage/default/251.uart_fifo_reset.3347500489
Short name	T165
Test name
Test status
Simulation time	100041160327 ps
CPU time	129.86 seconds
Started	Apr 15 02:55:37 PM PDT 24
Finished	Apr 15 02:57:48 PM PDT 24
Peak memory	200896 kb
Host	smart-7dbbea40-0b51-43b0-b800-f7569a6ece5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347500489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3347500489
Directory	/workspace/251.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_stress_all_with_rand_reset.636678652
Short name	T289
Test name
Test status
Simulation time	220045634462 ps
CPU time	450.87 seconds
Started	Apr 15 02:53:21 PM PDT 24
Finished	Apr 15 03:00:53 PM PDT 24
Peak memory	217508 kb
Host	smart-7d65b752-430c-40e1-87a7-7b38ca3a19c2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636678652 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.636678652
Directory	/workspace/38.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.uart_fifo_reset.4286888497
Short name	T152
Test name
Test status
Simulation time	70207577430 ps
CPU time	31.75 seconds
Started	Apr 15 02:53:53 PM PDT 24
Finished	Apr 15 02:54:25 PM PDT 24
Peak memory	200932 kb
Host	smart-b76828d1-103b-4e6c-8ebe-560544162e6c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286888497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4286888497
Directory	/workspace/46.uart_fifo_reset/latest

Test location	/workspace/coverage/default/115.uart_fifo_reset.479367423
Short name	T242
Test name
Test status
Simulation time	20588535571 ps
CPU time	9.65 seconds
Started	Apr 15 02:54:46 PM PDT 24
Finished	Apr 15 02:54:57 PM PDT 24
Peak memory	200900 kb
Host	smart-6d379937-e62e-412d-9c17-da42efe5b72c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479367423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.479367423
Directory	/workspace/115.uart_fifo_reset/latest

Test location	/workspace/coverage/default/58.uart_stress_all_with_rand_reset.522859665
Short name	T283
Test name
Test status
Simulation time	112926685449 ps
CPU time	355.12 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 03:00:14 PM PDT 24
Peak memory	225792 kb
Host	smart-8b968ada-9420-4bd2-a3c7-48c7d3e9dee8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522859665 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.522859665
Directory	/workspace/58.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_fifo_reset.791129167
Short name	T254
Test name
Test status
Simulation time	82553353908 ps
CPU time	59.36 seconds
Started	Apr 15 02:51:23 PM PDT 24
Finished	Apr 15 02:52:23 PM PDT 24
Peak memory	200928 kb
Host	smart-b297c3f5-d70a-4c50-8168-07890b8ff1d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=791129167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.791129167
Directory	/workspace/0.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_fifo_overflow.2075117391
Short name	T148
Test name
Test status
Simulation time	296405471959 ps
CPU time	146.94 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:54:11 PM PDT 24
Peak memory	200868 kb
Host	smart-50ba9bbd-8967-4e49-a596-454d85f4bd02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075117391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2075117391
Directory	/workspace/12.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/136.uart_fifo_reset.2072697761
Short name	T189
Test name
Test status
Simulation time	109772410003 ps
CPU time	48.03 seconds
Started	Apr 15 02:54:57 PM PDT 24
Finished	Apr 15 02:55:45 PM PDT 24
Peak memory	200880 kb
Host	smart-da1eb576-d001-4d8d-88f3-14f4f96094d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072697761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2072697761
Directory	/workspace/136.uart_fifo_reset/latest

Test location	/workspace/coverage/default/153.uart_fifo_reset.2900867443
Short name	T984
Test name
Test status
Simulation time	23794501762 ps
CPU time	46.5 seconds
Started	Apr 15 02:55:02 PM PDT 24
Finished	Apr 15 02:55:49 PM PDT 24
Peak memory	200892 kb
Host	smart-f504bc6b-0557-4fda-a1f3-44056410a63c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900867443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2900867443
Directory	/workspace/153.uart_fifo_reset/latest

Test location	/workspace/coverage/default/175.uart_fifo_reset.3119198502
Short name	T258
Test name
Test status
Simulation time	200949067220 ps
CPU time	187.48 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:58:25 PM PDT 24
Peak memory	200880 kb
Host	smart-2d02c8be-eb6b-4cc3-8fa5-e6807073c64c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119198502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3119198502
Directory	/workspace/175.uart_fifo_reset/latest

Test location	/workspace/coverage/default/181.uart_fifo_reset.3423313500
Short name	T158
Test name
Test status
Simulation time	55006149910 ps
CPU time	56.36 seconds
Started	Apr 15 02:55:14 PM PDT 24
Finished	Apr 15 02:56:11 PM PDT 24
Peak memory	200852 kb
Host	smart-64b25a8a-2f58-42ba-9291-0d615c7090f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423313500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3423313500
Directory	/workspace/181.uart_fifo_reset/latest

Test location	/workspace/coverage/default/82.uart_stress_all_with_rand_reset.4290573577
Short name	T51
Test name
Test status
Simulation time	163281747691 ps
CPU time	953.54 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:10:23 PM PDT 24
Peak memory	227040 kb
Host	smart-bf91095b-62b4-492a-8a73-3939a524f94c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290573577 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.4290573577
Directory	/workspace/82.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_fifo_reset.2611809582
Short name	T220
Test name
Test status
Simulation time	136160640187 ps
CPU time	66.41 seconds
Started	Apr 15 02:54:44 PM PDT 24
Finished	Apr 15 02:55:51 PM PDT 24
Peak memory	200904 kb
Host	smart-71d5ae88-bb51-4fac-ad89-9887cec8ac6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611809582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2611809582
Directory	/workspace/98.uart_fifo_reset/latest

Test location	/workspace/coverage/default/144.uart_fifo_reset.1454598258
Short name	T129
Test name
Test status
Simulation time	114482915894 ps
CPU time	199.12 seconds
Started	Apr 15 02:54:58 PM PDT 24
Finished	Apr 15 02:58:18 PM PDT 24
Peak memory	200888 kb
Host	smart-a2f5448d-5b6a-44e7-931d-accec4b99160
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454598258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1454598258
Directory	/workspace/144.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_perf.3152921847
Short name	T267
Test name
Test status
Simulation time	29878367326 ps
CPU time	107.49 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:53:53 PM PDT 24
Peak memory	200836 kb
Host	smart-25563a27-50f3-4563-a4b3-82be9968a99d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3152921847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3152921847
Directory	/workspace/15.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_stress_all.4294032626
Short name	T338
Test name
Test status
Simulation time	68781443179 ps
CPU time	57.12 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	200788 kb
Host	smart-aca8b65c-ca59-48e7-9e5d-d2ebccf7b977
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294032626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.4294032626
Directory	/workspace/16.uart_stress_all/latest

Test location	/workspace/coverage/default/188.uart_fifo_reset.1827643528
Short name	T195
Test name
Test status
Simulation time	65414058855 ps
CPU time	20.32 seconds
Started	Apr 15 02:55:20 PM PDT 24
Finished	Apr 15 02:55:41 PM PDT 24
Peak memory	200796 kb
Host	smart-d0f6eb91-ad2a-469c-b234-1b438c314935
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827643528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1827643528
Directory	/workspace/188.uart_fifo_reset/latest

Test location	/workspace/coverage/default/196.uart_fifo_reset.2763288710
Short name	T209
Test name
Test status
Simulation time	44021572423 ps
CPU time	38.15 seconds
Started	Apr 15 02:55:20 PM PDT 24
Finished	Apr 15 02:55:59 PM PDT 24
Peak memory	200796 kb
Host	smart-8e5b1910-f3f9-4283-89cf-634e97cfa64e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763288710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2763288710
Directory	/workspace/196.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_fifo_reset.3121965300
Short name	T223
Test name
Test status
Simulation time	42003801205 ps
CPU time	86.13 seconds
Started	Apr 15 02:52:17 PM PDT 24
Finished	Apr 15 02:53:44 PM PDT 24
Peak memory	200912 kb
Host	smart-6293c4b2-ca25-4d2e-991e-21307b549bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121965300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3121965300
Directory	/workspace/24.uart_fifo_reset/latest

Test location	/workspace/coverage/default/69.uart_stress_all_with_rand_reset.2819654998
Short name	T153
Test name
Test status
Simulation time	1100271750227 ps
CPU time	1545.23 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:20:15 PM PDT 24
Peak memory	227940 kb
Host	smart-0bb76651-7a6d-4c5c-b13a-2638d8ea6408
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819654998 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2819654998
Directory	/workspace/69.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_stress_all.1526287075
Short name	T239
Test name
Test status
Simulation time	69025344180 ps
CPU time	59.39 seconds
Started	Apr 15 02:51:17 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	200880 kb
Host	smart-e93c2029-2779-4d31-88d5-7d6541dff139
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526287075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1526287075
Directory	/workspace/0.uart_stress_all/latest

Test location	/workspace/coverage/default/1.uart_fifo_full.3976265321
Short name	T691
Test name
Test status
Simulation time	177225686179 ps
CPU time	143.89 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	200932 kb
Host	smart-73fc5716-c7a6-49e1-ba2e-145fc34cc892
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976265321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3976265321
Directory	/workspace/1.uart_fifo_full/latest

Test location	/workspace/coverage/default/1.uart_fifo_reset.1050155247
Short name	T132
Test name
Test status
Simulation time	88155937978 ps
CPU time	76.03 seconds
Started	Apr 15 02:51:10 PM PDT 24
Finished	Apr 15 02:52:26 PM PDT 24
Peak memory	200920 kb
Host	smart-d973c4b6-67f3-4034-998b-bf7d5bb7c852
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050155247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1050155247
Directory	/workspace/1.uart_fifo_reset/latest

Test location	/workspace/coverage/default/103.uart_fifo_reset.1473337533
Short name	T150
Test name
Test status
Simulation time	8135393778 ps
CPU time	15.5 seconds
Started	Apr 15 02:54:43 PM PDT 24
Finished	Apr 15 02:54:59 PM PDT 24
Peak memory	200924 kb
Host	smart-82dec4d8-3e64-4da4-bd53-48159108101e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1473337533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1473337533
Directory	/workspace/103.uart_fifo_reset/latest

Test location	/workspace/coverage/default/116.uart_fifo_reset.3230972258
Short name	T245
Test name
Test status
Simulation time	59224899528 ps
CPU time	31.73 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:55:21 PM PDT 24
Peak memory	201044 kb
Host	smart-73fedc29-30c4-486c-a2ac-710dcb9144de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230972258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3230972258
Directory	/workspace/116.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_stress_all.2918985228
Short name	T16
Test name
Test status
Simulation time	20549299276 ps
CPU time	143.54 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:54:14 PM PDT 24
Peak memory	200636 kb
Host	smart-51d39556-b71e-45bf-aaef-12e73e95d0e5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918985228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2918985228
Directory	/workspace/12.uart_stress_all/latest

Test location	/workspace/coverage/default/127.uart_fifo_reset.3332928987
Short name	T405
Test name
Test status
Simulation time	26666116976 ps
CPU time	17.8 seconds
Started	Apr 15 02:54:50 PM PDT 24
Finished	Apr 15 02:55:09 PM PDT 24
Peak memory	200708 kb
Host	smart-ebb222f6-c286-4abd-921b-e897147cab1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332928987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3332928987
Directory	/workspace/127.uart_fifo_reset/latest

Test location	/workspace/coverage/default/135.uart_fifo_reset.4209344729
Short name	T215
Test name
Test status
Simulation time	62655655083 ps
CPU time	15.53 seconds
Started	Apr 15 02:54:55 PM PDT 24
Finished	Apr 15 02:55:11 PM PDT 24
Peak memory	200796 kb
Host	smart-9393e5b1-7c51-47a0-bc44-6e40c73a6713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209344729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4209344729
Directory	/workspace/135.uart_fifo_reset/latest

Test location	/workspace/coverage/default/160.uart_fifo_reset.2065180611
Short name	T252
Test name
Test status
Simulation time	17884120312 ps
CPU time	16.25 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:55:25 PM PDT 24
Peak memory	200912 kb
Host	smart-6f7ccd80-efd2-4cf5-b663-8a55ae13d746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2065180611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2065180611
Directory	/workspace/160.uart_fifo_reset/latest

Test location	/workspace/coverage/default/161.uart_fifo_reset.523838095
Short name	T251
Test name
Test status
Simulation time	141196589846 ps
CPU time	87.14 seconds
Started	Apr 15 02:55:07 PM PDT 24
Finished	Apr 15 02:56:35 PM PDT 24
Peak memory	200924 kb
Host	smart-889eef0e-b347-4890-926a-30cd43164207
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523838095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.523838095
Directory	/workspace/161.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_fifo_reset.4087485604
Short name	T187
Test name
Test status
Simulation time	133747826745 ps
CPU time	189.1 seconds
Started	Apr 15 02:51:50 PM PDT 24
Finished	Apr 15 02:55:00 PM PDT 24
Peak memory	200892 kb
Host	smart-5936e509-0db0-4e10-aa52-4be068479f7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087485604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.4087485604
Directory	/workspace/17.uart_fifo_reset/latest

Test location	/workspace/coverage/default/182.uart_fifo_reset.1613872626
Short name	T211
Test name
Test status
Simulation time	124610801675 ps
CPU time	64.03 seconds
Started	Apr 15 02:55:15 PM PDT 24
Finished	Apr 15 02:56:21 PM PDT 24
Peak memory	200788 kb
Host	smart-c6a59a9d-09c0-4020-8356-44105506034f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613872626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1613872626
Directory	/workspace/182.uart_fifo_reset/latest

Test location	/workspace/coverage/default/190.uart_fifo_reset.930623384
Short name	T243
Test name
Test status
Simulation time	62735639880 ps
CPU time	30.27 seconds
Started	Apr 15 02:55:22 PM PDT 24
Finished	Apr 15 02:55:53 PM PDT 24
Peak memory	200932 kb
Host	smart-443e911d-9fb0-48d9-a002-86805e193e78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930623384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.930623384
Directory	/workspace/190.uart_fifo_reset/latest

Test location	/workspace/coverage/default/192.uart_fifo_reset.1928054834
Short name	T196
Test name
Test status
Simulation time	87935409324 ps
CPU time	73.47 seconds
Started	Apr 15 02:55:20 PM PDT 24
Finished	Apr 15 02:56:34 PM PDT 24
Peak memory	200920 kb
Host	smart-c476e799-422c-407b-838b-c84f95bffa81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1928054834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1928054834
Directory	/workspace/192.uart_fifo_reset/latest

Test location	/workspace/coverage/default/205.uart_fifo_reset.111693075
Short name	T227
Test name
Test status
Simulation time	87303798384 ps
CPU time	232.84 seconds
Started	Apr 15 02:55:27 PM PDT 24
Finished	Apr 15 02:59:21 PM PDT 24
Peak memory	200932 kb
Host	smart-24f40c1f-7f60-4933-b113-6a9fdadf1e5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111693075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.111693075
Directory	/workspace/205.uart_fifo_reset/latest

Test location	/workspace/coverage/default/224.uart_fifo_reset.22902302
Short name	T229
Test name
Test status
Simulation time	134449780077 ps
CPU time	48.41 seconds
Started	Apr 15 02:55:38 PM PDT 24
Finished	Apr 15 02:56:28 PM PDT 24
Peak memory	200712 kb
Host	smart-8bb62766-e79c-4e2e-836f-a721245e4f34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22902302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.22902302
Directory	/workspace/224.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_fifo_reset.3662217424
Short name	T213
Test name
Test status
Simulation time	123452314686 ps
CPU time	27.43 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:53:00 PM PDT 24
Peak memory	200836 kb
Host	smart-3dc6bd6f-3769-4975-b735-dfbfc5b82e09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662217424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3662217424
Directory	/workspace/26.uart_fifo_reset/latest

Test location	/workspace/coverage/default/262.uart_fifo_reset.4221792468
Short name	T201
Test name
Test status
Simulation time	89384707110 ps
CPU time	65.25 seconds
Started	Apr 15 02:55:50 PM PDT 24
Finished	Apr 15 02:56:56 PM PDT 24
Peak memory	200936 kb
Host	smart-1d6cf051-c473-4f36-bbd5-6f1fe12b1dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221792468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4221792468
Directory	/workspace/262.uart_fifo_reset/latest

Test location	/workspace/coverage/default/291.uart_fifo_reset.2283293734
Short name	T160
Test name
Test status
Simulation time	23055465655 ps
CPU time	45.61 seconds
Started	Apr 15 02:56:03 PM PDT 24
Finished	Apr 15 02:56:50 PM PDT 24
Peak memory	200664 kb
Host	smart-ecc7ffca-8066-405c-a713-955b1bb950df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283293734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2283293734
Directory	/workspace/291.uart_fifo_reset/latest

Test location	/workspace/coverage/default/32.uart_fifo_reset.4168724292
Short name	T255
Test name
Test status
Simulation time	25567946685 ps
CPU time	24.53 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:53:13 PM PDT 24
Peak memory	200852 kb
Host	smart-dbc88f3d-5102-4df1-812e-4060c0abd0b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4168724292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4168724292
Directory	/workspace/32.uart_fifo_reset/latest

Test location	/workspace/coverage/default/37.uart_fifo_reset.3359595294
Short name	T163
Test name
Test status
Simulation time	124067305460 ps
CPU time	29.32 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	200944 kb
Host	smart-f1ff7176-66cc-4210-bf2d-62365c8f432d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359595294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3359595294
Directory	/workspace/37.uart_fifo_reset/latest

Test location	/workspace/coverage/default/55.uart_fifo_reset.1754627529
Short name	T156
Test name
Test status
Simulation time	58556693512 ps
CPU time	57.26 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 02:55:11 PM PDT 24
Peak memory	200896 kb
Host	smart-994018f1-2c9e-429b-ada1-cc8330a7f828
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754627529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1754627529
Directory	/workspace/55.uart_fifo_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2547824575
Short name	T1269
Test name
Test status
Simulation time	15428795 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:21 PM PDT 24
Finished	Apr 15 03:24:22 PM PDT 24
Peak memory	196940 kb
Host	smart-1dfecb61-d70e-4800-9ac4-4f4431cbec91
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547824575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2547824575
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2418173713
Short name	T1303
Test name
Test status
Simulation time	177311790 ps
CPU time	1.48 seconds
Started	Apr 15 03:24:13 PM PDT 24
Finished	Apr 15 03:24:16 PM PDT 24
Peak memory	198040 kb
Host	smart-5aed5349-5a37-4490-8335-b0f585b6fb84
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418173713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2418173713
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2970795114
Short name	T1273
Test name
Test status
Simulation time	152289227 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:13 PM PDT 24
Finished	Apr 15 03:24:14 PM PDT 24
Peak memory	195460 kb
Host	smart-ff30faec-0385-4880-b348-26c525b22f94
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970795114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2970795114
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3182668007
Short name	T1213
Test name
Test status
Simulation time	68854524 ps
CPU time	0.72 seconds
Started	Apr 15 03:24:15 PM PDT 24
Finished	Apr 15 03:24:17 PM PDT 24
Peak memory	198832 kb
Host	smart-401f9854-da33-45b4-8e35-c07b47d947a5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182668007 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3182668007
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.3783350186
Short name	T84
Test name
Test status
Simulation time	18012130 ps
CPU time	0.66 seconds
Started	Apr 15 03:24:19 PM PDT 24
Finished	Apr 15 03:24:21 PM PDT 24
Peak memory	195444 kb
Host	smart-b46075f4-80a5-4ad4-96e3-360e1d21c313
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783350186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3783350186
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.58463107
Short name	T1265
Test name
Test status
Simulation time	17043956 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:14 PM PDT 24
Finished	Apr 15 03:24:15 PM PDT 24
Peak memory	194428 kb
Host	smart-23e645ac-5d87-45e6-b609-c200f1b50693
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58463107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.58463107
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1722889408
Short name	T80
Test name
Test status
Simulation time	82142846 ps
CPU time	0.67 seconds
Started	Apr 15 03:24:20 PM PDT 24
Finished	Apr 15 03:24:22 PM PDT 24
Peak memory	195956 kb
Host	smart-49f235e2-0c09-4a53-bf1b-36f9a8ef6512
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722889408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.1722889408
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.2132507331
Short name	T1299
Test name
Test status
Simulation time	52004273 ps
CPU time	1.43 seconds
Started	Apr 15 03:24:15 PM PDT 24
Finished	Apr 15 03:24:17 PM PDT 24
Peak memory	200124 kb
Host	smart-11e4c448-aa00-4222-a09b-2935e2eb0cdf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132507331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2132507331
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.415335725
Short name	T1292
Test name
Test status
Simulation time	287054502 ps
CPU time	0.9 seconds
Started	Apr 15 03:24:12 PM PDT 24
Finished	Apr 15 03:24:14 PM PDT 24
Peak memory	198712 kb
Host	smart-91b7a368-6836-45f0-81ee-718e6ae972fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415335725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.415335725
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.378957308
Short name	T1288
Test name
Test status
Simulation time	16147000 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:15 PM PDT 24
Finished	Apr 15 03:24:17 PM PDT 24
Peak memory	196376 kb
Host	smart-091ab174-5a0a-4d30-8f46-828738aea84c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378957308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.378957308
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3697582607
Short name	T65
Test name
Test status
Simulation time	132936643 ps
CPU time	1.59 seconds
Started	Apr 15 03:24:17 PM PDT 24
Finished	Apr 15 03:24:19 PM PDT 24
Peak memory	197760 kb
Host	smart-2e4c47c3-a829-4679-a007-83d7ef5cf0df
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697582607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3697582607
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2603984568
Short name	T1190
Test name
Test status
Simulation time	69565789 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:17 PM PDT 24
Finished	Apr 15 03:24:18 PM PDT 24
Peak memory	195476 kb
Host	smart-6a4164ec-da74-48fb-8110-6bc515647bef
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603984568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2603984568
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.962516926
Short name	T1199
Test name
Test status
Simulation time	112962570 ps
CPU time	0.82 seconds
Started	Apr 15 03:24:17 PM PDT 24
Finished	Apr 15 03:24:19 PM PDT 24
Peak memory	199732 kb
Host	smart-bab1c01a-f9be-493f-b330-907bbe8ccfc5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962516926 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.962516926
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.3955938527
Short name	T1202
Test name
Test status
Simulation time	86483840 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:18 PM PDT 24
Finished	Apr 15 03:24:19 PM PDT 24
Peak memory	194452 kb
Host	smart-548642ad-3149-429e-8230-0e70e50a9823
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955938527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3955938527
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3539771257
Short name	T81
Test name
Test status
Simulation time	16382766 ps
CPU time	0.7 seconds
Started	Apr 15 03:24:15 PM PDT 24
Finished	Apr 15 03:24:16 PM PDT 24
Peak memory	195856 kb
Host	smart-5685e98d-2d0b-47a5-9318-cf16d1c91628
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539771257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.3539771257
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.4026669686
Short name	T1274
Test name
Test status
Simulation time	75436840 ps
CPU time	1.75 seconds
Started	Apr 15 03:24:21 PM PDT 24
Finished	Apr 15 03:24:23 PM PDT 24
Peak memory	200088 kb
Host	smart-7d96c7aa-7979-4fc0-bad4-b34f5b032adf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026669686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.4026669686
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.177293781
Short name	T1284
Test name
Test status
Simulation time	341693195 ps
CPU time	1.42 seconds
Started	Apr 15 03:24:18 PM PDT 24
Finished	Apr 15 03:24:20 PM PDT 24
Peak memory	199700 kb
Host	smart-5346bf68-efbb-4ffb-835c-bae5f137c48d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177293781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.177293781
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.337426139
Short name	T1246
Test name
Test status
Simulation time	81184171 ps
CPU time	0.75 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	198292 kb
Host	smart-59cda696-7f36-4f7e-92ba-eed741f555cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337426139 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.337426139
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.158370064
Short name	T1270
Test name
Test status
Simulation time	12713101 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	195460 kb
Host	smart-68124a52-b412-466c-a2fb-07359326a5a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158370064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.158370064
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.1857037734
Short name	T1196
Test name
Test status
Simulation time	24122585 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:32 PM PDT 24
Finished	Apr 15 03:24:34 PM PDT 24
Peak memory	194380 kb
Host	smart-ec1b72ef-10ad-4734-88bc-456255c3dda1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857037734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1857037734
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1411096454
Short name	T1291
Test name
Test status
Simulation time	59666278 ps
CPU time	0.77 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	196968 kb
Host	smart-9ba8434c-8c4d-4edf-8d6b-4844ba17da92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411096454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.1411096454
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.4125362202
Short name	T1232
Test name
Test status
Simulation time	36365222 ps
CPU time	1.13 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	200088 kb
Host	smart-4bc5bffc-aede-4535-86a5-5488ecc65475
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125362202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.4125362202
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3702617795
Short name	T1251
Test name
Test status
Simulation time	55102442 ps
CPU time	0.99 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	199156 kb
Host	smart-4da28dc8-6483-4b99-ac33-1bbb460c3ed1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702617795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3702617795
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.784126971
Short name	T1237
Test name
Test status
Simulation time	55374861 ps
CPU time	0.66 seconds
Started	Apr 15 03:24:32 PM PDT 24
Finished	Apr 15 03:24:34 PM PDT 24
Peak memory	197324 kb
Host	smart-f7f3f906-e798-4e98-8d68-8099f9b1ff60
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784126971 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.784126971
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2160990177
Short name	T76
Test name
Test status
Simulation time	72484161 ps
CPU time	0.64 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	195484 kb
Host	smart-29b39510-f049-4bcc-80c9-79021fb03f63
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160990177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2160990177
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.2481161743
Short name	T1264
Test name
Test status
Simulation time	15090672 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	194368 kb
Host	smart-fd717beb-7e7b-400b-a926-bb783003a516
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481161743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2481161743
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.973284569
Short name	T1293
Test name
Test status
Simulation time	28962613 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:30 PM PDT 24
Finished	Apr 15 03:24:32 PM PDT 24
Peak memory	197696 kb
Host	smart-8929bd61-a5e9-4e55-a4b7-1d2dfa0d5939
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973284569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr _outstanding.973284569
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.1090838099
Short name	T1289
Test name
Test status
Simulation time	437641021 ps
CPU time	2.38 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	200076 kb
Host	smart-25236c5f-7e81-4596-992c-03adaf9e60e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090838099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1090838099
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2925283011
Short name	T90
Test name
Test status
Simulation time	139757158 ps
CPU time	1.29 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	199212 kb
Host	smart-8d068da8-5edc-4267-b1d2-688f0e335036
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925283011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2925283011
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3880964573
Short name	T1296
Test name
Test status
Simulation time	30605247 ps
CPU time	0.91 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	199820 kb
Host	smart-391cef62-5f42-445a-8305-69ef242a6d39
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880964573 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3880964573
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.1824478590
Short name	T1316
Test name
Test status
Simulation time	172120448 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	195540 kb
Host	smart-afb2d566-a073-4292-8f8d-445e4ab4c15e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824478590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1824478590
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.366206441
Short name	T1191
Test name
Test status
Simulation time	111282083 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:32 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	194360 kb
Host	smart-b26ce329-c2cb-4f3b-9f89-7f574bce736f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366206441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.366206441
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1653523824
Short name	T83
Test name
Test status
Simulation time	50120777 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:29 PM PDT 24
Finished	Apr 15 03:24:31 PM PDT 24
Peak memory	197096 kb
Host	smart-bdf2082e-c575-4ba0-a8e1-5eb252630250
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653523824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.1653523824
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.3007322432
Short name	T1262
Test name
Test status
Simulation time	101263387 ps
CPU time	2.67 seconds
Started	Apr 15 03:24:33 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	200132 kb
Host	smart-1bcc786d-17d2-4dc4-8272-298ecb9aedac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007322432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3007322432
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1319471101
Short name	T94
Test name
Test status
Simulation time	98499699 ps
CPU time	1.36 seconds
Started	Apr 15 03:24:33 PM PDT 24
Finished	Apr 15 03:24:35 PM PDT 24
Peak memory	199248 kb
Host	smart-72a6d599-e7c0-4bd0-be23-5d17e61cdcc7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319471101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1319471101
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3452363527
Short name	T1205
Test name
Test status
Simulation time	79265237 ps
CPU time	1.12 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	200156 kb
Host	smart-2d33fbc5-fb59-4e7e-9617-6ae05fd88491
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452363527 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3452363527
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3643937455
Short name	T1315
Test name
Test status
Simulation time	17888053 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:33 PM PDT 24
Finished	Apr 15 03:24:35 PM PDT 24
Peak memory	195636 kb
Host	smart-6a3ecb2d-0da0-4e9d-8ec0-b3905f7fe72e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643937455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3643937455
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.2247202202
Short name	T1258
Test name
Test status
Simulation time	120877179 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:31 PM PDT 24
Finished	Apr 15 03:24:33 PM PDT 24
Peak memory	194452 kb
Host	smart-f2be31c1-086b-4fb1-9a8f-4f5c8b9915f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247202202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2247202202
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3039421928
Short name	T1255
Test name
Test status
Simulation time	29777336 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:30 PM PDT 24
Finished	Apr 15 03:24:32 PM PDT 24
Peak memory	197628 kb
Host	smart-55b8ef81-529d-4471-84f6-7c704a8637e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039421928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3039421928
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.1978642515
Short name	T1187
Test name
Test status
Simulation time	23025996 ps
CPU time	1.03 seconds
Started	Apr 15 03:24:30 PM PDT 24
Finished	Apr 15 03:24:32 PM PDT 24
Peak memory	199892 kb
Host	smart-be85c3ef-14c1-4598-93d0-7b929fcb3916
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978642515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1978642515
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1675479029
Short name	T1298
Test name
Test status
Simulation time	137706158 ps
CPU time	0.86 seconds
Started	Apr 15 03:24:57 PM PDT 24
Finished	Apr 15 03:24:58 PM PDT 24
Peak memory	199040 kb
Host	smart-4a054312-a5ba-46cd-ac3d-054209cc8541
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675479029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1675479029
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1883841530
Short name	T1312
Test name
Test status
Simulation time	17273269 ps
CPU time	0.89 seconds
Started	Apr 15 03:24:38 PM PDT 24
Finished	Apr 15 03:24:40 PM PDT 24
Peak memory	199884 kb
Host	smart-1f4c5932-3148-46dc-a56c-f557b5a89cab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883841530 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1883841530
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.2222591216
Short name	T1301
Test name
Test status
Simulation time	62035422 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:38 PM PDT 24
Finished	Apr 15 03:24:40 PM PDT 24
Peak memory	195452 kb
Host	smart-29701522-6eea-4a92-b727-fad51579b442
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222591216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2222591216
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.3706670244
Short name	T1242
Test name
Test status
Simulation time	42207930 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:38 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	194312 kb
Host	smart-6ff0b9b2-8465-404f-96d3-ee436182f8f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706670244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3706670244
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.901856805
Short name	T1309
Test name
Test status
Simulation time	41520456 ps
CPU time	0.65 seconds
Started	Apr 15 03:24:36 PM PDT 24
Finished	Apr 15 03:24:38 PM PDT 24
Peak memory	195528 kb
Host	smart-e0d29109-fade-4a4d-bacc-cdb0f0aba65c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901856805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr _outstanding.901856805
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.3344860696
Short name	T1260
Test name
Test status
Simulation time	166527832 ps
CPU time	1.7 seconds
Started	Apr 15 03:24:36 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	200168 kb
Host	smart-5993fb40-a2b1-40ba-a5a1-8ad441de8048
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344860696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3344860696
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1513163590
Short name	T1225
Test name
Test status
Simulation time	52298526 ps
CPU time	0.72 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:41 PM PDT 24
Peak memory	198004 kb
Host	smart-b2c94b99-bef3-4936-ad79-63124ee448c5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513163590 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1513163590
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.2288679345
Short name	T1249
Test name
Test status
Simulation time	13842267 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:40 PM PDT 24
Finished	Apr 15 03:24:41 PM PDT 24
Peak memory	195496 kb
Host	smart-ab304bb2-508e-4eb6-af3d-7d80409b22a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288679345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2288679345
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.3597984156
Short name	T1227
Test name
Test status
Simulation time	40182002 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:37 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	194368 kb
Host	smart-00a2c8a5-583b-4acc-a022-b9b6de014f30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597984156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3597984156
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.283636231
Short name	T82
Test name
Test status
Simulation time	22640485 ps
CPU time	0.66 seconds
Started	Apr 15 03:24:41 PM PDT 24
Finished	Apr 15 03:24:43 PM PDT 24
Peak memory	195744 kb
Host	smart-930c31ca-0d84-4455-be52-4147ce3d404e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283636231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr _outstanding.283636231
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.3782136846
Short name	T1224
Test name
Test status
Simulation time	29169308 ps
CPU time	1.37 seconds
Started	Apr 15 03:24:36 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	200076 kb
Host	smart-bf0352d6-5e3f-48c6-a55a-f377512835d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782136846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3782136846
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2165109815
Short name	T88
Test name
Test status
Simulation time	82864300 ps
CPU time	1.29 seconds
Started	Apr 15 03:24:35 PM PDT 24
Finished	Apr 15 03:24:38 PM PDT 24
Peak memory	199084 kb
Host	smart-d2b235f2-f061-43a1-af83-68a383570ef0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165109815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2165109815
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.645640244
Short name	T1248
Test name
Test status
Simulation time	27990631 ps
CPU time	1.24 seconds
Started	Apr 15 03:24:40 PM PDT 24
Finished	Apr 15 03:24:42 PM PDT 24
Peak memory	200116 kb
Host	smart-ab0d38b5-4ecd-431b-b270-594135025acf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645640244 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.645640244
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.3784629225
Short name	T1216
Test name
Test status
Simulation time	51830980 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:41 PM PDT 24
Finished	Apr 15 03:24:43 PM PDT 24
Peak memory	195352 kb
Host	smart-5696cfd7-7cd8-44d2-b149-597d961eb5ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784629225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3784629225
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.650560763
Short name	T1198
Test name
Test status
Simulation time	14423867 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:41 PM PDT 24
Finished	Apr 15 03:24:42 PM PDT 24
Peak memory	194388 kb
Host	smart-82d421ba-c393-4cd7-beac-d469fd379a45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650560763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.650560763
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.115557174
Short name	T1261
Test name
Test status
Simulation time	73536470 ps
CPU time	0.65 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:40 PM PDT 24
Peak memory	195708 kb
Host	smart-560b6b99-8d74-41fe-9423-0320f2cdc38e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115557174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr _outstanding.115557174
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3076837108
Short name	T1283
Test name
Test status
Simulation time	98081542 ps
CPU time	2.18 seconds
Started	Apr 15 03:24:42 PM PDT 24
Finished	Apr 15 03:24:45 PM PDT 24
Peak memory	200148 kb
Host	smart-9a5a6108-d941-4e88-aa63-99f89f106b87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076837108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3076837108
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.38942668
Short name	T1272
Test name
Test status
Simulation time	55153989 ps
CPU time	0.97 seconds
Started	Apr 15 03:24:38 PM PDT 24
Finished	Apr 15 03:24:40 PM PDT 24
Peak memory	199004 kb
Host	smart-cd9d7844-888e-406b-aab7-55c5b908cd24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38942668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.38942668
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.4089755674
Short name	T1287
Test name
Test status
Simulation time	26750675 ps
CPU time	0.77 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:40 PM PDT 24
Peak memory	198832 kb
Host	smart-250a14a0-eca2-4c4b-a0c0-01db149eb6b6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089755674 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.4089755674
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.2066625671
Short name	T68
Test name
Test status
Simulation time	13932697 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:40 PM PDT 24
Finished	Apr 15 03:24:42 PM PDT 24
Peak memory	195516 kb
Host	smart-99e7b257-5cd8-4927-865d-975a9d752932
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066625671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2066625671
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.460356195
Short name	T1306
Test name
Test status
Simulation time	46884450 ps
CPU time	0.55 seconds
Started	Apr 15 03:24:37 PM PDT 24
Finished	Apr 15 03:24:39 PM PDT 24
Peak memory	194340 kb
Host	smart-9ae3978d-72c4-479a-92a1-f3020c2ae09c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460356195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.460356195
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2196228299
Short name	T1239
Test name
Test status
Simulation time	64561737 ps
CPU time	0.65 seconds
Started	Apr 15 03:24:41 PM PDT 24
Finished	Apr 15 03:24:43 PM PDT 24
Peak memory	194704 kb
Host	smart-a60837e1-179e-4533-8c8f-aafba46b86c9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196228299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.2196228299
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.3657223674
Short name	T1302
Test name
Test status
Simulation time	290323503 ps
CPU time	1.82 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:41 PM PDT 24
Peak memory	200056 kb
Host	smart-3ad86585-57c2-4d51-b700-68bf649e9bde
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657223674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3657223674
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.890489422
Short name	T92
Test name
Test status
Simulation time	1250645276 ps
CPU time	1.62 seconds
Started	Apr 15 03:24:40 PM PDT 24
Finished	Apr 15 03:24:43 PM PDT 24
Peak memory	199236 kb
Host	smart-3bdc25e9-850d-4d14-9381-ba0fe5eb1373
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890489422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.890489422
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3625815294
Short name	T1201
Test name
Test status
Simulation time	144140387 ps
CPU time	0.86 seconds
Started	Apr 15 03:24:44 PM PDT 24
Finished	Apr 15 03:24:46 PM PDT 24
Peak memory	199812 kb
Host	smart-4a558822-edd2-4111-adf6-f4ee903af86c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625815294 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3625815294
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.1851377834
Short name	T67
Test name
Test status
Simulation time	53475848 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:43 PM PDT 24
Finished	Apr 15 03:24:44 PM PDT 24
Peak memory	195588 kb
Host	smart-3bebd2ba-cc7e-4c54-a4bc-598a9d1bb43f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851377834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1851377834
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.1712771737
Short name	T1212
Test name
Test status
Simulation time	25535267 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:40 PM PDT 24
Finished	Apr 15 03:24:41 PM PDT 24
Peak memory	194396 kb
Host	smart-3339ace5-be99-4db2-be0f-5df9b25d6d10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712771737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1712771737
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1440185128
Short name	T1259
Test name
Test status
Simulation time	63455308 ps
CPU time	0.74 seconds
Started	Apr 15 03:24:43 PM PDT 24
Finished	Apr 15 03:24:44 PM PDT 24
Peak memory	197728 kb
Host	smart-3b8a5ffd-7221-452c-89a9-df185a0dac9c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440185128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.1440185128
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.2067331169
Short name	T1206
Test name
Test status
Simulation time	120897869 ps
CPU time	1.25 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:42 PM PDT 24
Peak memory	200156 kb
Host	smart-8eac741a-88e8-4380-b6b7-ec8606d8faee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067331169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2067331169
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1215635058
Short name	T95
Test name
Test status
Simulation time	198718880 ps
CPU time	1.03 seconds
Started	Apr 15 03:24:39 PM PDT 24
Finished	Apr 15 03:24:41 PM PDT 24
Peak memory	199024 kb
Host	smart-7f7434a0-ba34-415d-850d-54b427619afc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215635058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1215635058
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2548067591
Short name	T1192
Test name
Test status
Simulation time	48608846 ps
CPU time	0.73 seconds
Started	Apr 15 03:24:44 PM PDT 24
Finished	Apr 15 03:24:46 PM PDT 24
Peak memory	198460 kb
Host	smart-ffe403e6-2786-4bd2-9b70-80c34ced4fc1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548067591 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2548067591
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.4112181591
Short name	T1245
Test name
Test status
Simulation time	17714269 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	195500 kb
Host	smart-224cd2ef-2614-44d3-810e-1cecd4f61d15
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112181591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4112181591
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.1462387722
Short name	T1241
Test name
Test status
Simulation time	13165849 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:43 PM PDT 24
Finished	Apr 15 03:24:45 PM PDT 24
Peak memory	194380 kb
Host	smart-e4019f80-d85e-45b7-9844-042d6b2e68a0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462387722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1462387722
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2999927005
Short name	T1280
Test name
Test status
Simulation time	67463301 ps
CPU time	0.77 seconds
Started	Apr 15 03:24:45 PM PDT 24
Finished	Apr 15 03:24:47 PM PDT 24
Peak memory	197056 kb
Host	smart-9b396441-13f5-4bcb-ac49-827ac52b098d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999927005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.2999927005
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.1306173814
Short name	T1214
Test name
Test status
Simulation time	21694729 ps
CPU time	1.09 seconds
Started	Apr 15 03:24:44 PM PDT 24
Finished	Apr 15 03:24:46 PM PDT 24
Peak memory	199856 kb
Host	smart-725ca220-183a-40a2-a6ac-87fe452b5295
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306173814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1306173814
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2915468331
Short name	T89
Test name
Test status
Simulation time	564113434 ps
CPU time	1.33 seconds
Started	Apr 15 03:24:42 PM PDT 24
Finished	Apr 15 03:24:44 PM PDT 24
Peak memory	199464 kb
Host	smart-d53dfc5a-3923-4ce6-a30d-c356a5fa8737
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915468331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2915468331
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3587319256
Short name	T1271
Test name
Test status
Simulation time	20563760 ps
CPU time	0.67 seconds
Started	Apr 15 03:24:19 PM PDT 24
Finished	Apr 15 03:24:20 PM PDT 24
Peak memory	195480 kb
Host	smart-c67fbe87-10d4-4b96-88da-904cfe89f8d5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587319256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3587319256
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1953388136
Short name	T72
Test name
Test status
Simulation time	566303201 ps
CPU time	2.36 seconds
Started	Apr 15 03:24:20 PM PDT 24
Finished	Apr 15 03:24:23 PM PDT 24
Peak memory	197812 kb
Host	smart-532ddad1-1d79-4546-9171-1fe430648fc5
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953388136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1953388136
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3374996460
Short name	T70
Test name
Test status
Simulation time	38707231 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:18 PM PDT 24
Finished	Apr 15 03:24:20 PM PDT 24
Peak memory	195672 kb
Host	smart-0d501586-c1ea-4fab-8d5b-5d9e3d659310
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374996460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3374996460
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2029291381
Short name	T1220
Test name
Test status
Simulation time	169694321 ps
CPU time	0.86 seconds
Started	Apr 15 03:24:19 PM PDT 24
Finished	Apr 15 03:24:20 PM PDT 24
Peak memory	199860 kb
Host	smart-754c0fa8-05eb-4006-9c53-ba69a8f8c8fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029291381 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2029291381
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.914021644
Short name	T1307
Test name
Test status
Simulation time	103992961 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:20 PM PDT 24
Finished	Apr 15 03:24:21 PM PDT 24
Peak memory	195448 kb
Host	smart-9b05c4a5-b8e1-4ee8-9156-82ab512bc736
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914021644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.914021644
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1809386139
Short name	T1304
Test name
Test status
Simulation time	178341453 ps
CPU time	0.56 seconds
Started	Apr 15 03:24:21 PM PDT 24
Finished	Apr 15 03:24:22 PM PDT 24
Peak memory	194328 kb
Host	smart-d16c0efa-f60b-4bef-b3f3-326f0aa7c22e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809386139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1809386139
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2551289900
Short name	T1295
Test name
Test status
Simulation time	30491991 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:22 PM PDT 24
Finished	Apr 15 03:24:24 PM PDT 24
Peak memory	197036 kb
Host	smart-700af5bc-194c-4d5a-a358-933f1b709fa5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551289900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.2551289900
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.795559922
Short name	T1285
Test name
Test status
Simulation time	217644588 ps
CPU time	1.37 seconds
Started	Apr 15 03:24:17 PM PDT 24
Finished	Apr 15 03:24:19 PM PDT 24
Peak memory	200152 kb
Host	smart-116d4e93-fa1f-40c7-a7ac-fcff2ffb627e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795559922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.795559922
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2337635211
Short name	T1267
Test name
Test status
Simulation time	49607785 ps
CPU time	0.95 seconds
Started	Apr 15 03:24:16 PM PDT 24
Finished	Apr 15 03:24:18 PM PDT 24
Peak memory	198912 kb
Host	smart-66468978-e97f-40ec-b010-dd7012f02488
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337635211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2337635211
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.3790779769
Short name	T1305
Test name
Test status
Simulation time	55703679 ps
CPU time	0.55 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194400 kb
Host	smart-72f9e14f-5778-4c53-bfb6-f8e75b4bbbae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790779769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3790779769
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.875175054
Short name	T1186
Test name
Test status
Simulation time	16771763 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:44 PM PDT 24
Finished	Apr 15 03:24:45 PM PDT 24
Peak memory	194480 kb
Host	smart-bac38de7-47ab-4cec-9009-a278958a2f12
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875175054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.875175054
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.1093804126
Short name	T1319
Test name
Test status
Simulation time	18846144 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194376 kb
Host	smart-a355dc84-0630-4216-b2eb-040796243a57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093804126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1093804126
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.1410953312
Short name	T1290
Test name
Test status
Simulation time	46863700 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:45 PM PDT 24
Finished	Apr 15 03:24:46 PM PDT 24
Peak memory	194384 kb
Host	smart-4d7b6b93-811b-481c-8c75-148e23e9d2b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410953312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1410953312
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.3983799254
Short name	T1215
Test name
Test status
Simulation time	30192267 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:43 PM PDT 24
Finished	Apr 15 03:24:44 PM PDT 24
Peak memory	194356 kb
Host	smart-a4d075f9-c844-4d09-a120-fa6ee212e422
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983799254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3983799254
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.1866566863
Short name	T1189
Test name
Test status
Simulation time	14134469 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:45 PM PDT 24
Finished	Apr 15 03:24:46 PM PDT 24
Peak memory	194464 kb
Host	smart-b2d06a18-abf8-433e-a633-e6cf77daf54f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866566863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1866566863
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.1740791399
Short name	T1222
Test name
Test status
Simulation time	15825856 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:42 PM PDT 24
Finished	Apr 15 03:24:43 PM PDT 24
Peak memory	194384 kb
Host	smart-7fc7d279-9566-46df-87c1-30e6e9f9ab90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740791399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1740791399
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.2318630028
Short name	T1223
Test name
Test status
Simulation time	12268493 ps
CPU time	0.52 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194400 kb
Host	smart-edefcacd-8fe1-4a58-848d-a5991fee8e40
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318630028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2318630028
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.2077401557
Short name	T1240
Test name
Test status
Simulation time	21829398 ps
CPU time	0.55 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	194400 kb
Host	smart-bc2caf10-9582-420d-9c77-295e0f9e520e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077401557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2077401557
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.3804250192
Short name	T1229
Test name
Test status
Simulation time	12781303 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194392 kb
Host	smart-39238c73-9082-4d11-b9ba-cc22c38b75b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804250192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3804250192
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2804614318
Short name	T1318
Test name
Test status
Simulation time	323384804 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:24 PM PDT 24
Finished	Apr 15 03:24:25 PM PDT 24
Peak memory	195488 kb
Host	smart-547e393e-b63e-44bf-9984-b85d75ace661
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804614318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2804614318
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2807520233
Short name	T1188
Test name
Test status
Simulation time	381892304 ps
CPU time	1.46 seconds
Started	Apr 15 03:24:20 PM PDT 24
Finished	Apr 15 03:24:22 PM PDT 24
Peak memory	197824 kb
Host	smart-8c2f173c-3484-45fc-b1d4-aed119dbd690
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807520233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2807520233
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4041502425
Short name	T73
Test name
Test status
Simulation time	58390814 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:19 PM PDT 24
Finished	Apr 15 03:24:21 PM PDT 24
Peak memory	195496 kb
Host	smart-964faf00-5576-4872-aa4d-918797180c53
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041502425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4041502425
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1858689547
Short name	T1300
Test name
Test status
Simulation time	27731507 ps
CPU time	0.68 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	197812 kb
Host	smart-b58224f6-087f-4b0a-acc7-342b237bb393
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858689547 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1858689547
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.3501967636
Short name	T64
Test name
Test status
Simulation time	44543906 ps
CPU time	0.69 seconds
Started	Apr 15 03:24:22 PM PDT 24
Finished	Apr 15 03:24:23 PM PDT 24
Peak memory	195500 kb
Host	smart-09a2de49-21df-411d-b52d-3da9b5c2f2b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501967636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3501967636
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.692020894
Short name	T1194
Test name
Test status
Simulation time	15444192 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:22 PM PDT 24
Finished	Apr 15 03:24:23 PM PDT 24
Peak memory	194392 kb
Host	smart-fe6c8ea6-19b8-4eb8-8fc4-15e4719d114c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692020894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.692020894
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.260388243
Short name	T1228
Test name
Test status
Simulation time	18174859 ps
CPU time	0.73 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	197932 kb
Host	smart-402bbb67-793e-4ea9-a553-0cf2f2f2a84e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260388243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_ outstanding.260388243
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.134248187
Short name	T1235
Test name
Test status
Simulation time	358121054 ps
CPU time	1.21 seconds
Started	Apr 15 03:24:19 PM PDT 24
Finished	Apr 15 03:24:20 PM PDT 24
Peak memory	199932 kb
Host	smart-db94548a-14ff-44bf-a541-e5433f56eab0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134248187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.134248187
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1491027898
Short name	T93
Test name
Test status
Simulation time	43031352 ps
CPU time	0.92 seconds
Started	Apr 15 03:24:21 PM PDT 24
Finished	Apr 15 03:24:23 PM PDT 24
Peak memory	198608 kb
Host	smart-0c73fd7d-42c5-4684-a80c-4cfb826ee424
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491027898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1491027898
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.1079912312
Short name	T1233
Test name
Test status
Simulation time	47480991 ps
CPU time	0.56 seconds
Started	Apr 15 03:24:49 PM PDT 24
Finished	Apr 15 03:24:50 PM PDT 24
Peak memory	194452 kb
Host	smart-05d98bdc-fa4a-472b-9544-52ed983c1c5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079912312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1079912312
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.1184042118
Short name	T1314
Test name
Test status
Simulation time	51510617 ps
CPU time	0.56 seconds
Started	Apr 15 03:24:49 PM PDT 24
Finished	Apr 15 03:24:50 PM PDT 24
Peak memory	194448 kb
Host	smart-af901e21-43fa-42f5-baa2-0af258d67fdb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184042118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1184042118
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.725653710
Short name	T1317
Test name
Test status
Simulation time	14358414 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194356 kb
Host	smart-403a6be4-9a84-4b73-91fc-b2159c83fc7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725653710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.725653710
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.823697125
Short name	T1238
Test name
Test status
Simulation time	13663837 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:50 PM PDT 24
Finished	Apr 15 03:24:51 PM PDT 24
Peak memory	194304 kb
Host	smart-53378f43-31ed-4dc4-95d2-ac66deec0e9d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823697125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.823697125
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.2949405494
Short name	T1247
Test name
Test status
Simulation time	14231408 ps
CPU time	0.55 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	194396 kb
Host	smart-54f3c7ef-338a-4711-b6ca-8d1f7481c077
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949405494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2949405494
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.2331031901
Short name	T1236
Test name
Test status
Simulation time	104729706 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:50 PM PDT 24
Finished	Apr 15 03:24:51 PM PDT 24
Peak memory	194372 kb
Host	smart-86020974-6d2a-4238-a3e7-4fcb4a1a08eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331031901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2331031901
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.2756382234
Short name	T1211
Test name
Test status
Simulation time	52396126 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:50 PM PDT 24
Peak memory	194376 kb
Host	smart-15121040-b503-46bd-9365-124f45dba49d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756382234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2756382234
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.2473897283
Short name	T1278
Test name
Test status
Simulation time	12526678 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:53 PM PDT 24
Finished	Apr 15 03:24:54 PM PDT 24
Peak memory	194404 kb
Host	smart-acce5bcd-c5b0-4588-97b5-46ec203d7412
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473897283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2473897283
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.3706685408
Short name	T1243
Test name
Test status
Simulation time	29863393 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:50 PM PDT 24
Finished	Apr 15 03:24:51 PM PDT 24
Peak memory	194352 kb
Host	smart-6d151a43-70c1-4d91-9f71-dafb5294f3bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706685408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3706685408
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.2145540842
Short name	T1279
Test name
Test status
Simulation time	26031683 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	194404 kb
Host	smart-7ff3910b-64df-403d-bf26-f0c39852ec2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145540842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2145540842
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.758057120
Short name	T1208
Test name
Test status
Simulation time	350319159 ps
CPU time	0.79 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	196308 kb
Host	smart-8e60a941-c9cc-4641-80ca-a5a7e761f1ae
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758057120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.758057120
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2740834636
Short name	T1203
Test name
Test status
Simulation time	60846528 ps
CPU time	2.31 seconds
Started	Apr 15 03:24:23 PM PDT 24
Finished	Apr 15 03:24:26 PM PDT 24
Peak memory	197784 kb
Host	smart-33b6d160-970b-44b9-af51-9330633b3981
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740834636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2740834636
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.4168306898
Short name	T1256
Test name
Test status
Simulation time	16608842 ps
CPU time	0.65 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:27 PM PDT 24
Peak memory	195512 kb
Host	smart-d0c575eb-5da4-4259-9528-76bf646257c2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168306898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.4168306898
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.620482020
Short name	T1313
Test name
Test status
Simulation time	21623474 ps
CPU time	1.07 seconds
Started	Apr 15 03:24:24 PM PDT 24
Finished	Apr 15 03:24:25 PM PDT 24
Peak memory	199900 kb
Host	smart-336a3399-dc34-47fb-8907-f0793841adea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620482020 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.620482020
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.272864402
Short name	T69
Test name
Test status
Simulation time	17323731 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	195448 kb
Host	smart-ddecca4f-f709-4323-83d8-16e68d57d7e4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272864402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.272864402
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.975116733
Short name	T1277
Test name
Test status
Simulation time	24878157 ps
CPU time	0.55 seconds
Started	Apr 15 03:24:23 PM PDT 24
Finished	Apr 15 03:24:24 PM PDT 24
Peak memory	194452 kb
Host	smart-504e47af-7988-48c6-81f5-d60721b5dd3f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975116733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.975116733
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3445432232
Short name	T1263
Test name
Test status
Simulation time	28737247 ps
CPU time	0.76 seconds
Started	Apr 15 03:24:24 PM PDT 24
Finished	Apr 15 03:24:26 PM PDT 24
Peak memory	196904 kb
Host	smart-5d425948-af35-4766-befb-64f7b9198544
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445432232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.3445432232
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.1296698142
Short name	T1226
Test name
Test status
Simulation time	266597711 ps
CPU time	1.67 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	200180 kb
Host	smart-cd59f96e-3bed-4549-b765-0adb04042b98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296698142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1296698142
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3828068904
Short name	T1308
Test name
Test status
Simulation time	91736373 ps
CPU time	1.27 seconds
Started	Apr 15 03:24:25 PM PDT 24
Finished	Apr 15 03:24:27 PM PDT 24
Peak memory	199344 kb
Host	smart-2a3e4792-29ac-45e0-9e71-b72c819967c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828068904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3828068904
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.943900410
Short name	T1297
Test name
Test status
Simulation time	188038414 ps
CPU time	0.6 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	194452 kb
Host	smart-d844a1a1-c0af-4ac1-857a-8046c0261a46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943900410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.943900410
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.3844858978
Short name	T1286
Test name
Test status
Simulation time	13648573 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:49 PM PDT 24
Finished	Apr 15 03:24:50 PM PDT 24
Peak memory	194408 kb
Host	smart-81ae104a-a62c-439e-8ea6-a734166efed5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844858978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3844858978
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.62641457
Short name	T1210
Test name
Test status
Simulation time	17136293 ps
CPU time	0.66 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:49 PM PDT 24
Peak memory	194392 kb
Host	smart-fff2c8fd-55eb-402c-9438-56399188d132
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62641457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.62641457
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.3145128540
Short name	T1310
Test name
Test status
Simulation time	25394530 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:53 PM PDT 24
Finished	Apr 15 03:24:54 PM PDT 24
Peak memory	194472 kb
Host	smart-cdb80e7c-ef97-4388-89b1-1b4bcf77ae4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145128540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3145128540
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.2721569166
Short name	T1311
Test name
Test status
Simulation time	122451842 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:48 PM PDT 24
Finished	Apr 15 03:24:50 PM PDT 24
Peak memory	194460 kb
Host	smart-29551cd9-ccd1-46db-9f66-6e01d207a0df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721569166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2721569166
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.2003566390
Short name	T1209
Test name
Test status
Simulation time	21244040 ps
CPU time	0.56 seconds
Started	Apr 15 03:24:47 PM PDT 24
Finished	Apr 15 03:24:48 PM PDT 24
Peak memory	194432 kb
Host	smart-73f231fc-69d4-4eab-aa31-50a5f9f46efb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003566390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2003566390
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.2254029612
Short name	T1275
Test name
Test status
Simulation time	16714890 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:50 PM PDT 24
Finished	Apr 15 03:24:51 PM PDT 24
Peak memory	194412 kb
Host	smart-3396465d-70e9-449b-884d-5fd1c74fe578
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254029612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2254029612
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.2875973117
Short name	T1266
Test name
Test status
Simulation time	12611836 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:52 PM PDT 24
Finished	Apr 15 03:24:53 PM PDT 24
Peak memory	194400 kb
Host	smart-55bccea7-52a8-4ccc-a4aa-6fa663243c0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875973117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2875973117
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.907877799
Short name	T1193
Test name
Test status
Simulation time	143938974 ps
CPU time	0.59 seconds
Started	Apr 15 03:24:51 PM PDT 24
Finished	Apr 15 03:24:53 PM PDT 24
Peak memory	194384 kb
Host	smart-7939730d-f090-4809-813f-ca97fa9e9dae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907877799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.907877799
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.3288444047
Short name	T1195
Test name
Test status
Simulation time	17898221 ps
CPU time	0.56 seconds
Started	Apr 15 03:24:55 PM PDT 24
Finished	Apr 15 03:24:56 PM PDT 24
Peak memory	194440 kb
Host	smart-58c61e58-436f-453c-83a3-80be3dc13777
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288444047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3288444047
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1045063572
Short name	T1219
Test name
Test status
Simulation time	70897182 ps
CPU time	0.7 seconds
Started	Apr 15 03:24:25 PM PDT 24
Finished	Apr 15 03:24:26 PM PDT 24
Peak memory	197704 kb
Host	smart-ddf200d6-9b6e-4107-9dbc-b23bcec589ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045063572 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1045063572
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2540008054
Short name	T75
Test name
Test status
Simulation time	53534025 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:24 PM PDT 24
Finished	Apr 15 03:24:26 PM PDT 24
Peak memory	195564 kb
Host	smart-27885e85-03eb-49f4-be31-6878f377cebd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540008054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2540008054
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.1703014207
Short name	T1197
Test name
Test status
Simulation time	13367556 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:24 PM PDT 24
Finished	Apr 15 03:24:25 PM PDT 24
Peak memory	194452 kb
Host	smart-b8e76dcd-d49f-40c7-bb1a-da98f7cf9ada
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703014207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1703014207
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3618791712
Short name	T79
Test name
Test status
Simulation time	28533137 ps
CPU time	0.79 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:29 PM PDT 24
Peak memory	196908 kb
Host	smart-2a1a2e6c-a10f-486c-a38d-606e7ddb4873
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618791712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.3618791712
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.2882713504
Short name	T1257
Test name
Test status
Simulation time	515651973 ps
CPU time	2.22 seconds
Started	Apr 15 03:24:33 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	200128 kb
Host	smart-7df77327-f79c-48c6-9fe1-2dc994dcee7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882713504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2882713504
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2741971109
Short name	T1204
Test name
Test status
Simulation time	45732700 ps
CPU time	0.75 seconds
Started	Apr 15 03:24:28 PM PDT 24
Finished	Apr 15 03:24:30 PM PDT 24
Peak memory	199048 kb
Host	smart-16e78f85-63bd-4a6f-95aa-09335b0a2804
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741971109 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2741971109
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.520188179
Short name	T1244
Test name
Test status
Simulation time	16900924 ps
CPU time	0.64 seconds
Started	Apr 15 03:24:29 PM PDT 24
Finished	Apr 15 03:24:32 PM PDT 24
Peak memory	195608 kb
Host	smart-9f743f13-5acb-40be-8679-e87bf280e693
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520188179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.520188179
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.54151083
Short name	T1221
Test name
Test status
Simulation time	11767706 ps
CPU time	0.57 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	194400 kb
Host	smart-042a282c-1f9e-4671-a8be-9f679329798c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54151083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.54151083
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1355023288
Short name	T1254
Test name
Test status
Simulation time	31834091 ps
CPU time	0.66 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	195960 kb
Host	smart-5fe56ea9-b89f-4f97-8f30-61190050bf81
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355023288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1355023288
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.479059174
Short name	T1282
Test name
Test status
Simulation time	46917983 ps
CPU time	1.17 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:29 PM PDT 24
Peak memory	199908 kb
Host	smart-58836bb7-b647-41a5-ae6d-33791ca0a258
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479059174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.479059174
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.21894405
Short name	T87
Test name
Test status
Simulation time	100022238 ps
CPU time	1 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	199088 kb
Host	smart-4d5c3a1a-b249-4b1d-a9ea-f4050bc62c32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21894405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.21894405
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.641968531
Short name	T1200
Test name
Test status
Simulation time	16426607 ps
CPU time	0.67 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:27 PM PDT 24
Peak memory	198156 kb
Host	smart-9780a6ec-124a-43c9-87fb-e9e573aac47c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641968531 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.641968531
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.4074864329
Short name	T74
Test name
Test status
Simulation time	38074675 ps
CPU time	0.63 seconds
Started	Apr 15 03:24:29 PM PDT 24
Finished	Apr 15 03:24:31 PM PDT 24
Peak memory	195608 kb
Host	smart-592e8188-da3e-4257-8452-aca41ac0a48a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074864329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4074864329
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.225285502
Short name	T1268
Test name
Test status
Simulation time	20007366 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:35 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	194428 kb
Host	smart-ceff9593-98bd-4638-bf21-b516d76653f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225285502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.225285502
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1269364246
Short name	T1230
Test name
Test status
Simulation time	68410800 ps
CPU time	0.71 seconds
Started	Apr 15 03:24:35 PM PDT 24
Finished	Apr 15 03:24:37 PM PDT 24
Peak memory	195584 kb
Host	smart-c638f17d-52e1-49dd-940f-7dffc9209af9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269364246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.1269364246
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.1976585351
Short name	T1250
Test name
Test status
Simulation time	65548830 ps
CPU time	1.52 seconds
Started	Apr 15 03:24:28 PM PDT 24
Finished	Apr 15 03:24:31 PM PDT 24
Peak memory	200156 kb
Host	smart-c0d27141-47e1-4405-a869-c200eabc34e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976585351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1976585351
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1742461983
Short name	T122
Test name
Test status
Simulation time	90205747 ps
CPU time	1.44 seconds
Started	Apr 15 03:24:28 PM PDT 24
Finished	Apr 15 03:24:31 PM PDT 24
Peak memory	199456 kb
Host	smart-110be19e-b4f4-4203-9939-ce7a2c798e41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742461983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1742461983
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3486427877
Short name	T1281
Test name
Test status
Simulation time	31756705 ps
CPU time	0.88 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:29 PM PDT 24
Peak memory	199888 kb
Host	smart-1bf9f145-ccfe-4ee3-a207-6dddaa66fa5c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486427877 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3486427877
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.2435584605
Short name	T78
Test name
Test status
Simulation time	32705328 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:26 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	195596 kb
Host	smart-eb901a87-e7fb-48fa-ba3d-f6085d75a00b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435584605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2435584605
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.2350199022
Short name	T1207
Test name
Test status
Simulation time	23392436 ps
CPU time	0.58 seconds
Started	Apr 15 03:24:25 PM PDT 24
Finished	Apr 15 03:24:27 PM PDT 24
Peak memory	194452 kb
Host	smart-f62536e0-9097-46a1-b9cd-3ac8f2579ec2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350199022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2350199022
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3411813705
Short name	T1252
Test name
Test status
Simulation time	54702907 ps
CPU time	0.68 seconds
Started	Apr 15 03:24:29 PM PDT 24
Finished	Apr 15 03:24:31 PM PDT 24
Peak memory	197080 kb
Host	smart-83770dbe-56ab-4a14-ad9b-604a63908a52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411813705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.3411813705
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.3200273275
Short name	T1218
Test name
Test status
Simulation time	148169401 ps
CPU time	2.09 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:30 PM PDT 24
Peak memory	200068 kb
Host	smart-87cf33af-0da5-4fb5-ba79-0ffadaea065b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200273275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3200273275
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3960555553
Short name	T1294
Test name
Test status
Simulation time	77486989 ps
CPU time	1.34 seconds
Started	Apr 15 03:24:28 PM PDT 24
Finished	Apr 15 03:24:30 PM PDT 24
Peak memory	199500 kb
Host	smart-dfd9f149-8d05-475c-bcb9-26b3602361e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960555553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3960555553
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4159840998
Short name	T1253
Test name
Test status
Simulation time	88729287 ps
CPU time	0.78 seconds
Started	Apr 15 03:24:34 PM PDT 24
Finished	Apr 15 03:24:36 PM PDT 24
Peak memory	197188 kb
Host	smart-e85d8d00-0535-4c57-8620-2e2e0e20f34a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159840998 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4159840998
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.1439186826
Short name	T71
Test name
Test status
Simulation time	128249675 ps
CPU time	0.62 seconds
Started	Apr 15 03:24:28 PM PDT 24
Finished	Apr 15 03:24:30 PM PDT 24
Peak memory	195444 kb
Host	smart-69c51108-c20a-4d7f-bf5b-5227e38b2ec8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439186826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1439186826
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.3358931906
Short name	T1234
Test name
Test status
Simulation time	42849268 ps
CPU time	0.61 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:29 PM PDT 24
Peak memory	194408 kb
Host	smart-4f56dd1d-0f5c-47f4-befc-9bcf1054be1e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358931906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3358931906
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3051304999
Short name	T1231
Test name
Test status
Simulation time	20408433 ps
CPU time	0.67 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:29 PM PDT 24
Peak memory	195900 kb
Host	smart-b83242d3-c4d3-4d25-9509-794e4f718afe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051304999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.3051304999
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.1915458763
Short name	T1217
Test name
Test status
Simulation time	28786941 ps
CPU time	1.34 seconds
Started	Apr 15 03:24:29 PM PDT 24
Finished	Apr 15 03:24:32 PM PDT 24
Peak memory	200096 kb
Host	smart-d259c4d5-e157-4920-a505-6a772aa635d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915458763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1915458763
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.606037650
Short name	T1276
Test name
Test status
Simulation time	599542493 ps
CPU time	0.95 seconds
Started	Apr 15 03:24:27 PM PDT 24
Finished	Apr 15 03:24:28 PM PDT 24
Peak memory	198936 kb
Host	smart-2f75b417-3374-4296-bd21-6e923f16b246
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606037650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.606037650
Directory	/workspace/9.uart_tl_intg_err/latest

Test location	/workspace/coverage/default/0.uart_alert_test.840206768
Short name	T707
Test name
Test status
Simulation time	48396221 ps
CPU time	0.55 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 02:51:20 PM PDT 24
Peak memory	196172 kb
Host	smart-0058319f-d8e8-44f8-9814-43b75a68c082
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840206768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.840206768
Directory	/workspace/0.uart_alert_test/latest

Test location	/workspace/coverage/default/0.uart_fifo_full.1078679395
Short name	T1057
Test name
Test status
Simulation time	30983884237 ps
CPU time	37.63 seconds
Started	Apr 15 02:51:28 PM PDT 24
Finished	Apr 15 02:52:06 PM PDT 24
Peak memory	200936 kb
Host	smart-2d78a07f-e1cd-4b44-8c9a-1ed1d99e57fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078679395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1078679395
Directory	/workspace/0.uart_fifo_full/latest

Test location	/workspace/coverage/default/0.uart_fifo_overflow.2051572005
Short name	T334
Test name
Test status
Simulation time	74820150026 ps
CPU time	21.24 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:51:37 PM PDT 24
Peak memory	200820 kb
Host	smart-01c097e0-48d3-4f2a-ada8-9841531ed320
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051572005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2051572005
Directory	/workspace/0.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/0.uart_intr.1661126460
Short name	T1027
Test name
Test status
Simulation time	21104044058 ps
CPU time	3.5 seconds
Started	Apr 15 02:51:14 PM PDT 24
Finished	Apr 15 02:51:18 PM PDT 24
Peak memory	198460 kb
Host	smart-f282d644-47db-4dd2-b37d-6f66d98002ca
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661126460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1661126460
Directory	/workspace/0.uart_intr/latest

Test location	/workspace/coverage/default/0.uart_long_xfer_wo_dly.3867481773
Short name	T909
Test name
Test status
Simulation time	89398556994 ps
CPU time	537.12 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 03:00:16 PM PDT 24
Peak memory	200824 kb
Host	smart-172dd3d0-7993-4220-9a13-86990d2f832b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3867481773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3867481773
Directory	/workspace/0.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/0.uart_loopback.663512167
Short name	T343
Test name
Test status
Simulation time	7352784124 ps
CPU time	10.88 seconds
Started	Apr 15 02:51:20 PM PDT 24
Finished	Apr 15 02:51:32 PM PDT 24
Peak memory	200760 kb
Host	smart-03de0dbf-34da-443b-8435-f1f2bee4fc4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663512167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.663512167
Directory	/workspace/0.uart_loopback/latest

Test location	/workspace/coverage/default/0.uart_noise_filter.1364568654
Short name	T502
Test name
Test status
Simulation time	132032106405 ps
CPU time	52.68 seconds
Started	Apr 15 02:51:17 PM PDT 24
Finished	Apr 15 02:52:10 PM PDT 24
Peak memory	201068 kb
Host	smart-46d84269-1291-4eb3-90a0-b00dd1985c09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364568654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1364568654
Directory	/workspace/0.uart_noise_filter/latest

Test location	/workspace/coverage/default/0.uart_perf.3895243754
Short name	T394
Test name
Test status
Simulation time	11328216425 ps
CPU time	624.46 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 03:01:41 PM PDT 24
Peak memory	200912 kb
Host	smart-ff537385-d72c-48be-8234-4a8ba9b5d5c9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3895243754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3895243754
Directory	/workspace/0.uart_perf/latest

Test location	/workspace/coverage/default/0.uart_rx_oversample.2236442046
Short name	T448
Test name
Test status
Simulation time	4825049508 ps
CPU time	45.64 seconds
Started	Apr 15 02:51:11 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	199736 kb
Host	smart-eba153b4-4c92-43ea-9129-a70b6651c98f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2236442046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2236442046
Directory	/workspace/0.uart_rx_oversample/latest

Test location	/workspace/coverage/default/0.uart_rx_parity_err.910740193
Short name	T890
Test name
Test status
Simulation time	26200569057 ps
CPU time	54.08 seconds
Started	Apr 15 02:51:10 PM PDT 24
Finished	Apr 15 02:52:05 PM PDT 24
Peak memory	200844 kb
Host	smart-6ec9ab50-801f-45d4-9073-c7f36711a9dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910740193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.910740193
Directory	/workspace/0.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/0.uart_rx_start_bit_filter.1629630704
Short name	T980
Test name
Test status
Simulation time	33668802835 ps
CPU time	9.39 seconds
Started	Apr 15 02:51:14 PM PDT 24
Finished	Apr 15 02:51:24 PM PDT 24
Peak memory	196964 kb
Host	smart-38f281f2-5b93-4473-9b44-744e1e89e1ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629630704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1629630704
Directory	/workspace/0.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/0.uart_sec_cm.1975076463
Short name	T97
Test name
Test status
Simulation time	60961834 ps
CPU time	0.79 seconds
Started	Apr 15 02:51:13 PM PDT 24
Finished	Apr 15 02:51:16 PM PDT 24
Peak memory	218868 kb
Host	smart-751cea0c-9cca-4a0f-b487-ae3ceb08f7e7
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975076463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1975076463
Directory	/workspace/0.uart_sec_cm/latest

Test location	/workspace/coverage/default/0.uart_smoke.973096236
Short name	T587
Test name
Test status
Simulation time	689246749 ps
CPU time	2.61 seconds
Started	Apr 15 02:51:04 PM PDT 24
Finished	Apr 15 02:51:08 PM PDT 24
Peak memory	200880 kb
Host	smart-67eb50d1-12bd-4dab-af45-bc7ccd7d036a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973096236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.973096236
Directory	/workspace/0.uart_smoke/latest

Test location	/workspace/coverage/default/0.uart_stress_all_with_rand_reset.2476632453
Short name	T908
Test name
Test status
Simulation time	48590667648 ps
CPU time	192.59 seconds
Started	Apr 15 02:51:04 PM PDT 24
Finished	Apr 15 02:54:17 PM PDT 24
Peak memory	217416 kb
Host	smart-6ac2a9e1-e502-425c-b4eb-4ae04dd9a254
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476632453 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2476632453
Directory	/workspace/0.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.uart_tx_ovrd.2722623877
Short name	T307
Test name
Test status
Simulation time	7441347481 ps
CPU time	10.36 seconds
Started	Apr 15 02:51:11 PM PDT 24
Finished	Apr 15 02:51:22 PM PDT 24
Peak memory	200180 kb
Host	smart-bfa55635-6b9b-4b31-802b-19ddeaefef5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722623877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2722623877
Directory	/workspace/0.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/0.uart_tx_rx.204354104
Short name	T433
Test name
Test status
Simulation time	104896718816 ps
CPU time	70.14 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200920 kb
Host	smart-7e6101ff-3b14-47aa-8562-941de135f360
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204354104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.204354104
Directory	/workspace/0.uart_tx_rx/latest

Test location	/workspace/coverage/default/1.uart_alert_test.3470872232
Short name	T793
Test name
Test status
Simulation time	13946550 ps
CPU time	0.57 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:51:16 PM PDT 24
Peak memory	196104 kb
Host	smart-21e6bf15-1225-4356-93e8-9e5678a8aba2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470872232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3470872232
Directory	/workspace/1.uart_alert_test/latest

Test location	/workspace/coverage/default/1.uart_fifo_overflow.1944304049
Short name	T171
Test name
Test status
Simulation time	27693053769 ps
CPU time	9.7 seconds
Started	Apr 15 02:51:13 PM PDT 24
Finished	Apr 15 02:51:24 PM PDT 24
Peak memory	200872 kb
Host	smart-ceb6472b-c37a-4522-88f4-e35063068e5a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944304049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1944304049
Directory	/workspace/1.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/1.uart_intr.543216966
Short name	T520
Test name
Test status
Simulation time	156844680015 ps
CPU time	267 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:55:43 PM PDT 24
Peak memory	200652 kb
Host	smart-85229d0e-4da8-4563-a104-e198568c39b8
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543216966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.543216966
Directory	/workspace/1.uart_intr/latest

Test location	/workspace/coverage/default/1.uart_long_xfer_wo_dly.4030692032
Short name	T1011
Test name
Test status
Simulation time	100708585304 ps
CPU time	891.6 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 03:06:07 PM PDT 24
Peak memory	200720 kb
Host	smart-e8c894fc-7c44-40ae-adf4-782a84c3b6dd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4030692032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.4030692032
Directory	/workspace/1.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/1.uart_loopback.1297345597
Short name	T653
Test name
Test status
Simulation time	13247668081 ps
CPU time	7.47 seconds
Started	Apr 15 02:51:20 PM PDT 24
Finished	Apr 15 02:51:28 PM PDT 24
Peak memory	200888 kb
Host	smart-652bc7a9-31d7-4f73-89ed-f7fdbe1241f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1297345597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1297345597
Directory	/workspace/1.uart_loopback/latest

Test location	/workspace/coverage/default/1.uart_noise_filter.2197202096
Short name	T1160
Test name
Test status
Simulation time	20655121640 ps
CPU time	21.77 seconds
Started	Apr 15 02:51:22 PM PDT 24
Finished	Apr 15 02:51:44 PM PDT 24
Peak memory	199684 kb
Host	smart-0b787db7-0921-41f2-a7d1-e6a1ed362255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197202096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2197202096
Directory	/workspace/1.uart_noise_filter/latest

Test location	/workspace/coverage/default/1.uart_perf.4218775690
Short name	T936
Test name
Test status
Simulation time	17789922345 ps
CPU time	990.68 seconds
Started	Apr 15 02:51:19 PM PDT 24
Finished	Apr 15 03:07:51 PM PDT 24
Peak memory	200904 kb
Host	smart-89e21937-fdb0-4872-acff-fa838b54f31d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4218775690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4218775690
Directory	/workspace/1.uart_perf/latest

Test location	/workspace/coverage/default/1.uart_rx_oversample.3768105223
Short name	T518
Test name
Test status
Simulation time	7429466631 ps
CPU time	33.32 seconds
Started	Apr 15 02:51:11 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	198384 kb
Host	smart-6aff120f-f6b6-42d4-b0fe-d0d219cd5b6a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3768105223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3768105223
Directory	/workspace/1.uart_rx_oversample/latest

Test location	/workspace/coverage/default/1.uart_rx_parity_err.842539363
Short name	T278
Test name
Test status
Simulation time	110101350981 ps
CPU time	54.45 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:52:11 PM PDT 24
Peak memory	200896 kb
Host	smart-4e454b45-ca75-4cf7-8a2b-a455497b60ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842539363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.842539363
Directory	/workspace/1.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/1.uart_rx_start_bit_filter.4154617811
Short name	T506
Test name
Test status
Simulation time	49271117867 ps
CPU time	75.81 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 02:52:34 PM PDT 24
Peak memory	196644 kb
Host	smart-7c3a1b66-3b29-4e69-989e-9cec9ff6a229
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154617811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4154617811
Directory	/workspace/1.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/1.uart_sec_cm.620385082
Short name	T32
Test name
Test status
Simulation time	196249347 ps
CPU time	0.79 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:51:17 PM PDT 24
Peak memory	218940 kb
Host	smart-83e8c7e0-7974-4191-91ff-b34b0e168c00
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620385082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.620385082
Directory	/workspace/1.uart_sec_cm/latest

Test location	/workspace/coverage/default/1.uart_smoke.3430468642
Short name	T563
Test name
Test status
Simulation time	674841177 ps
CPU time	2.36 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:51:19 PM PDT 24
Peak memory	199252 kb
Host	smart-94f2f835-a500-46a2-b8cd-0e6a8a224d86
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3430468642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3430468642
Directory	/workspace/1.uart_smoke/latest

Test location	/workspace/coverage/default/1.uart_stress_all_with_rand_reset.345935335
Short name	T161
Test name
Test status
Simulation time	137312580216 ps
CPU time	518.76 seconds
Started	Apr 15 02:51:17 PM PDT 24
Finished	Apr 15 02:59:57 PM PDT 24
Peak memory	217316 kb
Host	smart-bbc7f638-6565-4032-b398-d38b4d67ed2a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345935335 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.345935335
Directory	/workspace/1.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.uart_tx_ovrd.4250241504
Short name	T668
Test name
Test status
Simulation time	1485461330 ps
CPU time	1.56 seconds
Started	Apr 15 02:51:13 PM PDT 24
Finished	Apr 15 02:51:15 PM PDT 24
Peak memory	199440 kb
Host	smart-0977d81c-e55d-48f0-a5dc-d9559b837c63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250241504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4250241504
Directory	/workspace/1.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/1.uart_tx_rx.3704829065
Short name	T539
Test name
Test status
Simulation time	36811737022 ps
CPU time	55.03 seconds
Started	Apr 15 02:51:17 PM PDT 24
Finished	Apr 15 02:52:12 PM PDT 24
Peak memory	200884 kb
Host	smart-dea24851-ac39-43db-aef8-04977ab7f2e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3704829065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3704829065
Directory	/workspace/1.uart_tx_rx/latest

Test location	/workspace/coverage/default/10.uart_alert_test.3947338850
Short name	T819
Test name
Test status
Simulation time	21355488 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:51:47 PM PDT 24
Peak memory	196240 kb
Host	smart-052140cd-24ab-4b79-9eaa-7cc5653bd65a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947338850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3947338850
Directory	/workspace/10.uart_alert_test/latest

Test location	/workspace/coverage/default/10.uart_fifo_full.1541218798
Short name	T151
Test name
Test status
Simulation time	168995003200 ps
CPU time	76.72 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	200848 kb
Host	smart-f82fa97c-0f1c-4c25-a57f-c0063bb108a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541218798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1541218798
Directory	/workspace/10.uart_fifo_full/latest

Test location	/workspace/coverage/default/10.uart_fifo_overflow.1757680654
Short name	T753
Test name
Test status
Simulation time	112996943829 ps
CPU time	180.06 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:54:46 PM PDT 24
Peak memory	200888 kb
Host	smart-ca616a4e-be4e-4bff-9499-33225a77d8b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757680654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1757680654
Directory	/workspace/10.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/10.uart_fifo_reset.2490884921
Short name	T654
Test name
Test status
Simulation time	263928903842 ps
CPU time	113.41 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:53:31 PM PDT 24
Peak memory	200852 kb
Host	smart-4bc67a6a-cc5d-4e79-8707-bcfb47d77d32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490884921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2490884921
Directory	/workspace/10.uart_fifo_reset/latest

Test location	/workspace/coverage/default/10.uart_intr.3495004897
Short name	T382
Test name
Test status
Simulation time	50987567260 ps
CPU time	19.81 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 02:51:52 PM PDT 24
Peak memory	200940 kb
Host	smart-d752a159-27c8-4ad9-97f9-0a472c17597c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495004897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3495004897
Directory	/workspace/10.uart_intr/latest

Test location	/workspace/coverage/default/10.uart_long_xfer_wo_dly.2740148137
Short name	T1085
Test name
Test status
Simulation time	221567459187 ps
CPU time	349.56 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:57:33 PM PDT 24
Peak memory	200828 kb
Host	smart-3e18292f-a9f7-435d-8366-870fd66e55cd
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2740148137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2740148137
Directory	/workspace/10.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/10.uart_loopback.1695268280
Short name	T103
Test name
Test status
Simulation time	2860929236 ps
CPU time	4.58 seconds
Started	Apr 15 02:51:39 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	198172 kb
Host	smart-ba2d35b4-5618-431a-bb68-1cc08444e17b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695268280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1695268280
Directory	/workspace/10.uart_loopback/latest

Test location	/workspace/coverage/default/10.uart_noise_filter.3895837147
Short name	T368
Test name
Test status
Simulation time	16137870317 ps
CPU time	15.11 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:51:58 PM PDT 24
Peak memory	198752 kb
Host	smart-ccedb64f-5c1e-4eb0-b709-9cb062ab966a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895837147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3895837147
Directory	/workspace/10.uart_noise_filter/latest

Test location	/workspace/coverage/default/10.uart_perf.3425347577
Short name	T435
Test name
Test status
Simulation time	26759267891 ps
CPU time	1168.74 seconds
Started	Apr 15 02:51:52 PM PDT 24
Finished	Apr 15 03:11:21 PM PDT 24
Peak memory	200884 kb
Host	smart-c9784f3e-63e9-474a-8764-00846c80cf85
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3425347577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3425347577
Directory	/workspace/10.uart_perf/latest

Test location	/workspace/coverage/default/10.uart_rx_oversample.3560338107
Short name	T1158
Test name
Test status
Simulation time	1691234117 ps
CPU time	4.65 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:51:44 PM PDT 24
Peak memory	198736 kb
Host	smart-2ee77765-093e-491e-a4f9-92bff8686a1c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3560338107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3560338107
Directory	/workspace/10.uart_rx_oversample/latest

Test location	/workspace/coverage/default/10.uart_rx_parity_err.2363269110
Short name	T496
Test name
Test status
Simulation time	27405696220 ps
CPU time	42.15 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:52:16 PM PDT 24
Peak memory	200696 kb
Host	smart-1836974d-c844-4d65-80c6-adb8a0aa8070
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363269110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2363269110
Directory	/workspace/10.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/10.uart_rx_start_bit_filter.638071631
Short name	T509
Test name
Test status
Simulation time	35114870449 ps
CPU time	10.93 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:51:58 PM PDT 24
Peak memory	196932 kb
Host	smart-41bca9e0-e019-40e5-9172-75f5dbc0711e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638071631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.638071631
Directory	/workspace/10.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/10.uart_smoke.863214567
Short name	T1120
Test name
Test status
Simulation time	5299888260 ps
CPU time	24.54 seconds
Started	Apr 15 02:52:02 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200508 kb
Host	smart-9d5c1141-8600-4044-96a1-f9c4be9dd928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863214567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.863214567
Directory	/workspace/10.uart_smoke/latest

Test location	/workspace/coverage/default/10.uart_stress_all_with_rand_reset.2459636549
Short name	T831
Test name
Test status
Simulation time	21524113020 ps
CPU time	264.46 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 02:56:13 PM PDT 24
Peak memory	213520 kb
Host	smart-9ad2ae38-a5e2-4989-9720-8d1f540a4f6f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459636549 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2459636549
Directory	/workspace/10.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.uart_tx_ovrd.218937646
Short name	T786
Test name
Test status
Simulation time	6347235339 ps
CPU time	13.52 seconds
Started	Apr 15 02:51:31 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	200044 kb
Host	smart-a2f1d9c9-d69f-4236-a2fa-42d528893966
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=218937646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.218937646
Directory	/workspace/10.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/10.uart_tx_rx.1340398721
Short name	T1025
Test name
Test status
Simulation time	65984696332 ps
CPU time	47.41 seconds
Started	Apr 15 02:51:52 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	200788 kb
Host	smart-184f2ee4-4f18-4abe-9e46-a33ee8107005
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340398721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1340398721
Directory	/workspace/10.uart_tx_rx/latest

Test location	/workspace/coverage/default/100.uart_fifo_reset.1540923659
Short name	T576
Test name
Test status
Simulation time	117107958307 ps
CPU time	99.93 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:56:30 PM PDT 24
Peak memory	200868 kb
Host	smart-9d2515ca-56e8-4aad-b75b-2648e25a47ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540923659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1540923659
Directory	/workspace/100.uart_fifo_reset/latest

Test location	/workspace/coverage/default/101.uart_fifo_reset.1377929846
Short name	T400
Test name
Test status
Simulation time	5980996950 ps
CPU time	10.44 seconds
Started	Apr 15 02:54:44 PM PDT 24
Finished	Apr 15 02:54:55 PM PDT 24
Peak memory	200848 kb
Host	smart-09aa097b-8df4-4d0c-8e27-3f6baca8caae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377929846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1377929846
Directory	/workspace/101.uart_fifo_reset/latest

Test location	/workspace/coverage/default/102.uart_fifo_reset.1107469505
Short name	T751
Test name
Test status
Simulation time	49140577918 ps
CPU time	82.86 seconds
Started	Apr 15 02:54:47 PM PDT 24
Finished	Apr 15 02:56:10 PM PDT 24
Peak memory	200852 kb
Host	smart-02cf5df0-5a1e-438b-b4c3-9b21b9f79b8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107469505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1107469505
Directory	/workspace/102.uart_fifo_reset/latest

Test location	/workspace/coverage/default/104.uart_fifo_reset.2349779363
Short name	T1104
Test name
Test status
Simulation time	63953861315 ps
CPU time	59.45 seconds
Started	Apr 15 02:54:44 PM PDT 24
Finished	Apr 15 02:55:44 PM PDT 24
Peak memory	200860 kb
Host	smart-39ddc66a-466c-4dcc-af48-9dee9a1472d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349779363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2349779363
Directory	/workspace/104.uart_fifo_reset/latest

Test location	/workspace/coverage/default/105.uart_fifo_reset.4059291168
Short name	T244
Test name
Test status
Simulation time	91254016716 ps
CPU time	37.22 seconds
Started	Apr 15 02:54:50 PM PDT 24
Finished	Apr 15 02:55:28 PM PDT 24
Peak memory	200804 kb
Host	smart-be8dd32c-b7d5-4022-b915-c5ba3bbba638
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059291168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4059291168
Directory	/workspace/105.uart_fifo_reset/latest

Test location	/workspace/coverage/default/106.uart_fifo_reset.8007145
Short name	T270
Test name
Test status
Simulation time	219159992455 ps
CPU time	131.51 seconds
Started	Apr 15 02:54:42 PM PDT 24
Finished	Apr 15 02:56:55 PM PDT 24
Peak memory	200900 kb
Host	smart-92c9b10e-6bd0-4fa5-be55-83b279ed0f0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8007145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.8007145
Directory	/workspace/106.uart_fifo_reset/latest

Test location	/workspace/coverage/default/107.uart_fifo_reset.953931589
Short name	T853
Test name
Test status
Simulation time	17967095285 ps
CPU time	33.92 seconds
Started	Apr 15 02:54:43 PM PDT 24
Finished	Apr 15 02:55:17 PM PDT 24
Peak memory	200864 kb
Host	smart-a592221b-4fe6-44e5-bcc0-da7ab3889328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953931589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.953931589
Directory	/workspace/107.uart_fifo_reset/latest

Test location	/workspace/coverage/default/108.uart_fifo_reset.3602184670
Short name	T949
Test name
Test status
Simulation time	38972266335 ps
CPU time	41.15 seconds
Started	Apr 15 02:54:51 PM PDT 24
Finished	Apr 15 02:55:33 PM PDT 24
Peak memory	200928 kb
Host	smart-f0326267-43c8-4f7d-8b65-a3628ebae860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602184670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3602184670
Directory	/workspace/108.uart_fifo_reset/latest

Test location	/workspace/coverage/default/109.uart_fifo_reset.1125211230
Short name	T104
Test name
Test status
Simulation time	23543403908 ps
CPU time	14.73 seconds
Started	Apr 15 02:54:50 PM PDT 24
Finished	Apr 15 02:55:06 PM PDT 24
Peak memory	200924 kb
Host	smart-a6fe6b3a-27cc-45f8-b6b3-1076c121f99e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125211230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1125211230
Directory	/workspace/109.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_alert_test.1231441562
Short name	T649
Test name
Test status
Simulation time	39201740 ps
CPU time	0.55 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:50 PM PDT 24
Peak memory	196180 kb
Host	smart-55e6ae38-9fd5-4b35-86bf-68d6c046f95f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231441562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1231441562
Directory	/workspace/11.uart_alert_test/latest

Test location	/workspace/coverage/default/11.uart_fifo_full.3504553044
Short name	T660
Test name
Test status
Simulation time	89533028501 ps
CPU time	67.17 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:52:50 PM PDT 24
Peak memory	200924 kb
Host	smart-6feeb8a6-885a-44b7-a906-d79055a1668a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504553044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3504553044
Directory	/workspace/11.uart_fifo_full/latest

Test location	/workspace/coverage/default/11.uart_fifo_overflow.1527283441
Short name	T900
Test name
Test status
Simulation time	32807305522 ps
CPU time	55.19 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	200852 kb
Host	smart-8c403e6b-4d39-49b3-8602-8860f939159a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1527283441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1527283441
Directory	/workspace/11.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/11.uart_fifo_reset.2790378675
Short name	T1114
Test name
Test status
Simulation time	113245498102 ps
CPU time	163.64 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:54:43 PM PDT 24
Peak memory	200912 kb
Host	smart-e3c8f563-42d3-4098-9877-02bbfb7171f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790378675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2790378675
Directory	/workspace/11.uart_fifo_reset/latest

Test location	/workspace/coverage/default/11.uart_intr.319287841
Short name	T896
Test name
Test status
Simulation time	157845312474 ps
CPU time	74.6 seconds
Started	Apr 15 02:51:37 PM PDT 24
Finished	Apr 15 02:52:53 PM PDT 24
Peak memory	200888 kb
Host	smart-8a85d390-112b-40ff-9350-3e97138990e3
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319287841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.319287841
Directory	/workspace/11.uart_intr/latest

Test location	/workspace/coverage/default/11.uart_long_xfer_wo_dly.84268499
Short name	T760
Test name
Test status
Simulation time	65481239059 ps
CPU time	258.45 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:55:55 PM PDT 24
Peak memory	200164 kb
Host	smart-a9d8a586-c73f-469d-a62a-86edff586a87
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=84268499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.84268499
Directory	/workspace/11.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/11.uart_loopback.2067812215
Short name	T1172
Test name
Test status
Simulation time	577301823 ps
CPU time	1.56 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:51:47 PM PDT 24
Peak memory	196320 kb
Host	smart-b7eedbc2-1035-4866-b855-8609f3b134d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2067812215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2067812215
Directory	/workspace/11.uart_loopback/latest

Test location	/workspace/coverage/default/11.uart_noise_filter.1839366442
Short name	T447
Test name
Test status
Simulation time	151936546028 ps
CPU time	74.62 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	209260 kb
Host	smart-e085fae3-1c5a-49b8-b4e3-e3e6a873f689
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839366442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1839366442
Directory	/workspace/11.uart_noise_filter/latest

Test location	/workspace/coverage/default/11.uart_perf.1059131877
Short name	T671
Test name
Test status
Simulation time	27798159306 ps
CPU time	119.9 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	200860 kb
Host	smart-04db2796-b94a-436f-af22-b93c7e369e90
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1059131877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1059131877
Directory	/workspace/11.uart_perf/latest

Test location	/workspace/coverage/default/11.uart_rx_oversample.2467917357
Short name	T478
Test name
Test status
Simulation time	2478038904 ps
CPU time	2.39 seconds
Started	Apr 15 02:51:37 PM PDT 24
Finished	Apr 15 02:51:41 PM PDT 24
Peak memory	199300 kb
Host	smart-ebb95c26-1b31-4148-bfd2-fcdd6597f205
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2467917357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2467917357
Directory	/workspace/11.uart_rx_oversample/latest

Test location	/workspace/coverage/default/11.uart_rx_parity_err.3852049997
Short name	T58
Test name
Test status
Simulation time	17085395417 ps
CPU time	34.09 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:52:29 PM PDT 24
Peak memory	200464 kb
Host	smart-69187898-9ff8-4e42-961c-2686d59bdbeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852049997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3852049997
Directory	/workspace/11.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/11.uart_rx_start_bit_filter.3564922549
Short name	T1101
Test name
Test status
Simulation time	6416773450 ps
CPU time	5.18 seconds
Started	Apr 15 02:51:39 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	196944 kb
Host	smart-7249fae5-c845-46aa-a428-4900e78706ac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564922549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3564922549
Directory	/workspace/11.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/11.uart_smoke.1943811201
Short name	T1100
Test name
Test status
Simulation time	1010595925 ps
CPU time	1.98 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:51:36 PM PDT 24
Peak memory	200548 kb
Host	smart-d77cdc8a-7444-483c-b30d-fc5c9c41671f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943811201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1943811201
Directory	/workspace/11.uart_smoke/latest

Test location	/workspace/coverage/default/11.uart_stress_all.569080269
Short name	T1175
Test name
Test status
Simulation time	53429255267 ps
CPU time	1460.79 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 03:16:05 PM PDT 24
Peak memory	200896 kb
Host	smart-0d29d665-0dda-4dba-9a04-a8d297c0dc00
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569080269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.569080269
Directory	/workspace/11.uart_stress_all/latest

Test location	/workspace/coverage/default/11.uart_stress_all_with_rand_reset.1022561846
Short name	T511
Test name
Test status
Simulation time	82115573388 ps
CPU time	1233.31 seconds
Started	Apr 15 02:51:56 PM PDT 24
Finished	Apr 15 03:12:31 PM PDT 24
Peak memory	217356 kb
Host	smart-41f41ab2-fa37-4996-b497-ce407b0a7b7b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022561846 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1022561846
Directory	/workspace/11.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.uart_tx_ovrd.1710926329
Short name	T418
Test name
Test status
Simulation time	336707283 ps
CPU time	1.49 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:50 PM PDT 24
Peak memory	199484 kb
Host	smart-360270a3-7e1b-41b4-91d5-b3d47bbe6a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710926329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1710926329
Directory	/workspace/11.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/11.uart_tx_rx.1054171177
Short name	T636
Test name
Test status
Simulation time	57567132994 ps
CPU time	26.49 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200800 kb
Host	smart-efa14d5a-186a-439c-ab22-0a6f11024e6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054171177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1054171177
Directory	/workspace/11.uart_tx_rx/latest

Test location	/workspace/coverage/default/110.uart_fifo_reset.4129091751
Short name	T142
Test name
Test status
Simulation time	51546020240 ps
CPU time	96.34 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:56:26 PM PDT 24
Peak memory	200856 kb
Host	smart-89082ddc-6235-42ef-aa4a-b342a0d9f93b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129091751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4129091751
Directory	/workspace/110.uart_fifo_reset/latest

Test location	/workspace/coverage/default/111.uart_fifo_reset.1664370011
Short name	T690
Test name
Test status
Simulation time	115123349218 ps
CPU time	40.4 seconds
Started	Apr 15 02:54:46 PM PDT 24
Finished	Apr 15 02:55:27 PM PDT 24
Peak memory	200828 kb
Host	smart-c869a36d-183b-429e-a407-a1ec758d36d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664370011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1664370011
Directory	/workspace/111.uart_fifo_reset/latest

Test location	/workspace/coverage/default/112.uart_fifo_reset.2921716925
Short name	T959
Test name
Test status
Simulation time	121625383235 ps
CPU time	104.08 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:56:33 PM PDT 24
Peak memory	200836 kb
Host	smart-75ba1c56-0e63-4540-897f-9b5bb0a3c1b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921716925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2921716925
Directory	/workspace/112.uart_fifo_reset/latest

Test location	/workspace/coverage/default/113.uart_fifo_reset.4046093504
Short name	T133
Test name
Test status
Simulation time	88376180898 ps
CPU time	149.64 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:57:20 PM PDT 24
Peak memory	200888 kb
Host	smart-c5d90cc5-1a4a-4099-94bc-c9fcf6e00505
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046093504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.4046093504
Directory	/workspace/113.uart_fifo_reset/latest

Test location	/workspace/coverage/default/114.uart_fifo_reset.259982787
Short name	T205
Test name
Test status
Simulation time	21630843955 ps
CPU time	32.84 seconds
Started	Apr 15 02:54:48 PM PDT 24
Finished	Apr 15 02:55:22 PM PDT 24
Peak memory	200924 kb
Host	smart-00ee8703-25d6-4aac-bb94-9a010d6c40ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259982787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.259982787
Directory	/workspace/114.uart_fifo_reset/latest

Test location	/workspace/coverage/default/117.uart_fifo_reset.495854029
Short name	T219
Test name
Test status
Simulation time	24610211761 ps
CPU time	13.3 seconds
Started	Apr 15 02:54:48 PM PDT 24
Finished	Apr 15 02:55:02 PM PDT 24
Peak memory	200864 kb
Host	smart-18ca96e4-a36b-4655-a1cf-507a15ed261c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495854029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.495854029
Directory	/workspace/117.uart_fifo_reset/latest

Test location	/workspace/coverage/default/118.uart_fifo_reset.2733173539
Short name	T514
Test name
Test status
Simulation time	28816731578 ps
CPU time	50.24 seconds
Started	Apr 15 02:54:47 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	200904 kb
Host	smart-d79a5378-9a77-4921-baaa-57e579b3186b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2733173539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2733173539
Directory	/workspace/118.uart_fifo_reset/latest

Test location	/workspace/coverage/default/119.uart_fifo_reset.4010858390
Short name	T951
Test name
Test status
Simulation time	90535581277 ps
CPU time	127.4 seconds
Started	Apr 15 02:54:51 PM PDT 24
Finished	Apr 15 02:56:59 PM PDT 24
Peak memory	200868 kb
Host	smart-ff430c65-9e87-4706-81c2-7c8ccda8b7c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010858390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4010858390
Directory	/workspace/119.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_alert_test.3402055924
Short name	T848
Test name
Test status
Simulation time	49369065 ps
CPU time	0.55 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:51:39 PM PDT 24
Peak memory	196188 kb
Host	smart-e2a84f5d-2b51-4125-a44b-3081735b5767
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402055924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3402055924
Directory	/workspace/12.uart_alert_test/latest

Test location	/workspace/coverage/default/12.uart_fifo_full.3623413871
Short name	T950
Test name
Test status
Simulation time	148811269893 ps
CPU time	65.62 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	200816 kb
Host	smart-32da1e40-05da-44cc-948e-301f16cc32fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623413871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3623413871
Directory	/workspace/12.uart_fifo_full/latest

Test location	/workspace/coverage/default/12.uart_fifo_reset.1686986198
Short name	T273
Test name
Test status
Simulation time	85329325814 ps
CPU time	327.53 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:57:14 PM PDT 24
Peak memory	200940 kb
Host	smart-f32ef698-14b0-434c-aad4-dfb2e32c3239
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686986198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1686986198
Directory	/workspace/12.uart_fifo_reset/latest

Test location	/workspace/coverage/default/12.uart_intr.3586433195
Short name	T386
Test name
Test status
Simulation time	31205153524 ps
CPU time	16.42 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:52:03 PM PDT 24
Peak memory	200948 kb
Host	smart-32bca1ba-c0c0-43a5-8b14-1a486ff7bbfc
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586433195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3586433195
Directory	/workspace/12.uart_intr/latest

Test location	/workspace/coverage/default/12.uart_long_xfer_wo_dly.3961421644
Short name	T624
Test name
Test status
Simulation time	62375763078 ps
CPU time	193.59 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:55:03 PM PDT 24
Peak memory	200828 kb
Host	smart-b0e60389-a8c6-4050-80df-42da76f60d35
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3961421644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3961421644
Directory	/workspace/12.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/12.uart_loopback.3905303418
Short name	T823
Test name
Test status
Simulation time	5592203004 ps
CPU time	11.02 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:52:01 PM PDT 24
Peak memory	199512 kb
Host	smart-4825a86b-c657-4015-a7e1-db47f44243b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905303418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3905303418
Directory	/workspace/12.uart_loopback/latest

Test location	/workspace/coverage/default/12.uart_noise_filter.3923962576
Short name	T727
Test name
Test status
Simulation time	33049344971 ps
CPU time	55.45 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:52:42 PM PDT 24
Peak memory	199960 kb
Host	smart-809350e9-156e-4280-bc6a-b043b024294d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923962576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3923962576
Directory	/workspace/12.uart_noise_filter/latest

Test location	/workspace/coverage/default/12.uart_perf.3949829860
Short name	T453
Test name
Test status
Simulation time	2788673954 ps
CPU time	132.15 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 02:54:00 PM PDT 24
Peak memory	200864 kb
Host	smart-2a507999-d15c-4ebe-bc56-57aecfa4d3ae
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3949829860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3949829860
Directory	/workspace/12.uart_perf/latest

Test location	/workspace/coverage/default/12.uart_rx_oversample.2215486804
Short name	T498
Test name
Test status
Simulation time	7272897737 ps
CPU time	32.2 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	199960 kb
Host	smart-39ee7f98-53c5-4165-a7f8-28aea521eea4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2215486804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2215486804
Directory	/workspace/12.uart_rx_oversample/latest

Test location	/workspace/coverage/default/12.uart_rx_parity_err.862005906
Short name	T1055
Test name
Test status
Simulation time	173815471292 ps
CPU time	159.49 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:54:27 PM PDT 24
Peak memory	200884 kb
Host	smart-98fb1963-0813-4275-b0b0-bc7093cfcfd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862005906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.862005906
Directory	/workspace/12.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/12.uart_rx_start_bit_filter.1908507543
Short name	T537
Test name
Test status
Simulation time	3119995930 ps
CPU time	3.23 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:51:46 PM PDT 24
Peak memory	197188 kb
Host	smart-0e2b5ced-4a1a-4685-9c3d-226f33dbdcf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1908507543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1908507543
Directory	/workspace/12.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/12.uart_smoke.924400774
Short name	T886
Test name
Test status
Simulation time	524952065 ps
CPU time	2.16 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:04 PM PDT 24
Peak memory	200220 kb
Host	smart-5ed2aa5e-9096-488a-8ca0-cd610affc63d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924400774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.924400774
Directory	/workspace/12.uart_smoke/latest

Test location	/workspace/coverage/default/12.uart_stress_all_with_rand_reset.3723245759
Short name	T110
Test name
Test status
Simulation time	57000999232 ps
CPU time	165.16 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 02:54:33 PM PDT 24
Peak memory	217360 kb
Host	smart-57d03fab-1941-4f31-ba51-ff9ebd6a376e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723245759 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3723245759
Directory	/workspace/12.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.uart_tx_ovrd.2131108885
Short name	T407
Test name
Test status
Simulation time	1612601121 ps
CPU time	2.48 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:51:50 PM PDT 24
Peak memory	199688 kb
Host	smart-ea7e3b56-6b0e-4681-ac49-c5e4bafd5af3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131108885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2131108885
Directory	/workspace/12.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/12.uart_tx_rx.1464757911
Short name	T315
Test name
Test status
Simulation time	131016127756 ps
CPU time	24.44 seconds
Started	Apr 15 02:51:50 PM PDT 24
Finished	Apr 15 02:52:15 PM PDT 24
Peak memory	200868 kb
Host	smart-d94e9b4a-0703-41ca-ac9d-2d9654277703
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464757911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1464757911
Directory	/workspace/12.uart_tx_rx/latest

Test location	/workspace/coverage/default/120.uart_fifo_reset.1500456090
Short name	T827
Test name
Test status
Simulation time	149708282427 ps
CPU time	202.03 seconds
Started	Apr 15 02:54:52 PM PDT 24
Finished	Apr 15 02:58:15 PM PDT 24
Peak memory	200904 kb
Host	smart-0d3bfabe-bede-406e-9e13-739fdcf92fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500456090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1500456090
Directory	/workspace/120.uart_fifo_reset/latest

Test location	/workspace/coverage/default/121.uart_fifo_reset.3466893193
Short name	T168
Test name
Test status
Simulation time	44176963032 ps
CPU time	21.09 seconds
Started	Apr 15 02:54:51 PM PDT 24
Finished	Apr 15 02:55:13 PM PDT 24
Peak memory	200912 kb
Host	smart-31b66abb-0c85-43bf-9c28-4c449f15b773
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466893193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3466893193
Directory	/workspace/121.uart_fifo_reset/latest

Test location	/workspace/coverage/default/122.uart_fifo_reset.3737751673
Short name	T234
Test name
Test status
Simulation time	93841625332 ps
CPU time	236.19 seconds
Started	Apr 15 02:54:50 PM PDT 24
Finished	Apr 15 02:58:47 PM PDT 24
Peak memory	200900 kb
Host	smart-24ea210d-3b75-417d-80de-e089eac1dc64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737751673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3737751673
Directory	/workspace/122.uart_fifo_reset/latest

Test location	/workspace/coverage/default/123.uart_fifo_reset.1168794601
Short name	T1019
Test name
Test status
Simulation time	24457782640 ps
CPU time	13.55 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 02:55:04 PM PDT 24
Peak memory	200884 kb
Host	smart-35906a5a-c7ed-42e1-a5d9-f1152874e511
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168794601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1168794601
Directory	/workspace/123.uart_fifo_reset/latest

Test location	/workspace/coverage/default/124.uart_fifo_reset.150014853
Short name	T730
Test name
Test status
Simulation time	97897709968 ps
CPU time	54.2 seconds
Started	Apr 15 02:54:51 PM PDT 24
Finished	Apr 15 02:55:46 PM PDT 24
Peak memory	200968 kb
Host	smart-f5b5d22d-a358-49a9-8578-914efa0cb8d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150014853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.150014853
Directory	/workspace/124.uart_fifo_reset/latest

Test location	/workspace/coverage/default/125.uart_fifo_reset.3692436234
Short name	T100
Test name
Test status
Simulation time	112185623321 ps
CPU time	187.01 seconds
Started	Apr 15 02:54:54 PM PDT 24
Finished	Apr 15 02:58:02 PM PDT 24
Peak memory	200844 kb
Host	smart-2239fee4-5d8f-4b32-8a4e-8aa3d78175cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692436234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3692436234
Directory	/workspace/125.uart_fifo_reset/latest

Test location	/workspace/coverage/default/126.uart_fifo_reset.197518071
Short name	T464
Test name
Test status
Simulation time	189425418520 ps
CPU time	88.61 seconds
Started	Apr 15 02:54:51 PM PDT 24
Finished	Apr 15 02:56:21 PM PDT 24
Peak memory	200840 kb
Host	smart-bdfcbca8-0b9a-4b7c-b588-ec0952b9e668
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197518071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.197518071
Directory	/workspace/126.uart_fifo_reset/latest

Test location	/workspace/coverage/default/128.uart_fifo_reset.4206420931
Short name	T634
Test name
Test status
Simulation time	35108343850 ps
CPU time	61.46 seconds
Started	Apr 15 02:54:55 PM PDT 24
Finished	Apr 15 02:55:57 PM PDT 24
Peak memory	200812 kb
Host	smart-53fe6f76-b027-48af-a284-6e1cfec60dc7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206420931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.4206420931
Directory	/workspace/128.uart_fifo_reset/latest

Test location	/workspace/coverage/default/129.uart_fifo_reset.2432578324
Short name	T1015
Test name
Test status
Simulation time	21168845924 ps
CPU time	34.28 seconds
Started	Apr 15 02:54:59 PM PDT 24
Finished	Apr 15 02:55:33 PM PDT 24
Peak memory	200812 kb
Host	smart-48ad8c5b-3272-4d23-ad6a-b036b29509da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432578324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2432578324
Directory	/workspace/129.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_fifo_full.2350794156
Short name	T1092
Test name
Test status
Simulation time	152886431998 ps
CPU time	540.07 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 03:00:48 PM PDT 24
Peak memory	200920 kb
Host	smart-b181c991-f16c-459d-8e66-ac63fb0116ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350794156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2350794156
Directory	/workspace/13.uart_fifo_full/latest

Test location	/workspace/coverage/default/13.uart_fifo_overflow.2979234156
Short name	T137
Test name
Test status
Simulation time	121893221966 ps
CPU time	211.38 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:55:26 PM PDT 24
Peak memory	200848 kb
Host	smart-677e8635-a637-4c2f-b70b-5d0cb3212f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979234156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2979234156
Directory	/workspace/13.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/13.uart_fifo_reset.1244000896
Short name	T621
Test name
Test status
Simulation time	13519191205 ps
CPU time	11.7 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:51:55 PM PDT 24
Peak memory	200836 kb
Host	smart-e1c42995-dd07-4c1d-b76c-dbd96c5ed1be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244000896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1244000896
Directory	/workspace/13.uart_fifo_reset/latest

Test location	/workspace/coverage/default/13.uart_intr.1983632094
Short name	T991
Test name
Test status
Simulation time	8119787619 ps
CPU time	2.33 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:51:53 PM PDT 24
Peak memory	197660 kb
Host	smart-df3a8ed9-4314-4951-b21e-08d773b7a049
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983632094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1983632094
Directory	/workspace/13.uart_intr/latest

Test location	/workspace/coverage/default/13.uart_long_xfer_wo_dly.2778033970
Short name	T491
Test name
Test status
Simulation time	74906286076 ps
CPU time	130.59 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:53:52 PM PDT 24
Peak memory	200924 kb
Host	smart-43d515a1-dc98-40cc-9e34-577455ff70f4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2778033970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2778033970
Directory	/workspace/13.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/13.uart_loopback.809387219
Short name	T391
Test name
Test status
Simulation time	8019487986 ps
CPU time	15.95 seconds
Started	Apr 15 02:51:49 PM PDT 24
Finished	Apr 15 02:52:06 PM PDT 24
Peak memory	200808 kb
Host	smart-e5d0b34b-fcbf-43a6-b81d-3cf6bd260a5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809387219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.809387219
Directory	/workspace/13.uart_loopback/latest

Test location	/workspace/coverage/default/13.uart_noise_filter.2977137683
Short name	T295
Test name
Test status
Simulation time	88872999200 ps
CPU time	42.35 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:51 PM PDT 24
Peak memory	201096 kb
Host	smart-cc7860d0-940d-4f19-b5ce-3629350d6f41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977137683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2977137683
Directory	/workspace/13.uart_noise_filter/latest

Test location	/workspace/coverage/default/13.uart_perf.1400405918
Short name	T724
Test name
Test status
Simulation time	4744765597 ps
CPU time	45.68 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:52:34 PM PDT 24
Peak memory	200760 kb
Host	smart-ce2e5629-8d5f-4cd0-9060-998d52e8e6f7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1400405918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1400405918
Directory	/workspace/13.uart_perf/latest

Test location	/workspace/coverage/default/13.uart_rx_oversample.134190695
Short name	T849
Test name
Test status
Simulation time	7092228359 ps
CPU time	68.3 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:52:53 PM PDT 24
Peak memory	199096 kb
Host	smart-0f76bd97-e97c-4efc-b3a1-669430cefe50
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=134190695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.134190695
Directory	/workspace/13.uart_rx_oversample/latest

Test location	/workspace/coverage/default/13.uart_rx_parity_err.2056690623
Short name	T274
Test name
Test status
Simulation time	147294400081 ps
CPU time	15.62 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:51:59 PM PDT 24
Peak memory	199540 kb
Host	smart-58bbdefb-98b6-445e-bc43-41995190aee8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056690623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2056690623
Directory	/workspace/13.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/13.uart_rx_start_bit_filter.4025310678
Short name	T948
Test name
Test status
Simulation time	4302389763 ps
CPU time	7.56 seconds
Started	Apr 15 02:51:50 PM PDT 24
Finished	Apr 15 02:51:58 PM PDT 24
Peak memory	196932 kb
Host	smart-264b9a45-546b-4c8c-9a6f-a3bf63486370
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025310678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4025310678
Directory	/workspace/13.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/13.uart_smoke.1502439716
Short name	T47
Test name
Test status
Simulation time	156957753 ps
CPU time	0.83 seconds
Started	Apr 15 02:51:52 PM PDT 24
Finished	Apr 15 02:51:53 PM PDT 24
Peak memory	197864 kb
Host	smart-319d9998-2b0f-4ca6-a4e3-9eba1feccd6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502439716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1502439716
Directory	/workspace/13.uart_smoke/latest

Test location	/workspace/coverage/default/13.uart_stress_all.2711056174
Short name	T1134
Test name
Test status
Simulation time	274475512207 ps
CPU time	266.65 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:56:20 PM PDT 24
Peak memory	200840 kb
Host	smart-3519b8c5-2223-47a4-aee8-2ab2e2343357
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711056174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2711056174
Directory	/workspace/13.uart_stress_all/latest

Test location	/workspace/coverage/default/13.uart_stress_all_with_rand_reset.684353043
Short name	T112
Test name
Test status
Simulation time	123949829007 ps
CPU time	457.06 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:59:29 PM PDT 24
Peak memory	225732 kb
Host	smart-20cc359c-a345-48bc-8634-a36329f78234
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684353043 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.684353043
Directory	/workspace/13.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.uart_tx_ovrd.3226270547
Short name	T1
Test name
Test status
Simulation time	1141509633 ps
CPU time	5.02 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:54 PM PDT 24
Peak memory	199728 kb
Host	smart-5fa576b9-5c79-4fbc-94b1-fd14ef786fc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226270547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3226270547
Directory	/workspace/13.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/13.uart_tx_rx.3116446231
Short name	T840
Test name
Test status
Simulation time	175954509447 ps
CPU time	84.16 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:53:18 PM PDT 24
Peak memory	200848 kb
Host	smart-6d7aeecb-40dc-440e-9eb5-d2ec11139887
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116446231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3116446231
Directory	/workspace/13.uart_tx_rx/latest

Test location	/workspace/coverage/default/130.uart_fifo_reset.891068227
Short name	T313
Test name
Test status
Simulation time	113654270271 ps
CPU time	49.45 seconds
Started	Apr 15 02:54:55 PM PDT 24
Finished	Apr 15 02:55:46 PM PDT 24
Peak memory	200832 kb
Host	smart-1ed76e7e-23a4-445d-a5c3-b9d5e0478c29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891068227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.891068227
Directory	/workspace/130.uart_fifo_reset/latest

Test location	/workspace/coverage/default/131.uart_fifo_reset.77461192
Short name	T248
Test name
Test status
Simulation time	39920589614 ps
CPU time	66.81 seconds
Started	Apr 15 02:54:58 PM PDT 24
Finished	Apr 15 02:56:05 PM PDT 24
Peak memory	200868 kb
Host	smart-7909d34c-c6a9-43ee-a4c1-3bbfb3cb4f4a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77461192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.77461192
Directory	/workspace/131.uart_fifo_reset/latest

Test location	/workspace/coverage/default/132.uart_fifo_reset.3911530548
Short name	T796
Test name
Test status
Simulation time	28451955900 ps
CPU time	42.56 seconds
Started	Apr 15 02:54:55 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	200872 kb
Host	smart-aff28452-7042-4c2a-84a2-1f9717545600
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911530548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3911530548
Directory	/workspace/132.uart_fifo_reset/latest

Test location	/workspace/coverage/default/133.uart_fifo_reset.392716154
Short name	T169
Test name
Test status
Simulation time	46811856393 ps
CPU time	20.16 seconds
Started	Apr 15 02:54:57 PM PDT 24
Finished	Apr 15 02:55:17 PM PDT 24
Peak memory	200896 kb
Host	smart-782356ff-c6df-4ff1-adb7-e2745dee5e13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=392716154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.392716154
Directory	/workspace/133.uart_fifo_reset/latest

Test location	/workspace/coverage/default/134.uart_fifo_reset.3149065433
Short name	T713
Test name
Test status
Simulation time	19111385793 ps
CPU time	22.33 seconds
Started	Apr 15 02:54:54 PM PDT 24
Finished	Apr 15 02:55:17 PM PDT 24
Peak memory	200916 kb
Host	smart-08624210-77f4-40c5-81a1-fdcecf4bbad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149065433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3149065433
Directory	/workspace/134.uart_fifo_reset/latest

Test location	/workspace/coverage/default/137.uart_fifo_reset.3421548519
Short name	T380
Test name
Test status
Simulation time	29714007030 ps
CPU time	10.87 seconds
Started	Apr 15 02:54:55 PM PDT 24
Finished	Apr 15 02:55:07 PM PDT 24
Peak memory	200904 kb
Host	smart-8f9e5bd4-47d0-4247-9b4c-b1815e7bc2d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421548519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3421548519
Directory	/workspace/137.uart_fifo_reset/latest

Test location	/workspace/coverage/default/138.uart_fifo_reset.824227835
Short name	T1021
Test name
Test status
Simulation time	76625423226 ps
CPU time	206.91 seconds
Started	Apr 15 02:55:05 PM PDT 24
Finished	Apr 15 02:58:33 PM PDT 24
Peak memory	200764 kb
Host	smart-d2a259a3-7d35-49f8-9aa2-d1d4aa047349
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824227835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.824227835
Directory	/workspace/138.uart_fifo_reset/latest

Test location	/workspace/coverage/default/139.uart_fifo_reset.3841483015
Short name	T1169
Test name
Test status
Simulation time	10175747971 ps
CPU time	16.74 seconds
Started	Apr 15 02:54:59 PM PDT 24
Finished	Apr 15 02:55:16 PM PDT 24
Peak memory	200892 kb
Host	smart-6b78353a-311b-4d5c-8097-0bb991669ad2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841483015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3841483015
Directory	/workspace/139.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_alert_test.629199592
Short name	T1017
Test name
Test status
Simulation time	40872469 ps
CPU time	0.6 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:01 PM PDT 24
Peak memory	196212 kb
Host	smart-ad5a05ed-09b0-4f2c-8f1e-4cb4e0144740
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629199592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.629199592
Directory	/workspace/14.uart_alert_test/latest

Test location	/workspace/coverage/default/14.uart_fifo_full.450977305
Short name	T862
Test name
Test status
Simulation time	26097878084 ps
CPU time	22.33 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 02:52:10 PM PDT 24
Peak memory	200700 kb
Host	smart-19b46692-d53c-42e1-9671-b0504818f831
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450977305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.450977305
Directory	/workspace/14.uart_fifo_full/latest

Test location	/workspace/coverage/default/14.uart_fifo_overflow.2602350954
Short name	T893
Test name
Test status
Simulation time	129628943341 ps
CPU time	106.91 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:53:38 PM PDT 24
Peak memory	200800 kb
Host	smart-6ae8ea1b-7ab4-4cd6-9bac-d049b97ced61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602350954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2602350954
Directory	/workspace/14.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/14.uart_fifo_reset.243546770
Short name	T206
Test name
Test status
Simulation time	9611538191 ps
CPU time	17.36 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:52:00 PM PDT 24
Peak memory	200860 kb
Host	smart-96c22e83-0b34-4f98-985f-447292f9eed5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243546770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.243546770
Directory	/workspace/14.uart_fifo_reset/latest

Test location	/workspace/coverage/default/14.uart_intr.1034292936
Short name	T492
Test name
Test status
Simulation time	19509101467 ps
CPU time	10.08 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:51:56 PM PDT 24
Peak memory	200716 kb
Host	smart-4a8122df-35a5-41ed-b410-b933fa17730d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034292936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1034292936
Directory	/workspace/14.uart_intr/latest

Test location	/workspace/coverage/default/14.uart_long_xfer_wo_dly.1991275728
Short name	T422
Test name
Test status
Simulation time	175266007662 ps
CPU time	225.53 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:55:52 PM PDT 24
Peak memory	200880 kb
Host	smart-9ac92381-d853-435a-9e62-b19bce3731ce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1991275728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1991275728
Directory	/workspace/14.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/14.uart_loopback.1323346842
Short name	T389
Test name
Test status
Simulation time	4231310473 ps
CPU time	3.14 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:51:55 PM PDT 24
Peak memory	199652 kb
Host	smart-8569b11f-40b5-4f3c-a76c-508fef00b903
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1323346842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1323346842
Directory	/workspace/14.uart_loopback/latest

Test location	/workspace/coverage/default/14.uart_noise_filter.3528073067
Short name	T561
Test name
Test status
Simulation time	34256678336 ps
CPU time	24.56 seconds
Started	Apr 15 02:51:50 PM PDT 24
Finished	Apr 15 02:52:15 PM PDT 24
Peak memory	200292 kb
Host	smart-bd10b04a-1d40-41e7-bf9d-504b788cd9d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3528073067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3528073067
Directory	/workspace/14.uart_noise_filter/latest

Test location	/workspace/coverage/default/14.uart_perf.231564291
Short name	T542
Test name
Test status
Simulation time	13959265112 ps
CPU time	211.43 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:55:31 PM PDT 24
Peak memory	200908 kb
Host	smart-4b62e62e-23ae-4fa4-85f9-505f6b3ce120
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=231564291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.231564291
Directory	/workspace/14.uart_perf/latest

Test location	/workspace/coverage/default/14.uart_rx_oversample.464033442
Short name	T1130
Test name
Test status
Simulation time	1453671719 ps
CPU time	0.82 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	196404 kb
Host	smart-be21128e-6013-4703-b032-588e3dd7c07c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=464033442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.464033442
Directory	/workspace/14.uart_rx_oversample/latest

Test location	/workspace/coverage/default/14.uart_rx_parity_err.4285570746
Short name	T675
Test name
Test status
Simulation time	314544272775 ps
CPU time	76.55 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:53:16 PM PDT 24
Peak memory	200808 kb
Host	smart-45ce7ebc-f247-4bab-8b04-554622d06a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285570746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4285570746
Directory	/workspace/14.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/14.uart_rx_start_bit_filter.3286857663
Short name	T318
Test name
Test status
Simulation time	3734848190 ps
CPU time	6.51 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:56 PM PDT 24
Peak memory	196908 kb
Host	smart-7ceee6aa-8084-4188-8576-c727ca4dce1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286857663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3286857663
Directory	/workspace/14.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/14.uart_smoke.962319683
Short name	T426
Test name
Test status
Simulation time	277410143 ps
CPU time	1.32 seconds
Started	Apr 15 02:51:56 PM PDT 24
Finished	Apr 15 02:51:58 PM PDT 24
Peak memory	199584 kb
Host	smart-7b44808a-8419-48d0-b034-cf08ee78a994
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962319683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.962319683
Directory	/workspace/14.uart_smoke/latest

Test location	/workspace/coverage/default/14.uart_stress_all.1409822166
Short name	T510
Test name
Test status
Simulation time	369421362405 ps
CPU time	259.64 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:56:05 PM PDT 24
Peak memory	201048 kb
Host	smart-c1389c3b-7ddd-4b68-902b-fd819fa30574
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409822166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1409822166
Directory	/workspace/14.uart_stress_all/latest

Test location	/workspace/coverage/default/14.uart_stress_all_with_rand_reset.1524333942
Short name	T1074
Test name
Test status
Simulation time	44157690286 ps
CPU time	574.18 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 03:01:26 PM PDT 24
Peak memory	217588 kb
Host	smart-80678422-66e4-4e92-9939-84c9a9dcf0a0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524333942 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1524333942
Directory	/workspace/14.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.uart_tx_ovrd.1920812239
Short name	T842
Test name
Test status
Simulation time	6673310577 ps
CPU time	11.84 seconds
Started	Apr 15 02:52:04 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	200196 kb
Host	smart-9948c3d9-216b-40b3-a7ad-610e44eadf8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920812239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1920812239
Directory	/workspace/14.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/14.uart_tx_rx.3331500732
Short name	T1094
Test name
Test status
Simulation time	31611403766 ps
CPU time	36.19 seconds
Started	Apr 15 02:52:01 PM PDT 24
Finished	Apr 15 02:52:38 PM PDT 24
Peak memory	200880 kb
Host	smart-dc329a65-961b-4a66-9848-831935bdf31a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331500732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3331500732
Directory	/workspace/14.uart_tx_rx/latest

Test location	/workspace/coverage/default/140.uart_fifo_reset.1359059239
Short name	T259
Test name
Test status
Simulation time	129674191612 ps
CPU time	52.84 seconds
Started	Apr 15 02:55:05 PM PDT 24
Finished	Apr 15 02:55:59 PM PDT 24
Peak memory	200748 kb
Host	smart-645a4000-1c91-40b3-8365-76421db2c339
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359059239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1359059239
Directory	/workspace/140.uart_fifo_reset/latest

Test location	/workspace/coverage/default/141.uart_fifo_reset.4096695053
Short name	T257
Test name
Test status
Simulation time	160862915951 ps
CPU time	29.13 seconds
Started	Apr 15 02:55:05 PM PDT 24
Finished	Apr 15 02:55:35 PM PDT 24
Peak memory	200872 kb
Host	smart-77369236-b8b8-4f42-87ec-e1ed310c2e2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096695053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4096695053
Directory	/workspace/141.uart_fifo_reset/latest

Test location	/workspace/coverage/default/142.uart_fifo_reset.1107899565
Short name	T309
Test name
Test status
Simulation time	22419402368 ps
CPU time	62.4 seconds
Started	Apr 15 02:54:58 PM PDT 24
Finished	Apr 15 02:56:01 PM PDT 24
Peak memory	200812 kb
Host	smart-22929edd-48f2-455a-a7ef-f6ee580f4bb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107899565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1107899565
Directory	/workspace/142.uart_fifo_reset/latest

Test location	/workspace/coverage/default/143.uart_fifo_reset.3650566935
Short name	T1001
Test name
Test status
Simulation time	143467169100 ps
CPU time	128.15 seconds
Started	Apr 15 02:54:59 PM PDT 24
Finished	Apr 15 02:57:08 PM PDT 24
Peak memory	200916 kb
Host	smart-7b0face6-2063-4e8a-80d2-953616d462c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650566935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3650566935
Directory	/workspace/143.uart_fifo_reset/latest

Test location	/workspace/coverage/default/145.uart_fifo_reset.1565128388
Short name	T182
Test name
Test status
Simulation time	193284707252 ps
CPU time	24.01 seconds
Started	Apr 15 02:55:00 PM PDT 24
Finished	Apr 15 02:55:24 PM PDT 24
Peak memory	200656 kb
Host	smart-8eb42bc2-76d5-4589-82ee-4b284acd0bf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565128388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1565128388
Directory	/workspace/145.uart_fifo_reset/latest

Test location	/workspace/coverage/default/146.uart_fifo_reset.1112440365
Short name	T4
Test name
Test status
Simulation time	19353362890 ps
CPU time	32.26 seconds
Started	Apr 15 02:55:00 PM PDT 24
Finished	Apr 15 02:55:33 PM PDT 24
Peak memory	200912 kb
Host	smart-b316796d-050f-4502-b6fa-4a0bf1a8c68f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112440365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1112440365
Directory	/workspace/146.uart_fifo_reset/latest

Test location	/workspace/coverage/default/147.uart_fifo_reset.526122804
Short name	T940
Test name
Test status
Simulation time	39479670924 ps
CPU time	17.43 seconds
Started	Apr 15 02:54:58 PM PDT 24
Finished	Apr 15 02:55:16 PM PDT 24
Peak memory	200792 kb
Host	smart-a05689a1-f0db-4da7-8614-ac626700e7ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526122804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.526122804
Directory	/workspace/147.uart_fifo_reset/latest

Test location	/workspace/coverage/default/148.uart_fifo_reset.1182072062
Short name	T8
Test name
Test status
Simulation time	69547676644 ps
CPU time	26.48 seconds
Started	Apr 15 02:55:02 PM PDT 24
Finished	Apr 15 02:55:30 PM PDT 24
Peak memory	200940 kb
Host	smart-e10f32cb-b112-407b-8388-6b3f703d95e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182072062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1182072062
Directory	/workspace/148.uart_fifo_reset/latest

Test location	/workspace/coverage/default/149.uart_fifo_reset.2922196323
Short name	T114
Test name
Test status
Simulation time	47881668429 ps
CPU time	21.9 seconds
Started	Apr 15 02:55:03 PM PDT 24
Finished	Apr 15 02:55:26 PM PDT 24
Peak memory	200872 kb
Host	smart-28721042-eac8-4cf8-bbfc-59cae2bbb5b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922196323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2922196323
Directory	/workspace/149.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_alert_test.2472115648
Short name	T28
Test name
Test status
Simulation time	130053890 ps
CPU time	0.54 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:52:00 PM PDT 24
Peak memory	196240 kb
Host	smart-c37016a2-ebf8-4e88-9022-04cd8e031502
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472115648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2472115648
Directory	/workspace/15.uart_alert_test/latest

Test location	/workspace/coverage/default/15.uart_fifo_overflow.3754472608
Short name	T375
Test name
Test status
Simulation time	15979374930 ps
CPU time	8.83 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	200924 kb
Host	smart-d46e751c-e69f-4591-800c-b1e0b4bb6894
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754472608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3754472608
Directory	/workspace/15.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/15.uart_fifo_reset.4035902819
Short name	T535
Test name
Test status
Simulation time	37647416818 ps
CPU time	30.25 seconds
Started	Apr 15 02:51:50 PM PDT 24
Finished	Apr 15 02:52:21 PM PDT 24
Peak memory	200888 kb
Host	smart-0f42ad90-3ede-42e3-872d-eae71643fd85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4035902819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4035902819
Directory	/workspace/15.uart_fifo_reset/latest

Test location	/workspace/coverage/default/15.uart_intr.649720379
Short name	T311
Test name
Test status
Simulation time	27669485719 ps
CPU time	90.57 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:53:38 PM PDT 24
Peak memory	200820 kb
Host	smart-9e96dd36-aa74-4c74-afdb-97cbc361444b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649720379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.649720379
Directory	/workspace/15.uart_intr/latest

Test location	/workspace/coverage/default/15.uart_long_xfer_wo_dly.3557409606
Short name	T735
Test name
Test status
Simulation time	227391304357 ps
CPU time	181.95 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:55:03 PM PDT 24
Peak memory	200888 kb
Host	smart-63c07591-4ff7-4468-be4f-8a3c50b9ca0c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3557409606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3557409606
Directory	/workspace/15.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/15.uart_loopback.2194282329
Short name	T1173
Test name
Test status
Simulation time	3379679139 ps
CPU time	3.97 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:51:55 PM PDT 24
Peak memory	199652 kb
Host	smart-15c6a190-158d-4234-8cc3-51d25aeb950a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194282329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2194282329
Directory	/workspace/15.uart_loopback/latest

Test location	/workspace/coverage/default/15.uart_noise_filter.3963059254
Short name	T979
Test name
Test status
Simulation time	179349131359 ps
CPU time	82.77 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:53:22 PM PDT 24
Peak memory	217368 kb
Host	smart-7fadac10-76fe-47c1-83c4-5ece52bb5610
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3963059254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3963059254
Directory	/workspace/15.uart_noise_filter/latest

Test location	/workspace/coverage/default/15.uart_rx_oversample.3143508253
Short name	T1152
Test name
Test status
Simulation time	5017457804 ps
CPU time	6.74 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:07 PM PDT 24
Peak memory	200072 kb
Host	smart-4410bf7e-2b7f-4120-8562-1e42a7901b37
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3143508253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3143508253
Directory	/workspace/15.uart_rx_oversample/latest

Test location	/workspace/coverage/default/15.uart_rx_parity_err.3827136639
Short name	T421
Test name
Test status
Simulation time	102467683760 ps
CPU time	48.14 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:52:40 PM PDT 24
Peak memory	200432 kb
Host	smart-15ba0eb8-da69-40d1-8cac-6f121e1a6c00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827136639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3827136639
Directory	/workspace/15.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/15.uart_rx_start_bit_filter.705848867
Short name	T437
Test name
Test status
Simulation time	4116779891 ps
CPU time	3.97 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:53 PM PDT 24
Peak memory	197228 kb
Host	smart-bae775fc-701f-46ab-af13-f5ede40fc6f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=705848867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.705848867
Directory	/workspace/15.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/15.uart_smoke.3244588437
Short name	T573
Test name
Test status
Simulation time	627392767 ps
CPU time	2.42 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	199620 kb
Host	smart-7721efd8-eb22-4d7f-b5b8-9d4814be95c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244588437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3244588437
Directory	/workspace/15.uart_smoke/latest

Test location	/workspace/coverage/default/15.uart_stress_all.2279455344
Short name	T528
Test name
Test status
Simulation time	166069797060 ps
CPU time	919.81 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 03:07:21 PM PDT 24
Peak memory	200844 kb
Host	smart-4aea1cc2-8359-4d08-86e1-70e23ccab8ad
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279455344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2279455344
Directory	/workspace/15.uart_stress_all/latest

Test location	/workspace/coverage/default/15.uart_stress_all_with_rand_reset.2904136903
Short name	T467
Test name
Test status
Simulation time	37428824512 ps
CPU time	503.28 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 03:00:20 PM PDT 24
Peak memory	217552 kb
Host	smart-8c02eb02-7c45-4c79-9f9f-a938f5e7b734
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904136903 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2904136903
Directory	/workspace/15.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.uart_tx_ovrd.2376594948
Short name	T961
Test name
Test status
Simulation time	1412180639 ps
CPU time	3.02 seconds
Started	Apr 15 02:51:56 PM PDT 24
Finished	Apr 15 02:52:00 PM PDT 24
Peak memory	200120 kb
Host	smart-5cd8464e-3b34-4f35-9324-2378d1057d11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376594948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2376594948
Directory	/workspace/15.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/15.uart_tx_rx.2347828029
Short name	T306
Test name
Test status
Simulation time	21284546018 ps
CPU time	32.59 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:52:22 PM PDT 24
Peak memory	200872 kb
Host	smart-0f62d0a6-70d0-46d6-8a76-7b8081a2612c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347828029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2347828029
Directory	/workspace/15.uart_tx_rx/latest

Test location	/workspace/coverage/default/150.uart_fifo_reset.3903060343
Short name	T1033
Test name
Test status
Simulation time	16989702327 ps
CPU time	27.9 seconds
Started	Apr 15 02:55:04 PM PDT 24
Finished	Apr 15 02:55:33 PM PDT 24
Peak memory	200912 kb
Host	smart-f8d45f1e-f297-4bbd-87b4-6d291841d8c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903060343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3903060343
Directory	/workspace/150.uart_fifo_reset/latest

Test location	/workspace/coverage/default/151.uart_fifo_reset.1129128334
Short name	T1151
Test name
Test status
Simulation time	55804679118 ps
CPU time	86.06 seconds
Started	Apr 15 02:55:04 PM PDT 24
Finished	Apr 15 02:56:31 PM PDT 24
Peak memory	201024 kb
Host	smart-8b870071-40ae-4ad1-adcc-e6efafcbf87c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129128334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1129128334
Directory	/workspace/151.uart_fifo_reset/latest

Test location	/workspace/coverage/default/152.uart_fifo_reset.3801700090
Short name	T1044
Test name
Test status
Simulation time	54825000126 ps
CPU time	22.56 seconds
Started	Apr 15 02:55:04 PM PDT 24
Finished	Apr 15 02:55:27 PM PDT 24
Peak memory	200836 kb
Host	smart-3bfba0ca-5f6a-4a01-94ea-89091922ef8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3801700090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3801700090
Directory	/workspace/152.uart_fifo_reset/latest

Test location	/workspace/coverage/default/154.uart_fifo_reset.3946178782
Short name	T208
Test name
Test status
Simulation time	44105308846 ps
CPU time	26.52 seconds
Started	Apr 15 02:55:03 PM PDT 24
Finished	Apr 15 02:55:31 PM PDT 24
Peak memory	200948 kb
Host	smart-d7170ca7-48f0-4118-8eb2-cc9c9bdfabcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946178782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3946178782
Directory	/workspace/154.uart_fifo_reset/latest

Test location	/workspace/coverage/default/155.uart_fifo_reset.3118432139
Short name	T277
Test name
Test status
Simulation time	98255064478 ps
CPU time	514.56 seconds
Started	Apr 15 02:55:02 PM PDT 24
Finished	Apr 15 03:03:38 PM PDT 24
Peak memory	200844 kb
Host	smart-f518e334-92c7-499d-9bbf-2d8b7ad66be2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118432139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3118432139
Directory	/workspace/155.uart_fifo_reset/latest

Test location	/workspace/coverage/default/156.uart_fifo_reset.3671034286
Short name	T720
Test name
Test status
Simulation time	88809284850 ps
CPU time	147.45 seconds
Started	Apr 15 02:55:05 PM PDT 24
Finished	Apr 15 02:57:33 PM PDT 24
Peak memory	200680 kb
Host	smart-48772a39-eb83-41b6-8465-0a1fd8136bae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671034286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3671034286
Directory	/workspace/156.uart_fifo_reset/latest

Test location	/workspace/coverage/default/157.uart_fifo_reset.1409722882
Short name	T430
Test name
Test status
Simulation time	21945024903 ps
CPU time	35.32 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:55:44 PM PDT 24
Peak memory	200668 kb
Host	smart-7663bfff-6d8d-4d70-bc11-f1831130c363
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409722882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1409722882
Directory	/workspace/157.uart_fifo_reset/latest

Test location	/workspace/coverage/default/158.uart_fifo_reset.4080912449
Short name	T1183
Test name
Test status
Simulation time	50390568711 ps
CPU time	52.27 seconds
Started	Apr 15 02:55:07 PM PDT 24
Finished	Apr 15 02:56:00 PM PDT 24
Peak memory	200924 kb
Host	smart-0d853f50-91a8-4e6c-a449-63c84c402034
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080912449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4080912449
Directory	/workspace/158.uart_fifo_reset/latest

Test location	/workspace/coverage/default/159.uart_fifo_reset.2431928268
Short name	T677
Test name
Test status
Simulation time	52658931665 ps
CPU time	28.95 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	200844 kb
Host	smart-203021c8-17f7-4677-9ed9-29ccf4c05e30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431928268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2431928268
Directory	/workspace/159.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_alert_test.53211507
Short name	T655
Test name
Test status
Simulation time	25002988 ps
CPU time	0.6 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:15 PM PDT 24
Peak memory	196208 kb
Host	smart-8bc95139-8f39-4011-8eb4-9d7e8ad59077
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53211507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.53211507
Directory	/workspace/16.uart_alert_test/latest

Test location	/workspace/coverage/default/16.uart_fifo_full.3742473794
Short name	T291
Test name
Test status
Simulation time	102826267919 ps
CPU time	41.91 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:52:46 PM PDT 24
Peak memory	200876 kb
Host	smart-4da845d5-3984-469d-9569-7c19106444ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3742473794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3742473794
Directory	/workspace/16.uart_fifo_full/latest

Test location	/workspace/coverage/default/16.uart_fifo_overflow.4181911325
Short name	T611
Test name
Test status
Simulation time	51387096755 ps
CPU time	39.67 seconds
Started	Apr 15 02:51:51 PM PDT 24
Finished	Apr 15 02:52:32 PM PDT 24
Peak memory	200892 kb
Host	smart-56d2919c-a0d5-40be-8b6c-dd3b79e19548
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181911325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4181911325
Directory	/workspace/16.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/16.uart_fifo_reset.3777189896
Short name	T990
Test name
Test status
Simulation time	185393579605 ps
CPU time	211.59 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:55:26 PM PDT 24
Peak memory	200804 kb
Host	smart-831363bf-01bc-4760-9845-a88ff21afce8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777189896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3777189896
Directory	/workspace/16.uart_fifo_reset/latest

Test location	/workspace/coverage/default/16.uart_intr.1051243314
Short name	T658
Test name
Test status
Simulation time	4344608982 ps
CPU time	2.36 seconds
Started	Apr 15 02:52:02 PM PDT 24
Finished	Apr 15 02:52:05 PM PDT 24
Peak memory	197580 kb
Host	smart-5b94c7c5-3647-4e83-b6d6-68ddc4c86c69
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051243314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1051243314
Directory	/workspace/16.uart_intr/latest

Test location	/workspace/coverage/default/16.uart_long_xfer_wo_dly.3343606819
Short name	T885
Test name
Test status
Simulation time	67529986510 ps
CPU time	142.59 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:54:21 PM PDT 24
Peak memory	200836 kb
Host	smart-36642d3e-f9e4-4ca1-9b3f-b67752b1c9c1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3343606819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3343606819
Directory	/workspace/16.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/16.uart_loopback.3088928415
Short name	T485
Test name
Test status
Simulation time	10652016704 ps
CPU time	9.18 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:04 PM PDT 24
Peak memory	199896 kb
Host	smart-25e94c8f-4fc0-4e6d-ba99-27e17270aa9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3088928415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3088928415
Directory	/workspace/16.uart_loopback/latest

Test location	/workspace/coverage/default/16.uart_noise_filter.1168642756
Short name	T494
Test name
Test status
Simulation time	11861765069 ps
CPU time	8.42 seconds
Started	Apr 15 02:52:01 PM PDT 24
Finished	Apr 15 02:52:10 PM PDT 24
Peak memory	199080 kb
Host	smart-499809da-9c10-4aa9-bb19-13c8a4832bf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168642756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1168642756
Directory	/workspace/16.uart_noise_filter/latest

Test location	/workspace/coverage/default/16.uart_perf.545991253
Short name	T385
Test name
Test status
Simulation time	19002639703 ps
CPU time	72.52 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	200868 kb
Host	smart-754d3ee9-34d7-4358-8ffb-cafdc2624963
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=545991253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.545991253
Directory	/workspace/16.uart_perf/latest

Test location	/workspace/coverage/default/16.uart_rx_oversample.1236044395
Short name	T639
Test name
Test status
Simulation time	5475567006 ps
CPU time	27.55 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	200024 kb
Host	smart-14745501-e8fb-49ad-b0f1-4de4dd3a5d63
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1236044395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1236044395
Directory	/workspace/16.uart_rx_oversample/latest

Test location	/workspace/coverage/default/16.uart_rx_parity_err.289604198
Short name	T106
Test name
Test status
Simulation time	149569342361 ps
CPU time	15.18 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:52:19 PM PDT 24
Peak memory	199604 kb
Host	smart-68bafdcb-8117-4746-bea5-fd7b1d9b8aff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289604198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.289604198
Directory	/workspace/16.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/16.uart_rx_start_bit_filter.1028566896
Short name	T387
Test name
Test status
Simulation time	3168358577 ps
CPU time	1.56 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:51:51 PM PDT 24
Peak memory	196608 kb
Host	smart-08ad8e0a-44c1-4e24-8217-b65d929bdbb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028566896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1028566896
Directory	/workspace/16.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/16.uart_smoke.1413658491
Short name	T800
Test name
Test status
Simulation time	5908773312 ps
CPU time	40.83 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:50 PM PDT 24
Peak memory	200836 kb
Host	smart-98b53159-d58b-443b-b13c-70192aa48555
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413658491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1413658491
Directory	/workspace/16.uart_smoke/latest

Test location	/workspace/coverage/default/16.uart_stress_all_with_rand_reset.3019305199
Short name	T1132
Test name
Test status
Simulation time	96314475345 ps
CPU time	417.39 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:58:58 PM PDT 24
Peak memory	216688 kb
Host	smart-e340d90f-4016-4db7-a253-3bedd0123250
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019305199 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3019305199
Directory	/workspace/16.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.uart_tx_ovrd.619478420
Short name	T608
Test name
Test status
Simulation time	7867465533 ps
CPU time	9.73 seconds
Started	Apr 15 02:52:01 PM PDT 24
Finished	Apr 15 02:52:12 PM PDT 24
Peak memory	200800 kb
Host	smart-95e61782-243f-45b9-a246-8c069f17aae5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619478420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.619478420
Directory	/workspace/16.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/16.uart_tx_rx.1253054496
Short name	T943
Test name
Test status
Simulation time	48577169729 ps
CPU time	18.98 seconds
Started	Apr 15 02:52:01 PM PDT 24
Finished	Apr 15 02:52:22 PM PDT 24
Peak memory	200820 kb
Host	smart-b8e2d8a7-b9a9-4559-bd2e-2b9dc4645777
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253054496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1253054496
Directory	/workspace/16.uart_tx_rx/latest

Test location	/workspace/coverage/default/162.uart_fifo_reset.4079716987
Short name	T953
Test name
Test status
Simulation time	54151443719 ps
CPU time	42.46 seconds
Started	Apr 15 02:55:10 PM PDT 24
Finished	Apr 15 02:55:53 PM PDT 24
Peak memory	200820 kb
Host	smart-feb0c2b2-2c7c-4160-85d3-3d7e8f60f7a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079716987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.4079716987
Directory	/workspace/162.uart_fifo_reset/latest

Test location	/workspace/coverage/default/163.uart_fifo_reset.871044954
Short name	T414
Test name
Test status
Simulation time	64698639308 ps
CPU time	133.72 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:57:23 PM PDT 24
Peak memory	200804 kb
Host	smart-b2291e11-276c-4c1d-9d2d-86168586015b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871044954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.871044954
Directory	/workspace/163.uart_fifo_reset/latest

Test location	/workspace/coverage/default/164.uart_fifo_reset.3826555432
Short name	T1156
Test name
Test status
Simulation time	89142992466 ps
CPU time	153.84 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:57:43 PM PDT 24
Peak memory	200920 kb
Host	smart-07cba5c5-a0cb-4062-87ef-c857ca34f73e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826555432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3826555432
Directory	/workspace/164.uart_fifo_reset/latest

Test location	/workspace/coverage/default/165.uart_fifo_reset.2690378356
Short name	T546
Test name
Test status
Simulation time	137571857691 ps
CPU time	68.78 seconds
Started	Apr 15 02:55:08 PM PDT 24
Finished	Apr 15 02:56:17 PM PDT 24
Peak memory	200844 kb
Host	smart-6d1772d5-eb6d-41f9-a9e0-6f1f3f87ffe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690378356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2690378356
Directory	/workspace/165.uart_fifo_reset/latest

Test location	/workspace/coverage/default/166.uart_fifo_reset.1918523128
Short name	T737
Test name
Test status
Simulation time	86517490553 ps
CPU time	193.14 seconds
Started	Apr 15 02:55:15 PM PDT 24
Finished	Apr 15 02:58:30 PM PDT 24
Peak memory	200836 kb
Host	smart-7d7b4602-3ac1-4d87-9162-381d4b9f11a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918523128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1918523128
Directory	/workspace/166.uart_fifo_reset/latest

Test location	/workspace/coverage/default/167.uart_fifo_reset.2894363390
Short name	T351
Test name
Test status
Simulation time	84914289739 ps
CPU time	33.49 seconds
Started	Apr 15 02:55:11 PM PDT 24
Finished	Apr 15 02:55:45 PM PDT 24
Peak memory	200904 kb
Host	smart-dd861250-459a-4fc7-956a-1a49273eca07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894363390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2894363390
Directory	/workspace/167.uart_fifo_reset/latest

Test location	/workspace/coverage/default/168.uart_fifo_reset.1166552601
Short name	T1118
Test name
Test status
Simulation time	83219863106 ps
CPU time	46.06 seconds
Started	Apr 15 02:55:11 PM PDT 24
Finished	Apr 15 02:55:58 PM PDT 24
Peak memory	200824 kb
Host	smart-f1b1f4d7-11c7-440e-9090-8f21dc1188fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166552601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1166552601
Directory	/workspace/168.uart_fifo_reset/latest

Test location	/workspace/coverage/default/169.uart_fifo_reset.1764158342
Short name	T347
Test name
Test status
Simulation time	211833622370 ps
CPU time	97.7 seconds
Started	Apr 15 02:55:14 PM PDT 24
Finished	Apr 15 02:56:52 PM PDT 24
Peak memory	200752 kb
Host	smart-f0d2ad44-6923-411d-9616-d174f44bca6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764158342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1764158342
Directory	/workspace/169.uart_fifo_reset/latest

Test location	/workspace/coverage/default/17.uart_alert_test.2012394380
Short name	T935
Test name
Test status
Simulation time	13378780 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:51:55 PM PDT 24
Peak memory	196180 kb
Host	smart-512de842-8af0-4b14-9ed9-f20b73fe87db
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012394380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2012394380
Directory	/workspace/17.uart_alert_test/latest

Test location	/workspace/coverage/default/17.uart_fifo_full.1170639651
Short name	T966
Test name
Test status
Simulation time	288546990036 ps
CPU time	902.7 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 03:07:04 PM PDT 24
Peak memory	200956 kb
Host	smart-6c2805ac-a055-4b83-b5a0-b6600b4b4371
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170639651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1170639651
Directory	/workspace/17.uart_fifo_full/latest

Test location	/workspace/coverage/default/17.uart_fifo_overflow.3083751924
Short name	T795
Test name
Test status
Simulation time	30973947778 ps
CPU time	13.26 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:09 PM PDT 24
Peak memory	200684 kb
Host	smart-3117d569-b36b-4b70-ae2d-a15a207b8ddf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083751924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3083751924
Directory	/workspace/17.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/17.uart_intr.2563481608
Short name	T102
Test name
Test status
Simulation time	44239670215 ps
CPU time	89.59 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:53:25 PM PDT 24
Peak memory	200784 kb
Host	smart-c9844ad4-c1f1-48f6-8b63-7004ec965374
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563481608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2563481608
Directory	/workspace/17.uart_intr/latest

Test location	/workspace/coverage/default/17.uart_long_xfer_wo_dly.3274144152
Short name	T593
Test name
Test status
Simulation time	35332656995 ps
CPU time	145.12 seconds
Started	Apr 15 02:52:04 PM PDT 24
Finished	Apr 15 02:54:30 PM PDT 24
Peak memory	200868 kb
Host	smart-6998333d-7bae-46dd-8708-c306d793af47
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3274144152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3274144152
Directory	/workspace/17.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/17.uart_loopback.3331121697
Short name	T927
Test name
Test status
Simulation time	2156046736 ps
CPU time	1.72 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:52:09 PM PDT 24
Peak memory	196992 kb
Host	smart-8e860405-8fe3-491e-bfaa-038b298ddfd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331121697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3331121697
Directory	/workspace/17.uart_loopback/latest

Test location	/workspace/coverage/default/17.uart_noise_filter.2908112883
Short name	T1084
Test name
Test status
Simulation time	132097929413 ps
CPU time	67.61 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:53:03 PM PDT 24
Peak memory	201104 kb
Host	smart-0711b842-a9e3-4a89-85fe-2c29d0c32a69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908112883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2908112883
Directory	/workspace/17.uart_noise_filter/latest

Test location	/workspace/coverage/default/17.uart_perf.3751308511
Short name	T9
Test name
Test status
Simulation time	23537879239 ps
CPU time	1446.48 seconds
Started	Apr 15 02:52:04 PM PDT 24
Finished	Apr 15 03:16:11 PM PDT 24
Peak memory	200948 kb
Host	smart-0cce8be6-3ee4-4791-a3ab-89e331a2e220
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3751308511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3751308511
Directory	/workspace/17.uart_perf/latest

Test location	/workspace/coverage/default/17.uart_rx_oversample.546892959
Short name	T704
Test name
Test status
Simulation time	4364794621 ps
CPU time	37.73 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	198948 kb
Host	smart-ebabd8e5-63d8-4ba2-ae33-1004613a1313
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=546892959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.546892959
Directory	/workspace/17.uart_rx_oversample/latest

Test location	/workspace/coverage/default/17.uart_rx_parity_err.3266164849
Short name	T22
Test name
Test status
Simulation time	35678614279 ps
CPU time	31.78 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	200820 kb
Host	smart-534b4aea-2f51-4ce2-a00f-484e2bc707a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266164849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3266164849
Directory	/workspace/17.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/17.uart_rx_start_bit_filter.1028173944
Short name	T914
Test name
Test status
Simulation time	513474870 ps
CPU time	1.06 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:02 PM PDT 24
Peak memory	196216 kb
Host	smart-47382361-bf0b-4a30-ba7a-141af6a19f24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1028173944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1028173944
Directory	/workspace/17.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/17.uart_smoke.2991759573
Short name	T474
Test name
Test status
Simulation time	648286428 ps
CPU time	3.75 seconds
Started	Apr 15 02:51:57 PM PDT 24
Finished	Apr 15 02:52:01 PM PDT 24
Peak memory	200532 kb
Host	smart-dc21a8c1-46cc-497e-ae6d-bc65c5187691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2991759573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2991759573
Directory	/workspace/17.uart_smoke/latest

Test location	/workspace/coverage/default/17.uart_stress_all.2209752150
Short name	T1012
Test name
Test status
Simulation time	151775615231 ps
CPU time	67.81 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	217084 kb
Host	smart-59774e98-1b6b-4b95-8ca9-eaa221687610
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209752150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2209752150
Directory	/workspace/17.uart_stress_all/latest

Test location	/workspace/coverage/default/17.uart_stress_all_with_rand_reset.2048841839
Short name	T721
Test name
Test status
Simulation time	62544581522 ps
CPU time	389.51 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:58:29 PM PDT 24
Peak memory	216356 kb
Host	smart-864c41fd-0df4-407d-a7cc-726f9c4b9b89
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048841839 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2048841839
Directory	/workspace/17.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.uart_tx_ovrd.2507575629
Short name	T734
Test name
Test status
Simulation time	690836811 ps
CPU time	2.09 seconds
Started	Apr 15 02:52:12 PM PDT 24
Finished	Apr 15 02:52:15 PM PDT 24
Peak memory	199104 kb
Host	smart-517370f4-c8ad-4cf5-8149-1fef414dc83f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507575629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2507575629
Directory	/workspace/17.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/17.uart_tx_rx.2822103856
Short name	T303
Test name
Test status
Simulation time	32555362895 ps
CPU time	12.07 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:52:18 PM PDT 24
Peak memory	200932 kb
Host	smart-947f7bc9-6bb6-4730-a81d-22ded9554c29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822103856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2822103856
Directory	/workspace/17.uart_tx_rx/latest

Test location	/workspace/coverage/default/170.uart_fifo_reset.1724093142
Short name	T269
Test name
Test status
Simulation time	235197668926 ps
CPU time	34.72 seconds
Started	Apr 15 02:55:13 PM PDT 24
Finished	Apr 15 02:55:48 PM PDT 24
Peak memory	200820 kb
Host	smart-73a9a90d-d1a6-4124-ab3d-6d25d0a379a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1724093142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1724093142
Directory	/workspace/170.uart_fifo_reset/latest

Test location	/workspace/coverage/default/171.uart_fifo_reset.3775736018
Short name	T174
Test name
Test status
Simulation time	28906533651 ps
CPU time	12.25 seconds
Started	Apr 15 02:55:13 PM PDT 24
Finished	Apr 15 02:55:25 PM PDT 24
Peak memory	200876 kb
Host	smart-0414429d-7c99-48ee-887c-0a7ea1175441
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775736018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3775736018
Directory	/workspace/171.uart_fifo_reset/latest

Test location	/workspace/coverage/default/172.uart_fifo_reset.3415097868
Short name	T778
Test name
Test status
Simulation time	116329214580 ps
CPU time	18.15 seconds
Started	Apr 15 02:55:15 PM PDT 24
Finished	Apr 15 02:55:34 PM PDT 24
Peak memory	200804 kb
Host	smart-b6713dcb-0373-439f-b03a-e6654dbe9797
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415097868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3415097868
Directory	/workspace/172.uart_fifo_reset/latest

Test location	/workspace/coverage/default/173.uart_fifo_reset.68870602
Short name	T199
Test name
Test status
Simulation time	81696614866 ps
CPU time	104.9 seconds
Started	Apr 15 02:55:13 PM PDT 24
Finished	Apr 15 02:56:58 PM PDT 24
Peak memory	200864 kb
Host	smart-ef2a1b16-3054-4a65-9ed9-762d4aa36fa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68870602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.68870602
Directory	/workspace/173.uart_fifo_reset/latest

Test location	/workspace/coverage/default/174.uart_fifo_reset.1151005280
Short name	T708
Test name
Test status
Simulation time	122530291328 ps
CPU time	221.52 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:58:59 PM PDT 24
Peak memory	200856 kb
Host	smart-3406e223-4455-429c-9322-ce3828843768
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151005280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1151005280
Directory	/workspace/174.uart_fifo_reset/latest

Test location	/workspace/coverage/default/176.uart_fifo_reset.1884090156
Short name	T235
Test name
Test status
Simulation time	63996653813 ps
CPU time	44.01 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:56:01 PM PDT 24
Peak memory	200912 kb
Host	smart-351c22f8-9554-45e9-8b50-ee6fc80df0d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884090156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1884090156
Directory	/workspace/176.uart_fifo_reset/latest

Test location	/workspace/coverage/default/177.uart_fifo_reset.2966797521
Short name	T588
Test name
Test status
Simulation time	8984353656 ps
CPU time	13.93 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:55:31 PM PDT 24
Peak memory	200640 kb
Host	smart-30126fff-ec5b-4bfa-bfa0-3ecea43b4d4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966797521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2966797521
Directory	/workspace/177.uart_fifo_reset/latest

Test location	/workspace/coverage/default/178.uart_fifo_reset.1902353438
Short name	T126
Test name
Test status
Simulation time	21658836911 ps
CPU time	38.1 seconds
Started	Apr 15 02:55:18 PM PDT 24
Finished	Apr 15 02:55:57 PM PDT 24
Peak memory	200928 kb
Host	smart-07610892-893f-4052-b8bc-5b48878ee3d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902353438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1902353438
Directory	/workspace/178.uart_fifo_reset/latest

Test location	/workspace/coverage/default/179.uart_fifo_reset.2502390411
Short name	T186
Test name
Test status
Simulation time	230714542621 ps
CPU time	20.06 seconds
Started	Apr 15 02:55:18 PM PDT 24
Finished	Apr 15 02:55:39 PM PDT 24
Peak memory	200920 kb
Host	smart-df11ca8b-2f5c-4aa6-9215-e2140edfb400
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502390411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2502390411
Directory	/workspace/179.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_alert_test.1742686752
Short name	T425
Test name
Test status
Simulation time	57481131 ps
CPU time	0.57 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 02:52:11 PM PDT 24
Peak memory	196236 kb
Host	smart-de58d78e-efc5-4408-8e14-1d6098ac3cd6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742686752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1742686752
Directory	/workspace/18.uart_alert_test/latest

Test location	/workspace/coverage/default/18.uart_fifo_full.2662744034
Short name	T1081
Test name
Test status
Simulation time	146835379102 ps
CPU time	22.95 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:52:29 PM PDT 24
Peak memory	200788 kb
Host	smart-b7550082-55ee-4ca2-a42e-493bc1beddb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662744034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2662744034
Directory	/workspace/18.uart_fifo_full/latest

Test location	/workspace/coverage/default/18.uart_fifo_overflow.1255713224
Short name	T41
Test name
Test status
Simulation time	55731561544 ps
CPU time	29.55 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 02:52:26 PM PDT 24
Peak memory	200896 kb
Host	smart-8ef2d103-3bb4-42a0-b8d9-7e3d0ed44260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255713224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1255713224
Directory	/workspace/18.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/18.uart_fifo_reset.1205570039
Short name	T1067
Test name
Test status
Simulation time	318246179251 ps
CPU time	57.31 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:59 PM PDT 24
Peak memory	200928 kb
Host	smart-ce53c618-2051-4da8-b65c-8c686411abd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205570039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1205570039
Directory	/workspace/18.uart_fifo_reset/latest

Test location	/workspace/coverage/default/18.uart_intr.3543474375
Short name	T25
Test name
Test status
Simulation time	144530532370 ps
CPU time	129.47 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:54:16 PM PDT 24
Peak memory	201032 kb
Host	smart-b445a248-0b21-4de2-a117-4006f114d7b7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543474375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3543474375
Directory	/workspace/18.uart_intr/latest

Test location	/workspace/coverage/default/18.uart_loopback.1112305188
Short name	T373
Test name
Test status
Simulation time	5430302021 ps
CPU time	14.29 seconds
Started	Apr 15 02:52:02 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	200812 kb
Host	smart-3da5bdfe-6720-406c-bc33-3a6fff3e33b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112305188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1112305188
Directory	/workspace/18.uart_loopback/latest

Test location	/workspace/coverage/default/18.uart_noise_filter.2451636627
Short name	T424
Test name
Test status
Simulation time	81356758650 ps
CPU time	40.3 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	200228 kb
Host	smart-10d67847-9c59-4b5c-8f6c-c7690299f129
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451636627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2451636627
Directory	/workspace/18.uart_noise_filter/latest

Test location	/workspace/coverage/default/18.uart_perf.1043528575
Short name	T1142
Test name
Test status
Simulation time	7084483783 ps
CPU time	87.39 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200924 kb
Host	smart-0f5b0aaa-17b2-4274-a0a2-e2b96fdf9fce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1043528575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1043528575
Directory	/workspace/18.uart_perf/latest

Test location	/workspace/coverage/default/18.uart_rx_oversample.2887724997
Short name	T797
Test name
Test status
Simulation time	2143087406 ps
CPU time	3.76 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:05 PM PDT 24
Peak memory	198764 kb
Host	smart-50e4e65e-f906-437a-9773-a0fb08d105da
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2887724997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2887724997
Directory	/workspace/18.uart_rx_oversample/latest

Test location	/workspace/coverage/default/18.uart_rx_parity_err.1575861804
Short name	T697
Test name
Test status
Simulation time	147927302343 ps
CPU time	89.88 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:53:24 PM PDT 24
Peak memory	200728 kb
Host	smart-0cc0098d-46d3-427e-b52a-952cab160b8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575861804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1575861804
Directory	/workspace/18.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/18.uart_rx_start_bit_filter.3513273349
Short name	T1047
Test name
Test status
Simulation time	37119998233 ps
CPU time	15.84 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:16 PM PDT 24
Peak memory	197200 kb
Host	smart-cb173aac-774c-4c12-98c5-1ccf942fee4c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513273349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3513273349
Directory	/workspace/18.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/18.uart_smoke.1293831734
Short name	T685
Test name
Test status
Simulation time	555423392 ps
CPU time	2.82 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:52:02 PM PDT 24
Peak memory	200552 kb
Host	smart-980e9c5c-cf85-430d-ae7e-cf8e9c83a03f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293831734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1293831734
Directory	/workspace/18.uart_smoke/latest

Test location	/workspace/coverage/default/18.uart_stress_all.3285952182
Short name	T715
Test name
Test status
Simulation time	121318346820 ps
CPU time	739.48 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 03:04:21 PM PDT 24
Peak memory	201100 kb
Host	smart-ed5fbdb3-6af2-4911-a767-1454fe020253
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285952182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3285952182
Directory	/workspace/18.uart_stress_all/latest

Test location	/workspace/coverage/default/18.uart_tx_ovrd.360684509
Short name	T388
Test name
Test status
Simulation time	6670018932 ps
CPU time	21.22 seconds
Started	Apr 15 02:52:02 PM PDT 24
Finished	Apr 15 02:52:24 PM PDT 24
Peak memory	200180 kb
Host	smart-5d8315c2-3a4f-4333-9b8a-6ac4fc5b1f24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360684509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.360684509
Directory	/workspace/18.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/18.uart_tx_rx.3245113241
Short name	T570
Test name
Test status
Simulation time	58826567302 ps
CPU time	46.25 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:56 PM PDT 24
Peak memory	200884 kb
Host	smart-e6983b5a-da3d-4aba-8141-e436fa6a1150
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245113241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3245113241
Directory	/workspace/18.uart_tx_rx/latest

Test location	/workspace/coverage/default/180.uart_fifo_reset.3627761847
Short name	T1062
Test name
Test status
Simulation time	16254796788 ps
CPU time	14.17 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:55:31 PM PDT 24
Peak memory	200780 kb
Host	smart-28d63618-b0c2-4f91-8957-00f5c7e8d367
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627761847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3627761847
Directory	/workspace/180.uart_fifo_reset/latest

Test location	/workspace/coverage/default/183.uart_fifo_reset.2406852830
Short name	T785
Test name
Test status
Simulation time	8389834163 ps
CPU time	12.71 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:55:29 PM PDT 24
Peak memory	199988 kb
Host	smart-29a6ebd6-a480-4a7c-b16a-23d61aab0b1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2406852830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2406852830
Directory	/workspace/183.uart_fifo_reset/latest

Test location	/workspace/coverage/default/184.uart_fifo_reset.1234082845
Short name	T203
Test name
Test status
Simulation time	102795238799 ps
CPU time	175.26 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:58:13 PM PDT 24
Peak memory	200876 kb
Host	smart-4cd3db71-a051-4bcb-b01a-7939a582b2cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234082845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1234082845
Directory	/workspace/184.uart_fifo_reset/latest

Test location	/workspace/coverage/default/185.uart_fifo_reset.2942108813
Short name	T590
Test name
Test status
Simulation time	24455904202 ps
CPU time	13.32 seconds
Started	Apr 15 02:55:17 PM PDT 24
Finished	Apr 15 02:55:31 PM PDT 24
Peak memory	200988 kb
Host	smart-c2c90e29-2a19-4629-92a7-599c6b8f0a97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2942108813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2942108813
Directory	/workspace/185.uart_fifo_reset/latest

Test location	/workspace/coverage/default/186.uart_fifo_reset.2988343617
Short name	T1138
Test name
Test status
Simulation time	38798765521 ps
CPU time	64.15 seconds
Started	Apr 15 02:55:16 PM PDT 24
Finished	Apr 15 02:56:21 PM PDT 24
Peak memory	200900 kb
Host	smart-24b981cf-2af9-45e9-9c34-553786685673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988343617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2988343617
Directory	/workspace/186.uart_fifo_reset/latest

Test location	/workspace/coverage/default/187.uart_fifo_reset.3457081189
Short name	T329
Test name
Test status
Simulation time	72303718297 ps
CPU time	154.58 seconds
Started	Apr 15 02:55:19 PM PDT 24
Finished	Apr 15 02:57:54 PM PDT 24
Peak memory	200884 kb
Host	smart-d115408f-d150-420d-8867-dda050d87492
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457081189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3457081189
Directory	/workspace/187.uart_fifo_reset/latest

Test location	/workspace/coverage/default/189.uart_fifo_reset.2745731192
Short name	T517
Test name
Test status
Simulation time	36985996164 ps
CPU time	62.52 seconds
Started	Apr 15 02:55:20 PM PDT 24
Finished	Apr 15 02:56:23 PM PDT 24
Peak memory	200860 kb
Host	smart-f9b1ce99-6019-408c-88e0-df829acf21b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745731192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2745731192
Directory	/workspace/189.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_alert_test.1466694874
Short name	T359
Test name
Test status
Simulation time	23509769 ps
CPU time	0.57 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:52:04 PM PDT 24
Peak memory	195680 kb
Host	smart-0e331ee4-0ec2-4b55-8425-c1c8111ac92b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466694874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1466694874
Directory	/workspace/19.uart_alert_test/latest

Test location	/workspace/coverage/default/19.uart_fifo_full.4043328364
Short name	T463
Test name
Test status
Simulation time	128047020142 ps
CPU time	17.61 seconds
Started	Apr 15 02:52:02 PM PDT 24
Finished	Apr 15 02:52:20 PM PDT 24
Peak memory	200912 kb
Host	smart-3e752216-a03a-49d5-a9bf-1b004baf16e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043328364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4043328364
Directory	/workspace/19.uart_fifo_full/latest

Test location	/workspace/coverage/default/19.uart_fifo_overflow.2242522834
Short name	T710
Test name
Test status
Simulation time	19572075670 ps
CPU time	29.75 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:38 PM PDT 24
Peak memory	200864 kb
Host	smart-cfe39a38-e688-4791-9270-a022cad48969
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242522834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2242522834
Directory	/workspace/19.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/19.uart_fifo_reset.213094546
Short name	T1060
Test name
Test status
Simulation time	52703205408 ps
CPU time	46.31 seconds
Started	Apr 15 02:51:57 PM PDT 24
Finished	Apr 15 02:52:44 PM PDT 24
Peak memory	200484 kb
Host	smart-69248b4c-76d6-445c-b484-04ca228b0a7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=213094546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.213094546
Directory	/workspace/19.uart_fifo_reset/latest

Test location	/workspace/coverage/default/19.uart_intr.1557326679
Short name	T867
Test name
Test status
Simulation time	64499340195 ps
CPU time	115.87 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	200856 kb
Host	smart-bcea56fa-33c2-4be4-8078-94a0e3f2d540
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557326679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1557326679
Directory	/workspace/19.uart_intr/latest

Test location	/workspace/coverage/default/19.uart_loopback.1146915790
Short name	T937
Test name
Test status
Simulation time	3192062041 ps
CPU time	3.48 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:13 PM PDT 24
Peak memory	199368 kb
Host	smart-ffed5a05-1980-4882-b899-5d36438950b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146915790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1146915790
Directory	/workspace/19.uart_loopback/latest

Test location	/workspace/coverage/default/19.uart_noise_filter.339474860
Short name	T125
Test name
Test status
Simulation time	22764986513 ps
CPU time	14.78 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:15 PM PDT 24
Peak memory	200368 kb
Host	smart-5b2f1a55-1dda-4ac4-9021-8787d7027549
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=339474860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.339474860
Directory	/workspace/19.uart_noise_filter/latest

Test location	/workspace/coverage/default/19.uart_perf.3001989750
Short name	T1039
Test name
Test status
Simulation time	641824823 ps
CPU time	32.14 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:42 PM PDT 24
Peak memory	200720 kb
Host	smart-f082beda-26d5-4f77-a17a-4d74cc95183a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3001989750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3001989750
Directory	/workspace/19.uart_perf/latest

Test location	/workspace/coverage/default/19.uart_rx_oversample.3190890127
Short name	T830
Test name
Test status
Simulation time	6296889711 ps
CPU time	26.7 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:36 PM PDT 24
Peak memory	200032 kb
Host	smart-97445f00-2aa5-4ce8-9565-3e89f55c3ba6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3190890127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3190890127
Directory	/workspace/19.uart_rx_oversample/latest

Test location	/workspace/coverage/default/19.uart_rx_parity_err.310458110
Short name	T812
Test name
Test status
Simulation time	13530532042 ps
CPU time	16.64 seconds
Started	Apr 15 02:51:59 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	200884 kb
Host	smart-8a088114-14b1-4c35-868f-197a9b00d3a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310458110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.310458110
Directory	/workspace/19.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/19.uart_rx_start_bit_filter.585934065
Short name	T575
Test name
Test status
Simulation time	28871779518 ps
CPU time	46.44 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	196932 kb
Host	smart-6ef044b3-e988-4172-9f42-5e947981b5cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=585934065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.585934065
Directory	/workspace/19.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/19.uart_smoke.3676945087
Short name	T360
Test name
Test status
Simulation time	312441195 ps
CPU time	1.31 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:52:08 PM PDT 24
Peak memory	199440 kb
Host	smart-66a914f0-86bf-42db-9376-a74bce0118af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676945087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3676945087
Directory	/workspace/19.uart_smoke/latest

Test location	/workspace/coverage/default/19.uart_stress_all_with_rand_reset.2496180122
Short name	T686
Test name
Test status
Simulation time	29284019680 ps
CPU time	181.34 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:55:10 PM PDT 24
Peak memory	216752 kb
Host	smart-ce8117aa-59b1-4fff-8838-36de87a5d2ee
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496180122 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2496180122
Directory	/workspace/19.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.uart_tx_ovrd.1548366626
Short name	T682
Test name
Test status
Simulation time	507627137 ps
CPU time	1.16 seconds
Started	Apr 15 02:51:57 PM PDT 24
Finished	Apr 15 02:51:59 PM PDT 24
Peak memory	197848 kb
Host	smart-bb1de0ca-2c75-4cc1-b0d7-3c857193b193
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548366626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1548366626
Directory	/workspace/19.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/19.uart_tx_rx.2547954909
Short name	T1180
Test name
Test status
Simulation time	110685158061 ps
CPU time	20.21 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	200916 kb
Host	smart-8c11e252-81aa-4143-8d25-c31955de7ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547954909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2547954909
Directory	/workspace/19.uart_tx_rx/latest

Test location	/workspace/coverage/default/191.uart_fifo_reset.137198491
Short name	T138
Test name
Test status
Simulation time	70093754816 ps
CPU time	57.56 seconds
Started	Apr 15 02:55:22 PM PDT 24
Finished	Apr 15 02:56:20 PM PDT 24
Peak memory	200840 kb
Host	smart-efe8190c-9e9f-40d9-b341-2f3817abe1c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137198491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.137198491
Directory	/workspace/191.uart_fifo_reset/latest

Test location	/workspace/coverage/default/194.uart_fifo_reset.2056979512
Short name	T216
Test name
Test status
Simulation time	60907816137 ps
CPU time	15.47 seconds
Started	Apr 15 02:55:22 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	200896 kb
Host	smart-08fab43e-a262-4a78-ac6b-2c2a918d8a8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056979512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2056979512
Directory	/workspace/194.uart_fifo_reset/latest

Test location	/workspace/coverage/default/195.uart_fifo_reset.699038051
Short name	T952
Test name
Test status
Simulation time	140174778084 ps
CPU time	66.1 seconds
Started	Apr 15 02:55:20 PM PDT 24
Finished	Apr 15 02:56:27 PM PDT 24
Peak memory	200828 kb
Host	smart-2d39d8ef-efa1-422c-8006-b4be83a001a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699038051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.699038051
Directory	/workspace/195.uart_fifo_reset/latest

Test location	/workspace/coverage/default/197.uart_fifo_reset.3695381134
Short name	T487
Test name
Test status
Simulation time	301087962772 ps
CPU time	38.82 seconds
Started	Apr 15 02:55:19 PM PDT 24
Finished	Apr 15 02:55:59 PM PDT 24
Peak memory	200912 kb
Host	smart-bd403a0e-cf61-4e3c-af66-5ebf1d2326b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695381134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3695381134
Directory	/workspace/197.uart_fifo_reset/latest

Test location	/workspace/coverage/default/198.uart_fifo_reset.1625154950
Short name	T997
Test name
Test status
Simulation time	151623123040 ps
CPU time	154.67 seconds
Started	Apr 15 02:55:19 PM PDT 24
Finished	Apr 15 02:57:55 PM PDT 24
Peak memory	200960 kb
Host	smart-3746b335-da36-4b00-a566-c1dd324308fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1625154950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1625154950
Directory	/workspace/198.uart_fifo_reset/latest

Test location	/workspace/coverage/default/199.uart_fifo_reset.1035969462
Short name	T887
Test name
Test status
Simulation time	40406441882 ps
CPU time	65.96 seconds
Started	Apr 15 02:55:22 PM PDT 24
Finished	Apr 15 02:56:29 PM PDT 24
Peak memory	200840 kb
Host	smart-e33d9a6e-af06-44f0-9fe1-9ee4bbe80140
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035969462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1035969462
Directory	/workspace/199.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_alert_test.3451530133
Short name	T56
Test name
Test status
Simulation time	42772607 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:22 PM PDT 24
Finished	Apr 15 02:51:23 PM PDT 24
Peak memory	196240 kb
Host	smart-2f3a8b8e-c77b-4758-bda5-9c5b19b4b5fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451530133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3451530133
Directory	/workspace/2.uart_alert_test/latest

Test location	/workspace/coverage/default/2.uart_fifo_full.751223728
Short name	T556
Test name
Test status
Simulation time	54655705325 ps
CPU time	17.58 seconds
Started	Apr 15 02:51:14 PM PDT 24
Finished	Apr 15 02:51:32 PM PDT 24
Peak memory	200912 kb
Host	smart-29823c72-a1aa-4fb5-aa04-0d875cb253eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751223728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.751223728
Directory	/workspace/2.uart_fifo_full/latest

Test location	/workspace/coverage/default/2.uart_fifo_overflow.3630685766
Short name	T820
Test name
Test status
Simulation time	23682714287 ps
CPU time	42.93 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:51:58 PM PDT 24
Peak memory	200848 kb
Host	smart-79fda3e4-f814-494c-b39f-818254fdfa5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630685766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3630685766
Directory	/workspace/2.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/2.uart_fifo_reset.2878575123
Short name	T505
Test name
Test status
Simulation time	123506599618 ps
CPU time	281.94 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:55:58 PM PDT 24
Peak memory	200900 kb
Host	smart-5a34bb24-9ada-488e-8f22-f13c0cb78eeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878575123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2878575123
Directory	/workspace/2.uart_fifo_reset/latest

Test location	/workspace/coverage/default/2.uart_intr.881000379
Short name	T1009
Test name
Test status
Simulation time	412890645356 ps
CPU time	702.61 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 03:03:00 PM PDT 24
Peak memory	199728 kb
Host	smart-a93b3b13-ba2f-4ae3-b373-9c01c3397209
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881000379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.881000379
Directory	/workspace/2.uart_intr/latest

Test location	/workspace/coverage/default/2.uart_long_xfer_wo_dly.2053437969
Short name	T488
Test name
Test status
Simulation time	144964831488 ps
CPU time	224.1 seconds
Started	Apr 15 02:51:21 PM PDT 24
Finished	Apr 15 02:55:06 PM PDT 24
Peak memory	200880 kb
Host	smart-b05bf90a-35ac-4dc4-9fa5-257806790869
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2053437969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2053437969
Directory	/workspace/2.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/2.uart_loopback.2130973945
Short name	T978
Test name
Test status
Simulation time	1202940708 ps
CPU time	3.56 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	199536 kb
Host	smart-b7606435-73d0-4d4b-b738-fbdc41915479
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2130973945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2130973945
Directory	/workspace/2.uart_loopback/latest

Test location	/workspace/coverage/default/2.uart_noise_filter.3040814884
Short name	T45
Test name
Test status
Simulation time	26785587762 ps
CPU time	50.7 seconds
Started	Apr 15 02:51:29 PM PDT 24
Finished	Apr 15 02:52:20 PM PDT 24
Peak memory	199516 kb
Host	smart-b704d99b-becc-447f-984b-517a0635bbe5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040814884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3040814884
Directory	/workspace/2.uart_noise_filter/latest

Test location	/workspace/coverage/default/2.uart_perf.798672492
Short name	T504
Test name
Test status
Simulation time	10765380774 ps
CPU time	164.72 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:54:09 PM PDT 24
Peak memory	200840 kb
Host	smart-92126535-aaae-40c9-ae0c-a0933b978715
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=798672492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.798672492
Directory	/workspace/2.uart_perf/latest

Test location	/workspace/coverage/default/2.uart_rx_oversample.3324150285
Short name	T1123
Test name
Test status
Simulation time	5314957949 ps
CPU time	10.11 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:51:26 PM PDT 24
Peak memory	199012 kb
Host	smart-c5b146c7-9bd4-4a9d-996c-63be1e281b68
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3324150285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3324150285
Directory	/workspace/2.uart_rx_oversample/latest

Test location	/workspace/coverage/default/2.uart_rx_parity_err.1483059062
Short name	T268
Test name
Test status
Simulation time	25795280318 ps
CPU time	42.47 seconds
Started	Apr 15 02:51:19 PM PDT 24
Finished	Apr 15 02:52:02 PM PDT 24
Peak memory	200784 kb
Host	smart-35e01fa0-e4c6-46a2-9339-31b735d003d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483059062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1483059062
Directory	/workspace/2.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/2.uart_rx_start_bit_filter.267915833
Short name	T525
Test name
Test status
Simulation time	3297837127 ps
CPU time	1.83 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:32 PM PDT 24
Peak memory	196700 kb
Host	smart-aea50d5b-ad1f-40fa-86bd-e07d4aaef989
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267915833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.267915833
Directory	/workspace/2.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/2.uart_sec_cm.4255921377
Short name	T96
Test name
Test status
Simulation time	283507315 ps
CPU time	0.87 seconds
Started	Apr 15 02:51:19 PM PDT 24
Finished	Apr 15 02:51:20 PM PDT 24
Peak memory	218932 kb
Host	smart-6ea595a3-ab4f-49e8-b102-47efe9e1df93
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255921377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4255921377
Directory	/workspace/2.uart_sec_cm/latest

Test location	/workspace/coverage/default/2.uart_smoke.2291398477
Short name	T1042
Test name
Test status
Simulation time	708428120 ps
CPU time	1.73 seconds
Started	Apr 15 02:51:19 PM PDT 24
Finished	Apr 15 02:51:21 PM PDT 24
Peak memory	199620 kb
Host	smart-8dee5b3d-ebc8-472c-b2f5-1d09105a10d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2291398477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2291398477
Directory	/workspace/2.uart_smoke/latest

Test location	/workspace/coverage/default/2.uart_stress_all.121930569
Short name	T798
Test name
Test status
Simulation time	165348568696 ps
CPU time	59.96 seconds
Started	Apr 15 02:51:21 PM PDT 24
Finished	Apr 15 02:52:21 PM PDT 24
Peak memory	200848 kb
Host	smart-c1a66e42-a1b1-4b3a-97c9-6c307a5c65d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121930569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.121930569
Directory	/workspace/2.uart_stress_all/latest

Test location	/workspace/coverage/default/2.uart_stress_all_with_rand_reset.354357389
Short name	T847
Test name
Test status
Simulation time	377033724020 ps
CPU time	659.89 seconds
Started	Apr 15 02:51:23 PM PDT 24
Finished	Apr 15 03:02:24 PM PDT 24
Peak memory	214984 kb
Host	smart-55442479-17ce-4f3d-a119-a0e18475c899
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354357389 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.354357389
Directory	/workspace/2.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.uart_tx_ovrd.2789428630
Short name	T1137
Test name
Test status
Simulation time	1392675280 ps
CPU time	3.88 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:51:50 PM PDT 24
Peak memory	199920 kb
Host	smart-436f10d5-d3cd-4c1e-8e3c-17edf3060ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789428630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2789428630
Directory	/workspace/2.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/2.uart_tx_rx.1986271803
Short name	T929
Test name
Test status
Simulation time	33049597676 ps
CPU time	49.69 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:52:14 PM PDT 24
Peak memory	201036 kb
Host	smart-4aaab546-089c-486c-8c72-94c09fc87ed1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986271803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1986271803
Directory	/workspace/2.uart_tx_rx/latest

Test location	/workspace/coverage/default/20.uart_alert_test.2819796202
Short name	T902
Test name
Test status
Simulation time	35589230 ps
CPU time	0.57 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:52:06 PM PDT 24
Peak memory	196232 kb
Host	smart-cc6abb02-6370-4e25-9732-20c7e9ea7ef2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819796202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2819796202
Directory	/workspace/20.uart_alert_test/latest

Test location	/workspace/coverage/default/20.uart_fifo_full.2885354477
Short name	T779
Test name
Test status
Simulation time	182654629943 ps
CPU time	572.03 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 03:01:33 PM PDT 24
Peak memory	200916 kb
Host	smart-602bf431-7d38-4928-8546-9fc4d97d88d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2885354477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2885354477
Directory	/workspace/20.uart_fifo_full/latest

Test location	/workspace/coverage/default/20.uart_fifo_overflow.1873233696
Short name	T877
Test name
Test status
Simulation time	122870978806 ps
CPU time	25.49 seconds
Started	Apr 15 02:52:04 PM PDT 24
Finished	Apr 15 02:52:30 PM PDT 24
Peak memory	200828 kb
Host	smart-da151fe0-ca7f-493a-a272-ee6131363956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873233696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1873233696
Directory	/workspace/20.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/20.uart_fifo_reset.1623130748
Short name	T784
Test name
Test status
Simulation time	10481949694 ps
CPU time	15.55 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:23 PM PDT 24
Peak memory	200864 kb
Host	smart-2a035b3c-138b-4dce-bf89-27d337cac266
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623130748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1623130748
Directory	/workspace/20.uart_fifo_reset/latest

Test location	/workspace/coverage/default/20.uart_intr.1187400723
Short name	T630
Test name
Test status
Simulation time	60505910419 ps
CPU time	107.86 seconds
Started	Apr 15 02:52:00 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	200912 kb
Host	smart-10035d4e-efa5-40a5-a15f-8919b3a4e976
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187400723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1187400723
Directory	/workspace/20.uart_intr/latest

Test location	/workspace/coverage/default/20.uart_long_xfer_wo_dly.3240596018
Short name	T1119
Test name
Test status
Simulation time	110070835577 ps
CPU time	330.67 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:57:39 PM PDT 24
Peak memory	200804 kb
Host	smart-7df61dc8-b2e1-4b7f-bcd9-fb04188ea615
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3240596018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3240596018
Directory	/workspace/20.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/20.uart_loopback.1989631260
Short name	T852
Test name
Test status
Simulation time	1055884930 ps
CPU time	1.02 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:52:09 PM PDT 24
Peak memory	196856 kb
Host	smart-2f0f5eb0-f53e-4784-8af2-2cfd4a539e1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989631260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1989631260
Directory	/workspace/20.uart_loopback/latest

Test location	/workspace/coverage/default/20.uart_noise_filter.2759300064
Short name	T21
Test name
Test status
Simulation time	84128772216 ps
CPU time	43.43 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:57 PM PDT 24
Peak memory	217248 kb
Host	smart-6828bda5-6cf5-4095-b4f8-6b0f0f573b13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759300064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2759300064
Directory	/workspace/20.uart_noise_filter/latest

Test location	/workspace/coverage/default/20.uart_perf.3798010586
Short name	T676
Test name
Test status
Simulation time	21295835034 ps
CPU time	550.64 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 03:01:20 PM PDT 24
Peak memory	200920 kb
Host	smart-67f1fb4c-a54d-41db-ad58-bc81bde91829
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3798010586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3798010586
Directory	/workspace/20.uart_perf/latest

Test location	/workspace/coverage/default/20.uart_rx_oversample.2849681462
Short name	T939
Test name
Test status
Simulation time	3588296553 ps
CPU time	4.76 seconds
Started	Apr 15 02:51:56 PM PDT 24
Finished	Apr 15 02:52:02 PM PDT 24
Peak memory	199092 kb
Host	smart-34389a93-80dd-456d-8e80-d0a4e51dcafb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2849681462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2849681462
Directory	/workspace/20.uart_rx_oversample/latest

Test location	/workspace/coverage/default/20.uart_rx_parity_err.1040491863
Short name	T933
Test name
Test status
Simulation time	118195397315 ps
CPU time	55.48 seconds
Started	Apr 15 02:52:11 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	200792 kb
Host	smart-0b3c7c09-1f6d-4ca7-9f34-af01387736f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040491863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1040491863
Directory	/workspace/20.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/20.uart_rx_start_bit_filter.2147115336
Short name	T788
Test name
Test status
Simulation time	4898994547 ps
CPU time	1.03 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:52:08 PM PDT 24
Peak memory	196912 kb
Host	smart-0212b10d-128b-463c-a4ec-5fae63db04b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147115336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2147115336
Directory	/workspace/20.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/20.uart_smoke.3418407046
Short name	T443
Test name
Test status
Simulation time	6286603847 ps
CPU time	16.9 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:26 PM PDT 24
Peak memory	200812 kb
Host	smart-a7b215d7-e8a4-4238-87ce-f89a37d3a767
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418407046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3418407046
Directory	/workspace/20.uart_smoke/latest

Test location	/workspace/coverage/default/20.uart_stress_all.4243617529
Short name	T610
Test name
Test status
Simulation time	231041037393 ps
CPU time	222.64 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:55:52 PM PDT 24
Peak memory	200888 kb
Host	smart-943e299f-7f06-4a25-9e26-e9f294d3e28b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243617529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4243617529
Directory	/workspace/20.uart_stress_all/latest

Test location	/workspace/coverage/default/20.uart_stress_all_with_rand_reset.1569395789
Short name	T688
Test name
Test status
Simulation time	168436912229 ps
CPU time	415.26 seconds
Started	Apr 15 02:52:12 PM PDT 24
Finished	Apr 15 02:59:08 PM PDT 24
Peak memory	217524 kb
Host	smart-f480db00-0d21-43fb-bb4a-253e9f69ad20
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569395789 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1569395789
Directory	/workspace/20.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.uart_tx_ovrd.1435517992
Short name	T431
Test name
Test status
Simulation time	987746971 ps
CPU time	3.21 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:52:07 PM PDT 24
Peak memory	200224 kb
Host	smart-e2dcaec2-371e-4498-a97d-267736e863f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435517992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1435517992
Directory	/workspace/20.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/20.uart_tx_rx.2489580836
Short name	T1091
Test name
Test status
Simulation time	20611557408 ps
CPU time	41.52 seconds
Started	Apr 15 02:52:10 PM PDT 24
Finished	Apr 15 02:52:52 PM PDT 24
Peak memory	200172 kb
Host	smart-c293a3b7-ce0d-4fb3-b9e4-fc60b803de70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489580836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2489580836
Directory	/workspace/20.uart_tx_rx/latest

Test location	/workspace/coverage/default/200.uart_fifo_reset.1185031572
Short name	T1105
Test name
Test status
Simulation time	99767133032 ps
CPU time	174.45 seconds
Started	Apr 15 02:55:23 PM PDT 24
Finished	Apr 15 02:58:18 PM PDT 24
Peak memory	200920 kb
Host	smart-ac745fb7-d99b-45b2-b8a0-23351cac1589
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185031572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1185031572
Directory	/workspace/200.uart_fifo_reset/latest

Test location	/workspace/coverage/default/201.uart_fifo_reset.2736516135
Short name	T856
Test name
Test status
Simulation time	4908560609 ps
CPU time	18.23 seconds
Started	Apr 15 02:55:23 PM PDT 24
Finished	Apr 15 02:55:42 PM PDT 24
Peak memory	200844 kb
Host	smart-cda0b151-9909-43f9-b26d-39cc2c3f600d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736516135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2736516135
Directory	/workspace/201.uart_fifo_reset/latest

Test location	/workspace/coverage/default/202.uart_fifo_reset.1348751291
Short name	T811
Test name
Test status
Simulation time	95768952468 ps
CPU time	161.35 seconds
Started	Apr 15 02:55:23 PM PDT 24
Finished	Apr 15 02:58:05 PM PDT 24
Peak memory	200592 kb
Host	smart-f9111ed0-7abe-4314-9ca8-409e5a24008e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348751291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1348751291
Directory	/workspace/202.uart_fifo_reset/latest

Test location	/workspace/coverage/default/203.uart_fifo_reset.1227577130
Short name	T815
Test name
Test status
Simulation time	187733577411 ps
CPU time	298.17 seconds
Started	Apr 15 02:55:24 PM PDT 24
Finished	Apr 15 03:00:23 PM PDT 24
Peak memory	200892 kb
Host	smart-5c50fe2b-de21-4250-ba3d-77c1e5468d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227577130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1227577130
Directory	/workspace/203.uart_fifo_reset/latest

Test location	/workspace/coverage/default/204.uart_fifo_reset.592889443
Short name	T116
Test name
Test status
Simulation time	247532088909 ps
CPU time	108.25 seconds
Started	Apr 15 02:55:22 PM PDT 24
Finished	Apr 15 02:57:12 PM PDT 24
Peak memory	200712 kb
Host	smart-b556d734-3270-4340-9a72-c13f791b4617
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592889443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.592889443
Directory	/workspace/204.uart_fifo_reset/latest

Test location	/workspace/coverage/default/206.uart_fifo_reset.1651522307
Short name	T814
Test name
Test status
Simulation time	72700415764 ps
CPU time	130.66 seconds
Started	Apr 15 02:55:27 PM PDT 24
Finished	Apr 15 02:57:38 PM PDT 24
Peak memory	200928 kb
Host	smart-50c95e39-9163-41a4-ba5e-1d0d00f82edf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651522307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1651522307
Directory	/workspace/206.uart_fifo_reset/latest

Test location	/workspace/coverage/default/207.uart_fifo_reset.380284444
Short name	T971
Test name
Test status
Simulation time	10562124989 ps
CPU time	19.21 seconds
Started	Apr 15 02:55:26 PM PDT 24
Finished	Apr 15 02:55:46 PM PDT 24
Peak memory	200400 kb
Host	smart-3d105499-5bd9-45e3-bb25-3ac7f746a016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380284444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.380284444
Directory	/workspace/207.uart_fifo_reset/latest

Test location	/workspace/coverage/default/208.uart_fifo_reset.2221585475
Short name	T454
Test name
Test status
Simulation time	52634702739 ps
CPU time	33.36 seconds
Started	Apr 15 02:55:28 PM PDT 24
Finished	Apr 15 02:56:02 PM PDT 24
Peak memory	200816 kb
Host	smart-3b6221a2-8626-4aac-b276-dd9691747358
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221585475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2221585475
Directory	/workspace/208.uart_fifo_reset/latest

Test location	/workspace/coverage/default/209.uart_fifo_reset.4207521727
Short name	T910
Test name
Test status
Simulation time	13097824673 ps
CPU time	26.86 seconds
Started	Apr 15 02:55:29 PM PDT 24
Finished	Apr 15 02:55:57 PM PDT 24
Peak memory	200792 kb
Host	smart-79af4c2f-aefa-479f-8a28-a05bda87e2b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4207521727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4207521727
Directory	/workspace/209.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_alert_test.2997655941
Short name	T974
Test name
Test status
Simulation time	12235574 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 02:52:11 PM PDT 24
Peak memory	196196 kb
Host	smart-69ddeef2-9216-4040-8795-6724009405ae
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997655941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2997655941
Directory	/workspace/21.uart_alert_test/latest

Test location	/workspace/coverage/default/21.uart_fifo_overflow.1284287285
Short name	T444
Test name
Test status
Simulation time	117887530958 ps
CPU time	178.45 seconds
Started	Apr 15 02:52:03 PM PDT 24
Finished	Apr 15 02:55:02 PM PDT 24
Peak memory	200688 kb
Host	smart-f473ef72-bdb8-406f-ace4-98a720c5dc4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284287285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1284287285
Directory	/workspace/21.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/21.uart_fifo_reset.1682485549
Short name	T548
Test name
Test status
Simulation time	14308006609 ps
CPU time	13.06 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200920 kb
Host	smart-1e3b4a82-b5a6-4e19-bd30-4768f4a7b27e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682485549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1682485549
Directory	/workspace/21.uart_fifo_reset/latest

Test location	/workspace/coverage/default/21.uart_intr.2897724768
Short name	T12
Test name
Test status
Simulation time	15481841510 ps
CPU time	14.59 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 02:52:25 PM PDT 24
Peak memory	199112 kb
Host	smart-1a74f350-88bf-4a81-9d79-3d70306b8a64
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897724768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2897724768
Directory	/workspace/21.uart_intr/latest

Test location	/workspace/coverage/default/21.uart_long_xfer_wo_dly.1382902493
Short name	T393
Test name
Test status
Simulation time	183441282106 ps
CPU time	1817.09 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 03:22:25 PM PDT 24
Peak memory	200912 kb
Host	smart-4d8e5308-90f7-426d-87c5-edc83a599d1b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1382902493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1382902493
Directory	/workspace/21.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/21.uart_loopback.2144059354
Short name	T868
Test name
Test status
Simulation time	6385700525 ps
CPU time	2.48 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:52:11 PM PDT 24
Peak memory	199128 kb
Host	smart-8ede6556-855c-4e25-9f11-07cf76187559
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144059354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2144059354
Directory	/workspace/21.uart_loopback/latest

Test location	/workspace/coverage/default/21.uart_noise_filter.1712333276
Short name	T1117
Test name
Test status
Simulation time	92337755731 ps
CPU time	57.54 seconds
Started	Apr 15 02:52:10 PM PDT 24
Finished	Apr 15 02:53:09 PM PDT 24
Peak memory	200044 kb
Host	smart-27ac2e91-f6da-40d1-a97e-6b8957477764
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712333276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1712333276
Directory	/workspace/21.uart_noise_filter/latest

Test location	/workspace/coverage/default/21.uart_perf.617806832
Short name	T672
Test name
Test status
Simulation time	11272731562 ps
CPU time	576.18 seconds
Started	Apr 15 02:52:10 PM PDT 24
Finished	Apr 15 03:01:47 PM PDT 24
Peak memory	200880 kb
Host	smart-365bb8f0-861c-4b01-817d-74f10e7cb8f2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=617806832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.617806832
Directory	/workspace/21.uart_perf/latest

Test location	/workspace/coverage/default/21.uart_rx_oversample.3637783132
Short name	T456
Test name
Test status
Simulation time	3168581173 ps
CPU time	17.12 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	198964 kb
Host	smart-0cb83cb3-3e4d-4e5a-b26d-2f5ffb2eb6a7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3637783132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3637783132
Directory	/workspace/21.uart_rx_oversample/latest

Test location	/workspace/coverage/default/21.uart_rx_parity_err.1723181595
Short name	T732
Test name
Test status
Simulation time	92384214391 ps
CPU time	159.61 seconds
Started	Apr 15 02:52:06 PM PDT 24
Finished	Apr 15 02:54:47 PM PDT 24
Peak memory	200884 kb
Host	smart-e57845f9-d0b7-4c46-ae2d-45d1aa268473
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723181595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1723181595
Directory	/workspace/21.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/21.uart_rx_start_bit_filter.3817541744
Short name	T5
Test name
Test status
Simulation time	4652706240 ps
CPU time	8.79 seconds
Started	Apr 15 02:52:10 PM PDT 24
Finished	Apr 15 02:52:20 PM PDT 24
Peak memory	196132 kb
Host	smart-fe93f794-3283-43a9-a4dd-bc9b33675b7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817541744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3817541744
Directory	/workspace/21.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/21.uart_smoke.1272845075
Short name	T1102
Test name
Test status
Simulation time	6217476896 ps
CPU time	9.62 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:52:16 PM PDT 24
Peak memory	200824 kb
Host	smart-5e1caad3-7562-4675-8f97-639b9f69e7da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272845075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1272845075
Directory	/workspace/21.uart_smoke/latest

Test location	/workspace/coverage/default/21.uart_stress_all.2329160667
Short name	T264
Test name
Test status
Simulation time	7984732105 ps
CPU time	14.01 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:52:24 PM PDT 24
Peak memory	200900 kb
Host	smart-fce8e61d-b9f6-455d-a0d9-32d0ecd8f4eb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329160667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2329160667
Directory	/workspace/21.uart_stress_all/latest

Test location	/workspace/coverage/default/21.uart_stress_all_with_rand_reset.3005435587
Short name	T748
Test name
Test status
Simulation time	59964457992 ps
CPU time	514.87 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 03:00:45 PM PDT 24
Peak memory	217716 kb
Host	smart-149cb605-4920-4cd4-853f-9805171f88b6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005435587 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3005435587
Directory	/workspace/21.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.uart_tx_ovrd.948065971
Short name	T320
Test name
Test status
Simulation time	6618832265 ps
CPU time	17.23 seconds
Started	Apr 15 02:52:05 PM PDT 24
Finished	Apr 15 02:52:23 PM PDT 24
Peak memory	200920 kb
Host	smart-ecd0e118-0b92-4a1a-9d1e-0982c7352b19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948065971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.948065971
Directory	/workspace/21.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/21.uart_tx_rx.2749354803
Short name	T482
Test name
Test status
Simulation time	135557492622 ps
CPU time	53.39 seconds
Started	Apr 15 02:52:07 PM PDT 24
Finished	Apr 15 02:53:02 PM PDT 24
Peak memory	200788 kb
Host	smart-2ed9d20c-653d-4f55-a24f-e931e91aa6a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749354803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2749354803
Directory	/workspace/21.uart_tx_rx/latest

Test location	/workspace/coverage/default/210.uart_fifo_reset.3021401841
Short name	T399
Test name
Test status
Simulation time	55304678560 ps
CPU time	23.67 seconds
Started	Apr 15 02:55:28 PM PDT 24
Finished	Apr 15 02:55:52 PM PDT 24
Peak memory	200912 kb
Host	smart-dfddd584-2f78-4ecb-9fe4-3a3889056e34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021401841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3021401841
Directory	/workspace/210.uart_fifo_reset/latest

Test location	/workspace/coverage/default/211.uart_fifo_reset.3542879297
Short name	T843
Test name
Test status
Simulation time	124077089000 ps
CPU time	52.97 seconds
Started	Apr 15 02:55:29 PM PDT 24
Finished	Apr 15 02:56:22 PM PDT 24
Peak memory	200912 kb
Host	smart-7e78ecf7-7fa6-4773-9550-23bcd8c2c7b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542879297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3542879297
Directory	/workspace/211.uart_fifo_reset/latest

Test location	/workspace/coverage/default/212.uart_fifo_reset.1452163403
Short name	T98
Test name
Test status
Simulation time	23434757031 ps
CPU time	39.4 seconds
Started	Apr 15 02:55:29 PM PDT 24
Finished	Apr 15 02:56:09 PM PDT 24
Peak memory	200864 kb
Host	smart-2e0344f1-c783-4edc-8e7e-05b41b4869c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452163403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1452163403
Directory	/workspace/212.uart_fifo_reset/latest

Test location	/workspace/coverage/default/213.uart_fifo_reset.296003592
Short name	T661
Test name
Test status
Simulation time	18607675181 ps
CPU time	28.63 seconds
Started	Apr 15 02:55:27 PM PDT 24
Finished	Apr 15 02:55:56 PM PDT 24
Peak memory	200852 kb
Host	smart-31ffd9e6-e148-4618-8493-abb71a4a70c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296003592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.296003592
Directory	/workspace/213.uart_fifo_reset/latest

Test location	/workspace/coverage/default/214.uart_fifo_reset.4165546099
Short name	T1115
Test name
Test status
Simulation time	32538524706 ps
CPU time	28.02 seconds
Started	Apr 15 02:55:28 PM PDT 24
Finished	Apr 15 02:55:56 PM PDT 24
Peak memory	200768 kb
Host	smart-a2b74d74-6498-4337-b3f3-e75345fb2d92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165546099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4165546099
Directory	/workspace/214.uart_fifo_reset/latest

Test location	/workspace/coverage/default/215.uart_fifo_reset.1495642326
Short name	T499
Test name
Test status
Simulation time	13215076668 ps
CPU time	14.86 seconds
Started	Apr 15 02:55:31 PM PDT 24
Finished	Apr 15 02:55:47 PM PDT 24
Peak memory	200652 kb
Host	smart-cc18f294-a5b6-4c07-8722-9c418a2dd47f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495642326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1495642326
Directory	/workspace/215.uart_fifo_reset/latest

Test location	/workspace/coverage/default/216.uart_fifo_reset.1321204673
Short name	T46
Test name
Test status
Simulation time	217665395080 ps
CPU time	37.49 seconds
Started	Apr 15 02:55:30 PM PDT 24
Finished	Apr 15 02:56:08 PM PDT 24
Peak memory	200860 kb
Host	smart-c3f11565-820a-4145-97c8-063211453bdf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321204673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1321204673
Directory	/workspace/216.uart_fifo_reset/latest

Test location	/workspace/coverage/default/217.uart_fifo_reset.4004739565
Short name	T341
Test name
Test status
Simulation time	25855055987 ps
CPU time	21.57 seconds
Started	Apr 15 02:55:29 PM PDT 24
Finished	Apr 15 02:55:52 PM PDT 24
Peak memory	199588 kb
Host	smart-e40d59c6-b16a-4a5b-b075-7707f88d003f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004739565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.4004739565
Directory	/workspace/217.uart_fifo_reset/latest

Test location	/workspace/coverage/default/218.uart_fifo_reset.1280697310
Short name	T825
Test name
Test status
Simulation time	28389977062 ps
CPU time	46.92 seconds
Started	Apr 15 02:55:33 PM PDT 24
Finished	Apr 15 02:56:20 PM PDT 24
Peak memory	200908 kb
Host	smart-1c2a60d7-887d-4e13-8bb7-4debacb2c2c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280697310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1280697310
Directory	/workspace/218.uart_fifo_reset/latest

Test location	/workspace/coverage/default/219.uart_fifo_reset.3711500856
Short name	T1003
Test name
Test status
Simulation time	111653198724 ps
CPU time	67.43 seconds
Started	Apr 15 02:55:35 PM PDT 24
Finished	Apr 15 02:56:43 PM PDT 24
Peak memory	200864 kb
Host	smart-a0c8abf0-e8c6-4db3-a4f6-f1a5cfd45245
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711500856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3711500856
Directory	/workspace/219.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_alert_test.2567531308
Short name	T560
Test name
Test status
Simulation time	45143821 ps
CPU time	0.58 seconds
Started	Apr 15 02:52:16 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	196228 kb
Host	smart-f0e43308-eb79-46c1-8cf0-b01648f9cc8b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567531308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2567531308
Directory	/workspace/22.uart_alert_test/latest

Test location	/workspace/coverage/default/22.uart_fifo_full.4280508321
Short name	T554
Test name
Test status
Simulation time	46131975577 ps
CPU time	9.49 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:52:29 PM PDT 24
Peak memory	200904 kb
Host	smart-83000e78-c0cf-4890-beb9-60d27d9d46b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280508321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4280508321
Directory	/workspace/22.uart_fifo_full/latest

Test location	/workspace/coverage/default/22.uart_fifo_overflow.3490464191
Short name	T1046
Test name
Test status
Simulation time	126229220917 ps
CPU time	219.41 seconds
Started	Apr 15 02:52:08 PM PDT 24
Finished	Apr 15 02:55:49 PM PDT 24
Peak memory	200824 kb
Host	smart-24a92d51-3052-4288-add7-a4886248275b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490464191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3490464191
Directory	/workspace/22.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/22.uart_fifo_reset.4022333765
Short name	T260
Test name
Test status
Simulation time	167998182869 ps
CPU time	47.47 seconds
Started	Apr 15 02:52:11 PM PDT 24
Finished	Apr 15 02:52:59 PM PDT 24
Peak memory	200852 kb
Host	smart-a2b67f08-3a9a-4631-9df7-e3f7c0b9144a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022333765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4022333765
Directory	/workspace/22.uart_fifo_reset/latest

Test location	/workspace/coverage/default/22.uart_intr.4288256308
Short name	T925
Test name
Test status
Simulation time	64381982888 ps
CPU time	29.35 seconds
Started	Apr 15 02:52:09 PM PDT 24
Finished	Apr 15 02:52:40 PM PDT 24
Peak memory	200884 kb
Host	smart-2782f588-673d-4e6a-b62c-a9d4fc5affcb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288256308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4288256308
Directory	/workspace/22.uart_intr/latest

Test location	/workspace/coverage/default/22.uart_long_xfer_wo_dly.2873084661
Short name	T743
Test name
Test status
Simulation time	91728955447 ps
CPU time	232.77 seconds
Started	Apr 15 02:52:15 PM PDT 24
Finished	Apr 15 02:56:08 PM PDT 24
Peak memory	200852 kb
Host	smart-7e0217f3-ea99-4b6f-ad0e-3c0809ea755f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2873084661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2873084661
Directory	/workspace/22.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/22.uart_loopback.3277238312
Short name	T507
Test name
Test status
Simulation time	2153476862 ps
CPU time	2.83 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:52:21 PM PDT 24
Peak memory	198808 kb
Host	smart-1baa8d65-fc6e-4dcb-baec-b8923763df6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3277238312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3277238312
Directory	/workspace/22.uart_loopback/latest

Test location	/workspace/coverage/default/22.uart_noise_filter.1666374856
Short name	T287
Test name
Test status
Simulation time	415634978 ps
CPU time	1.01 seconds
Started	Apr 15 02:52:16 PM PDT 24
Finished	Apr 15 02:52:17 PM PDT 24
Peak memory	195656 kb
Host	smart-fd54d298-c4db-4129-8b7c-7d9557263968
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666374856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1666374856
Directory	/workspace/22.uart_noise_filter/latest

Test location	/workspace/coverage/default/22.uart_perf.3202519487
Short name	T465
Test name
Test status
Simulation time	24678762488 ps
CPU time	190.07 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:55:29 PM PDT 24
Peak memory	200916 kb
Host	smart-3d21a60c-6ccd-4f54-b4e0-f3f63767730b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3202519487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3202519487
Directory	/workspace/22.uart_perf/latest

Test location	/workspace/coverage/default/22.uart_rx_oversample.2628238255
Short name	T475
Test name
Test status
Simulation time	5359591744 ps
CPU time	12.77 seconds
Started	Apr 15 02:52:14 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	198984 kb
Host	smart-e6fe72e2-a2f0-4dfd-b1ee-770dde3457a5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2628238255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2628238255
Directory	/workspace/22.uart_rx_oversample/latest

Test location	/workspace/coverage/default/22.uart_rx_parity_err.2407281067
Short name	T777
Test name
Test status
Simulation time	45254046526 ps
CPU time	67.34 seconds
Started	Apr 15 02:52:11 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	200924 kb
Host	smart-edbda3a4-15d0-4556-afbf-76a17e8dbd9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407281067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2407281067
Directory	/workspace/22.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/22.uart_rx_start_bit_filter.3976832808
Short name	T718
Test name
Test status
Simulation time	4880941193 ps
CPU time	9.14 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	196804 kb
Host	smart-5f2f08be-c4e8-4ff0-8dda-3c182c2c8431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976832808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3976832808
Directory	/workspace/22.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/22.uart_smoke.811133508
Short name	T776
Test name
Test status
Simulation time	497472601 ps
CPU time	2.13 seconds
Started	Apr 15 02:52:10 PM PDT 24
Finished	Apr 15 02:52:13 PM PDT 24
Peak memory	200460 kb
Host	smart-c9f8f6a6-c60b-4c66-a369-5e6821b5a463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811133508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.811133508
Directory	/workspace/22.uart_smoke/latest

Test location	/workspace/coverage/default/22.uart_stress_all_with_rand_reset.933881896
Short name	T906
Test name
Test status
Simulation time	228019634997 ps
CPU time	902.81 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 03:07:16 PM PDT 24
Peak memory	225692 kb
Host	smart-9dcebcd6-2296-4616-adfe-c502ef09be28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933881896 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.933881896
Directory	/workspace/22.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.uart_tx_ovrd.1064478145
Short name	T479
Test name
Test status
Simulation time	805056503 ps
CPU time	1.59 seconds
Started	Apr 15 02:52:14 PM PDT 24
Finished	Apr 15 02:52:16 PM PDT 24
Peak memory	199936 kb
Host	smart-3c5923ec-a91a-43c0-beee-7df27746a365
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1064478145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1064478145
Directory	/workspace/22.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/22.uart_tx_rx.2543512995
Short name	T366
Test name
Test status
Simulation time	12415739307 ps
CPU time	19.21 seconds
Started	Apr 15 02:52:14 PM PDT 24
Finished	Apr 15 02:52:34 PM PDT 24
Peak memory	200852 kb
Host	smart-be9d8961-7a20-4d2f-a3f6-0b47fb92c27b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543512995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2543512995
Directory	/workspace/22.uart_tx_rx/latest

Test location	/workspace/coverage/default/220.uart_fifo_reset.1133184767
Short name	T282
Test name
Test status
Simulation time	76452340344 ps
CPU time	32.58 seconds
Started	Apr 15 02:55:30 PM PDT 24
Finished	Apr 15 02:56:03 PM PDT 24
Peak memory	200892 kb
Host	smart-a8a56e1d-c867-4153-8a2a-d970b761e5f8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133184767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1133184767
Directory	/workspace/220.uart_fifo_reset/latest

Test location	/workspace/coverage/default/222.uart_fifo_reset.1637447709
Short name	T740
Test name
Test status
Simulation time	148515506315 ps
CPU time	201.77 seconds
Started	Apr 15 02:55:30 PM PDT 24
Finished	Apr 15 02:58:52 PM PDT 24
Peak memory	200928 kb
Host	smart-5bef1cdf-fdff-4a12-9757-d5bc3010dab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637447709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1637447709
Directory	/workspace/222.uart_fifo_reset/latest

Test location	/workspace/coverage/default/223.uart_fifo_reset.3050818848
Short name	T348
Test name
Test status
Simulation time	126731301509 ps
CPU time	83.81 seconds
Started	Apr 15 02:55:32 PM PDT 24
Finished	Apr 15 02:56:56 PM PDT 24
Peak memory	200924 kb
Host	smart-a95db1d7-8ecd-4cbe-baa5-afd0de4ac6a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050818848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3050818848
Directory	/workspace/223.uart_fifo_reset/latest

Test location	/workspace/coverage/default/225.uart_fifo_reset.3560747148
Short name	T1164
Test name
Test status
Simulation time	94735518696 ps
CPU time	42.47 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:56:19 PM PDT 24
Peak memory	200924 kb
Host	smart-5ba5b84e-5a20-4d44-9d50-9be0dcf1b800
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560747148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3560747148
Directory	/workspace/225.uart_fifo_reset/latest

Test location	/workspace/coverage/default/226.uart_fifo_reset.574919718
Short name	T1041
Test name
Test status
Simulation time	12837631815 ps
CPU time	22.83 seconds
Started	Apr 15 02:55:37 PM PDT 24
Finished	Apr 15 02:56:01 PM PDT 24
Peak memory	200860 kb
Host	smart-a9f07181-515e-4dbe-8b33-671b0ef5781b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574919718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.574919718
Directory	/workspace/226.uart_fifo_reset/latest

Test location	/workspace/coverage/default/227.uart_fifo_reset.2071007611
Short name	T1076
Test name
Test status
Simulation time	121628589879 ps
CPU time	99.83 seconds
Started	Apr 15 02:55:39 PM PDT 24
Finished	Apr 15 02:57:19 PM PDT 24
Peak memory	200620 kb
Host	smart-47fdea24-217d-4437-ab6c-e2fd82dbb049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071007611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2071007611
Directory	/workspace/227.uart_fifo_reset/latest

Test location	/workspace/coverage/default/228.uart_fifo_reset.1322352587
Short name	T523
Test name
Test status
Simulation time	190561367456 ps
CPU time	43.71 seconds
Started	Apr 15 02:55:35 PM PDT 24
Finished	Apr 15 02:56:19 PM PDT 24
Peak memory	200888 kb
Host	smart-cda71455-4480-400d-84c8-ff25f5854f87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322352587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1322352587
Directory	/workspace/228.uart_fifo_reset/latest

Test location	/workspace/coverage/default/229.uart_fifo_reset.3615429408
Short name	T946
Test name
Test status
Simulation time	227105958009 ps
CPU time	48.03 seconds
Started	Apr 15 02:55:33 PM PDT 24
Finished	Apr 15 02:56:21 PM PDT 24
Peak memory	200776 kb
Host	smart-bbe4e812-26cf-4c44-b77d-f9c9da0c89ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615429408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3615429408
Directory	/workspace/229.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_alert_test.2599846141
Short name	T545
Test name
Test status
Simulation time	11797801 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:52:20 PM PDT 24
Peak memory	196156 kb
Host	smart-64fe6448-50b8-45b7-a445-0ce9b53755fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599846141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2599846141
Directory	/workspace/23.uart_alert_test/latest

Test location	/workspace/coverage/default/23.uart_fifo_full.2365710654
Short name	T628
Test name
Test status
Simulation time	307089114444 ps
CPU time	72.53 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:53:26 PM PDT 24
Peak memory	200920 kb
Host	smart-7e872238-20aa-4b6a-84d1-c1fdfef07a36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2365710654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2365710654
Directory	/workspace/23.uart_fifo_full/latest

Test location	/workspace/coverage/default/23.uart_fifo_overflow.2290069040
Short name	T179
Test name
Test status
Simulation time	204668720211 ps
CPU time	64.2 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:53:23 PM PDT 24
Peak memory	200892 kb
Host	smart-f23f3076-1cec-4806-884e-550a41058683
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290069040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2290069040
Directory	/workspace/23.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/23.uart_fifo_reset.4121259630
Short name	T1066
Test name
Test status
Simulation time	183821922362 ps
CPU time	33.48 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:52:52 PM PDT 24
Peak memory	200916 kb
Host	smart-a0469f7a-b513-4910-84e3-735b3b183db1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121259630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4121259630
Directory	/workspace/23.uart_fifo_reset/latest

Test location	/workspace/coverage/default/23.uart_intr.2736488224
Short name	T60
Test name
Test status
Simulation time	102151757014 ps
CPU time	199.35 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:55:40 PM PDT 24
Peak memory	200852 kb
Host	smart-6ca98ebd-9ab0-459c-8019-941fe13f0472
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736488224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2736488224
Directory	/workspace/23.uart_intr/latest

Test location	/workspace/coverage/default/23.uart_long_xfer_wo_dly.234764458
Short name	T565
Test name
Test status
Simulation time	86747094711 ps
CPU time	253.35 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200876 kb
Host	smart-a3893dee-ab7a-482a-bde3-82889302a596
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=234764458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.234764458
Directory	/workspace/23.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/23.uart_loopback.4212201385
Short name	T863
Test name
Test status
Simulation time	5382282713 ps
CPU time	3.5 seconds
Started	Apr 15 02:52:17 PM PDT 24
Finished	Apr 15 02:52:22 PM PDT 24
Peak memory	200600 kb
Host	smart-201a3879-8d2f-4069-9ecd-ffb8fe01ce14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212201385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4212201385
Directory	/workspace/23.uart_loopback/latest

Test location	/workspace/coverage/default/23.uart_noise_filter.1422536927
Short name	T870
Test name
Test status
Simulation time	46891359468 ps
CPU time	89.97 seconds
Started	Apr 15 02:52:18 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	200608 kb
Host	smart-2b5ff0bc-c8c0-4fca-8845-dbd2e2f63cf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422536927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1422536927
Directory	/workspace/23.uart_noise_filter/latest

Test location	/workspace/coverage/default/23.uart_perf.1940760277
Short name	T1083
Test name
Test status
Simulation time	6581137187 ps
CPU time	397.37 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:58:58 PM PDT 24
Peak memory	200832 kb
Host	smart-0c9efc1a-7e58-4098-ae22-42248335684f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1940760277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1940760277
Directory	/workspace/23.uart_perf/latest

Test location	/workspace/coverage/default/23.uart_rx_oversample.2980174156
Short name	T631
Test name
Test status
Simulation time	5662400179 ps
CPU time	27.27 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	199000 kb
Host	smart-bcd67320-0028-4fbe-afac-7af84c9a0100
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2980174156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2980174156
Directory	/workspace/23.uart_rx_oversample/latest

Test location	/workspace/coverage/default/23.uart_rx_parity_err.1433982270
Short name	T881
Test name
Test status
Simulation time	57586747257 ps
CPU time	11.01 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:52:31 PM PDT 24
Peak memory	200888 kb
Host	smart-39b4adb8-7857-41d1-ae1b-b1e8c8de437f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433982270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1433982270
Directory	/workspace/23.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/23.uart_rx_start_bit_filter.3040837644
Short name	T272
Test name
Test status
Simulation time	51826223859 ps
CPU time	14.81 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:52:35 PM PDT 24
Peak memory	196932 kb
Host	smart-c6fe3029-a952-49ac-998f-65d2d72b6331
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040837644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3040837644
Directory	/workspace/23.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/23.uart_smoke.3012302085
Short name	T1106
Test name
Test status
Simulation time	529023460 ps
CPU time	1.37 seconds
Started	Apr 15 02:52:13 PM PDT 24
Finished	Apr 15 02:52:16 PM PDT 24
Peak memory	199224 kb
Host	smart-c9913701-d30d-4741-9eec-91fce15c44a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012302085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3012302085
Directory	/workspace/23.uart_smoke/latest

Test location	/workspace/coverage/default/23.uart_stress_all.2208288014
Short name	T913
Test name
Test status
Simulation time	519641514981 ps
CPU time	1436.96 seconds
Started	Apr 15 02:52:17 PM PDT 24
Finished	Apr 15 03:16:15 PM PDT 24
Peak memory	209332 kb
Host	smart-bc76eb13-a655-4995-bbca-ff49b658b599
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208288014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2208288014
Directory	/workspace/23.uart_stress_all/latest

Test location	/workspace/coverage/default/23.uart_stress_all_with_rand_reset.1077563842
Short name	T1128
Test name
Test status
Simulation time	15936035105 ps
CPU time	415.56 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:59:16 PM PDT 24
Peak memory	216884 kb
Host	smart-1495fd0b-ed1c-4f05-9728-96434b68d462
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077563842 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1077563842
Directory	/workspace/23.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.uart_tx_ovrd.197603326
Short name	T531
Test name
Test status
Simulation time	6971374497 ps
CPU time	10.75 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:52:31 PM PDT 24
Peak memory	200840 kb
Host	smart-eea72dc8-aad8-49b9-a1ce-0308bcb847fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197603326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.197603326
Directory	/workspace/23.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/23.uart_tx_rx.2637586387
Short name	T461
Test name
Test status
Simulation time	58540428485 ps
CPU time	65.96 seconds
Started	Apr 15 02:52:17 PM PDT 24
Finished	Apr 15 02:53:23 PM PDT 24
Peak memory	200844 kb
Host	smart-c2fa18f9-e0d2-4535-bde4-5c9659c9af3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637586387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2637586387
Directory	/workspace/23.uart_tx_rx/latest

Test location	/workspace/coverage/default/230.uart_fifo_reset.3145613606
Short name	T547
Test name
Test status
Simulation time	131224105641 ps
CPU time	39.39 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:56:16 PM PDT 24
Peak memory	200888 kb
Host	smart-d198ff0a-5063-4d3f-9a19-bf117561b204
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145613606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3145613606
Directory	/workspace/230.uart_fifo_reset/latest

Test location	/workspace/coverage/default/231.uart_fifo_reset.692813231
Short name	T1069
Test name
Test status
Simulation time	135697024765 ps
CPU time	57.94 seconds
Started	Apr 15 02:55:33 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200712 kb
Host	smart-e33abc4a-a265-4598-84c2-7965c7b58dbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692813231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.692813231
Directory	/workspace/231.uart_fifo_reset/latest

Test location	/workspace/coverage/default/232.uart_fifo_reset.286172953
Short name	T851
Test name
Test status
Simulation time	18599220522 ps
CPU time	20 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:55:56 PM PDT 24
Peak memory	200832 kb
Host	smart-926e1511-e924-4b64-8ebf-127aebac890c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286172953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.286172953
Directory	/workspace/232.uart_fifo_reset/latest

Test location	/workspace/coverage/default/233.uart_fifo_reset.2118935385
Short name	T616
Test name
Test status
Simulation time	152620956803 ps
CPU time	143.76 seconds
Started	Apr 15 02:55:34 PM PDT 24
Finished	Apr 15 02:57:59 PM PDT 24
Peak memory	200872 kb
Host	smart-ec34606d-7bec-4f0d-98ab-d6889deff992
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118935385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2118935385
Directory	/workspace/233.uart_fifo_reset/latest

Test location	/workspace/coverage/default/234.uart_fifo_reset.4108611183
Short name	T932
Test name
Test status
Simulation time	18886068826 ps
CPU time	7.58 seconds
Started	Apr 15 02:55:34 PM PDT 24
Finished	Apr 15 02:55:42 PM PDT 24
Peak memory	200868 kb
Host	smart-e6c26162-82fe-40d5-85ee-195a4e732582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108611183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4108611183
Directory	/workspace/234.uart_fifo_reset/latest

Test location	/workspace/coverage/default/235.uart_fifo_reset.3595195962
Short name	T703
Test name
Test status
Simulation time	40366598678 ps
CPU time	17.49 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:55:55 PM PDT 24
Peak memory	200840 kb
Host	smart-fe912038-3543-402b-b0ba-def43a318691
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595195962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3595195962
Directory	/workspace/235.uart_fifo_reset/latest

Test location	/workspace/coverage/default/236.uart_fifo_reset.2873659418
Short name	T976
Test name
Test status
Simulation time	264068485181 ps
CPU time	57.78 seconds
Started	Apr 15 02:55:33 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200848 kb
Host	smart-bd9613ba-d132-47ef-9181-0d4dd054510c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873659418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2873659418
Directory	/workspace/236.uart_fifo_reset/latest

Test location	/workspace/coverage/default/237.uart_fifo_reset.3295305902
Short name	T725
Test name
Test status
Simulation time	23678113402 ps
CPU time	40.19 seconds
Started	Apr 15 02:55:37 PM PDT 24
Finished	Apr 15 02:56:18 PM PDT 24
Peak memory	200776 kb
Host	smart-448b9656-6fcd-4fcf-9d87-90204dd0bb42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295305902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3295305902
Directory	/workspace/237.uart_fifo_reset/latest

Test location	/workspace/coverage/default/238.uart_fifo_reset.2195513858
Short name	T1008
Test name
Test status
Simulation time	227012831261 ps
CPU time	155.28 seconds
Started	Apr 15 02:55:35 PM PDT 24
Finished	Apr 15 02:58:11 PM PDT 24
Peak memory	200904 kb
Host	smart-d9df1815-2b27-4535-a4db-6edb7af9f491
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195513858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2195513858
Directory	/workspace/238.uart_fifo_reset/latest

Test location	/workspace/coverage/default/239.uart_fifo_reset.3917493127
Short name	T183
Test name
Test status
Simulation time	17799222602 ps
CPU time	31 seconds
Started	Apr 15 02:55:34 PM PDT 24
Finished	Apr 15 02:56:06 PM PDT 24
Peak memory	200880 kb
Host	smart-00e3e02c-efea-4ba1-aded-fe5667fc6ceb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917493127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3917493127
Directory	/workspace/239.uart_fifo_reset/latest

Test location	/workspace/coverage/default/24.uart_alert_test.3246291883
Short name	T513
Test name
Test status
Simulation time	13470429 ps
CPU time	0.58 seconds
Started	Apr 15 02:52:24 PM PDT 24
Finished	Apr 15 02:52:25 PM PDT 24
Peak memory	196220 kb
Host	smart-0bba5281-525b-4517-85a4-31308c563b1f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246291883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3246291883
Directory	/workspace/24.uart_alert_test/latest

Test location	/workspace/coverage/default/24.uart_fifo_full.2386177870
Short name	T728
Test name
Test status
Simulation time	30077627420 ps
CPU time	16.23 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:52:37 PM PDT 24
Peak memory	200884 kb
Host	smart-a6c4802f-5420-4a59-8804-746984d066c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386177870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2386177870
Directory	/workspace/24.uart_fifo_full/latest

Test location	/workspace/coverage/default/24.uart_fifo_overflow.1946974475
Short name	T762
Test name
Test status
Simulation time	133592474778 ps
CPU time	93.81 seconds
Started	Apr 15 02:52:22 PM PDT 24
Finished	Apr 15 02:53:57 PM PDT 24
Peak memory	200648 kb
Host	smart-feefb06f-42bf-48a0-bccf-d6227c2f346d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946974475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1946974475
Directory	/workspace/24.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/24.uart_intr.1745129366
Short name	T524
Test name
Test status
Simulation time	478434742247 ps
CPU time	249.81 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200844 kb
Host	smart-d8f16c01-80b5-49c9-aabb-fdc0be59f28c
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745129366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1745129366
Directory	/workspace/24.uart_intr/latest

Test location	/workspace/coverage/default/24.uart_long_xfer_wo_dly.2401067543
Short name	T1167
Test name
Test status
Simulation time	90435069020 ps
CPU time	446.9 seconds
Started	Apr 15 02:52:23 PM PDT 24
Finished	Apr 15 02:59:50 PM PDT 24
Peak memory	200912 kb
Host	smart-ec70b6c1-08ba-447e-afa9-0b25215d3503
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2401067543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2401067543
Directory	/workspace/24.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/24.uart_loopback.3592399157
Short name	T678
Test name
Test status
Simulation time	10747244996 ps
CPU time	21.35 seconds
Started	Apr 15 02:52:22 PM PDT 24
Finished	Apr 15 02:52:44 PM PDT 24
Peak memory	200688 kb
Host	smart-b954952a-1027-40a6-9ca8-ae8207fd826d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592399157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3592399157
Directory	/workspace/24.uart_loopback/latest

Test location	/workspace/coverage/default/24.uart_noise_filter.518510276
Short name	T807
Test name
Test status
Simulation time	310854692623 ps
CPU time	84.1 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:53:46 PM PDT 24
Peak memory	200944 kb
Host	smart-1837f77d-02e5-405a-99e0-8da8dbb056ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=518510276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.518510276
Directory	/workspace/24.uart_noise_filter/latest

Test location	/workspace/coverage/default/24.uart_perf.950882349
Short name	T625
Test name
Test status
Simulation time	17828190063 ps
CPU time	1060.38 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 03:10:02 PM PDT 24
Peak memory	200896 kb
Host	smart-636a230a-d8c3-4450-80bd-5c4d11e85976
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=950882349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.950882349
Directory	/workspace/24.uart_perf/latest

Test location	/workspace/coverage/default/24.uart_rx_oversample.2710470692
Short name	T872
Test name
Test status
Simulation time	4544050431 ps
CPU time	10.39 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:52:30 PM PDT 24
Peak memory	199044 kb
Host	smart-9c1e2ea1-df1d-4a31-b9af-f652b74497e2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2710470692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2710470692
Directory	/workspace/24.uart_rx_oversample/latest

Test location	/workspace/coverage/default/24.uart_rx_parity_err.2228230616
Short name	T945
Test name
Test status
Simulation time	226560123518 ps
CPU time	82.85 seconds
Started	Apr 15 02:52:25 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	200812 kb
Host	smart-9ab8da1f-09b4-4fb8-bdd0-38c97673f255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228230616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2228230616
Directory	/workspace/24.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/24.uart_rx_start_bit_filter.1350233427
Short name	T882
Test name
Test status
Simulation time	4227226102 ps
CPU time	1.51 seconds
Started	Apr 15 02:52:23 PM PDT 24
Finished	Apr 15 02:52:25 PM PDT 24
Peak memory	196908 kb
Host	smart-2ebaab73-a2ba-4fba-bf20-613ff1260bef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350233427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1350233427
Directory	/workspace/24.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/24.uart_smoke.2490861644
Short name	T582
Test name
Test status
Simulation time	491652740 ps
CPU time	2.41 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:52:23 PM PDT 24
Peak memory	199568 kb
Host	smart-dcf78ddc-9da7-4aa7-8890-b45f3cc2ecec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490861644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2490861644
Directory	/workspace/24.uart_smoke/latest

Test location	/workspace/coverage/default/24.uart_stress_all.2434339214
Short name	T1099
Test name
Test status
Simulation time	96107876969 ps
CPU time	160.58 seconds
Started	Apr 15 02:52:22 PM PDT 24
Finished	Apr 15 02:55:04 PM PDT 24
Peak memory	200900 kb
Host	smart-297d2a45-60af-4e6f-b00a-5ad519be20a7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434339214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2434339214
Directory	/workspace/24.uart_stress_all/latest

Test location	/workspace/coverage/default/24.uart_stress_all_with_rand_reset.974467592
Short name	T316
Test name
Test status
Simulation time	105277863313 ps
CPU time	346.42 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:58:08 PM PDT 24
Peak memory	225692 kb
Host	smart-3d6b69eb-264c-44d7-88f9-cfa712fa0841
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974467592 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.974467592
Directory	/workspace/24.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.uart_tx_ovrd.1470909119
Short name	T846
Test name
Test status
Simulation time	1075458528 ps
CPU time	4.41 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200788 kb
Host	smart-af6e7062-4477-443b-861b-6f7872058fe8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470909119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1470909119
Directory	/workspace/24.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/24.uart_tx_rx.2153832166
Short name	T1040
Test name
Test status
Simulation time	229944865777 ps
CPU time	44.45 seconds
Started	Apr 15 02:52:19 PM PDT 24
Finished	Apr 15 02:53:04 PM PDT 24
Peak memory	200832 kb
Host	smart-202a4fce-062f-4ed8-a6a4-2b52253d01d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153832166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2153832166
Directory	/workspace/24.uart_tx_rx/latest

Test location	/workspace/coverage/default/240.uart_fifo_reset.1407010077
Short name	T121
Test name
Test status
Simulation time	69485037290 ps
CPU time	23.46 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:56:00 PM PDT 24
Peak memory	200916 kb
Host	smart-191b0533-1857-4d24-b3f9-6c544bc9d4cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407010077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1407010077
Directory	/workspace/240.uart_fifo_reset/latest

Test location	/workspace/coverage/default/241.uart_fifo_reset.2722042328
Short name	T696
Test name
Test status
Simulation time	68197800463 ps
CPU time	27.5 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:56:04 PM PDT 24
Peak memory	200960 kb
Host	smart-8160b53d-1023-46a5-b506-978308736161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722042328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2722042328
Directory	/workspace/241.uart_fifo_reset/latest

Test location	/workspace/coverage/default/242.uart_fifo_reset.4006633042
Short name	T61
Test name
Test status
Simulation time	58632366589 ps
CPU time	56.83 seconds
Started	Apr 15 02:55:37 PM PDT 24
Finished	Apr 15 02:56:34 PM PDT 24
Peak memory	200784 kb
Host	smart-c53679e9-92c7-4fd7-917c-b4badf78b756
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006633042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4006633042
Directory	/workspace/242.uart_fifo_reset/latest

Test location	/workspace/coverage/default/243.uart_fifo_reset.830311189
Short name	T188
Test name
Test status
Simulation time	32039937775 ps
CPU time	56.12 seconds
Started	Apr 15 02:55:39 PM PDT 24
Finished	Apr 15 02:56:36 PM PDT 24
Peak memory	200872 kb
Host	smart-e7578fda-465a-48a9-b5ce-88bd3a6b0fe0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830311189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.830311189
Directory	/workspace/243.uart_fifo_reset/latest

Test location	/workspace/coverage/default/244.uart_fifo_reset.3600776928
Short name	T579
Test name
Test status
Simulation time	41750061447 ps
CPU time	76.35 seconds
Started	Apr 15 02:55:38 PM PDT 24
Finished	Apr 15 02:56:56 PM PDT 24
Peak memory	200912 kb
Host	smart-2128c794-1725-4955-a8ea-3428c631aa6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3600776928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3600776928
Directory	/workspace/244.uart_fifo_reset/latest

Test location	/workspace/coverage/default/245.uart_fifo_reset.1764579309
Short name	T240
Test name
Test status
Simulation time	35460865920 ps
CPU time	17.74 seconds
Started	Apr 15 02:55:40 PM PDT 24
Finished	Apr 15 02:55:58 PM PDT 24
Peak memory	200824 kb
Host	smart-53718d37-598a-41b3-bb55-1658733e0c20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764579309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1764579309
Directory	/workspace/245.uart_fifo_reset/latest

Test location	/workspace/coverage/default/246.uart_fifo_reset.3228121197
Short name	T249
Test name
Test status
Simulation time	124586763479 ps
CPU time	49.99 seconds
Started	Apr 15 02:55:37 PM PDT 24
Finished	Apr 15 02:56:28 PM PDT 24
Peak memory	200928 kb
Host	smart-9bb0bf0f-4228-41dd-878a-4f5c854ea2be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228121197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3228121197
Directory	/workspace/246.uart_fifo_reset/latest

Test location	/workspace/coverage/default/247.uart_fifo_reset.2599887727
Short name	T818
Test name
Test status
Simulation time	154217646811 ps
CPU time	270.91 seconds
Started	Apr 15 02:55:38 PM PDT 24
Finished	Apr 15 03:00:10 PM PDT 24
Peak memory	200796 kb
Host	smart-684318eb-9898-4850-a1fb-7643cbf5435b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599887727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2599887727
Directory	/workspace/247.uart_fifo_reset/latest

Test location	/workspace/coverage/default/248.uart_fifo_reset.1849110332
Short name	T705
Test name
Test status
Simulation time	65273226698 ps
CPU time	182.54 seconds
Started	Apr 15 02:55:41 PM PDT 24
Finished	Apr 15 02:58:44 PM PDT 24
Peak memory	200848 kb
Host	smart-44087272-4d77-4e42-a76e-965f43d9bf92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849110332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1849110332
Directory	/workspace/248.uart_fifo_reset/latest

Test location	/workspace/coverage/default/249.uart_fifo_reset.437328751
Short name	T869
Test name
Test status
Simulation time	111242123190 ps
CPU time	109.89 seconds
Started	Apr 15 02:55:36 PM PDT 24
Finished	Apr 15 02:57:27 PM PDT 24
Peak memory	200708 kb
Host	smart-48d82e3b-5ee6-4120-973c-1f3136459796
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437328751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.437328751
Directory	/workspace/249.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_alert_test.634902211
Short name	T637
Test name
Test status
Simulation time	15297127 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:52:32 PM PDT 24
Peak memory	196236 kb
Host	smart-2695298d-a2ab-4ae5-9ebf-ba75f7859613
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634902211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.634902211
Directory	/workspace/25.uart_alert_test/latest

Test location	/workspace/coverage/default/25.uart_fifo_full.3660459893
Short name	T355
Test name
Test status
Simulation time	201155016565 ps
CPU time	82.41 seconds
Started	Apr 15 02:52:20 PM PDT 24
Finished	Apr 15 02:53:43 PM PDT 24
Peak memory	200860 kb
Host	smart-bdb1b2cd-1bb9-4935-8287-87b9bcfc71c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660459893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3660459893
Directory	/workspace/25.uart_fifo_full/latest

Test location	/workspace/coverage/default/25.uart_fifo_overflow.206203711
Short name	T930
Test name
Test status
Simulation time	16976722222 ps
CPU time	24.95 seconds
Started	Apr 15 02:52:22 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	200732 kb
Host	smart-f76081c9-1e7f-45f5-9aa3-4a628ca6cac9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206203711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.206203711
Directory	/workspace/25.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/25.uart_fifo_reset.2569133255
Short name	T662
Test name
Test status
Simulation time	6449550621 ps
CPU time	14.86 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:52:37 PM PDT 24
Peak memory	200840 kb
Host	smart-583c4653-c5a1-4d6f-b551-8dc0ff2f985c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569133255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2569133255
Directory	/workspace/25.uart_fifo_reset/latest

Test location	/workspace/coverage/default/25.uart_intr.681233889
Short name	T659
Test name
Test status
Simulation time	44317061873 ps
CPU time	68.2 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:53:30 PM PDT 24
Peak memory	200428 kb
Host	smart-af702bd4-5065-4c1c-8142-4ae00a204beb
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681233889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.681233889
Directory	/workspace/25.uart_intr/latest

Test location	/workspace/coverage/default/25.uart_long_xfer_wo_dly.3604060161
Short name	T326
Test name
Test status
Simulation time	128154835229 ps
CPU time	296.44 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 02:57:26 PM PDT 24
Peak memory	200804 kb
Host	smart-79c53b9c-480a-488e-abbf-7b0c3884b19f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3604060161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3604060161
Directory	/workspace/25.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/25.uart_loopback.2333984881
Short name	T1159
Test name
Test status
Simulation time	9975168255 ps
CPU time	16.73 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	200216 kb
Host	smart-54fe1deb-b43a-47ec-99e1-36a22a889f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333984881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2333984881
Directory	/workspace/25.uart_loopback/latest

Test location	/workspace/coverage/default/25.uart_noise_filter.2502488828
Short name	T376
Test name
Test status
Simulation time	73412492425 ps
CPU time	34.6 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:53:09 PM PDT 24
Peak memory	209160 kb
Host	smart-08ef6d88-6fcc-4490-bb3b-e914bb4cffd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502488828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2502488828
Directory	/workspace/25.uart_noise_filter/latest

Test location	/workspace/coverage/default/25.uart_perf.3686727490
Short name	T304
Test name
Test status
Simulation time	20271091330 ps
CPU time	998.4 seconds
Started	Apr 15 02:52:26 PM PDT 24
Finished	Apr 15 03:09:05 PM PDT 24
Peak memory	200880 kb
Host	smart-0133d506-ea88-4532-bd09-4d5b01972555
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3686727490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3686727490
Directory	/workspace/25.uart_perf/latest

Test location	/workspace/coverage/default/25.uart_rx_oversample.3505790296
Short name	T963
Test name
Test status
Simulation time	2666503867 ps
CPU time	5.28 seconds
Started	Apr 15 02:52:23 PM PDT 24
Finished	Apr 15 02:52:29 PM PDT 24
Peak memory	198728 kb
Host	smart-255913ff-dd57-4ac0-83bd-fba7cbbe99c0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3505790296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3505790296
Directory	/workspace/25.uart_rx_oversample/latest

Test location	/workspace/coverage/default/25.uart_rx_parity_err.2099213311
Short name	T917
Test name
Test status
Simulation time	207528964217 ps
CPU time	89.62 seconds
Started	Apr 15 02:52:25 PM PDT 24
Finished	Apr 15 02:53:56 PM PDT 24
Peak memory	200800 kb
Host	smart-b4650a49-e973-4599-b397-b14204790097
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099213311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2099213311
Directory	/workspace/25.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/25.uart_rx_start_bit_filter.1069027021
Short name	T300
Test name
Test status
Simulation time	621148849 ps
CPU time	1.12 seconds
Started	Apr 15 02:52:26 PM PDT 24
Finished	Apr 15 02:52:28 PM PDT 24
Peak memory	196580 kb
Host	smart-b24250e8-6f2a-48f5-bc29-b6dd9de31206
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069027021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1069027021
Directory	/workspace/25.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/25.uart_smoke.223646826
Short name	T1031
Test name
Test status
Simulation time	465792380 ps
CPU time	1.87 seconds
Started	Apr 15 02:52:25 PM PDT 24
Finished	Apr 15 02:52:27 PM PDT 24
Peak memory	200324 kb
Host	smart-4c66706d-d953-4bf2-a1e1-5c8371eacbfd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223646826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.223646826
Directory	/workspace/25.uart_smoke/latest

Test location	/workspace/coverage/default/25.uart_stress_all.2879959160
Short name	T452
Test name
Test status
Simulation time	202070759972 ps
CPU time	426.05 seconds
Started	Apr 15 02:52:26 PM PDT 24
Finished	Apr 15 02:59:33 PM PDT 24
Peak memory	201108 kb
Host	smart-051c1cd8-2953-4d49-9d63-e2bd68b6ad2b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879959160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2879959160
Directory	/workspace/25.uart_stress_all/latest

Test location	/workspace/coverage/default/25.uart_stress_all_with_rand_reset.3198597611
Short name	T440
Test name
Test status
Simulation time	91547162916 ps
CPU time	627.59 seconds
Started	Apr 15 02:52:27 PM PDT 24
Finished	Apr 15 03:02:56 PM PDT 24
Peak memory	225672 kb
Host	smart-d9d2805c-7189-4980-97bb-6a0979dcdd57
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198597611 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3198597611
Directory	/workspace/25.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.uart_tx_ovrd.3247835400
Short name	T918
Test name
Test status
Simulation time	1140418130 ps
CPU time	3.36 seconds
Started	Apr 15 02:52:26 PM PDT 24
Finished	Apr 15 02:52:30 PM PDT 24
Peak memory	199688 kb
Host	smart-3663e6d0-375a-4b90-bd38-73155a7ff085
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247835400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3247835400
Directory	/workspace/25.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/25.uart_tx_rx.262039108
Short name	T1124
Test name
Test status
Simulation time	44292104390 ps
CPU time	85.71 seconds
Started	Apr 15 02:52:21 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	200920 kb
Host	smart-ee9bbd18-d6ec-4a34-9d33-0224327c6222
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262039108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.262039108
Directory	/workspace/25.uart_tx_rx/latest

Test location	/workspace/coverage/default/250.uart_fifo_reset.2264453663
Short name	T1045
Test name
Test status
Simulation time	193201271893 ps
CPU time	97.89 seconds
Started	Apr 15 02:55:39 PM PDT 24
Finished	Apr 15 02:57:17 PM PDT 24
Peak memory	200760 kb
Host	smart-70c3803c-836a-44da-9253-5be48c9def57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264453663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2264453663
Directory	/workspace/250.uart_fifo_reset/latest

Test location	/workspace/coverage/default/252.uart_fifo_reset.895120165
Short name	T1071
Test name
Test status
Simulation time	8359566881 ps
CPU time	14.8 seconds
Started	Apr 15 02:55:43 PM PDT 24
Finished	Apr 15 02:55:59 PM PDT 24
Peak memory	200732 kb
Host	smart-3fb5529a-647d-4735-be3b-b399c012622c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895120165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.895120165
Directory	/workspace/252.uart_fifo_reset/latest

Test location	/workspace/coverage/default/253.uart_fifo_reset.2755712428
Short name	T495
Test name
Test status
Simulation time	154835855359 ps
CPU time	145.62 seconds
Started	Apr 15 02:55:43 PM PDT 24
Finished	Apr 15 02:58:09 PM PDT 24
Peak memory	200928 kb
Host	smart-8b5be0c4-9d13-4d96-9a0b-e1e0019871ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755712428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2755712428
Directory	/workspace/253.uart_fifo_reset/latest

Test location	/workspace/coverage/default/255.uart_fifo_reset.901539500
Short name	T197
Test name
Test status
Simulation time	23056983340 ps
CPU time	18.71 seconds
Started	Apr 15 02:55:43 PM PDT 24
Finished	Apr 15 02:56:02 PM PDT 24
Peak memory	200908 kb
Host	smart-6df67746-ebc0-4107-b80d-0639577f21fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901539500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.901539500
Directory	/workspace/255.uart_fifo_reset/latest

Test location	/workspace/coverage/default/256.uart_fifo_reset.2488561161
Short name	T480
Test name
Test status
Simulation time	129931293402 ps
CPU time	48.19 seconds
Started	Apr 15 02:55:41 PM PDT 24
Finished	Apr 15 02:56:29 PM PDT 24
Peak memory	200844 kb
Host	smart-86fe1dfe-83c1-45c9-a9c5-9b6792a63d3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488561161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2488561161
Directory	/workspace/256.uart_fifo_reset/latest

Test location	/workspace/coverage/default/257.uart_fifo_reset.2328982556
Short name	T147
Test name
Test status
Simulation time	48973771550 ps
CPU time	72.74 seconds
Started	Apr 15 02:55:42 PM PDT 24
Finished	Apr 15 02:56:55 PM PDT 24
Peak memory	200844 kb
Host	smart-647ca376-b40e-4f4f-a6f7-632cd72d3ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328982556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2328982556
Directory	/workspace/257.uart_fifo_reset/latest

Test location	/workspace/coverage/default/258.uart_fifo_reset.431476330
Short name	T130
Test name
Test status
Simulation time	35097927069 ps
CPU time	14.76 seconds
Started	Apr 15 02:55:45 PM PDT 24
Finished	Apr 15 02:56:00 PM PDT 24
Peak memory	200828 kb
Host	smart-bab70771-269e-44d7-bb86-098141b7edb0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431476330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.431476330
Directory	/workspace/258.uart_fifo_reset/latest

Test location	/workspace/coverage/default/259.uart_fifo_reset.2374557624
Short name	T1086
Test name
Test status
Simulation time	67767172794 ps
CPU time	95.13 seconds
Started	Apr 15 02:55:48 PM PDT 24
Finished	Apr 15 02:57:24 PM PDT 24
Peak memory	200896 kb
Host	smart-4cc4e961-f6a2-4aa6-9a3a-c4f3cb77283c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374557624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2374557624
Directory	/workspace/259.uart_fifo_reset/latest

Test location	/workspace/coverage/default/26.uart_alert_test.3079951258
Short name	T397
Test name
Test status
Simulation time	17077805 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:30 PM PDT 24
Finished	Apr 15 02:52:31 PM PDT 24
Peak memory	196196 kb
Host	smart-725e1b0a-5168-45b8-800f-9a57a35d8045
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079951258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3079951258
Directory	/workspace/26.uart_alert_test/latest

Test location	/workspace/coverage/default/26.uart_fifo_full.492262010
Short name	T1064
Test name
Test status
Simulation time	153275061858 ps
CPU time	506.94 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 03:00:56 PM PDT 24
Peak memory	200816 kb
Host	smart-e4ff8068-06a1-4323-a8a5-21bb9d545b2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492262010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.492262010
Directory	/workspace/26.uart_fifo_full/latest

Test location	/workspace/coverage/default/26.uart_fifo_overflow.2551374594
Short name	T442
Test name
Test status
Simulation time	81181601315 ps
CPU time	29.45 seconds
Started	Apr 15 02:52:24 PM PDT 24
Finished	Apr 15 02:52:54 PM PDT 24
Peak memory	200908 kb
Host	smart-98de1812-97a8-4b8c-8a03-0a42b16e8b85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551374594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2551374594
Directory	/workspace/26.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/26.uart_intr.769403277
Short name	T861
Test name
Test status
Simulation time	41539490872 ps
CPU time	69.65 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	200484 kb
Host	smart-2b1b01ec-2a66-4931-8d51-5f0a1685fbce
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769403277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.769403277
Directory	/workspace/26.uart_intr/latest

Test location	/workspace/coverage/default/26.uart_long_xfer_wo_dly.509494716
Short name	T645
Test name
Test status
Simulation time	153980288849 ps
CPU time	1429.38 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 03:16:23 PM PDT 24
Peak memory	200896 kb
Host	smart-a25d269f-c269-44d7-ac5a-ad7d4da7ca5c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=509494716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.509494716
Directory	/workspace/26.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/26.uart_loopback.2668940961
Short name	T650
Test name
Test status
Simulation time	7192699909 ps
CPU time	16.35 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	200116 kb
Host	smart-4cd3e7fd-f850-4997-9dc2-2e8864f1f4c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668940961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2668940961
Directory	/workspace/26.uart_loopback/latest

Test location	/workspace/coverage/default/26.uart_noise_filter.4098963322
Short name	T912
Test name
Test status
Simulation time	23860554343 ps
CPU time	64.78 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200956 kb
Host	smart-1d2333bf-6e1e-4c0a-a70e-67863a544fa9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4098963322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.4098963322
Directory	/workspace/26.uart_noise_filter/latest

Test location	/workspace/coverage/default/26.uart_perf.1216158949
Short name	T726
Test name
Test status
Simulation time	10333880611 ps
CPU time	288.6 seconds
Started	Apr 15 02:52:30 PM PDT 24
Finished	Apr 15 02:57:19 PM PDT 24
Peak memory	200772 kb
Host	smart-02b42997-3e74-4c88-b5fc-6e813d66c8f8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1216158949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1216158949
Directory	/workspace/26.uart_perf/latest

Test location	/workspace/coverage/default/26.uart_rx_oversample.1019634786
Short name	T18
Test name
Test status
Simulation time	3704840270 ps
CPU time	7.89 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:52:40 PM PDT 24
Peak memory	199964 kb
Host	smart-bdd338f3-2f77-48c7-8887-de76bbf9abed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1019634786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1019634786
Directory	/workspace/26.uart_rx_oversample/latest

Test location	/workspace/coverage/default/26.uart_rx_parity_err.1845742898
Short name	T602
Test name
Test status
Simulation time	40614508611 ps
CPU time	45.47 seconds
Started	Apr 15 02:52:30 PM PDT 24
Finished	Apr 15 02:53:16 PM PDT 24
Peak memory	200764 kb
Host	smart-27a80a1d-ab32-4215-9a7e-114e5ee074e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845742898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1845742898
Directory	/workspace/26.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/26.uart_rx_start_bit_filter.3529528915
Short name	T324
Test name
Test status
Simulation time	5693285339 ps
CPU time	4.42 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 02:52:35 PM PDT 24
Peak memory	196736 kb
Host	smart-b2bd11c6-60ea-4639-a033-e6ca61d03ffb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529528915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3529528915
Directory	/workspace/26.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/26.uart_smoke.2724035589
Short name	T897
Test name
Test status
Simulation time	121157508 ps
CPU time	1.03 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:52:33 PM PDT 24
Peak memory	199588 kb
Host	smart-d1419054-5b46-4d1c-a95f-b8919f31558b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724035589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2724035589
Directory	/workspace/26.uart_smoke/latest

Test location	/workspace/coverage/default/26.uart_stress_all.2474517695
Short name	T118
Test name
Test status
Simulation time	77353878655 ps
CPU time	115.73 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:54:28 PM PDT 24
Peak memory	200788 kb
Host	smart-20cb8044-088d-4fe5-98b1-fa8d6cd3d05e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474517695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2474517695
Directory	/workspace/26.uart_stress_all/latest

Test location	/workspace/coverage/default/26.uart_stress_all_with_rand_reset.61688340
Short name	T111
Test name
Test status
Simulation time	51775358685 ps
CPU time	464.83 seconds
Started	Apr 15 02:52:28 PM PDT 24
Finished	Apr 15 03:00:14 PM PDT 24
Peak memory	217368 kb
Host	smart-979b8d9c-0fa9-42a1-b802-28000bfe2a8a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61688340 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.61688340
Directory	/workspace/26.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.uart_tx_ovrd.3371329644
Short name	T928
Test name
Test status
Simulation time	1182667198 ps
CPU time	2.21 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:52:35 PM PDT 24
Peak memory	199568 kb
Host	smart-4d4f24e2-b57f-462a-8f57-5e6c467addd0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371329644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3371329644
Directory	/workspace/26.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/26.uart_tx_rx.1753064674
Short name	T469
Test name
Test status
Simulation time	208930447478 ps
CPU time	124.13 seconds
Started	Apr 15 02:52:28 PM PDT 24
Finished	Apr 15 02:54:33 PM PDT 24
Peak memory	200832 kb
Host	smart-f17fcaae-7f18-4153-b737-6291c057cd5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1753064674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1753064674
Directory	/workspace/26.uart_tx_rx/latest

Test location	/workspace/coverage/default/260.uart_fifo_reset.1534397268
Short name	T1072
Test name
Test status
Simulation time	55380568956 ps
CPU time	22.54 seconds
Started	Apr 15 02:55:45 PM PDT 24
Finished	Apr 15 02:56:08 PM PDT 24
Peak memory	200752 kb
Host	smart-1a453df8-815c-4c12-bf47-fa70d1323549
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534397268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1534397268
Directory	/workspace/260.uart_fifo_reset/latest

Test location	/workspace/coverage/default/261.uart_fifo_reset.3776617392
Short name	T1029
Test name
Test status
Simulation time	76834453082 ps
CPU time	122.07 seconds
Started	Apr 15 02:55:47 PM PDT 24
Finished	Apr 15 02:57:49 PM PDT 24
Peak memory	200900 kb
Host	smart-70ac7683-8a30-4dee-a377-01d338fec2b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3776617392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3776617392
Directory	/workspace/261.uart_fifo_reset/latest

Test location	/workspace/coverage/default/263.uart_fifo_reset.1160900674
Short name	T354
Test name
Test status
Simulation time	132556721605 ps
CPU time	217.66 seconds
Started	Apr 15 02:55:52 PM PDT 24
Finished	Apr 15 02:59:31 PM PDT 24
Peak memory	200832 kb
Host	smart-c5a4e0e1-76d1-4f6b-ae66-332bb76b1f1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160900674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1160900674
Directory	/workspace/263.uart_fifo_reset/latest

Test location	/workspace/coverage/default/264.uart_fifo_reset.1538928468
Short name	T473
Test name
Test status
Simulation time	41581741479 ps
CPU time	29.59 seconds
Started	Apr 15 02:55:50 PM PDT 24
Finished	Apr 15 02:56:21 PM PDT 24
Peak memory	200876 kb
Host	smart-a45425dd-d76b-4f9c-b54b-b0b2202ef633
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538928468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1538928468
Directory	/workspace/264.uart_fifo_reset/latest

Test location	/workspace/coverage/default/265.uart_fifo_reset.4185155312
Short name	T185
Test name
Test status
Simulation time	46904481765 ps
CPU time	39.07 seconds
Started	Apr 15 02:55:52 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200860 kb
Host	smart-0c64f699-6939-4ba4-93e3-31a290fc6a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4185155312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4185155312
Directory	/workspace/265.uart_fifo_reset/latest

Test location	/workspace/coverage/default/266.uart_fifo_reset.3830924110
Short name	T1163
Test name
Test status
Simulation time	63138040043 ps
CPU time	115.31 seconds
Started	Apr 15 02:55:52 PM PDT 24
Finished	Apr 15 02:57:48 PM PDT 24
Peak memory	200848 kb
Host	smart-0f323334-fc60-431a-addc-01f1541a376d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830924110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3830924110
Directory	/workspace/266.uart_fifo_reset/latest

Test location	/workspace/coverage/default/267.uart_fifo_reset.2290803732
Short name	T1059
Test name
Test status
Simulation time	52484291988 ps
CPU time	19.64 seconds
Started	Apr 15 02:55:50 PM PDT 24
Finished	Apr 15 02:56:10 PM PDT 24
Peak memory	200936 kb
Host	smart-1ceb959c-e2a2-4cee-9a17-eb34df5ded7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290803732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2290803732
Directory	/workspace/267.uart_fifo_reset/latest

Test location	/workspace/coverage/default/268.uart_fifo_reset.48397867
Short name	T236
Test name
Test status
Simulation time	100968820526 ps
CPU time	18.33 seconds
Started	Apr 15 02:55:50 PM PDT 24
Finished	Apr 15 02:56:09 PM PDT 24
Peak memory	200924 kb
Host	smart-90588367-45f9-4bfc-8b62-68d1c11edd3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48397867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.48397867
Directory	/workspace/268.uart_fifo_reset/latest

Test location	/workspace/coverage/default/269.uart_fifo_reset.2039260121
Short name	T217
Test name
Test status
Simulation time	63517747644 ps
CPU time	28.76 seconds
Started	Apr 15 02:55:54 PM PDT 24
Finished	Apr 15 02:56:24 PM PDT 24
Peak memory	200876 kb
Host	smart-04942830-9cd7-4364-8d0a-280926ad9f68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039260121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2039260121
Directory	/workspace/269.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_alert_test.4077389570
Short name	T620
Test name
Test status
Simulation time	66125708 ps
CPU time	0.54 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:52:33 PM PDT 24
Peak memory	195648 kb
Host	smart-42671bc5-f9d5-4cf1-976a-9a4d3c76d921
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077389570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4077389570
Directory	/workspace/27.uart_alert_test/latest

Test location	/workspace/coverage/default/27.uart_fifo_full.1680953979
Short name	T599
Test name
Test status
Simulation time	15630795292 ps
CPU time	7.52 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:52:47 PM PDT 24
Peak memory	199960 kb
Host	smart-154ee02f-eb7d-4794-bb5a-e535f4712c3b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680953979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1680953979
Directory	/workspace/27.uart_fifo_full/latest

Test location	/workspace/coverage/default/27.uart_fifo_overflow.1666011157
Short name	T944
Test name
Test status
Simulation time	155499339126 ps
CPU time	90.39 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	200792 kb
Host	smart-6a739242-1e06-4b2f-9801-0ac6d7413067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666011157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1666011157
Directory	/workspace/27.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/27.uart_fifo_reset.3964801789
Short name	T392
Test name
Test status
Simulation time	31896342362 ps
CPU time	25.58 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:52:59 PM PDT 24
Peak memory	200896 kb
Host	smart-9d48e508-5eaf-4b06-8d4e-85a9174d3568
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3964801789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3964801789
Directory	/workspace/27.uart_fifo_reset/latest

Test location	/workspace/coverage/default/27.uart_long_xfer_wo_dly.808633905
Short name	T838
Test name
Test status
Simulation time	57558308355 ps
CPU time	120.87 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:54:34 PM PDT 24
Peak memory	200904 kb
Host	smart-63bc7e46-6ade-4660-be3d-1f6d1ecb0651
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=808633905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.808633905
Directory	/workspace/27.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/27.uart_loopback.1856770704
Short name	T342
Test name
Test status
Simulation time	13145728539 ps
CPU time	38.73 seconds
Started	Apr 15 02:52:31 PM PDT 24
Finished	Apr 15 02:53:10 PM PDT 24
Peak memory	199504 kb
Host	smart-d842144f-d75f-433c-a5f4-f71c36d55124
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856770704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1856770704
Directory	/workspace/27.uart_loopback/latest

Test location	/workspace/coverage/default/27.uart_noise_filter.3499099266
Short name	T733
Test name
Test status
Simulation time	68410695977 ps
CPU time	112.55 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:54:26 PM PDT 24
Peak memory	200260 kb
Host	smart-43e35071-956a-48d0-8e9a-e50a03ab983e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499099266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3499099266
Directory	/workspace/27.uart_noise_filter/latest

Test location	/workspace/coverage/default/27.uart_perf.564795675
Short name	T642
Test name
Test status
Simulation time	17134896919 ps
CPU time	94.82 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 02:54:05 PM PDT 24
Peak memory	200868 kb
Host	smart-fbd126ed-5627-44ae-8831-b2ea7a501a3a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=564795675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.564795675
Directory	/workspace/27.uart_perf/latest

Test location	/workspace/coverage/default/27.uart_rx_oversample.1634859305
Short name	T883
Test name
Test status
Simulation time	6780616965 ps
CPU time	57.47 seconds
Started	Apr 15 02:52:30 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	199956 kb
Host	smart-02d389b8-4606-407a-bbc5-de1e75697de7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1634859305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1634859305
Directory	/workspace/27.uart_rx_oversample/latest

Test location	/workspace/coverage/default/27.uart_rx_parity_err.4028605395
Short name	T589
Test name
Test status
Simulation time	32791237603 ps
CPU time	54.3 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	200832 kb
Host	smart-f2d20dbf-30d3-458e-a922-baedb6ff888c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028605395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4028605395
Directory	/workspace/27.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/27.uart_rx_start_bit_filter.2608538095
Short name	T567
Test name
Test status
Simulation time	2076994970 ps
CPU time	1.56 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:52:34 PM PDT 24
Peak memory	196272 kb
Host	smart-eab3aa1d-6506-417e-8dfa-4c45444948de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608538095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2608538095
Directory	/workspace/27.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/27.uart_smoke.2070671603
Short name	T689
Test name
Test status
Simulation time	692989888 ps
CPU time	3.74 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:52:36 PM PDT 24
Peak memory	200472 kb
Host	smart-dd6599eb-afc2-413c-a000-8feb2e727342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070671603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2070671603
Directory	/workspace/27.uart_smoke/latest

Test location	/workspace/coverage/default/27.uart_stress_all_with_rand_reset.1009749710
Short name	T38
Test name
Test status
Simulation time	18036971925 ps
CPU time	225.62 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:56:19 PM PDT 24
Peak memory	217380 kb
Host	smart-2f1c4b9b-df82-4f12-b778-db5f822a52c3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009749710 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1009749710
Directory	/workspace/27.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.uart_tx_ovrd.1327518409
Short name	T423
Test name
Test status
Simulation time	2451471147 ps
CPU time	2.86 seconds
Started	Apr 15 02:52:29 PM PDT 24
Finished	Apr 15 02:52:33 PM PDT 24
Peak memory	199664 kb
Host	smart-758c26e3-57c3-495a-8126-8ce07a5e5cbd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327518409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1327518409
Directory	/workspace/27.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/27.uart_tx_rx.3354598058
Short name	T640
Test name
Test status
Simulation time	105067067464 ps
CPU time	162.3 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:55:21 PM PDT 24
Peak memory	200768 kb
Host	smart-933b2810-7c6e-4e77-a83c-06beb60921a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354598058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3354598058
Directory	/workspace/27.uart_tx_rx/latest

Test location	/workspace/coverage/default/271.uart_fifo_reset.287607488
Short name	T926
Test name
Test status
Simulation time	191392740492 ps
CPU time	163.84 seconds
Started	Apr 15 02:55:55 PM PDT 24
Finished	Apr 15 02:58:40 PM PDT 24
Peak memory	200856 kb
Host	smart-93c2439f-c90d-4495-a8f4-1f6a6a89b01a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287607488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.287607488
Directory	/workspace/271.uart_fifo_reset/latest

Test location	/workspace/coverage/default/272.uart_fifo_reset.2736490560
Short name	T214
Test name
Test status
Simulation time	15987434674 ps
CPU time	36.84 seconds
Started	Apr 15 02:55:55 PM PDT 24
Finished	Apr 15 02:56:33 PM PDT 24
Peak memory	200864 kb
Host	smart-33767634-5680-4d0d-9dde-8e1f62ecb074
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2736490560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2736490560
Directory	/workspace/272.uart_fifo_reset/latest

Test location	/workspace/coverage/default/273.uart_fifo_reset.3187995772
Short name	T711
Test name
Test status
Simulation time	194251678092 ps
CPU time	181.53 seconds
Started	Apr 15 02:55:53 PM PDT 24
Finished	Apr 15 02:58:55 PM PDT 24
Peak memory	200916 kb
Host	smart-080ac303-ec22-466c-b5cd-3b6bbb5b9e99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3187995772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3187995772
Directory	/workspace/273.uart_fifo_reset/latest

Test location	/workspace/coverage/default/274.uart_fifo_reset.4239665740
Short name	T3
Test name
Test status
Simulation time	56863164433 ps
CPU time	90.74 seconds
Started	Apr 15 02:55:55 PM PDT 24
Finished	Apr 15 02:57:26 PM PDT 24
Peak memory	200800 kb
Host	smart-7c5f7350-0222-45d1-9898-cd8a12311b5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4239665740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4239665740
Directory	/workspace/274.uart_fifo_reset/latest

Test location	/workspace/coverage/default/275.uart_fifo_reset.2574892211
Short name	T353
Test name
Test status
Simulation time	106292336220 ps
CPU time	332.54 seconds
Started	Apr 15 02:55:54 PM PDT 24
Finished	Apr 15 03:01:27 PM PDT 24
Peak memory	200872 kb
Host	smart-51a81cfa-0f64-4dcd-8e21-42e5874a97a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574892211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2574892211
Directory	/workspace/275.uart_fifo_reset/latest

Test location	/workspace/coverage/default/276.uart_fifo_reset.1623483714
Short name	T603
Test name
Test status
Simulation time	22359072755 ps
CPU time	44.04 seconds
Started	Apr 15 02:55:58 PM PDT 24
Finished	Apr 15 02:56:43 PM PDT 24
Peak memory	200900 kb
Host	smart-fde8ba33-b30b-4cf7-8ecf-4a1e6f87ae6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623483714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1623483714
Directory	/workspace/276.uart_fifo_reset/latest

Test location	/workspace/coverage/default/277.uart_fifo_reset.482532559
Short name	T738
Test name
Test status
Simulation time	42809692942 ps
CPU time	36.3 seconds
Started	Apr 15 02:55:59 PM PDT 24
Finished	Apr 15 02:56:36 PM PDT 24
Peak memory	200580 kb
Host	smart-9411143f-023a-4f3c-af61-3bd29222aaf2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482532559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.482532559
Directory	/workspace/277.uart_fifo_reset/latest

Test location	/workspace/coverage/default/278.uart_fifo_reset.2855620182
Short name	T286
Test name
Test status
Simulation time	70682253355 ps
CPU time	116.56 seconds
Started	Apr 15 02:55:59 PM PDT 24
Finished	Apr 15 02:57:57 PM PDT 24
Peak memory	200920 kb
Host	smart-88ce434b-3bf0-48b4-a19b-1ef01b469521
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855620182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2855620182
Directory	/workspace/278.uart_fifo_reset/latest

Test location	/workspace/coverage/default/279.uart_fifo_reset.1470982725
Short name	T519
Test name
Test status
Simulation time	31551106569 ps
CPU time	58.62 seconds
Started	Apr 15 02:55:57 PM PDT 24
Finished	Apr 15 02:56:56 PM PDT 24
Peak memory	200924 kb
Host	smart-e5b9d592-79d2-4b3f-9e83-2cf905f38a5b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470982725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1470982725
Directory	/workspace/279.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_alert_test.1440361383
Short name	T432
Test name
Test status
Simulation time	21034994 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:52:40 PM PDT 24
Peak memory	195712 kb
Host	smart-555c28f8-6304-4eba-8210-a674a463b255
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440361383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1440361383
Directory	/workspace/28.uart_alert_test/latest

Test location	/workspace/coverage/default/28.uart_fifo_full.125605855
Short name	T43
Test name
Test status
Simulation time	162537298972 ps
CPU time	28.09 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:53:01 PM PDT 24
Peak memory	200796 kb
Host	smart-673a1ae4-bb1d-4cd9-b742-9f4477f40227
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125605855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.125605855
Directory	/workspace/28.uart_fifo_full/latest

Test location	/workspace/coverage/default/28.uart_fifo_reset.3298671968
Short name	T1068
Test name
Test status
Simulation time	40010264007 ps
CPU time	39.27 seconds
Started	Apr 15 02:52:38 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	200892 kb
Host	smart-13f3852f-52bf-43fe-816a-9595ae456b80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298671968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3298671968
Directory	/workspace/28.uart_fifo_reset/latest

Test location	/workspace/coverage/default/28.uart_intr.4038570270
Short name	T879
Test name
Test status
Simulation time	25975842015 ps
CPU time	14.5 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:52:54 PM PDT 24
Peak memory	200608 kb
Host	smart-ac0ce1da-0702-4f35-980b-cee19bcd6283
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038570270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4038570270
Directory	/workspace/28.uart_intr/latest

Test location	/workspace/coverage/default/28.uart_long_xfer_wo_dly.3220353596
Short name	T789
Test name
Test status
Simulation time	71890920420 ps
CPU time	376.04 seconds
Started	Apr 15 02:52:34 PM PDT 24
Finished	Apr 15 02:58:51 PM PDT 24
Peak memory	200900 kb
Host	smart-bb1fe987-c8ec-4e3e-bbda-7dfa470369e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3220353596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3220353596
Directory	/workspace/28.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/28.uart_loopback.2105533763
Short name	T745
Test name
Test status
Simulation time	3226416230 ps
CPU time	1.31 seconds
Started	Apr 15 02:52:35 PM PDT 24
Finished	Apr 15 02:52:37 PM PDT 24
Peak memory	198172 kb
Host	smart-1522acce-bdc0-47b2-b797-ac17eb59b067
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105533763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2105533763
Directory	/workspace/28.uart_loopback/latest

Test location	/workspace/coverage/default/28.uart_noise_filter.478614454
Short name	T1184
Test name
Test status
Simulation time	34293503848 ps
CPU time	66.8 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	201072 kb
Host	smart-ee0c6387-8bcd-402c-adc7-deac5fa3fb4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478614454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.478614454
Directory	/workspace/28.uart_noise_filter/latest

Test location	/workspace/coverage/default/28.uart_perf.965849836
Short name	T617
Test name
Test status
Simulation time	6471193413 ps
CPU time	266.95 seconds
Started	Apr 15 02:52:32 PM PDT 24
Finished	Apr 15 02:57:00 PM PDT 24
Peak memory	200940 kb
Host	smart-f5813250-8bd4-450a-91e0-03d3f2854379
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=965849836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.965849836
Directory	/workspace/28.uart_perf/latest

Test location	/workspace/coverage/default/28.uart_rx_oversample.514787066
Short name	T533
Test name
Test status
Simulation time	5567275281 ps
CPU time	13.39 seconds
Started	Apr 15 02:52:35 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	200240 kb
Host	smart-ea399054-4e42-45a6-94d0-c24bf4529846
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=514787066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.514787066
Directory	/workspace/28.uart_rx_oversample/latest

Test location	/workspace/coverage/default/28.uart_rx_parity_err.3313768223
Short name	T349
Test name
Test status
Simulation time	91769556413 ps
CPU time	37.13 seconds
Started	Apr 15 02:52:34 PM PDT 24
Finished	Apr 15 02:53:12 PM PDT 24
Peak memory	200888 kb
Host	smart-8d41f013-9fef-45c7-9570-61d7c04a7452
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3313768223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3313768223
Directory	/workspace/28.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/28.uart_rx_start_bit_filter.8223568
Short name	T973
Test name
Test status
Simulation time	4460599518 ps
CPU time	1.42 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:52:36 PM PDT 24
Peak memory	197156 kb
Host	smart-a44a62fc-9c49-4246-8681-dc2c3ce9a22a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8223568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.8223568
Directory	/workspace/28.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/28.uart_smoke.1749195204
Short name	T670
Test name
Test status
Simulation time	482996746 ps
CPU time	2.13 seconds
Started	Apr 15 02:52:34 PM PDT 24
Finished	Apr 15 02:52:37 PM PDT 24
Peak memory	200228 kb
Host	smart-1675aafb-330b-4e57-95d5-a0bf3408e196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749195204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1749195204
Directory	/workspace/28.uart_smoke/latest

Test location	/workspace/coverage/default/28.uart_stress_all.3804995812
Short name	T920
Test name
Test status
Simulation time	57945375248 ps
CPU time	282.93 seconds
Started	Apr 15 02:52:38 PM PDT 24
Finished	Apr 15 02:57:23 PM PDT 24
Peak memory	200632 kb
Host	smart-b08352d6-bc51-4733-a9a5-35835372e7ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804995812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3804995812
Directory	/workspace/28.uart_stress_all/latest

Test location	/workspace/coverage/default/28.uart_stress_all_with_rand_reset.2061894129
Short name	T915
Test name
Test status
Simulation time	190662047923 ps
CPU time	493.15 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 03:00:51 PM PDT 24
Peak memory	225780 kb
Host	smart-bb9612c8-3e8e-40a6-b1c8-0af70a409097
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061894129 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2061894129
Directory	/workspace/28.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.uart_tx_ovrd.2774751055
Short name	T895
Test name
Test status
Simulation time	12411652521 ps
CPU time	30.02 seconds
Started	Apr 15 02:52:35 PM PDT 24
Finished	Apr 15 02:53:05 PM PDT 24
Peak memory	200812 kb
Host	smart-906a66c9-4905-4188-ae98-4bf0c541da09
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774751055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2774751055
Directory	/workspace/28.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/28.uart_tx_rx.752785820
Short name	T759
Test name
Test status
Simulation time	6938873883 ps
CPU time	12.6 seconds
Started	Apr 15 02:52:33 PM PDT 24
Finished	Apr 15 02:52:46 PM PDT 24
Peak memory	200880 kb
Host	smart-781cbd03-e5c1-4417-b3b1-e085f6125548
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752785820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.752785820
Directory	/workspace/28.uart_tx_rx/latest

Test location	/workspace/coverage/default/280.uart_fifo_reset.2880466209
Short name	T601
Test name
Test status
Simulation time	223855953441 ps
CPU time	44.36 seconds
Started	Apr 15 02:55:59 PM PDT 24
Finished	Apr 15 02:56:44 PM PDT 24
Peak memory	200524 kb
Host	smart-23adbdfd-7a6d-4385-a670-44ac8d142881
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880466209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2880466209
Directory	/workspace/280.uart_fifo_reset/latest

Test location	/workspace/coverage/default/281.uart_fifo_reset.3345379298
Short name	T1122
Test name
Test status
Simulation time	146355241623 ps
CPU time	182.73 seconds
Started	Apr 15 02:55:59 PM PDT 24
Finished	Apr 15 02:59:02 PM PDT 24
Peak memory	200904 kb
Host	smart-c41c709f-8cf0-4dca-a1ce-45bc80b60dd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345379298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3345379298
Directory	/workspace/281.uart_fifo_reset/latest

Test location	/workspace/coverage/default/282.uart_fifo_reset.1299197853
Short name	T225
Test name
Test status
Simulation time	29959645208 ps
CPU time	14.1 seconds
Started	Apr 15 02:55:59 PM PDT 24
Finished	Apr 15 02:56:13 PM PDT 24
Peak memory	200984 kb
Host	smart-d2321524-f729-44e7-af46-7f160a5cec6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299197853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1299197853
Directory	/workspace/282.uart_fifo_reset/latest

Test location	/workspace/coverage/default/283.uart_fifo_reset.3087550473
Short name	T667
Test name
Test status
Simulation time	43457767036 ps
CPU time	18.19 seconds
Started	Apr 15 02:56:00 PM PDT 24
Finished	Apr 15 02:56:19 PM PDT 24
Peak memory	200848 kb
Host	smart-4fa36789-d69f-4a3f-beef-71783a0cfde0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087550473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3087550473
Directory	/workspace/283.uart_fifo_reset/latest

Test location	/workspace/coverage/default/284.uart_fifo_reset.3535765182
Short name	T457
Test name
Test status
Simulation time	16235546688 ps
CPU time	14.47 seconds
Started	Apr 15 02:56:00 PM PDT 24
Finished	Apr 15 02:56:15 PM PDT 24
Peak memory	200612 kb
Host	smart-0fcb9109-1985-4ae7-9546-b25a78f8b9fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535765182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3535765182
Directory	/workspace/284.uart_fifo_reset/latest

Test location	/workspace/coverage/default/285.uart_fifo_reset.3294969420
Short name	T1157
Test name
Test status
Simulation time	170405436523 ps
CPU time	295.63 seconds
Started	Apr 15 02:55:58 PM PDT 24
Finished	Apr 15 03:00:54 PM PDT 24
Peak memory	200920 kb
Host	smart-1e0a6d8d-6e1b-4adf-b2bb-480f58f89e6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294969420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3294969420
Directory	/workspace/285.uart_fifo_reset/latest

Test location	/workspace/coverage/default/286.uart_fifo_reset.56998532
Short name	T210
Test name
Test status
Simulation time	32016195181 ps
CPU time	50.52 seconds
Started	Apr 15 02:55:58 PM PDT 24
Finished	Apr 15 02:56:50 PM PDT 24
Peak memory	200720 kb
Host	smart-9cea887e-b3ae-4d2a-a551-61a5f264919c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56998532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.56998532
Directory	/workspace/286.uart_fifo_reset/latest

Test location	/workspace/coverage/default/287.uart_fifo_reset.902404473
Short name	T450
Test name
Test status
Simulation time	159280420051 ps
CPU time	58.89 seconds
Started	Apr 15 02:56:03 PM PDT 24
Finished	Apr 15 02:57:02 PM PDT 24
Peak memory	200472 kb
Host	smart-8b5e08c3-cedb-4df8-bf36-860424929220
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902404473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.902404473
Directory	/workspace/287.uart_fifo_reset/latest

Test location	/workspace/coverage/default/288.uart_fifo_reset.2777916230
Short name	T962
Test name
Test status
Simulation time	27294267085 ps
CPU time	42.69 seconds
Started	Apr 15 02:56:03 PM PDT 24
Finished	Apr 15 02:56:46 PM PDT 24
Peak memory	200912 kb
Host	smart-eb2c6a82-d470-4935-99b1-44c3bdaa9ad0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777916230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2777916230
Directory	/workspace/288.uart_fifo_reset/latest

Test location	/workspace/coverage/default/289.uart_fifo_reset.3727307799
Short name	T222
Test name
Test status
Simulation time	16531311390 ps
CPU time	29.16 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:56:34 PM PDT 24
Peak memory	200632 kb
Host	smart-b9ba096a-d4c2-4354-b88c-2141452ed48c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727307799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3727307799
Directory	/workspace/289.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_alert_test.1188061694
Short name	T744
Test name
Test status
Simulation time	47708235 ps
CPU time	0.58 seconds
Started	Apr 15 02:52:42 PM PDT 24
Finished	Apr 15 02:52:43 PM PDT 24
Peak memory	196244 kb
Host	smart-371c811c-3d13-448f-8479-abf95c91d371
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188061694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1188061694
Directory	/workspace/29.uart_alert_test/latest

Test location	/workspace/coverage/default/29.uart_fifo_full.973558170
Short name	T155
Test name
Test status
Simulation time	55199027300 ps
CPU time	21.42 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:53:01 PM PDT 24
Peak memory	200824 kb
Host	smart-30b63be5-517f-42f9-87cc-db7d42111d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973558170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.973558170
Directory	/workspace/29.uart_fifo_full/latest

Test location	/workspace/coverage/default/29.uart_fifo_overflow.1622482442
Short name	T1176
Test name
Test status
Simulation time	41128493018 ps
CPU time	37.13 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:53:15 PM PDT 24
Peak memory	200876 kb
Host	smart-3fc1b59c-57be-404c-9bb2-c313a89e3e49
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622482442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1622482442
Directory	/workspace/29.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/29.uart_fifo_reset.2201892140
Short name	T333
Test name
Test status
Simulation time	187636979066 ps
CPU time	74.91 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 02:53:53 PM PDT 24
Peak memory	200860 kb
Host	smart-a8351c8e-f058-4657-a30d-ab03605e3137
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201892140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2201892140
Directory	/workspace/29.uart_fifo_reset/latest

Test location	/workspace/coverage/default/29.uart_intr.1109984959
Short name	T411
Test name
Test status
Simulation time	5216277174 ps
CPU time	4.53 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 02:52:42 PM PDT 24
Peak memory	198764 kb
Host	smart-8f4734a6-4d7b-4f4f-a988-170e6eb394d1
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109984959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1109984959
Directory	/workspace/29.uart_intr/latest

Test location	/workspace/coverage/default/29.uart_long_xfer_wo_dly.165959237
Short name	T1121
Test name
Test status
Simulation time	89537602240 ps
CPU time	171.31 seconds
Started	Apr 15 02:52:43 PM PDT 24
Finished	Apr 15 02:55:36 PM PDT 24
Peak memory	200836 kb
Host	smart-53162131-fe73-42ad-8120-2adf20048e10
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=165959237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.165959237
Directory	/workspace/29.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/29.uart_loopback.3476415827
Short name	T503
Test name
Test status
Simulation time	7025658149 ps
CPU time	7.08 seconds
Started	Apr 15 02:52:44 PM PDT 24
Finished	Apr 15 02:52:52 PM PDT 24
Peak memory	199920 kb
Host	smart-0d3c68b2-96e1-475b-a521-0cff0bebf1a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3476415827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3476415827
Directory	/workspace/29.uart_loopback/latest

Test location	/workspace/coverage/default/29.uart_noise_filter.3214348310
Short name	T553
Test name
Test status
Simulation time	78202461952 ps
CPU time	136.2 seconds
Started	Apr 15 02:52:38 PM PDT 24
Finished	Apr 15 02:54:56 PM PDT 24
Peak memory	201028 kb
Host	smart-2ecf96be-911d-4391-a0ba-58a2639ba468
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3214348310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3214348310
Directory	/workspace/29.uart_noise_filter/latest

Test location	/workspace/coverage/default/29.uart_perf.435084639
Short name	T1028
Test name
Test status
Simulation time	15966322732 ps
CPU time	175.27 seconds
Started	Apr 15 02:52:44 PM PDT 24
Finished	Apr 15 02:55:40 PM PDT 24
Peak memory	200908 kb
Host	smart-b6456637-3d67-412b-ab89-644e7210c493
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=435084639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.435084639
Directory	/workspace/29.uart_perf/latest

Test location	/workspace/coverage/default/29.uart_rx_oversample.3211937348
Short name	T1161
Test name
Test status
Simulation time	7534242935 ps
CPU time	6.09 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 02:52:44 PM PDT 24
Peak memory	199096 kb
Host	smart-0515d9fd-644d-43dd-b4ad-ea9a5705c8ed
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3211937348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.3211937348
Directory	/workspace/29.uart_rx_oversample/latest

Test location	/workspace/coverage/default/29.uart_rx_parity_err.1752554829
Short name	T145
Test name
Test status
Simulation time	152600886741 ps
CPU time	252.82 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 02:56:49 PM PDT 24
Peak memory	200768 kb
Host	smart-106998bc-4729-418c-8b20-360cff395848
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752554829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1752554829
Directory	/workspace/29.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/29.uart_rx_start_bit_filter.3935801181
Short name	T607
Test name
Test status
Simulation time	4254764626 ps
CPU time	2.16 seconds
Started	Apr 15 02:52:36 PM PDT 24
Finished	Apr 15 02:52:39 PM PDT 24
Peak memory	196900 kb
Host	smart-2101f0a9-79ff-4c76-94d9-fe0069638c1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935801181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3935801181
Directory	/workspace/29.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/29.uart_smoke.1855817142
Short name	T1127
Test name
Test status
Simulation time	291233441 ps
CPU time	1.55 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	199712 kb
Host	smart-20a02b9a-1c5f-420f-bb28-f2119f0472d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855817142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1855817142
Directory	/workspace/29.uart_smoke/latest

Test location	/workspace/coverage/default/29.uart_stress_all.4003685261
Short name	T451
Test name
Test status
Simulation time	351220080563 ps
CPU time	826.78 seconds
Started	Apr 15 02:52:43 PM PDT 24
Finished	Apr 15 03:06:30 PM PDT 24
Peak memory	200788 kb
Host	smart-958658ac-b3e9-40de-ba55-63a0cb8faf7c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003685261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4003685261
Directory	/workspace/29.uart_stress_all/latest

Test location	/workspace/coverage/default/29.uart_stress_all_with_rand_reset.1767556198
Short name	T580
Test name
Test status
Simulation time	39177328625 ps
CPU time	221.27 seconds
Started	Apr 15 02:52:42 PM PDT 24
Finished	Apr 15 02:56:25 PM PDT 24
Peak memory	217508 kb
Host	smart-6abd92f4-5db6-4aa7-8858-e4a1bed2e542
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767556198 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1767556198
Directory	/workspace/29.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.uart_tx_ovrd.3340091054
Short name	T1038
Test name
Test status
Simulation time	913944917 ps
CPU time	2.84 seconds
Started	Apr 15 02:52:37 PM PDT 24
Finished	Apr 15 02:52:42 PM PDT 24
Peak memory	199480 kb
Host	smart-abddce67-972e-4d62-bf4d-36cca9b1d64f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340091054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3340091054
Directory	/workspace/29.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/29.uart_tx_rx.698865262
Short name	T626
Test name
Test status
Simulation time	45497055251 ps
CPU time	72.6 seconds
Started	Apr 15 02:52:38 PM PDT 24
Finished	Apr 15 02:53:52 PM PDT 24
Peak memory	200836 kb
Host	smart-94ad94fe-ef63-480d-b627-eda6e827a4d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698865262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.698865262
Directory	/workspace/29.uart_tx_rx/latest

Test location	/workspace/coverage/default/290.uart_fifo_reset.477507982
Short name	T540
Test name
Test status
Simulation time	17163445599 ps
CPU time	25.65 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:56:30 PM PDT 24
Peak memory	200464 kb
Host	smart-0af70109-7eda-4e4a-b95b-7711fe51050a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477507982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.477507982
Directory	/workspace/290.uart_fifo_reset/latest

Test location	/workspace/coverage/default/292.uart_fifo_reset.2428639194
Short name	T923
Test name
Test status
Simulation time	96863576373 ps
CPU time	238.37 seconds
Started	Apr 15 02:56:07 PM PDT 24
Finished	Apr 15 03:00:06 PM PDT 24
Peak memory	200860 kb
Host	smart-b07aeda9-4390-4652-96ea-59f82ed222f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428639194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2428639194
Directory	/workspace/292.uart_fifo_reset/latest

Test location	/workspace/coverage/default/293.uart_fifo_reset.3274196432
Short name	T1177
Test name
Test status
Simulation time	26865302779 ps
CPU time	18.22 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:56:23 PM PDT 24
Peak memory	200552 kb
Host	smart-509e0031-a9f6-40cc-8f04-1cf64c245e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274196432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3274196432
Directory	/workspace/293.uart_fifo_reset/latest

Test location	/workspace/coverage/default/294.uart_fifo_reset.540950130
Short name	T1149
Test name
Test status
Simulation time	31951635264 ps
CPU time	33.82 seconds
Started	Apr 15 02:56:03 PM PDT 24
Finished	Apr 15 02:56:38 PM PDT 24
Peak memory	200888 kb
Host	smart-ccd76a3d-c44e-49ea-ab70-2d03993cd1b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540950130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.540950130
Directory	/workspace/294.uart_fifo_reset/latest

Test location	/workspace/coverage/default/295.uart_fifo_reset.1554482374
Short name	T181
Test name
Test status
Simulation time	92528987518 ps
CPU time	44.79 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:56:49 PM PDT 24
Peak memory	200728 kb
Host	smart-3e1e55db-f6c2-4a45-b168-3807f9fcf74f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1554482374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1554482374
Directory	/workspace/295.uart_fifo_reset/latest

Test location	/workspace/coverage/default/296.uart_fifo_reset.772038936
Short name	T817
Test name
Test status
Simulation time	58806231384 ps
CPU time	77.72 seconds
Started	Apr 15 02:56:03 PM PDT 24
Finished	Apr 15 02:57:22 PM PDT 24
Peak memory	200888 kb
Host	smart-8c4afb78-9f4f-4ca8-8b21-19f97658163c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772038936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.772038936
Directory	/workspace/296.uart_fifo_reset/latest

Test location	/workspace/coverage/default/297.uart_fifo_reset.2345697488
Short name	T648
Test name
Test status
Simulation time	124670433109 ps
CPU time	207.53 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:59:32 PM PDT 24
Peak memory	200884 kb
Host	smart-0f5f3540-2ea6-404d-909d-01838574c9a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345697488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2345697488
Directory	/workspace/297.uart_fifo_reset/latest

Test location	/workspace/coverage/default/298.uart_fifo_reset.2186434958
Short name	T173
Test name
Test status
Simulation time	69134145643 ps
CPU time	27.17 seconds
Started	Apr 15 02:56:05 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200864 kb
Host	smart-3a695fe5-01be-4fd6-8d63-ca681440e755
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186434958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2186434958
Directory	/workspace/298.uart_fifo_reset/latest

Test location	/workspace/coverage/default/299.uart_fifo_reset.1143445876
Short name	T224
Test name
Test status
Simulation time	31595383018 ps
CPU time	52.09 seconds
Started	Apr 15 02:56:04 PM PDT 24
Finished	Apr 15 02:56:57 PM PDT 24
Peak memory	200924 kb
Host	smart-a8856a5f-dc0d-4139-a38e-d1d411c88c02
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143445876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1143445876
Directory	/workspace/299.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_alert_test.1590471933
Short name	T29
Test name
Test status
Simulation time	14814705 ps
CPU time	0.61 seconds
Started	Apr 15 02:51:21 PM PDT 24
Finished	Apr 15 02:51:23 PM PDT 24
Peak memory	196184 kb
Host	smart-368fd5c0-af51-4582-9005-0f7d00e74585
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590471933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1590471933
Directory	/workspace/3.uart_alert_test/latest

Test location	/workspace/coverage/default/3.uart_fifo_full.528985295
Short name	T821
Test name
Test status
Simulation time	79227890530 ps
CPU time	145.32 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:53:50 PM PDT 24
Peak memory	200812 kb
Host	smart-23b60210-98e2-441e-b3a4-95ab84aad198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528985295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.528985295
Directory	/workspace/3.uart_fifo_full/latest

Test location	/workspace/coverage/default/3.uart_fifo_overflow.1994490742
Short name	T594
Test name
Test status
Simulation time	26151397145 ps
CPU time	23.19 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 02:51:41 PM PDT 24
Peak memory	200820 kb
Host	smart-cbe5bcc3-d7eb-44e7-ba73-7d0be0a740c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994490742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1994490742
Directory	/workspace/3.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/3.uart_fifo_reset.2439543940
Short name	T176
Test name
Test status
Simulation time	14868778059 ps
CPU time	28.57 seconds
Started	Apr 15 02:51:20 PM PDT 24
Finished	Apr 15 02:51:49 PM PDT 24
Peak memory	200884 kb
Host	smart-076f1f75-ae61-401c-a8ec-b00613336fee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2439543940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2439543940
Directory	/workspace/3.uart_fifo_reset/latest

Test location	/workspace/coverage/default/3.uart_intr.2870906832
Short name	T756
Test name
Test status
Simulation time	106410841071 ps
CPU time	49.1 seconds
Started	Apr 15 02:51:28 PM PDT 24
Finished	Apr 15 02:52:18 PM PDT 24
Peak memory	200064 kb
Host	smart-dac0cf69-57ff-48f6-a16c-49d651332df4
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870906832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2870906832
Directory	/workspace/3.uart_intr/latest

Test location	/workspace/coverage/default/3.uart_long_xfer_wo_dly.1348234444
Short name	T844
Test name
Test status
Simulation time	138667932999 ps
CPU time	729.37 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 03:03:42 PM PDT 24
Peak memory	200924 kb
Host	smart-be86497f-0f37-42c4-8eb7-f17bfb6a6520
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1348234444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1348234444
Directory	/workspace/3.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/3.uart_loopback.2947077737
Short name	T996
Test name
Test status
Simulation time	4515201727 ps
CPU time	9.42 seconds
Started	Apr 15 02:51:23 PM PDT 24
Finished	Apr 15 02:51:33 PM PDT 24
Peak memory	199484 kb
Host	smart-d3d079a0-5b63-4ad7-ae07-e8399902979e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947077737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2947077737
Directory	/workspace/3.uart_loopback/latest

Test location	/workspace/coverage/default/3.uart_noise_filter.435957276
Short name	T516
Test name
Test status
Simulation time	126746480533 ps
CPU time	121.49 seconds
Started	Apr 15 02:51:18 PM PDT 24
Finished	Apr 15 02:53:20 PM PDT 24
Peak memory	200608 kb
Host	smart-f498e8a7-1790-4f2e-b7e6-862c2597fba0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435957276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.435957276
Directory	/workspace/3.uart_noise_filter/latest

Test location	/workspace/coverage/default/3.uart_perf.3637630347
Short name	T972
Test name
Test status
Simulation time	2404992094 ps
CPU time	14.65 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:51:56 PM PDT 24
Peak memory	200668 kb
Host	smart-94b0d347-b9c9-4ed7-bb9b-b8e817ceaa43
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3637630347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3637630347
Directory	/workspace/3.uart_perf/latest

Test location	/workspace/coverage/default/3.uart_rx_oversample.2488353656
Short name	T362
Test name
Test status
Simulation time	4044449513 ps
CPU time	9.26 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:51:34 PM PDT 24
Peak memory	199296 kb
Host	smart-97147cc9-9fb4-4c29-884e-762f3157fdc8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2488353656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2488353656
Directory	/workspace/3.uart_rx_oversample/latest

Test location	/workspace/coverage/default/3.uart_rx_parity_err.3993415991
Short name	T769
Test name
Test status
Simulation time	111591654312 ps
CPU time	187.44 seconds
Started	Apr 15 02:51:22 PM PDT 24
Finished	Apr 15 02:54:30 PM PDT 24
Peak memory	200844 kb
Host	smart-83e58cf4-1837-4bfb-8f4c-8f478a4118af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993415991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3993415991
Directory	/workspace/3.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/3.uart_rx_start_bit_filter.184352062
Short name	T530
Test name
Test status
Simulation time	3697651408 ps
CPU time	3.32 seconds
Started	Apr 15 02:51:16 PM PDT 24
Finished	Apr 15 02:51:20 PM PDT 24
Peak memory	197176 kb
Host	smart-4159e6dc-9822-4c3c-be7c-c5e519d0e4d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184352062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.184352062
Directory	/workspace/3.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/3.uart_sec_cm.1672017304
Short name	T31
Test name
Test status
Simulation time	389980555 ps
CPU time	0.88 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:51:34 PM PDT 24
Peak memory	219044 kb
Host	smart-f477b842-39d3-44b3-b708-02d59a878da0
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672017304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1672017304
Directory	/workspace/3.uart_sec_cm/latest

Test location	/workspace/coverage/default/3.uart_smoke.459947371
Short name	T381
Test name
Test status
Simulation time	572286566 ps
CPU time	1.83 seconds
Started	Apr 15 02:51:15 PM PDT 24
Finished	Apr 15 02:51:18 PM PDT 24
Peak memory	200788 kb
Host	smart-aaa18804-09a3-4fe4-9be9-23692a97cad9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459947371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.459947371
Directory	/workspace/3.uart_smoke/latest

Test location	/workspace/coverage/default/3.uart_stress_all.160198030
Short name	T864
Test name
Test status
Simulation time	268557418372 ps
CPU time	215 seconds
Started	Apr 15 02:51:28 PM PDT 24
Finished	Apr 15 02:55:03 PM PDT 24
Peak memory	200788 kb
Host	smart-9eec0149-be68-4e01-bc45-2befc0b738f7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160198030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.160198030
Directory	/workspace/3.uart_stress_all/latest

Test location	/workspace/coverage/default/3.uart_tx_ovrd.567518022
Short name	T855
Test name
Test status
Simulation time	2452349162 ps
CPU time	2.51 seconds
Started	Apr 15 02:51:25 PM PDT 24
Finished	Apr 15 02:51:28 PM PDT 24
Peak memory	199396 kb
Host	smart-e0ffef2b-0d55-4679-835a-088fa6da574d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567518022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.567518022
Directory	/workspace/3.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/3.uart_tx_rx.3657091240
Short name	T559
Test name
Test status
Simulation time	79258660912 ps
CPU time	142.19 seconds
Started	Apr 15 02:51:17 PM PDT 24
Finished	Apr 15 02:53:40 PM PDT 24
Peak memory	200884 kb
Host	smart-5c57d611-9d06-41f3-8aa9-910e5a50efb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657091240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3657091240
Directory	/workspace/3.uart_tx_rx/latest

Test location	/workspace/coverage/default/30.uart_alert_test.281549670
Short name	T586
Test name
Test status
Simulation time	12354440 ps
CPU time	0.55 seconds
Started	Apr 15 02:52:46 PM PDT 24
Finished	Apr 15 02:52:47 PM PDT 24
Peak memory	196112 kb
Host	smart-caf8f121-d679-4bad-95da-a8da54af8b19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281549670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.281549670
Directory	/workspace/30.uart_alert_test/latest

Test location	/workspace/coverage/default/30.uart_fifo_full.2137297685
Short name	T1004
Test name
Test status
Simulation time	22707625734 ps
CPU time	11.55 seconds
Started	Apr 15 02:52:41 PM PDT 24
Finished	Apr 15 02:52:53 PM PDT 24
Peak memory	200916 kb
Host	smart-bd9ef08e-8924-43ed-b6ba-7ce2535f9e4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2137297685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2137297685
Directory	/workspace/30.uart_fifo_full/latest

Test location	/workspace/coverage/default/30.uart_fifo_overflow.2816052754
Short name	T135
Test name
Test status
Simulation time	52298215920 ps
CPU time	52.68 seconds
Started	Apr 15 02:52:41 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	200864 kb
Host	smart-cb2a0a94-a219-46c6-8a45-95a0f7352eb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816052754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2816052754
Directory	/workspace/30.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/30.uart_fifo_reset.4150961732
Short name	T1141
Test name
Test status
Simulation time	32310832037 ps
CPU time	57.62 seconds
Started	Apr 15 02:52:43 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	200848 kb
Host	smart-eb23d9f6-fdf3-430c-bbea-79318ecaa025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150961732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4150961732
Directory	/workspace/30.uart_fifo_reset/latest

Test location	/workspace/coverage/default/30.uart_intr.2670608002
Short name	T1000
Test name
Test status
Simulation time	9873539263 ps
CPU time	18.14 seconds
Started	Apr 15 02:52:44 PM PDT 24
Finished	Apr 15 02:53:03 PM PDT 24
Peak memory	200424 kb
Host	smart-838dc901-6d50-4dc2-8acf-d1148c718032
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670608002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2670608002
Directory	/workspace/30.uart_intr/latest

Test location	/workspace/coverage/default/30.uart_long_xfer_wo_dly.1511481619
Short name	T527
Test name
Test status
Simulation time	53736502769 ps
CPU time	235.7 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:56:44 PM PDT 24
Peak memory	200896 kb
Host	smart-5c1b8392-0630-4591-b60d-10e8eebce903
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1511481619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1511481619
Directory	/workspace/30.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/30.uart_loopback.1234174818
Short name	T1048
Test name
Test status
Simulation time	3744328761 ps
CPU time	2.55 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:52:52 PM PDT 24
Peak memory	198888 kb
Host	smart-5c72c0fb-9272-407a-85e2-0fb949e09196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234174818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1234174818
Directory	/workspace/30.uart_loopback/latest

Test location	/workspace/coverage/default/30.uart_noise_filter.1148114031
Short name	T578
Test name
Test status
Simulation time	114807496600 ps
CPU time	48.84 seconds
Started	Apr 15 02:52:45 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	200816 kb
Host	smart-bda1ed26-fd3a-41a7-9e4f-00c98e5eebf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148114031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1148114031
Directory	/workspace/30.uart_noise_filter/latest

Test location	/workspace/coverage/default/30.uart_perf.1312741230
Short name	T434
Test name
Test status
Simulation time	14752088762 ps
CPU time	208.92 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 02:56:20 PM PDT 24
Peak memory	200804 kb
Host	smart-3f937ef7-d577-44fe-94ff-cd3445eb8063
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1312741230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1312741230
Directory	/workspace/30.uart_perf/latest

Test location	/workspace/coverage/default/30.uart_rx_oversample.584956442
Short name	T585
Test name
Test status
Simulation time	3520011473 ps
CPU time	7.69 seconds
Started	Apr 15 02:52:42 PM PDT 24
Finished	Apr 15 02:52:51 PM PDT 24
Peak memory	199488 kb
Host	smart-bb4444c6-72ae-446e-b122-20803732140d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=584956442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.584956442
Directory	/workspace/30.uart_rx_oversample/latest

Test location	/workspace/coverage/default/30.uart_rx_parity_err.4115293932
Short name	T694
Test name
Test status
Simulation time	84729381941 ps
CPU time	34.16 seconds
Started	Apr 15 02:52:45 PM PDT 24
Finished	Apr 15 02:53:20 PM PDT 24
Peak memory	200896 kb
Host	smart-e954a8d1-0b0f-48af-b4c2-82dec8c38d4d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115293932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.4115293932
Directory	/workspace/30.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/30.uart_rx_start_bit_filter.2537658449
Short name	T889
Test name
Test status
Simulation time	5670905476 ps
CPU time	5.52 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:52:54 PM PDT 24
Peak memory	196896 kb
Host	smart-beb4cf21-c43e-4ee9-84af-bf68ed0c90c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2537658449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2537658449
Directory	/workspace/30.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/30.uart_smoke.3161867602
Short name	T364
Test name
Test status
Simulation time	670785016 ps
CPU time	3.62 seconds
Started	Apr 15 02:52:42 PM PDT 24
Finished	Apr 15 02:52:46 PM PDT 24
Peak memory	199556 kb
Host	smart-3e552ff8-baf9-45ef-8d6c-6198197384ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161867602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3161867602
Directory	/workspace/30.uart_smoke/latest

Test location	/workspace/coverage/default/30.uart_stress_all.94298930
Short name	T854
Test name
Test status
Simulation time	40906594808 ps
CPU time	63.79 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:53:53 PM PDT 24
Peak memory	200916 kb
Host	smart-755944cd-fcdb-47e5-8011-007d65209789
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94298930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.94298930
Directory	/workspace/30.uart_stress_all/latest

Test location	/workspace/coverage/default/30.uart_tx_ovrd.1829797261
Short name	T99
Test name
Test status
Simulation time	1419005390 ps
CPU time	1.83 seconds
Started	Apr 15 02:52:46 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	199584 kb
Host	smart-1c642b22-dad5-4e47-ab67-a9d8075c84ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829797261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1829797261
Directory	/workspace/30.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/30.uart_tx_rx.334376616
Short name	T1010
Test name
Test status
Simulation time	2915877453 ps
CPU time	1.96 seconds
Started	Apr 15 02:52:44 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	199960 kb
Host	smart-a78560fa-1480-4fdc-b7b6-9c5b56941463
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334376616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.334376616
Directory	/workspace/30.uart_tx_rx/latest

Test location	/workspace/coverage/default/31.uart_alert_test.3050436386
Short name	T1036
Test name
Test status
Simulation time	11046942 ps
CPU time	0.59 seconds
Started	Apr 15 02:52:50 PM PDT 24
Finished	Apr 15 02:52:51 PM PDT 24
Peak memory	196212 kb
Host	smart-8ace772e-ecc8-4372-85ea-ee487813daa5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050436386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3050436386
Directory	/workspace/31.uart_alert_test/latest

Test location	/workspace/coverage/default/31.uart_fifo_full.2163456122
Short name	T774
Test name
Test status
Simulation time	120293569952 ps
CPU time	224.4 seconds
Started	Apr 15 02:52:47 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200836 kb
Host	smart-66275576-bc55-45ec-ad90-f9b8c2043a96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2163456122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2163456122
Directory	/workspace/31.uart_fifo_full/latest

Test location	/workspace/coverage/default/31.uart_fifo_overflow.1658358352
Short name	T664
Test name
Test status
Simulation time	67001790879 ps
CPU time	112.31 seconds
Started	Apr 15 02:52:45 PM PDT 24
Finished	Apr 15 02:54:39 PM PDT 24
Peak memory	200712 kb
Host	smart-95ed365b-8e03-4d80-8a50-0c5ed34032f9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658358352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1658358352
Directory	/workspace/31.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/31.uart_fifo_reset.3949769810
Short name	T1078
Test name
Test status
Simulation time	33633923611 ps
CPU time	33.15 seconds
Started	Apr 15 02:52:44 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	200880 kb
Host	smart-9bb6fbc3-ffba-4b62-a039-e9411399c849
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949769810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3949769810
Directory	/workspace/31.uart_fifo_reset/latest

Test location	/workspace/coverage/default/31.uart_intr.1656084211
Short name	T712
Test name
Test status
Simulation time	142202077544 ps
CPU time	228.46 seconds
Started	Apr 15 02:52:50 PM PDT 24
Finished	Apr 15 02:56:39 PM PDT 24
Peak memory	197016 kb
Host	smart-2186a3ec-20e9-4a01-af18-f505418d72bf
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656084211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1656084211
Directory	/workspace/31.uart_intr/latest

Test location	/workspace/coverage/default/31.uart_long_xfer_wo_dly.1843484825
Short name	T860
Test name
Test status
Simulation time	232853859472 ps
CPU time	567.19 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 03:02:18 PM PDT 24
Peak memory	200904 kb
Host	smart-46638f82-347a-4ccd-806f-3d723dc0106d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1843484825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1843484825
Directory	/workspace/31.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/31.uart_loopback.3422827887
Short name	T647
Test name
Test status
Simulation time	7884305396 ps
CPU time	6.02 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 02:52:58 PM PDT 24
Peak memory	200880 kb
Host	smart-875cf8a6-7081-4258-b18e-4e79c953fad7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422827887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3422827887
Directory	/workspace/31.uart_loopback/latest

Test location	/workspace/coverage/default/31.uart_noise_filter.2771744309
Short name	T339
Test name
Test status
Simulation time	27403315520 ps
CPU time	20.84 seconds
Started	Apr 15 02:52:53 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	195468 kb
Host	smart-952ba0f5-58ae-4af4-aab6-512423794d1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771744309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2771744309
Directory	/workspace/31.uart_noise_filter/latest

Test location	/workspace/coverage/default/31.uart_perf.883601946
Short name	T1112
Test name
Test status
Simulation time	20587244413 ps
CPU time	516.49 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 03:01:25 PM PDT 24
Peak memory	200904 kb
Host	smart-25007433-f244-4a6a-9c47-f63b825355f5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=883601946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.883601946
Directory	/workspace/31.uart_perf/latest

Test location	/workspace/coverage/default/31.uart_rx_oversample.3488238733
Short name	T6
Test name
Test status
Simulation time	5652675004 ps
CPU time	23.64 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:53:12 PM PDT 24
Peak memory	199044 kb
Host	smart-40b5e826-7958-4002-ac0c-ce1d60d5b6e1
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3488238733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3488238733
Directory	/workspace/31.uart_rx_oversample/latest

Test location	/workspace/coverage/default/31.uart_rx_parity_err.1750637730
Short name	T938
Test name
Test status
Simulation time	39398530269 ps
CPU time	60.1 seconds
Started	Apr 15 02:52:53 PM PDT 24
Finished	Apr 15 02:53:54 PM PDT 24
Peak memory	200864 kb
Host	smart-ce611941-0f0a-4000-8ab4-c5b91afdb947
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750637730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1750637730
Directory	/workspace/31.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/31.uart_rx_start_bit_filter.888237850
Short name	T59
Test name
Test status
Simulation time	33186131389 ps
CPU time	10.07 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 02:53:01 PM PDT 24
Peak memory	196904 kb
Host	smart-07e88792-be66-4c15-918e-5d2dd1885a55
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888237850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.888237850
Directory	/workspace/31.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/31.uart_smoke.4043994170
Short name	T824
Test name
Test status
Simulation time	960566633 ps
CPU time	2.51 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:52:51 PM PDT 24
Peak memory	199484 kb
Host	smart-1762b47e-ebb4-4701-94e9-44a9c704eb78
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043994170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4043994170
Directory	/workspace/31.uart_smoke/latest

Test location	/workspace/coverage/default/31.uart_stress_all.2766487644
Short name	T1035
Test name
Test status
Simulation time	95851354648 ps
CPU time	42.81 seconds
Started	Apr 15 02:52:52 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	200804 kb
Host	smart-687f7e83-2191-4865-a07c-56bb7aca86d5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766487644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2766487644
Directory	/workspace/31.uart_stress_all/latest

Test location	/workspace/coverage/default/31.uart_stress_all_with_rand_reset.790307201
Short name	T337
Test name
Test status
Simulation time	111015126595 ps
CPU time	388.17 seconds
Started	Apr 15 02:52:49 PM PDT 24
Finished	Apr 15 02:59:17 PM PDT 24
Peak memory	217540 kb
Host	smart-3cf54f27-076c-472c-98c9-d8c98778a221
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790307201 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.790307201
Directory	/workspace/31.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.uart_tx_ovrd.3688067336
Short name	T319
Test name
Test status
Simulation time	2754775381 ps
CPU time	1.47 seconds
Started	Apr 15 02:52:57 PM PDT 24
Finished	Apr 15 02:52:59 PM PDT 24
Peak memory	199600 kb
Host	smart-86173b09-d7b6-49a1-b7f9-6b2f65e169fd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688067336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3688067336
Directory	/workspace/31.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/31.uart_tx_rx.3503795886
Short name	T609
Test name
Test status
Simulation time	11971818673 ps
CPU time	19.08 seconds
Started	Apr 15 02:52:48 PM PDT 24
Finished	Apr 15 02:53:08 PM PDT 24
Peak memory	200836 kb
Host	smart-4a2c8afc-15c5-443a-9153-1d9e283354d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503795886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3503795886
Directory	/workspace/31.uart_tx_rx/latest

Test location	/workspace/coverage/default/32.uart_alert_test.2184999610
Short name	T1053
Test name
Test status
Simulation time	39771695 ps
CPU time	0.57 seconds
Started	Apr 15 02:52:55 PM PDT 24
Finished	Apr 15 02:52:56 PM PDT 24
Peak memory	196200 kb
Host	smart-3e3d38e3-3338-40c2-8a67-f9acc0d0ba72
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184999610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2184999610
Directory	/workspace/32.uart_alert_test/latest

Test location	/workspace/coverage/default/32.uart_fifo_full.2164322880
Short name	T1090
Test name
Test status
Simulation time	67697817871 ps
CPU time	45.71 seconds
Started	Apr 15 02:52:57 PM PDT 24
Finished	Apr 15 02:53:43 PM PDT 24
Peak memory	200648 kb
Host	smart-7e2b41ce-4c75-4224-a17a-7e5075576871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164322880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2164322880
Directory	/workspace/32.uart_fifo_full/latest

Test location	/workspace/coverage/default/32.uart_fifo_overflow.1882971527
Short name	T7
Test name
Test status
Simulation time	8578833717 ps
CPU time	15.98 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	200144 kb
Host	smart-c7aedd03-7d42-43f5-adb2-bcaaa1b17f8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882971527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1882971527
Directory	/workspace/32.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/32.uart_intr.1380137449
Short name	T723
Test name
Test status
Simulation time	57152887737 ps
CPU time	99.5 seconds
Started	Apr 15 02:52:49 PM PDT 24
Finished	Apr 15 02:54:29 PM PDT 24
Peak memory	200788 kb
Host	smart-dabcb962-d509-461b-9648-4e5e230a6e96
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380137449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1380137449
Directory	/workspace/32.uart_intr/latest

Test location	/workspace/coverage/default/32.uart_long_xfer_wo_dly.2801982268
Short name	T837
Test name
Test status
Simulation time	53818383370 ps
CPU time	107.29 seconds
Started	Apr 15 02:52:55 PM PDT 24
Finished	Apr 15 02:54:43 PM PDT 24
Peak memory	200908 kb
Host	smart-24cbbc83-890b-4fd3-9431-d2a107338268
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2801982268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2801982268
Directory	/workspace/32.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/32.uart_loopback.3820593469
Short name	T1144
Test name
Test status
Simulation time	7687153940 ps
CPU time	5.89 seconds
Started	Apr 15 02:53:00 PM PDT 24
Finished	Apr 15 02:53:06 PM PDT 24
Peak memory	200808 kb
Host	smart-3a912ff1-67a0-4b36-9fb5-9018a798995d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820593469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3820593469
Directory	/workspace/32.uart_loopback/latest

Test location	/workspace/coverage/default/32.uart_noise_filter.1604147826
Short name	T403
Test name
Test status
Simulation time	29592299272 ps
CPU time	13.43 seconds
Started	Apr 15 02:52:56 PM PDT 24
Finished	Apr 15 02:53:10 PM PDT 24
Peak memory	198576 kb
Host	smart-61e0fd40-5786-4092-8752-3713cdc74cb5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604147826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1604147826
Directory	/workspace/32.uart_noise_filter/latest

Test location	/workspace/coverage/default/32.uart_perf.2367925327
Short name	T719
Test name
Test status
Simulation time	12771391606 ps
CPU time	643.66 seconds
Started	Apr 15 02:52:59 PM PDT 24
Finished	Apr 15 03:03:43 PM PDT 24
Peak memory	200876 kb
Host	smart-e1ee5bfe-7d1c-4704-a153-32e60999596a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2367925327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2367925327
Directory	/workspace/32.uart_perf/latest

Test location	/workspace/coverage/default/32.uart_rx_oversample.4281246019
Short name	T794
Test name
Test status
Simulation time	2745206213 ps
CPU time	5.34 seconds
Started	Apr 15 02:52:52 PM PDT 24
Finished	Apr 15 02:52:58 PM PDT 24
Peak memory	199136 kb
Host	smart-542ca7e9-978c-4f48-b913-0916fa6abb41
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4281246019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4281246019
Directory	/workspace/32.uart_rx_oversample/latest

Test location	/workspace/coverage/default/32.uart_rx_parity_err.592859471
Short name	T538
Test name
Test status
Simulation time	57672554036 ps
CPU time	38.2 seconds
Started	Apr 15 02:52:55 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200840 kb
Host	smart-1688e7b4-d12e-46d3-9e81-ebe387f7154a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592859471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.592859471
Directory	/workspace/32.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/32.uart_rx_start_bit_filter.3435156843
Short name	T458
Test name
Test status
Simulation time	5954857563 ps
CPU time	10.47 seconds
Started	Apr 15 02:52:53 PM PDT 24
Finished	Apr 15 02:53:04 PM PDT 24
Peak memory	196936 kb
Host	smart-5394cb1d-fadc-46f0-a590-17d1149fdc6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435156843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3435156843
Directory	/workspace/32.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/32.uart_smoke.872770117
Short name	T441
Test name
Test status
Simulation time	6122819544 ps
CPU time	7.42 seconds
Started	Apr 15 02:52:52 PM PDT 24
Finished	Apr 15 02:53:00 PM PDT 24
Peak memory	200712 kb
Host	smart-f829c377-667b-44b4-a510-12d7435aa7d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872770117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.872770117
Directory	/workspace/32.uart_smoke/latest

Test location	/workspace/coverage/default/32.uart_stress_all.407705868
Short name	T175
Test name
Test status
Simulation time	314374188085 ps
CPU time	267.7 seconds
Started	Apr 15 02:52:55 PM PDT 24
Finished	Apr 15 02:57:23 PM PDT 24
Peak memory	200856 kb
Host	smart-28ae9e57-7f6f-49c9-921d-6a2e9346470a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407705868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.407705868
Directory	/workspace/32.uart_stress_all/latest

Test location	/workspace/coverage/default/32.uart_stress_all_with_rand_reset.1363055821
Short name	T992
Test name
Test status
Simulation time	557691707892 ps
CPU time	429.79 seconds
Started	Apr 15 02:52:57 PM PDT 24
Finished	Apr 15 03:00:08 PM PDT 24
Peak memory	217352 kb
Host	smart-bfcd6006-c4ec-4c4c-b5ce-216ee07ca705
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363055821 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1363055821
Directory	/workspace/32.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.uart_tx_ovrd.2384392350
Short name	T1126
Test name
Test status
Simulation time	967017063 ps
CPU time	3.13 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:53:02 PM PDT 24
Peak memory	200712 kb
Host	smart-85d4ae87-869b-4f2d-af26-b60e16dda9ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384392350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2384392350
Directory	/workspace/32.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/32.uart_tx_rx.3967345827
Short name	T489
Test name
Test status
Simulation time	8358196374 ps
CPU time	14.21 seconds
Started	Apr 15 02:52:51 PM PDT 24
Finished	Apr 15 02:53:06 PM PDT 24
Peak memory	197996 kb
Host	smart-6ef91f93-a4d4-492f-895a-7d461a13a73d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3967345827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3967345827
Directory	/workspace/32.uart_tx_rx/latest

Test location	/workspace/coverage/default/33.uart_alert_test.2316817544
Short name	T436
Test name
Test status
Simulation time	12948365 ps
CPU time	0.56 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	196228 kb
Host	smart-c13ae84d-0825-4ebe-88b0-53b3a68efec6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316817544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2316817544
Directory	/workspace/33.uart_alert_test/latest

Test location	/workspace/coverage/default/33.uart_fifo_full.3941537231
Short name	T446
Test name
Test status
Simulation time	145589508784 ps
CPU time	243.47 seconds
Started	Apr 15 02:52:56 PM PDT 24
Finished	Apr 15 02:57:00 PM PDT 24
Peak memory	200916 kb
Host	smart-b0246210-0be2-441d-a34b-da3181a808b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941537231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3941537231
Directory	/workspace/33.uart_fifo_full/latest

Test location	/workspace/coverage/default/33.uart_fifo_overflow.1988555097
Short name	T657
Test name
Test status
Simulation time	104654569374 ps
CPU time	89.63 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:54:28 PM PDT 24
Peak memory	200840 kb
Host	smart-82ad96ae-5fec-4cb4-a1c4-efc910e90dd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988555097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1988555097
Directory	/workspace/33.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/33.uart_fifo_reset.916260488
Short name	T330
Test name
Test status
Simulation time	9504760253 ps
CPU time	20.41 seconds
Started	Apr 15 02:52:53 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	200884 kb
Host	smart-53c114c2-9b32-4833-bd5f-182e8bcc1025
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916260488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.916260488
Directory	/workspace/33.uart_fifo_reset/latest

Test location	/workspace/coverage/default/33.uart_intr.3464334447
Short name	T113
Test name
Test status
Simulation time	51075411169 ps
CPU time	91.45 seconds
Started	Apr 15 02:52:54 PM PDT 24
Finished	Apr 15 02:54:26 PM PDT 24
Peak memory	199820 kb
Host	smart-dc4fd380-bdff-498d-a5be-8cda597fb057
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464334447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3464334447
Directory	/workspace/33.uart_intr/latest

Test location	/workspace/coverage/default/33.uart_long_xfer_wo_dly.191194057
Short name	T484
Test name
Test status
Simulation time	279389104183 ps
CPU time	337.12 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:58:36 PM PDT 24
Peak memory	200940 kb
Host	smart-bb4d9bc5-8c64-4b74-a65f-838702cb8fa6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=191194057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.191194057
Directory	/workspace/33.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/33.uart_loopback.1755850708
Short name	T1054
Test name
Test status
Simulation time	11215216500 ps
CPU time	11.49 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 02:53:13 PM PDT 24
Peak memory	200484 kb
Host	smart-b47243b7-9ccd-4f96-b52e-fe2fa541c110
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755850708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1755850708
Directory	/workspace/33.uart_loopback/latest

Test location	/workspace/coverage/default/33.uart_noise_filter.1166996836
Short name	T335
Test name
Test status
Simulation time	54202202999 ps
CPU time	13.8 seconds
Started	Apr 15 02:52:53 PM PDT 24
Finished	Apr 15 02:53:07 PM PDT 24
Peak memory	198704 kb
Host	smart-940581f4-76df-40f8-9b9a-eef849dfc00f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166996836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1166996836
Directory	/workspace/33.uart_noise_filter/latest

Test location	/workspace/coverage/default/33.uart_perf.1100264095
Short name	T1146
Test name
Test status
Simulation time	13789616849 ps
CPU time	699.49 seconds
Started	Apr 15 02:52:59 PM PDT 24
Finished	Apr 15 03:04:39 PM PDT 24
Peak memory	200904 kb
Host	smart-dbd4c8c2-f886-4457-857c-a0583c6b7d79
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1100264095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1100264095
Directory	/workspace/33.uart_perf/latest

Test location	/workspace/coverage/default/33.uart_rx_oversample.3396400937
Short name	T627
Test name
Test status
Simulation time	6677177864 ps
CPU time	50.37 seconds
Started	Apr 15 02:52:54 PM PDT 24
Finished	Apr 15 02:53:45 PM PDT 24
Peak memory	199000 kb
Host	smart-25bfa818-026e-4bc3-a250-bbc427d81431
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3396400937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3396400937
Directory	/workspace/33.uart_rx_oversample/latest

Test location	/workspace/coverage/default/33.uart_rx_parity_err.394908053
Short name	T1070
Test name
Test status
Simulation time	113477541904 ps
CPU time	194.98 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:56:14 PM PDT 24
Peak memory	200740 kb
Host	smart-7aa198a0-58e2-4ee0-b744-28250bae3728
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394908053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.394908053
Directory	/workspace/33.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/33.uart_rx_start_bit_filter.1027019372
Short name	T340
Test name
Test status
Simulation time	48455139368 ps
CPU time	33.9 seconds
Started	Apr 15 02:52:54 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	196624 kb
Host	smart-82a1453f-5312-43d1-8e4d-98b34f8a26fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027019372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1027019372
Directory	/workspace/33.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/33.uart_smoke.1364484649
Short name	T770
Test name
Test status
Simulation time	928269224 ps
CPU time	3.57 seconds
Started	Apr 15 02:52:57 PM PDT 24
Finished	Apr 15 02:53:01 PM PDT 24
Peak memory	199664 kb
Host	smart-f3319686-6c57-4cfd-b021-3e452df302cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364484649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1364484649
Directory	/workspace/33.uart_smoke/latest

Test location	/workspace/coverage/default/33.uart_stress_all_with_rand_reset.185693678
Short name	T905
Test name
Test status
Simulation time	400065042877 ps
CPU time	517.79 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 03:01:37 PM PDT 24
Peak memory	217604 kb
Host	smart-69f8492a-f378-455f-bd73-7e5a4396cdda
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185693678 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.185693678
Directory	/workspace/33.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.uart_tx_ovrd.969487224
Short name	T302
Test name
Test status
Simulation time	2741483423 ps
CPU time	1.83 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:53:00 PM PDT 24
Peak memory	199580 kb
Host	smart-98d5c17d-1bd7-4a77-a019-891ba930fc1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969487224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.969487224
Directory	/workspace/33.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/33.uart_tx_rx.2027487693
Short name	T262
Test name
Test status
Simulation time	106593132342 ps
CPU time	124.71 seconds
Started	Apr 15 02:52:55 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200872 kb
Host	smart-871003a0-408d-4477-873b-b1d947d4713f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027487693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2027487693
Directory	/workspace/33.uart_tx_rx/latest

Test location	/workspace/coverage/default/34.uart_alert_test.1277534401
Short name	T1020
Test name
Test status
Simulation time	141627246 ps
CPU time	0.61 seconds
Started	Apr 15 02:53:02 PM PDT 24
Finished	Apr 15 02:53:03 PM PDT 24
Peak memory	195204 kb
Host	smart-86aed315-37c3-4e3d-9bb8-e4edd4ea9110
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277534401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1277534401
Directory	/workspace/34.uart_alert_test/latest

Test location	/workspace/coverage/default/34.uart_fifo_full.4095183979
Short name	T833
Test name
Test status
Simulation time	123034776817 ps
CPU time	49.29 seconds
Started	Apr 15 02:53:00 PM PDT 24
Finished	Apr 15 02:53:50 PM PDT 24
Peak memory	200824 kb
Host	smart-e75aed7f-3e5f-46bf-bf58-5bd8907af71d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095183979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4095183979
Directory	/workspace/34.uart_fifo_full/latest

Test location	/workspace/coverage/default/34.uart_fifo_overflow.2483131773
Short name	T501
Test name
Test status
Simulation time	28608638266 ps
CPU time	37.27 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:53:44 PM PDT 24
Peak memory	200904 kb
Host	smart-5dfd05e8-7b55-49b9-b821-05a08d2be71b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483131773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2483131773
Directory	/workspace/34.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/34.uart_fifo_reset.2175090393
Short name	T810
Test name
Test status
Simulation time	128386472278 ps
CPU time	45.38 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:53:53 PM PDT 24
Peak memory	200884 kb
Host	smart-8ad8adaa-e883-47f7-9e36-bee767e2cb3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175090393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2175090393
Directory	/workspace/34.uart_fifo_reset/latest

Test location	/workspace/coverage/default/34.uart_intr.672296731
Short name	T1056
Test name
Test status
Simulation time	61495620073 ps
CPU time	43.1 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 02:53:44 PM PDT 24
Peak memory	200876 kb
Host	smart-55fa1070-7b98-4134-8982-103fd6acfdf2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672296731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.672296731
Directory	/workspace/34.uart_intr/latest

Test location	/workspace/coverage/default/34.uart_long_xfer_wo_dly.77659217
Short name	T298
Test name
Test status
Simulation time	36997911189 ps
CPU time	248.3 seconds
Started	Apr 15 02:52:59 PM PDT 24
Finished	Apr 15 02:57:08 PM PDT 24
Peak memory	200840 kb
Host	smart-bba6aa66-8cf1-440a-938b-1f4f6184fa58
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=77659217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.77659217
Directory	/workspace/34.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/34.uart_loopback.2295935299
Short name	T834
Test name
Test status
Simulation time	8704201332 ps
CPU time	6.85 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	200540 kb
Host	smart-588126a1-2eae-4d60-8a74-622a7bfe4e57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295935299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2295935299
Directory	/workspace/34.uart_loopback/latest

Test location	/workspace/coverage/default/34.uart_noise_filter.1350179283
Short name	T317
Test name
Test status
Simulation time	120537314090 ps
CPU time	55.28 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	201208 kb
Host	smart-338627f6-3a15-49b7-9aa8-d175776c75dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350179283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1350179283
Directory	/workspace/34.uart_noise_filter/latest

Test location	/workspace/coverage/default/34.uart_perf.4056279559
Short name	T483
Test name
Test status
Simulation time	10330747169 ps
CPU time	285.91 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:57:52 PM PDT 24
Peak memory	200840 kb
Host	smart-95df75d8-824f-4503-9190-ec14c2802e03
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4056279559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4056279559
Directory	/workspace/34.uart_perf/latest

Test location	/workspace/coverage/default/34.uart_rx_oversample.1091051083
Short name	T618
Test name
Test status
Simulation time	4204913280 ps
CPU time	32.55 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	198876 kb
Host	smart-8d024449-1885-4ab0-b072-7f0fc0fab71b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1091051083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1091051083
Directory	/workspace/34.uart_rx_oversample/latest

Test location	/workspace/coverage/default/34.uart_rx_parity_err.2057214303
Short name	T162
Test name
Test status
Simulation time	28197035695 ps
CPU time	12.4 seconds
Started	Apr 15 02:53:02 PM PDT 24
Finished	Apr 15 02:53:15 PM PDT 24
Peak memory	200900 kb
Host	smart-2bb230ad-81da-4004-838b-e8054957123a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057214303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2057214303
Directory	/workspace/34.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/34.uart_rx_start_bit_filter.3269689793
Short name	T998
Test name
Test status
Simulation time	40913112180 ps
CPU time	4.9 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:53:12 PM PDT 24
Peak memory	196868 kb
Host	smart-02fa14f3-a26c-4527-add8-2c7e49fe7401
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269689793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3269689793
Directory	/workspace/34.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/34.uart_smoke.752067182
Short name	T378
Test name
Test status
Simulation time	664494727 ps
CPU time	4.84 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 02:53:06 PM PDT 24
Peak memory	200764 kb
Host	smart-8692df29-fce2-429e-8807-7d876ab38d70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752067182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.752067182
Directory	/workspace/34.uart_smoke/latest

Test location	/workspace/coverage/default/34.uart_stress_all.1110368570
Short name	T1162
Test name
Test status
Simulation time	115711190454 ps
CPU time	518.38 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 03:01:46 PM PDT 24
Peak memory	200932 kb
Host	smart-2fa41de1-97ba-49a6-ad4a-6e9503666f53
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110368570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1110368570
Directory	/workspace/34.uart_stress_all/latest

Test location	/workspace/coverage/default/34.uart_stress_all_with_rand_reset.79607638
Short name	T967
Test name
Test status
Simulation time	44746541636 ps
CPU time	113.3 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 02:54:55 PM PDT 24
Peak memory	209112 kb
Host	smart-d9de32b1-7a55-45f8-9de9-b5ea021d166d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79607638 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.79607638
Directory	/workspace/34.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.uart_tx_ovrd.2450456260
Short name	T1073
Test name
Test status
Simulation time	1317912537 ps
CPU time	4.29 seconds
Started	Apr 15 02:52:58 PM PDT 24
Finished	Apr 15 02:53:03 PM PDT 24
Peak memory	200724 kb
Host	smart-7ae4bdb0-6f99-4527-8352-c9504466c2c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2450456260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2450456260
Directory	/workspace/34.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/34.uart_tx_rx.2850970830
Short name	T325
Test name
Test status
Simulation time	20020996126 ps
CPU time	32.1 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:53:38 PM PDT 24
Peak memory	200824 kb
Host	smart-bf2d0d33-498c-4339-a170-b71813954d53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2850970830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2850970830
Directory	/workspace/34.uart_tx_rx/latest

Test location	/workspace/coverage/default/35.uart_alert_test.535775448
Short name	T27
Test name
Test status
Simulation time	41893860 ps
CPU time	0.56 seconds
Started	Apr 15 02:53:04 PM PDT 24
Finished	Apr 15 02:53:05 PM PDT 24
Peak memory	196220 kb
Host	smart-5e5c3402-a5fc-4a67-adfe-68ed628ab257
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535775448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.535775448
Directory	/workspace/35.uart_alert_test/latest

Test location	/workspace/coverage/default/35.uart_fifo_full.1387598738
Short name	T1095
Test name
Test status
Simulation time	124193260746 ps
CPU time	205.18 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:56:31 PM PDT 24
Peak memory	200916 kb
Host	smart-f0ea178e-a8df-4462-bbdc-66ab1c33f35b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387598738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1387598738
Directory	/workspace/35.uart_fifo_full/latest

Test location	/workspace/coverage/default/35.uart_fifo_overflow.1210353836
Short name	T836
Test name
Test status
Simulation time	189412791247 ps
CPU time	45.07 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:53:52 PM PDT 24
Peak memory	200856 kb
Host	smart-9314d1f4-a70a-49e3-8ae9-332091a1dd44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210353836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1210353836
Directory	/workspace/35.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/35.uart_fifo_reset.859528986
Short name	T192
Test name
Test status
Simulation time	20844985377 ps
CPU time	43.97 seconds
Started	Apr 15 02:53:02 PM PDT 24
Finished	Apr 15 02:53:46 PM PDT 24
Peak memory	200888 kb
Host	smart-63411a6d-05e4-4b5d-994b-3399d6739daa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859528986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.859528986
Directory	/workspace/35.uart_fifo_reset/latest

Test location	/workspace/coverage/default/35.uart_intr.1207678872
Short name	T700
Test name
Test status
Simulation time	243179646366 ps
CPU time	100.67 seconds
Started	Apr 15 02:53:04 PM PDT 24
Finished	Apr 15 02:54:45 PM PDT 24
Peak memory	198608 kb
Host	smart-d2f9532c-43d4-4cde-83ef-3da0327e2b80
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207678872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1207678872
Directory	/workspace/35.uart_intr/latest

Test location	/workspace/coverage/default/35.uart_long_xfer_wo_dly.4180731237
Short name	T673
Test name
Test status
Simulation time	65109110517 ps
CPU time	146.09 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:55:32 PM PDT 24
Peak memory	200904 kb
Host	smart-009414ae-5d40-4672-b0fd-026a573200ca
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4180731237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4180731237
Directory	/workspace/35.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/35.uart_loopback.475663596
Short name	T551
Test name
Test status
Simulation time	3694551927 ps
CPU time	2.59 seconds
Started	Apr 15 02:53:02 PM PDT 24
Finished	Apr 15 02:53:05 PM PDT 24
Peak memory	198940 kb
Host	smart-540ecf18-109e-48be-968b-1c0075d3852f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475663596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.475663596
Directory	/workspace/35.uart_loopback/latest

Test location	/workspace/coverage/default/35.uart_noise_filter.3363817030
Short name	T279
Test name
Test status
Simulation time	117041021630 ps
CPU time	223.42 seconds
Started	Apr 15 02:53:04 PM PDT 24
Finished	Apr 15 02:56:48 PM PDT 24
Peak memory	209104 kb
Host	smart-dab86d63-4f3a-44e0-a6c1-c7390e02a50e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363817030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3363817030
Directory	/workspace/35.uart_noise_filter/latest

Test location	/workspace/coverage/default/35.uart_perf.3682210748
Short name	T275
Test name
Test status
Simulation time	17879606678 ps
CPU time	729.22 seconds
Started	Apr 15 02:53:03 PM PDT 24
Finished	Apr 15 03:05:13 PM PDT 24
Peak memory	200884 kb
Host	smart-e3066bc1-4387-406b-8115-3a8aabf1a5c4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3682210748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3682210748
Directory	/workspace/35.uart_perf/latest

Test location	/workspace/coverage/default/35.uart_rx_oversample.152533956
Short name	T357
Test name
Test status
Simulation time	2970125590 ps
CPU time	1.89 seconds
Started	Apr 15 02:53:03 PM PDT 24
Finished	Apr 15 02:53:05 PM PDT 24
Peak memory	200724 kb
Host	smart-ddfbb91e-c9e6-49cb-9db2-c29afc76a67a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=152533956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.152533956
Directory	/workspace/35.uart_rx_oversample/latest

Test location	/workspace/coverage/default/35.uart_rx_parity_err.2760349630
Short name	T884
Test name
Test status
Simulation time	118671618610 ps
CPU time	164.66 seconds
Started	Apr 15 02:53:03 PM PDT 24
Finished	Apr 15 02:55:48 PM PDT 24
Peak memory	200888 kb
Host	smart-7bd7ad0c-83a3-4f85-b677-03a5cd51ea8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2760349630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2760349630
Directory	/workspace/35.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/35.uart_rx_start_bit_filter.47900730
Short name	T577
Test name
Test status
Simulation time	2281463835 ps
CPU time	1.63 seconds
Started	Apr 15 02:53:02 PM PDT 24
Finished	Apr 15 02:53:04 PM PDT 24
Peak memory	196344 kb
Host	smart-af4d1cf0-435e-45ee-b8d4-17fa7df54205
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47900730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.47900730
Directory	/workspace/35.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/35.uart_smoke.2611745768
Short name	T331
Test name
Test status
Simulation time	481612032 ps
CPU time	1.37 seconds
Started	Apr 15 02:53:03 PM PDT 24
Finished	Apr 15 02:53:05 PM PDT 24
Peak memory	199152 kb
Host	smart-b61b7226-2069-4ae0-8098-73ede449652b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611745768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2611745768
Directory	/workspace/35.uart_smoke/latest

Test location	/workspace/coverage/default/35.uart_stress_all.2521049804
Short name	T859
Test name
Test status
Simulation time	237674198831 ps
CPU time	400.58 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 02:59:49 PM PDT 24
Peak memory	217404 kb
Host	smart-946ff44f-440d-476a-9af2-5e9d7b843c87
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521049804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2521049804
Directory	/workspace/35.uart_stress_all/latest

Test location	/workspace/coverage/default/35.uart_stress_all_with_rand_reset.1908701189
Short name	T48
Test name
Test status
Simulation time	47157209820 ps
CPU time	431.16 seconds
Started	Apr 15 02:53:01 PM PDT 24
Finished	Apr 15 03:00:13 PM PDT 24
Peak memory	216716 kb
Host	smart-dc8e287c-b459-4247-8bdb-d27f0a6d98ae
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908701189 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1908701189
Directory	/workspace/35.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.uart_tx_ovrd.709793051
Short name	T758
Test name
Test status
Simulation time	626121089 ps
CPU time	2.34 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:53:08 PM PDT 24
Peak memory	199456 kb
Host	smart-3625f6b3-dfae-4a1f-b249-4d821be20728
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709793051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.709793051
Directory	/workspace/35.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/35.uart_tx_rx.2479779661
Short name	T1087
Test name
Test status
Simulation time	69314237111 ps
CPU time	30.28 seconds
Started	Apr 15 02:53:04 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	200872 kb
Host	smart-3a1165d2-dfc0-4a95-a359-7c2e1042b261
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479779661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2479779661
Directory	/workspace/35.uart_tx_rx/latest

Test location	/workspace/coverage/default/36.uart_alert_test.3317889038
Short name	T383
Test name
Test status
Simulation time	12498271 ps
CPU time	0.57 seconds
Started	Apr 15 02:53:13 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	196184 kb
Host	smart-a5be3c64-0f38-41da-b5dd-9f8b97c13eba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317889038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3317889038
Directory	/workspace/36.uart_alert_test/latest

Test location	/workspace/coverage/default/36.uart_fifo_full.3410454602
Short name	T1185
Test name
Test status
Simulation time	142630091276 ps
CPU time	566.11 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 03:02:35 PM PDT 24
Peak memory	200876 kb
Host	smart-21392e98-30a7-4b77-a494-4b788af80652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410454602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3410454602
Directory	/workspace/36.uart_fifo_full/latest

Test location	/workspace/coverage/default/36.uart_fifo_overflow.2080339595
Short name	T33
Test name
Test status
Simulation time	134061422495 ps
CPU time	16.87 seconds
Started	Apr 15 02:53:10 PM PDT 24
Finished	Apr 15 02:53:27 PM PDT 24
Peak memory	199568 kb
Host	smart-5a73d8e2-172b-406d-9586-83b729fb32c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080339595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2080339595
Directory	/workspace/36.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/36.uart_fifo_reset.962616494
Short name	T86
Test name
Test status
Simulation time	14602319400 ps
CPU time	28.56 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	200904 kb
Host	smart-245a5af4-31ab-44ae-a32f-f237afb7012d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962616494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.962616494
Directory	/workspace/36.uart_fifo_reset/latest

Test location	/workspace/coverage/default/36.uart_intr.3702088443
Short name	T989
Test name
Test status
Simulation time	50244327204 ps
CPU time	27.27 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	200860 kb
Host	smart-fd5152cc-ef7b-4770-8345-4eedeaeb7354
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702088443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3702088443
Directory	/workspace/36.uart_intr/latest

Test location	/workspace/coverage/default/36.uart_long_xfer_wo_dly.2756049592
Short name	T635
Test name
Test status
Simulation time	152201174360 ps
CPU time	326.21 seconds
Started	Apr 15 02:53:05 PM PDT 24
Finished	Apr 15 02:58:32 PM PDT 24
Peak memory	200872 kb
Host	smart-a6f9cf4b-7edc-4ab6-9517-e8ae9b3c6d98
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2756049592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2756049592
Directory	/workspace/36.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/36.uart_loopback.2124494655
Short name	T1002
Test name
Test status
Simulation time	7008925219 ps
CPU time	10.21 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	199516 kb
Host	smart-a206eb26-62ad-4383-a2f6-1965d5a8d3df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2124494655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2124494655
Directory	/workspace/36.uart_loopback/latest

Test location	/workspace/coverage/default/36.uart_noise_filter.2909249582
Short name	T739
Test name
Test status
Simulation time	99736983128 ps
CPU time	43.41 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 02:53:51 PM PDT 24
Peak memory	199828 kb
Host	smart-fe748bc1-9155-45ee-a35a-1c02ccda75ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2909249582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2909249582
Directory	/workspace/36.uart_noise_filter/latest

Test location	/workspace/coverage/default/36.uart_perf.3413586222
Short name	T44
Test name
Test status
Simulation time	11765189857 ps
CPU time	133.13 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 02:55:22 PM PDT 24
Peak memory	200880 kb
Host	smart-fab0af63-ee22-4f5b-a4ed-9b02e54a08ec
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3413586222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3413586222
Directory	/workspace/36.uart_perf/latest

Test location	/workspace/coverage/default/36.uart_rx_oversample.4220582389
Short name	T780
Test name
Test status
Simulation time	5715117809 ps
CPU time	55.28 seconds
Started	Apr 15 02:53:06 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	200056 kb
Host	smart-28bd50e6-82b5-411d-bba6-525b9a3fa557
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4220582389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4220582389
Directory	/workspace/36.uart_rx_oversample/latest

Test location	/workspace/coverage/default/36.uart_rx_parity_err.1760377628
Short name	T1113
Test name
Test status
Simulation time	37822840178 ps
CPU time	18.52 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 02:53:27 PM PDT 24
Peak memory	200804 kb
Host	smart-f04b5638-05b7-4d8a-8129-574cf28977b8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1760377628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1760377628
Directory	/workspace/36.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/36.uart_rx_start_bit_filter.3474267585
Short name	T598
Test name
Test status
Simulation time	7105203058 ps
CPU time	13.29 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 02:53:22 PM PDT 24
Peak memory	196864 kb
Host	smart-a2780c94-77ad-4596-a84c-ffee5bce5da1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474267585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3474267585
Directory	/workspace/36.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/36.uart_smoke.635160454
Short name	T369
Test name
Test status
Simulation time	665032066 ps
CPU time	1.63 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 02:53:10 PM PDT 24
Peak memory	200796 kb
Host	smart-5d08d2ec-6fdf-4b94-8ea8-93438eff74c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635160454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.635160454
Directory	/workspace/36.uart_smoke/latest

Test location	/workspace/coverage/default/36.uart_stress_all.2372807696
Short name	T652
Test name
Test status
Simulation time	111963131839 ps
CPU time	269.77 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:57:41 PM PDT 24
Peak memory	200808 kb
Host	smart-d7bcbc8e-8446-49e8-b2fa-f7e03fe7a97b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372807696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2372807696
Directory	/workspace/36.uart_stress_all/latest

Test location	/workspace/coverage/default/36.uart_stress_all_with_rand_reset.2019519917
Short name	T124
Test name
Test status
Simulation time	89028466730 ps
CPU time	823.68 seconds
Started	Apr 15 02:53:08 PM PDT 24
Finished	Apr 15 03:06:53 PM PDT 24
Peak memory	225764 kb
Host	smart-7723ff51-2853-4857-ae86-c255155c9c2e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019519917 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2019519917
Directory	/workspace/36.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.uart_tx_ovrd.3012781993
Short name	T638
Test name
Test status
Simulation time	248956449 ps
CPU time	1.08 seconds
Started	Apr 15 02:53:07 PM PDT 24
Finished	Apr 15 02:53:09 PM PDT 24
Peak memory	197968 kb
Host	smart-d99a7759-59b7-4684-b0ab-2195b6580177
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012781993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3012781993
Directory	/workspace/36.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/36.uart_tx_rx.3206386907
Short name	T571
Test name
Test status
Simulation time	15322150708 ps
CPU time	25.13 seconds
Started	Apr 15 02:53:10 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	200900 kb
Host	smart-4b1ca949-9b73-40b8-9cd3-70670ed0be79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206386907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3206386907
Directory	/workspace/36.uart_tx_rx/latest

Test location	/workspace/coverage/default/37.uart_alert_test.376314549
Short name	T706
Test name
Test status
Simulation time	124141346 ps
CPU time	0.56 seconds
Started	Apr 15 02:53:15 PM PDT 24
Finished	Apr 15 02:53:17 PM PDT 24
Peak memory	196228 kb
Host	smart-957e9741-d458-4592-a5e2-660c3db95b1f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376314549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.376314549
Directory	/workspace/37.uart_alert_test/latest

Test location	/workspace/coverage/default/37.uart_fifo_full.3455758651
Short name	T765
Test name
Test status
Simulation time	91311115594 ps
CPU time	142.29 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:55:35 PM PDT 24
Peak memory	200928 kb
Host	smart-2d87f2c1-2833-4b04-bf33-0671984d852a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455758651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3455758651
Directory	/workspace/37.uart_fifo_full/latest

Test location	/workspace/coverage/default/37.uart_fifo_overflow.526777092
Short name	T982
Test name
Test status
Simulation time	8307176158 ps
CPU time	6.91 seconds
Started	Apr 15 02:53:13 PM PDT 24
Finished	Apr 15 02:53:20 PM PDT 24
Peak memory	200404 kb
Host	smart-672d3a7f-4040-4f00-ac55-bd5c25f837a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526777092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.526777092
Directory	/workspace/37.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/37.uart_intr.217505599
Short name	T681
Test name
Test status
Simulation time	16247438759 ps
CPU time	29.54 seconds
Started	Apr 15 02:53:13 PM PDT 24
Finished	Apr 15 02:53:43 PM PDT 24
Peak memory	200920 kb
Host	smart-2560e852-f942-4f57-8295-cb43d26cb93b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217505599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.217505599
Directory	/workspace/37.uart_intr/latest

Test location	/workspace/coverage/default/37.uart_long_xfer_wo_dly.1975961335
Short name	T117
Test name
Test status
Simulation time	129959458505 ps
CPU time	939.15 seconds
Started	Apr 15 02:53:12 PM PDT 24
Finished	Apr 15 03:08:52 PM PDT 24
Peak memory	200864 kb
Host	smart-f4c50a91-45dd-47fc-aef0-1562ea32c742
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1975961335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1975961335
Directory	/workspace/37.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/37.uart_loopback.3708667991
Short name	T11
Test name
Test status
Simulation time	1463246638 ps
CPU time	1.4 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:53:14 PM PDT 24
Peak memory	197872 kb
Host	smart-76708463-bf20-476e-b9e1-1db7f5754a5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708667991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3708667991
Directory	/workspace/37.uart_loopback/latest

Test location	/workspace/coverage/default/37.uart_noise_filter.20286420
Short name	T481
Test name
Test status
Simulation time	18309546794 ps
CPU time	32.52 seconds
Started	Apr 15 02:53:10 PM PDT 24
Finished	Apr 15 02:53:43 PM PDT 24
Peak memory	199728 kb
Host	smart-b86b9ec0-32e1-4a24-b86a-251a02f11c08
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20286420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.20286420
Directory	/workspace/37.uart_noise_filter/latest

Test location	/workspace/coverage/default/37.uart_perf.1827164277
Short name	T462
Test name
Test status
Simulation time	8773114872 ps
CPU time	154.71 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:55:47 PM PDT 24
Peak memory	200888 kb
Host	smart-2110f77b-289b-4c28-bcc6-4efe84c8ee2b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1827164277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1827164277
Directory	/workspace/37.uart_perf/latest

Test location	/workspace/coverage/default/37.uart_rx_oversample.712538891
Short name	T584
Test name
Test status
Simulation time	6550064628 ps
CPU time	6.33 seconds
Started	Apr 15 02:53:13 PM PDT 24
Finished	Apr 15 02:53:20 PM PDT 24
Peak memory	199116 kb
Host	smart-ae08a7dd-b614-452a-8c1c-4ed6d3687d73
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=712538891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.712538891
Directory	/workspace/37.uart_rx_oversample/latest

Test location	/workspace/coverage/default/37.uart_rx_parity_err.2221775235
Short name	T261
Test name
Test status
Simulation time	226112592605 ps
CPU time	70.07 seconds
Started	Apr 15 02:53:15 PM PDT 24
Finished	Apr 15 02:54:26 PM PDT 24
Peak memory	200824 kb
Host	smart-38328d42-33b8-4dda-a44e-4f22b8d98bf5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221775235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2221775235
Directory	/workspace/37.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/37.uart_rx_start_bit_filter.1151713113
Short name	T409
Test name
Test status
Simulation time	5712911466 ps
CPU time	1.85 seconds
Started	Apr 15 02:53:13 PM PDT 24
Finished	Apr 15 02:53:15 PM PDT 24
Peak memory	197184 kb
Host	smart-7bcd144f-474b-4711-821f-9f415e37e899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151713113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1151713113
Directory	/workspace/37.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/37.uart_smoke.1087096888
Short name	T10
Test name
Test status
Simulation time	264183772 ps
CPU time	1.34 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:53:13 PM PDT 24
Peak memory	199440 kb
Host	smart-c111566e-124e-47e6-ae74-478f85062984
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087096888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1087096888
Directory	/workspace/37.uart_smoke/latest

Test location	/workspace/coverage/default/37.uart_stress_all.3220397911
Short name	T699
Test name
Test status
Simulation time	192878954186 ps
CPU time	328.88 seconds
Started	Apr 15 02:53:10 PM PDT 24
Finished	Apr 15 02:58:40 PM PDT 24
Peak memory	201100 kb
Host	smart-dfadc100-cec7-4217-bcd4-e799a452fc4a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220397911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3220397911
Directory	/workspace/37.uart_stress_all/latest

Test location	/workspace/coverage/default/37.uart_stress_all_with_rand_reset.1697085466
Short name	T1133
Test name
Test status
Simulation time	19788686097 ps
CPU time	176.65 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:56:08 PM PDT 24
Peak memory	217192 kb
Host	smart-d88436e9-b851-4f63-9a71-b34b36021050
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697085466 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1697085466
Directory	/workspace/37.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.uart_tx_ovrd.3496864832
Short name	T615
Test name
Test status
Simulation time	6323411628 ps
CPU time	22.2 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200904 kb
Host	smart-a40f2547-66db-4aad-8c09-8577cfda5c9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496864832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3496864832
Directory	/workspace/37.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/37.uart_tx_rx.2398628457
Short name	T564
Test name
Test status
Simulation time	23978842753 ps
CPU time	36.83 seconds
Started	Apr 15 02:53:11 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	200720 kb
Host	smart-078a9881-3513-48a7-9fd2-9dc5fde99f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2398628457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2398628457
Directory	/workspace/37.uart_tx_rx/latest

Test location	/workspace/coverage/default/38.uart_alert_test.3023464804
Short name	T1079
Test name
Test status
Simulation time	13588138 ps
CPU time	0.56 seconds
Started	Apr 15 02:53:23 PM PDT 24
Finished	Apr 15 02:53:24 PM PDT 24
Peak memory	195672 kb
Host	smart-5211b86d-c1c0-441f-a849-b505af48fa41
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023464804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3023464804
Directory	/workspace/38.uart_alert_test/latest

Test location	/workspace/coverage/default/38.uart_fifo_full.3858684994
Short name	T679
Test name
Test status
Simulation time	46704270427 ps
CPU time	80.5 seconds
Started	Apr 15 02:53:15 PM PDT 24
Finished	Apr 15 02:54:36 PM PDT 24
Peak memory	200780 kb
Host	smart-f38ccc6e-7957-49a5-a2d7-a6213460ad75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858684994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3858684994
Directory	/workspace/38.uart_fifo_full/latest

Test location	/workspace/coverage/default/38.uart_fifo_overflow.1142126433
Short name	T808
Test name
Test status
Simulation time	34368800595 ps
CPU time	72.28 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:54:29 PM PDT 24
Peak memory	200920 kb
Host	smart-ae3dcf20-9f12-46d6-bd7c-34cf89ffed0d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142126433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1142126433
Directory	/workspace/38.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/38.uart_fifo_reset.3580610961
Short name	T218
Test name
Test status
Simulation time	84221991401 ps
CPU time	34.05 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:53:51 PM PDT 24
Peak memory	200908 kb
Host	smart-dfef5371-5853-4b0b-a1c4-3048c929f7ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580610961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3580610961
Directory	/workspace/38.uart_fifo_reset/latest

Test location	/workspace/coverage/default/38.uart_intr.693237010
Short name	T390
Test name
Test status
Simulation time	171348231088 ps
CPU time	88.34 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:54:45 PM PDT 24
Peak memory	200892 kb
Host	smart-fb21e629-a7ce-447a-87fb-f8f78dd127f2
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693237010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.693237010
Directory	/workspace/38.uart_intr/latest

Test location	/workspace/coverage/default/38.uart_long_xfer_wo_dly.556643585
Short name	T994
Test name
Test status
Simulation time	42685326840 ps
CPU time	80.2 seconds
Started	Apr 15 02:53:22 PM PDT 24
Finished	Apr 15 02:54:43 PM PDT 24
Peak memory	200912 kb
Host	smart-644bc234-a35f-4bb5-a39a-2a4887b657d3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=556643585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.556643585
Directory	/workspace/38.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/38.uart_loopback.3914790696
Short name	T1181
Test name
Test status
Simulation time	5327206224 ps
CPU time	3.49 seconds
Started	Apr 15 02:53:15 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	200224 kb
Host	smart-d59653b9-780b-460d-8780-5b19850f53a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3914790696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3914790696
Directory	/workspace/38.uart_loopback/latest

Test location	/workspace/coverage/default/38.uart_noise_filter.2555040558
Short name	T281
Test name
Test status
Simulation time	70375909174 ps
CPU time	66.11 seconds
Started	Apr 15 02:53:17 PM PDT 24
Finished	Apr 15 02:54:23 PM PDT 24
Peak memory	201068 kb
Host	smart-dd519b85-489d-499f-a160-30f5f650d739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555040558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2555040558
Directory	/workspace/38.uart_noise_filter/latest

Test location	/workspace/coverage/default/38.uart_perf.3483768063
Short name	T1018
Test name
Test status
Simulation time	7639376202 ps
CPU time	373.81 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:59:30 PM PDT 24
Peak memory	200836 kb
Host	smart-b03e899c-653e-4f48-9472-744b955c211d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3483768063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3483768063
Directory	/workspace/38.uart_perf/latest

Test location	/workspace/coverage/default/38.uart_rx_oversample.43292782
Short name	T977
Test name
Test status
Simulation time	2754610983 ps
CPU time	3.95 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:53:20 PM PDT 24
Peak memory	199796 kb
Host	smart-85705d00-7e55-4778-a87f-8914673addb8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=43292782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.43292782
Directory	/workspace/38.uart_rx_oversample/latest

Test location	/workspace/coverage/default/38.uart_rx_parity_err.1237726864
Short name	T1014
Test name
Test status
Simulation time	153457167505 ps
CPU time	107.81 seconds
Started	Apr 15 02:53:17 PM PDT 24
Finished	Apr 15 02:55:05 PM PDT 24
Peak memory	200724 kb
Host	smart-948ff4c4-d3e1-46f3-8f8b-aa7a7b372f76
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237726864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1237726864
Directory	/workspace/38.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/38.uart_rx_start_bit_filter.159835781
Short name	T541
Test name
Test status
Simulation time	2930576741 ps
CPU time	1.64 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	196860 kb
Host	smart-134686b8-6054-4860-86dc-0323a73237dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159835781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.159835781
Directory	/workspace/38.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/38.uart_smoke.485142486
Short name	T809
Test name
Test status
Simulation time	754346540 ps
CPU time	1.76 seconds
Started	Apr 15 02:53:15 PM PDT 24
Finished	Apr 15 02:53:17 PM PDT 24
Peak memory	200672 kb
Host	smart-4769beb1-db61-4617-878d-c5b119b2d134
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485142486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.485142486
Directory	/workspace/38.uart_smoke/latest

Test location	/workspace/coverage/default/38.uart_stress_all.1154858310
Short name	T406
Test name
Test status
Simulation time	156746758160 ps
CPU time	395.42 seconds
Started	Apr 15 02:53:23 PM PDT 24
Finished	Apr 15 02:59:59 PM PDT 24
Peak memory	200824 kb
Host	smart-97390fd3-b4ff-4a42-b5a2-88c5eaf93609
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154858310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1154858310
Directory	/workspace/38.uart_stress_all/latest

Test location	/workspace/coverage/default/38.uart_tx_ovrd.4106819170
Short name	T365
Test name
Test status
Simulation time	955359023 ps
CPU time	2.11 seconds
Started	Apr 15 02:53:17 PM PDT 24
Finished	Apr 15 02:53:19 PM PDT 24
Peak memory	199380 kb
Host	smart-4f9024f0-59b3-4425-bc39-3a377974e4a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106819170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4106819170
Directory	/workspace/38.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/38.uart_tx_rx.1116499316
Short name	T683
Test name
Test status
Simulation time	6603651769 ps
CPU time	11.21 seconds
Started	Apr 15 02:53:16 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	197748 kb
Host	smart-d93ab69b-ac07-41b3-b782-f46f65892144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116499316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1116499316
Directory	/workspace/38.uart_tx_rx/latest

Test location	/workspace/coverage/default/39.uart_alert_test.1278801991
Short name	T731
Test name
Test status
Simulation time	46393333 ps
CPU time	0.55 seconds
Started	Apr 15 02:53:23 PM PDT 24
Finished	Apr 15 02:53:24 PM PDT 24
Peak memory	196224 kb
Host	smart-ad431afb-1148-47fe-a9e0-b9d051a44939
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278801991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1278801991
Directory	/workspace/39.uart_alert_test/latest

Test location	/workspace/coverage/default/39.uart_fifo_full.3606770213
Short name	T154
Test name
Test status
Simulation time	66438811392 ps
CPU time	27.06 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	200832 kb
Host	smart-60fbfd4a-e43c-4a9e-8003-204d8122c161
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606770213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3606770213
Directory	/workspace/39.uart_fifo_full/latest

Test location	/workspace/coverage/default/39.uart_fifo_overflow.1936506222
Short name	T1013
Test name
Test status
Simulation time	23210039084 ps
CPU time	10.7 seconds
Started	Apr 15 02:53:21 PM PDT 24
Finished	Apr 15 02:53:32 PM PDT 24
Peak memory	199584 kb
Host	smart-972e1b3a-47f5-4a7f-8221-72c609087bcd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936506222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1936506222
Directory	/workspace/39.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/39.uart_fifo_reset.3932691406
Short name	T924
Test name
Test status
Simulation time	119298029986 ps
CPU time	171.78 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 02:56:12 PM PDT 24
Peak memory	200864 kb
Host	smart-570dea57-e5c7-4147-a39b-16d4aa270e79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932691406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3932691406
Directory	/workspace/39.uart_fifo_reset/latest

Test location	/workspace/coverage/default/39.uart_intr.2730606181
Short name	T292
Test name
Test status
Simulation time	52799222314 ps
CPU time	87.87 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 02:54:48 PM PDT 24
Peak memory	200880 kb
Host	smart-764bcabc-1f50-45c6-9789-502f25f12d62
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730606181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2730606181
Directory	/workspace/39.uart_intr/latest

Test location	/workspace/coverage/default/39.uart_long_xfer_wo_dly.2423904968
Short name	T632
Test name
Test status
Simulation time	68377162254 ps
CPU time	406.61 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 03:00:13 PM PDT 24
Peak memory	200876 kb
Host	smart-d4426eec-834a-4d04-b1f9-70d575452245
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2423904968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2423904968
Directory	/workspace/39.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/39.uart_loopback.2883718033
Short name	T402
Test name
Test status
Simulation time	7300377119 ps
CPU time	10.89 seconds
Started	Apr 15 02:53:22 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200288 kb
Host	smart-e4217f5b-5ad7-4d77-b28a-189ecce9dfe2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883718033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2883718033
Directory	/workspace/39.uart_loopback/latest

Test location	/workspace/coverage/default/39.uart_noise_filter.1341850159
Short name	T323
Test name
Test status
Simulation time	175285111226 ps
CPU time	73.23 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:54:39 PM PDT 24
Peak memory	209072 kb
Host	smart-785725b6-72f4-4a3a-a32b-4559f4217118
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341850159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1341850159
Directory	/workspace/39.uart_noise_filter/latest

Test location	/workspace/coverage/default/39.uart_perf.2543829081
Short name	T749
Test name
Test status
Simulation time	20273753159 ps
CPU time	98.03 seconds
Started	Apr 15 02:53:21 PM PDT 24
Finished	Apr 15 02:55:00 PM PDT 24
Peak memory	200916 kb
Host	smart-21ce703f-55da-4ff5-a01b-92a413759832
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2543829081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2543829081
Directory	/workspace/39.uart_perf/latest

Test location	/workspace/coverage/default/39.uart_rx_oversample.2832914669
Short name	T23
Test name
Test status
Simulation time	4396722359 ps
CPU time	10.02 seconds
Started	Apr 15 02:53:26 PM PDT 24
Finished	Apr 15 02:53:37 PM PDT 24
Peak memory	200276 kb
Host	smart-97c6bf8d-f424-4d29-a7f0-ae4ea73c2486
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2832914669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2832914669
Directory	/workspace/39.uart_rx_oversample/latest

Test location	/workspace/coverage/default/39.uart_rx_parity_err.2868653683
Short name	T322
Test name
Test status
Simulation time	14037600382 ps
CPU time	21.01 seconds
Started	Apr 15 02:53:19 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	200864 kb
Host	smart-704aa0e3-698a-424e-a162-f39e1bf073a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868653683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2868653683
Directory	/workspace/39.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/39.uart_rx_start_bit_filter.1559665237
Short name	T572
Test name
Test status
Simulation time	30633998890 ps
CPU time	13.42 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	196968 kb
Host	smart-e915e5cf-a824-446b-b248-c1ac5f70f3e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1559665237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1559665237
Directory	/workspace/39.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/39.uart_smoke.1213186311
Short name	T741
Test name
Test status
Simulation time	11094226500 ps
CPU time	41.55 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:54:08 PM PDT 24
Peak memory	200332 kb
Host	smart-59629669-bf34-409a-972d-4016f5f8223a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213186311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1213186311
Directory	/workspace/39.uart_smoke/latest

Test location	/workspace/coverage/default/39.uart_stress_all.897520511
Short name	T1182
Test name
Test status
Simulation time	211292462499 ps
CPU time	531.94 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 03:02:13 PM PDT 24
Peak memory	200824 kb
Host	smart-ecaf0b60-6dea-4091-a199-0694adebbe36
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897520511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.897520511
Directory	/workspace/39.uart_stress_all/latest

Test location	/workspace/coverage/default/39.uart_stress_all_with_rand_reset.3142129561
Short name	T709
Test name
Test status
Simulation time	34569550226 ps
CPU time	596.69 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 03:03:17 PM PDT 24
Peak memory	217328 kb
Host	smart-c482513c-1225-4e19-ba79-125f29fd2a7b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142129561 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3142129561
Directory	/workspace/39.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.uart_tx_ovrd.1275520867
Short name	T771
Test name
Test status
Simulation time	6412893706 ps
CPU time	14.7 seconds
Started	Apr 15 02:53:20 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	200132 kb
Host	smart-79e54269-d20f-463c-9b63-6834668fa31f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275520867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1275520867
Directory	/workspace/39.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/39.uart_tx_rx.2215836645
Short name	T614
Test name
Test status
Simulation time	48728982685 ps
CPU time	81.67 seconds
Started	Apr 15 02:53:21 PM PDT 24
Finished	Apr 15 02:54:43 PM PDT 24
Peak memory	200792 kb
Host	smart-99f4005b-e97e-45db-bec3-25e1ed961980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215836645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2215836645
Directory	/workspace/39.uart_tx_rx/latest

Test location	/workspace/coverage/default/4.uart_alert_test.1698285310
Short name	T832
Test name
Test status
Simulation time	65002207 ps
CPU time	0.55 seconds
Started	Apr 15 02:51:21 PM PDT 24
Finished	Apr 15 02:51:22 PM PDT 24
Peak memory	195564 kb
Host	smart-6290d844-bf17-44a8-9dc5-f945db6344c3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698285310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1698285310
Directory	/workspace/4.uart_alert_test/latest

Test location	/workspace/coverage/default/4.uart_fifo_full.1278627433
Short name	T781
Test name
Test status
Simulation time	74955963416 ps
CPU time	16.82 seconds
Started	Apr 15 02:51:31 PM PDT 24
Finished	Apr 15 02:51:54 PM PDT 24
Peak memory	200920 kb
Host	smart-c70eaaac-15e7-40cf-8404-30af989fe2e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278627433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1278627433
Directory	/workspace/4.uart_fifo_full/latest

Test location	/workspace/coverage/default/4.uart_fifo_overflow.562088348
Short name	T526
Test name
Test status
Simulation time	35333546012 ps
CPU time	17.8 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:52:00 PM PDT 24
Peak memory	200776 kb
Host	smart-3565957a-0a17-43b6-ac9a-2537d831830e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=562088348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.562088348
Directory	/workspace/4.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/4.uart_fifo_reset.4094779332
Short name	T791
Test name
Test status
Simulation time	20073373661 ps
CPU time	10.19 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:40 PM PDT 24
Peak memory	200924 kb
Host	smart-691af902-790d-4ea5-a12c-e6ec4e87b987
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094779332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.4094779332
Directory	/workspace/4.uart_fifo_reset/latest

Test location	/workspace/coverage/default/4.uart_intr.1714299788
Short name	T532
Test name
Test status
Simulation time	89110763103 ps
CPU time	117.59 seconds
Started	Apr 15 02:51:26 PM PDT 24
Finished	Apr 15 02:53:24 PM PDT 24
Peak memory	200676 kb
Host	smart-ac8d01f3-2861-4d91-94cb-c98c3cf7748d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714299788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1714299788
Directory	/workspace/4.uart_intr/latest

Test location	/workspace/coverage/default/4.uart_long_xfer_wo_dly.1059720101
Short name	T562
Test name
Test status
Simulation time	170318820369 ps
CPU time	1368.69 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 03:14:30 PM PDT 24
Peak memory	200832 kb
Host	smart-5c676e21-a290-4b7d-b1e9-9c15662307d7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1059720101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1059720101
Directory	/workspace/4.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/4.uart_loopback.3483237591
Short name	T1171
Test name
Test status
Simulation time	6723041315 ps
CPU time	11.47 seconds
Started	Apr 15 02:51:23 PM PDT 24
Finished	Apr 15 02:51:40 PM PDT 24
Peak memory	199208 kb
Host	smart-55c4308a-3be6-42f6-a9ad-19b10d4e6d22
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483237591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3483237591
Directory	/workspace/4.uart_loopback/latest

Test location	/workspace/coverage/default/4.uart_noise_filter.786573919
Short name	T428
Test name
Test status
Simulation time	180604167861 ps
CPU time	113.86 seconds
Started	Apr 15 02:51:28 PM PDT 24
Finished	Apr 15 02:53:23 PM PDT 24
Peak memory	201124 kb
Host	smart-e11c2014-1284-497c-ba45-6d02f23b054a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786573919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.786573919
Directory	/workspace/4.uart_noise_filter/latest

Test location	/workspace/coverage/default/4.uart_perf.1053097416
Short name	T486
Test name
Test status
Simulation time	9704813002 ps
CPU time	376.98 seconds
Started	Apr 15 02:51:29 PM PDT 24
Finished	Apr 15 02:57:46 PM PDT 24
Peak memory	200828 kb
Host	smart-a11d3fa7-b2bd-4813-a782-68687a4d7cc7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1053097416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1053097416
Directory	/workspace/4.uart_perf/latest

Test location	/workspace/coverage/default/4.uart_rx_oversample.8611929
Short name	T515
Test name
Test status
Simulation time	7036463218 ps
CPU time	6.84 seconds
Started	Apr 15 02:51:37 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	199064 kb
Host	smart-92c21a55-3289-426d-99a1-c6cb95c840a6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=8611929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.8611929
Directory	/workspace/4.uart_rx_oversample/latest

Test location	/workspace/coverage/default/4.uart_rx_parity_err.742656010
Short name	T497
Test name
Test status
Simulation time	70752416004 ps
CPU time	53.62 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 02:52:36 PM PDT 24
Peak memory	200688 kb
Host	smart-41c6618a-2720-4ab6-a7a4-86b62a5d9cee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742656010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.742656010
Directory	/workspace/4.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/4.uart_rx_start_bit_filter.4063972195
Short name	T321
Test name
Test status
Simulation time	3245094517 ps
CPU time	5.31 seconds
Started	Apr 15 02:51:22 PM PDT 24
Finished	Apr 15 02:51:28 PM PDT 24
Peak memory	196912 kb
Host	smart-e234d0d0-3279-4f9f-93f7-cb49c866d354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063972195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.4063972195
Directory	/workspace/4.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/4.uart_smoke.3966055575
Short name	T1166
Test name
Test status
Simulation time	943971257 ps
CPU time	3.1 seconds
Started	Apr 15 02:51:22 PM PDT 24
Finished	Apr 15 02:51:26 PM PDT 24
Peak memory	200296 kb
Host	smart-6ae4ed96-e778-47e9-8b45-c78ca14a425a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966055575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3966055575
Directory	/workspace/4.uart_smoke/latest

Test location	/workspace/coverage/default/4.uart_stress_all.3381905618
Short name	T747
Test name
Test status
Simulation time	358185001914 ps
CPU time	1411.75 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 03:15:09 PM PDT 24
Peak memory	200812 kb
Host	smart-69a88ffe-1a68-4674-83c2-f0d92bb0de3f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381905618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3381905618
Directory	/workspace/4.uart_stress_all/latest

Test location	/workspace/coverage/default/4.uart_stress_all_with_rand_reset.1290597636
Short name	T536
Test name
Test status
Simulation time	156011285772 ps
CPU time	1341.85 seconds
Started	Apr 15 02:51:28 PM PDT 24
Finished	Apr 15 03:13:51 PM PDT 24
Peak memory	226812 kb
Host	smart-502c0b0e-c194-4400-8ab3-f9b2ffaeec8e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290597636 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1290597636
Directory	/workspace/4.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.uart_tx_ovrd.1652551670
Short name	T401
Test name
Test status
Simulation time	1004828465 ps
CPU time	3.13 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:51:28 PM PDT 24
Peak memory	199604 kb
Host	smart-a078375b-4b6f-4455-88ca-b68e29490201
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652551670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1652551670
Directory	/workspace/4.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/4.uart_tx_rx.554079809
Short name	T1179
Test name
Test status
Simulation time	51970382158 ps
CPU time	82.87 seconds
Started	Apr 15 02:51:19 PM PDT 24
Finished	Apr 15 02:52:42 PM PDT 24
Peak memory	200928 kb
Host	smart-87cb9394-4d99-4488-8a5b-665d742612a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554079809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.554079809
Directory	/workspace/4.uart_tx_rx/latest

Test location	/workspace/coverage/default/40.uart_alert_test.1950247976
Short name	T574
Test name
Test status
Simulation time	13655423 ps
CPU time	0.53 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:53:26 PM PDT 24
Peak memory	195224 kb
Host	smart-8a587774-9041-46b1-92e2-3092a4118a62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950247976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1950247976
Directory	/workspace/40.uart_alert_test/latest

Test location	/workspace/coverage/default/40.uart_fifo_overflow.4070755559
Short name	T613
Test name
Test status
Simulation time	18578782414 ps
CPU time	29.59 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:53:56 PM PDT 24
Peak memory	200880 kb
Host	smart-173f5337-d2ff-44a2-8ca9-0291154c97c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070755559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4070755559
Directory	/workspace/40.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/40.uart_fifo_reset.3193005643
Short name	T581
Test name
Test status
Simulation time	35352749496 ps
CPU time	12.23 seconds
Started	Apr 15 02:53:22 PM PDT 24
Finished	Apr 15 02:53:35 PM PDT 24
Peak memory	199628 kb
Host	smart-3f98efc0-44b6-4f6d-9ae6-8d040e193111
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193005643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3193005643
Directory	/workspace/40.uart_fifo_reset/latest

Test location	/workspace/coverage/default/40.uart_intr.1490217941
Short name	T305
Test name
Test status
Simulation time	12222176460 ps
CPU time	21.51 seconds
Started	Apr 15 02:53:26 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	200796 kb
Host	smart-a221647c-1611-41f7-9fcc-93e4381a84de
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490217941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1490217941
Directory	/workspace/40.uart_intr/latest

Test location	/workspace/coverage/default/40.uart_long_xfer_wo_dly.1700151448
Short name	T1096
Test name
Test status
Simulation time	160115848633 ps
CPU time	1130.5 seconds
Started	Apr 15 02:53:24 PM PDT 24
Finished	Apr 15 03:12:15 PM PDT 24
Peak memory	200928 kb
Host	smart-5b7f27cd-c385-4d05-917a-b92ad44a284d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1700151448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1700151448
Directory	/workspace/40.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/40.uart_loopback.3261379013
Short name	T857
Test name
Test status
Simulation time	5043374826 ps
CPU time	3.22 seconds
Started	Apr 15 02:53:24 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	199572 kb
Host	smart-0769cbfb-b77f-44bd-b974-da1e96a15cf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261379013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3261379013
Directory	/workspace/40.uart_loopback/latest

Test location	/workspace/coverage/default/40.uart_noise_filter.2823364823
Short name	T922
Test name
Test status
Simulation time	403966293577 ps
CPU time	56.53 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:54:22 PM PDT 24
Peak memory	209288 kb
Host	smart-2cdb3fac-22c4-4792-a657-dbf50e4413b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2823364823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2823364823
Directory	/workspace/40.uart_noise_filter/latest

Test location	/workspace/coverage/default/40.uart_perf.2078912390
Short name	T644
Test name
Test status
Simulation time	28259130281 ps
CPU time	356.63 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:59:22 PM PDT 24
Peak memory	200840 kb
Host	smart-cf015ad8-5af2-4e50-92a0-253864df504f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2078912390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2078912390
Directory	/workspace/40.uart_perf/latest

Test location	/workspace/coverage/default/40.uart_rx_oversample.4100461907
Short name	T17
Test name
Test status
Simulation time	6958132918 ps
CPU time	60.51 seconds
Started	Apr 15 02:53:24 PM PDT 24
Finished	Apr 15 02:54:25 PM PDT 24
Peak memory	199176 kb
Host	smart-35f4a919-afe4-4c94-a2f3-c73ba5fc57db
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4100461907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4100461907
Directory	/workspace/40.uart_rx_oversample/latest

Test location	/workspace/coverage/default/40.uart_rx_parity_err.1815738563
Short name	T666
Test name
Test status
Simulation time	8580452821 ps
CPU time	16.49 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	200580 kb
Host	smart-8dc60423-e08e-4788-908a-3f2e2a5bd289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815738563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1815738563
Directory	/workspace/40.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/40.uart_rx_start_bit_filter.1329525371
Short name	T766
Test name
Test status
Simulation time	4207760173 ps
CPU time	4.36 seconds
Started	Apr 15 02:53:23 PM PDT 24
Finished	Apr 15 02:53:28 PM PDT 24
Peak memory	197208 kb
Host	smart-6a57ca56-b3c4-41ce-b937-155b2597bbde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329525371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1329525371
Directory	/workspace/40.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/40.uart_smoke.754960974
Short name	T310
Test name
Test status
Simulation time	11106479952 ps
CPU time	10.95 seconds
Started	Apr 15 02:53:24 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	200764 kb
Host	smart-cdf6b03a-e2a6-40f7-84e7-56698ce180e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754960974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.754960974
Directory	/workspace/40.uart_smoke/latest

Test location	/workspace/coverage/default/40.uart_stress_all.640764412
Short name	T352
Test name
Test status
Simulation time	298743617145 ps
CPU time	945.32 seconds
Started	Apr 15 02:53:26 PM PDT 24
Finished	Apr 15 03:09:12 PM PDT 24
Peak memory	200856 kb
Host	smart-13506da5-9bd9-4a1a-8519-f76640f9c77c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640764412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.640764412
Directory	/workspace/40.uart_stress_all/latest

Test location	/workspace/coverage/default/40.uart_stress_all_with_rand_reset.2504465312
Short name	T894
Test name
Test status
Simulation time	72100365095 ps
CPU time	820.28 seconds
Started	Apr 15 02:53:23 PM PDT 24
Finished	Apr 15 03:07:04 PM PDT 24
Peak memory	226168 kb
Host	smart-9d76f30f-8427-41ab-a9a0-a4186514272f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504465312 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2504465312
Directory	/workspace/40.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.uart_tx_ovrd.3530694290
Short name	T804
Test name
Test status
Simulation time	7116263133 ps
CPU time	25.55 seconds
Started	Apr 15 02:53:25 PM PDT 24
Finished	Apr 15 02:53:51 PM PDT 24
Peak memory	200852 kb
Host	smart-0890ea2a-db3d-4b05-bc94-846739df462a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3530694290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3530694290
Directory	/workspace/40.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/40.uart_tx_rx.3797817212
Short name	T606
Test name
Test status
Simulation time	36321939633 ps
CPU time	52.38 seconds
Started	Apr 15 02:53:24 PM PDT 24
Finished	Apr 15 02:54:17 PM PDT 24
Peak memory	200892 kb
Host	smart-2dc652fb-9a03-44e5-9364-31e9b2fac375
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797817212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3797817212
Directory	/workspace/40.uart_tx_rx/latest

Test location	/workspace/coverage/default/41.uart_alert_test.49882977
Short name	T891
Test name
Test status
Simulation time	14213703 ps
CPU time	0.58 seconds
Started	Apr 15 02:53:38 PM PDT 24
Finished	Apr 15 02:53:39 PM PDT 24
Peak memory	196196 kb
Host	smart-b0b06c16-ee6e-4188-90dc-f6acd9c2b81d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49882977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.49882977
Directory	/workspace/41.uart_alert_test/latest

Test location	/workspace/coverage/default/41.uart_fifo_full.2958046965
Short name	T641
Test name
Test status
Simulation time	145548123163 ps
CPU time	118.21 seconds
Started	Apr 15 02:53:27 PM PDT 24
Finished	Apr 15 02:55:26 PM PDT 24
Peak memory	200912 kb
Host	smart-dfe7f0ad-096b-4c80-9035-6c4f2aecabd7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958046965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2958046965
Directory	/workspace/41.uart_fifo_full/latest

Test location	/workspace/coverage/default/41.uart_fifo_overflow.1030688452
Short name	T57
Test name
Test status
Simulation time	68849117799 ps
CPU time	30.61 seconds
Started	Apr 15 02:53:31 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	200816 kb
Host	smart-48e34fe1-6108-4aec-9361-1a23d58c1fea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030688452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1030688452
Directory	/workspace/41.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/41.uart_fifo_reset.3861177403
Short name	T1005
Test name
Test status
Simulation time	25692520859 ps
CPU time	22.07 seconds
Started	Apr 15 02:53:27 PM PDT 24
Finished	Apr 15 02:53:50 PM PDT 24
Peak memory	200932 kb
Host	smart-c6021a77-4a1b-4973-88e2-2bcecf4cf0a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861177403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3861177403
Directory	/workspace/41.uart_fifo_reset/latest

Test location	/workspace/coverage/default/41.uart_intr.2665242797
Short name	T970
Test name
Test status
Simulation time	13218131872 ps
CPU time	6.11 seconds
Started	Apr 15 02:53:27 PM PDT 24
Finished	Apr 15 02:53:33 PM PDT 24
Peak memory	198028 kb
Host	smart-35826071-69dc-4749-b670-552848d8fd12
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665242797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2665242797
Directory	/workspace/41.uart_intr/latest

Test location	/workspace/coverage/default/41.uart_long_xfer_wo_dly.1887344907
Short name	T752
Test name
Test status
Simulation time	39929707103 ps
CPU time	129.53 seconds
Started	Apr 15 02:53:33 PM PDT 24
Finished	Apr 15 02:55:43 PM PDT 24
Peak memory	200848 kb
Host	smart-6f6b2139-f2d9-4f99-81f6-76da7e14681f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1887344907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1887344907
Directory	/workspace/41.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/41.uart_loopback.774426230
Short name	T755
Test name
Test status
Simulation time	139115133 ps
CPU time	1.06 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	198936 kb
Host	smart-f5b18e3f-6114-44c3-87f5-6cf51531e6ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=774426230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.774426230
Directory	/workspace/41.uart_loopback/latest

Test location	/workspace/coverage/default/41.uart_noise_filter.3808678025
Short name	T301
Test name
Test status
Simulation time	149669672668 ps
CPU time	131.06 seconds
Started	Apr 15 02:53:28 PM PDT 24
Finished	Apr 15 02:55:40 PM PDT 24
Peak memory	209060 kb
Host	smart-e58a8e16-9e9d-4a66-bd74-f245e1e25be7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808678025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3808678025
Directory	/workspace/41.uart_noise_filter/latest

Test location	/workspace/coverage/default/41.uart_perf.3983687801
Short name	T266
Test name
Test status
Simulation time	19126496724 ps
CPU time	1040.3 seconds
Started	Apr 15 02:53:31 PM PDT 24
Finished	Apr 15 03:10:52 PM PDT 24
Peak memory	200916 kb
Host	smart-fffd385b-cf9b-49ee-9f23-7688ce5d81ce
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3983687801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3983687801
Directory	/workspace/41.uart_perf/latest

Test location	/workspace/coverage/default/41.uart_rx_oversample.2301340520
Short name	T361
Test name
Test status
Simulation time	4276111254 ps
CPU time	16.76 seconds
Started	Apr 15 02:53:28 PM PDT 24
Finished	Apr 15 02:53:45 PM PDT 24
Peak memory	198908 kb
Host	smart-49b1af6f-91ab-4bb4-84e9-3d1d39a77bf4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2301340520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2301340520
Directory	/workspace/41.uart_rx_oversample/latest

Test location	/workspace/coverage/default/41.uart_rx_parity_err.2070140836
Short name	T865
Test name
Test status
Simulation time	158705618532 ps
CPU time	127.18 seconds
Started	Apr 15 02:53:29 PM PDT 24
Finished	Apr 15 02:55:37 PM PDT 24
Peak memory	200868 kb
Host	smart-2edd4d6e-8f5a-4b27-b52e-47756f3cb264
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070140836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2070140836
Directory	/workspace/41.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/41.uart_rx_start_bit_filter.3024818690
Short name	T522
Test name
Test status
Simulation time	36442769836 ps
CPU time	13.69 seconds
Started	Apr 15 02:53:28 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	196652 kb
Host	smart-23aff43f-fa25-4af8-bf8e-2a2b2d777ec7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024818690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3024818690
Directory	/workspace/41.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/41.uart_smoke.646596793
Short name	T439
Test name
Test status
Simulation time	506500226 ps
CPU time	1.95 seconds
Started	Apr 15 02:53:27 PM PDT 24
Finished	Apr 15 02:53:30 PM PDT 24
Peak memory	199492 kb
Host	smart-886dbea3-4c53-4d55-8aaa-991e1314bf74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=646596793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.646596793
Directory	/workspace/41.uart_smoke/latest

Test location	/workspace/coverage/default/41.uart_stress_all.3052379826
Short name	T1075
Test name
Test status
Simulation time	351041938577 ps
CPU time	1538.94 seconds
Started	Apr 15 02:53:38 PM PDT 24
Finished	Apr 15 03:19:18 PM PDT 24
Peak memory	200792 kb
Host	smart-3d2456aa-05e9-4f32-aa93-bfaa3488c547
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052379826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3052379826
Directory	/workspace/41.uart_stress_all/latest

Test location	/workspace/coverage/default/41.uart_stress_all_with_rand_reset.2980926126
Short name	T761
Test name
Test status
Simulation time	124177910231 ps
CPU time	314.35 seconds
Started	Apr 15 02:53:39 PM PDT 24
Finished	Apr 15 02:58:54 PM PDT 24
Peak memory	216612 kb
Host	smart-cf988e6c-4186-4dce-b1e5-86e4c4113636
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980926126 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2980926126
Directory	/workspace/41.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.uart_tx_ovrd.3115385056
Short name	T964
Test name
Test status
Simulation time	1405740086 ps
CPU time	1.59 seconds
Started	Apr 15 02:53:26 PM PDT 24
Finished	Apr 15 02:53:29 PM PDT 24
Peak memory	199144 kb
Host	smart-863acfc3-edaa-4f63-9717-63b7beefa7a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115385056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3115385056
Directory	/workspace/41.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/41.uart_tx_rx.3605873843
Short name	T714
Test name
Test status
Simulation time	27404022575 ps
CPU time	41.87 seconds
Started	Apr 15 02:53:27 PM PDT 24
Finished	Apr 15 02:54:10 PM PDT 24
Peak memory	200820 kb
Host	smart-10ece2c3-c262-4bfb-9e3f-66c86e679d83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605873843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3605873843
Directory	/workspace/41.uart_tx_rx/latest

Test location	/workspace/coverage/default/42.uart_alert_test.1384174180
Short name	T975
Test name
Test status
Simulation time	33767953 ps
CPU time	0.53 seconds
Started	Apr 15 02:53:37 PM PDT 24
Finished	Apr 15 02:53:38 PM PDT 24
Peak memory	196216 kb
Host	smart-1a677b36-2ce6-4452-9ec5-86b7095bcdd5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384174180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1384174180
Directory	/workspace/42.uart_alert_test/latest

Test location	/workspace/coverage/default/42.uart_fifo_full.3114424901
Short name	T1088
Test name
Test status
Simulation time	25810104446 ps
CPU time	44.48 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:54:17 PM PDT 24
Peak memory	200828 kb
Host	smart-75194267-6489-4c71-9d3d-fe161eda41c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114424901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3114424901
Directory	/workspace/42.uart_fifo_full/latest

Test location	/workspace/coverage/default/42.uart_fifo_overflow.2939492665
Short name	T413
Test name
Test status
Simulation time	35588142321 ps
CPU time	16.92 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:53:50 PM PDT 24
Peak memory	200884 kb
Host	smart-e5f035c4-a39f-44ab-ac94-757c3f026006
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939492665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2939492665
Directory	/workspace/42.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/42.uart_fifo_reset.401539190
Short name	T193
Test name
Test status
Simulation time	45551527382 ps
CPU time	24.9 seconds
Started	Apr 15 02:53:36 PM PDT 24
Finished	Apr 15 02:54:01 PM PDT 24
Peak memory	200912 kb
Host	smart-bc347576-4750-4061-b12d-bfed715d119a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401539190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.401539190
Directory	/workspace/42.uart_fifo_reset/latest

Test location	/workspace/coverage/default/42.uart_intr.824846144
Short name	T941
Test name
Test status
Simulation time	255638396944 ps
CPU time	103.17 seconds
Started	Apr 15 02:53:31 PM PDT 24
Finished	Apr 15 02:55:15 PM PDT 24
Peak memory	199440 kb
Host	smart-65c47316-d9e5-447c-aa2b-6a275c79371d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824846144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.824846144
Directory	/workspace/42.uart_intr/latest

Test location	/workspace/coverage/default/42.uart_long_xfer_wo_dly.1937867032
Short name	T566
Test name
Test status
Simulation time	115485731701 ps
CPU time	1046.14 seconds
Started	Apr 15 02:53:37 PM PDT 24
Finished	Apr 15 03:11:04 PM PDT 24
Peak memory	200844 kb
Host	smart-2471c89f-a77f-47ce-aa37-af5236ea2a12
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1937867032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1937867032
Directory	/workspace/42.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/42.uart_loopback.1666836085
Short name	T377
Test name
Test status
Simulation time	4182004242 ps
CPU time	2.39 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	197460 kb
Host	smart-f94b732b-da2d-4d4a-b09f-075ddf9cd843
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666836085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1666836085
Directory	/workspace/42.uart_loopback/latest

Test location	/workspace/coverage/default/42.uart_noise_filter.1264142672
Short name	T276
Test name
Test status
Simulation time	55495454371 ps
CPU time	123.37 seconds
Started	Apr 15 02:53:37 PM PDT 24
Finished	Apr 15 02:55:41 PM PDT 24
Peak memory	200844 kb
Host	smart-61c736c6-2f4d-432e-8b1c-4ff2576de59b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264142672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1264142672
Directory	/workspace/42.uart_noise_filter/latest

Test location	/workspace/coverage/default/42.uart_perf.893933167
Short name	T534
Test name
Test status
Simulation time	13600531895 ps
CPU time	228.48 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:57:30 PM PDT 24
Peak memory	200832 kb
Host	smart-329a9145-5b8e-4945-9774-151b8e7942bf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=893933167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.893933167
Directory	/workspace/42.uart_perf/latest

Test location	/workspace/coverage/default/42.uart_rx_oversample.852956013
Short name	T956
Test name
Test status
Simulation time	2917041949 ps
CPU time	2.74 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:53:36 PM PDT 24
Peak memory	199760 kb
Host	smart-81ee6e9b-a702-4863-83ac-e2dbcb2c372f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=852956013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.852956013
Directory	/workspace/42.uart_rx_oversample/latest

Test location	/workspace/coverage/default/42.uart_rx_parity_err.2974617771
Short name	T164
Test name
Test status
Simulation time	256747836106 ps
CPU time	81.14 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:54:54 PM PDT 24
Peak memory	200820 kb
Host	smart-50b80bef-3edb-4992-b358-506837c3e196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974617771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2974617771
Directory	/workspace/42.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/42.uart_rx_start_bit_filter.1588111839
Short name	T468
Test name
Test status
Simulation time	1577434561 ps
CPU time	1.86 seconds
Started	Apr 15 02:53:39 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	196552 kb
Host	smart-461a420a-9df5-4843-ac8d-7d7b0c07d67e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1588111839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1588111839
Directory	/workspace/42.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/42.uart_smoke.2443958933
Short name	T873
Test name
Test status
Simulation time	635158506 ps
CPU time	1.77 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:53:34 PM PDT 24
Peak memory	200428 kb
Host	smart-cd54118e-6b0f-4c58-9526-39ecdc88b5f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443958933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2443958933
Directory	/workspace/42.uart_smoke/latest

Test location	/workspace/coverage/default/42.uart_stress_all.398419696
Short name	T429
Test name
Test status
Simulation time	189969509334 ps
CPU time	324.96 seconds
Started	Apr 15 02:53:43 PM PDT 24
Finished	Apr 15 02:59:09 PM PDT 24
Peak memory	217352 kb
Host	smart-0c209c6f-eeb4-4011-b60c-e172dc4aa157
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398419696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.398419696
Directory	/workspace/42.uart_stress_all/latest

Test location	/workspace/coverage/default/42.uart_stress_all_with_rand_reset.1669115642
Short name	T52
Test name
Test status
Simulation time	86696165331 ps
CPU time	808.28 seconds
Started	Apr 15 02:53:39 PM PDT 24
Finished	Apr 15 03:07:08 PM PDT 24
Peak memory	230064 kb
Host	smart-0cc820f5-a116-4371-85e4-978c2d35b173
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669115642 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1669115642
Directory	/workspace/42.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.uart_tx_ovrd.2328016496
Short name	T374
Test name
Test status
Simulation time	600226452 ps
CPU time	1.05 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	199524 kb
Host	smart-94858de1-0baf-4d5e-b562-7907cd581904
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328016496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2328016496
Directory	/workspace/42.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/42.uart_tx_rx.4245311837
Short name	T1058
Test name
Test status
Simulation time	70012726033 ps
CPU time	91.22 seconds
Started	Apr 15 02:53:32 PM PDT 24
Finished	Apr 15 02:55:04 PM PDT 24
Peak memory	200912 kb
Host	smart-12fb9ee1-7348-40c7-b0a4-174da53cbcf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245311837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4245311837
Directory	/workspace/42.uart_tx_rx/latest

Test location	/workspace/coverage/default/43.uart_alert_test.2038555789
Short name	T787
Test name
Test status
Simulation time	41241961 ps
CPU time	0.59 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:53:41 PM PDT 24
Peak memory	195676 kb
Host	smart-fe2a952a-4e73-4b76-aeb8-9c5041c660d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038555789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2038555789
Directory	/workspace/43.uart_alert_test/latest

Test location	/workspace/coverage/default/43.uart_fifo_full.2030473735
Short name	T420
Test name
Test status
Simulation time	44279829319 ps
CPU time	68.81 seconds
Started	Apr 15 02:53:38 PM PDT 24
Finished	Apr 15 02:54:47 PM PDT 24
Peak memory	200864 kb
Host	smart-74a34b5b-fbd9-43f8-b55e-ff72e4b064f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030473735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2030473735
Directory	/workspace/43.uart_fifo_full/latest

Test location	/workspace/coverage/default/43.uart_fifo_overflow.2524848296
Short name	T957
Test name
Test status
Simulation time	11521289905 ps
CPU time	20.19 seconds
Started	Apr 15 02:53:37 PM PDT 24
Finished	Apr 15 02:53:58 PM PDT 24
Peak memory	200884 kb
Host	smart-a4ef06ea-1f2f-4094-b9b4-b493546dc6af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524848296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2524848296
Directory	/workspace/43.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/43.uart_fifo_reset.786263558
Short name	T1043
Test name
Test status
Simulation time	4653219216 ps
CPU time	5.18 seconds
Started	Apr 15 02:53:42 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	200836 kb
Host	smart-6e5b1ce1-abda-4bbc-aa5a-6a00d30e4424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=786263558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.786263558
Directory	/workspace/43.uart_fifo_reset/latest

Test location	/workspace/coverage/default/43.uart_intr.436265753
Short name	T120
Test name
Test status
Simulation time	76748694735 ps
CPU time	120.98 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:55:41 PM PDT 24
Peak memory	200924 kb
Host	smart-f9c16119-17ab-4d67-bab9-1b2313e9b1df
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436265753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.436265753
Directory	/workspace/43.uart_intr/latest

Test location	/workspace/coverage/default/43.uart_long_xfer_wo_dly.177806077
Short name	T986
Test name
Test status
Simulation time	120229959198 ps
CPU time	252.3 seconds
Started	Apr 15 02:53:43 PM PDT 24
Finished	Apr 15 02:57:56 PM PDT 24
Peak memory	200836 kb
Host	smart-1a30fb10-4966-49bf-82ff-73238485657f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=177806077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.177806077
Directory	/workspace/43.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/43.uart_loopback.2258637167
Short name	T1131
Test name
Test status
Simulation time	3163917946 ps
CPU time	2.75 seconds
Started	Apr 15 02:53:39 PM PDT 24
Finished	Apr 15 02:53:42 PM PDT 24
Peak memory	198468 kb
Host	smart-32ba98e6-1110-409f-b278-0cfaa12d750b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258637167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2258637167
Directory	/workspace/43.uart_loopback/latest

Test location	/workspace/coverage/default/43.uart_noise_filter.898410381
Short name	T308
Test name
Test status
Simulation time	125977152846 ps
CPU time	118.88 seconds
Started	Apr 15 02:53:38 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	201084 kb
Host	smart-2af35212-159a-453c-bb1a-3d308ccd286d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898410381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.898410381
Directory	/workspace/43.uart_noise_filter/latest

Test location	/workspace/coverage/default/43.uart_perf.3360258171
Short name	T363
Test name
Test status
Simulation time	11280155967 ps
CPU time	557.59 seconds
Started	Apr 15 02:53:42 PM PDT 24
Finished	Apr 15 03:03:00 PM PDT 24
Peak memory	200904 kb
Host	smart-3624b149-b87c-4b2a-9768-3de03e8692d5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3360258171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3360258171
Directory	/workspace/43.uart_perf/latest

Test location	/workspace/coverage/default/43.uart_rx_oversample.3349868409
Short name	T384
Test name
Test status
Simulation time	1663903195 ps
CPU time	2.92 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	199356 kb
Host	smart-df2bff8b-91bd-42a9-b15e-2c68ed61c4c3
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3349868409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3349868409
Directory	/workspace/43.uart_rx_oversample/latest

Test location	/workspace/coverage/default/43.uart_rx_parity_err.2394153454
Short name	T596
Test name
Test status
Simulation time	36174638513 ps
CPU time	62.16 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:54:43 PM PDT 24
Peak memory	200816 kb
Host	smart-028d5fda-5c65-4a27-9a8e-3ef615389edb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394153454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2394153454
Directory	/workspace/43.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/43.uart_rx_start_bit_filter.3759412336
Short name	T460
Test name
Test status
Simulation time	49433751290 ps
CPU time	41.33 seconds
Started	Apr 15 02:53:39 PM PDT 24
Finished	Apr 15 02:54:21 PM PDT 24
Peak memory	196680 kb
Host	smart-077769fe-2589-49a8-b961-f23c408fd751
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3759412336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3759412336
Directory	/workspace/43.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/43.uart_smoke.1798559962
Short name	T470
Test name
Test status
Simulation time	5759245970 ps
CPU time	4.59 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:53:46 PM PDT 24
Peak memory	200592 kb
Host	smart-8cfe66f5-1912-4b75-94f7-4862a0dc3481
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798559962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1798559962
Directory	/workspace/43.uart_smoke/latest

Test location	/workspace/coverage/default/43.uart_stress_all.2909969769
Short name	T643
Test name
Test status
Simulation time	37794820407 ps
CPU time	61.36 seconds
Started	Apr 15 02:53:42 PM PDT 24
Finished	Apr 15 02:54:44 PM PDT 24
Peak memory	217472 kb
Host	smart-db129224-cb71-4c82-acfb-5e10327126aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909969769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2909969769
Directory	/workspace/43.uart_stress_all/latest

Test location	/workspace/coverage/default/43.uart_stress_all_with_rand_reset.2674404452
Short name	T987
Test name
Test status
Simulation time	58400284628 ps
CPU time	635.23 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 03:04:17 PM PDT 24
Peak memory	217352 kb
Host	smart-63b0eb35-2f0e-4ce8-a8a0-765e47708789
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674404452 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2674404452
Directory	/workspace/43.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.uart_tx_ovrd.810177350
Short name	T612
Test name
Test status
Simulation time	920255904 ps
CPU time	3.22 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:53:44 PM PDT 24
Peak memory	200292 kb
Host	smart-db447de1-f167-4cbd-b2f7-56aab9231847
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=810177350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.810177350
Directory	/workspace/43.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/43.uart_tx_rx.914420389
Short name	T764
Test name
Test status
Simulation time	36565400311 ps
CPU time	16.96 seconds
Started	Apr 15 02:53:37 PM PDT 24
Finished	Apr 15 02:53:55 PM PDT 24
Peak memory	200836 kb
Host	smart-61611a1e-5a9e-43ea-90f4-7b9f5f5df717
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914420389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.914420389
Directory	/workspace/43.uart_tx_rx/latest

Test location	/workspace/coverage/default/44.uart_alert_test.1949671307
Short name	T960
Test name
Test status
Simulation time	13419019 ps
CPU time	0.58 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:53:47 PM PDT 24
Peak memory	196204 kb
Host	smart-024cd9aa-fb57-409b-8ad2-06f5e1867c96
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949671307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1949671307
Directory	/workspace/44.uart_alert_test/latest

Test location	/workspace/coverage/default/44.uart_fifo_full.3764997662
Short name	T445
Test name
Test status
Simulation time	83983483276 ps
CPU time	40.95 seconds
Started	Apr 15 02:53:41 PM PDT 24
Finished	Apr 15 02:54:23 PM PDT 24
Peak memory	200856 kb
Host	smart-6f50448c-0d77-4b24-897e-e40fe4e01085
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3764997662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3764997662
Directory	/workspace/44.uart_fifo_full/latest

Test location	/workspace/coverage/default/44.uart_fifo_overflow.3593712346
Short name	T907
Test name
Test status
Simulation time	185792835270 ps
CPU time	243.39 seconds
Started	Apr 15 02:53:46 PM PDT 24
Finished	Apr 15 02:57:50 PM PDT 24
Peak memory	200896 kb
Host	smart-ab184357-93dd-4d25-a119-f7705bc4155a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3593712346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3593712346
Directory	/workspace/44.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/44.uart_fifo_reset.2022354501
Short name	T695
Test name
Test status
Simulation time	18264514370 ps
CPU time	27.67 seconds
Started	Apr 15 02:53:47 PM PDT 24
Finished	Apr 15 02:54:15 PM PDT 24
Peak memory	200896 kb
Host	smart-16673bf1-3c51-41b1-b11a-3317d69056fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022354501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2022354501
Directory	/workspace/44.uart_fifo_reset/latest

Test location	/workspace/coverage/default/44.uart_intr.1484903593
Short name	T372
Test name
Test status
Simulation time	13746515921 ps
CPU time	13.94 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:54:00 PM PDT 24
Peak memory	200256 kb
Host	smart-c29cfd3e-e4c9-4cab-9d2b-dc5b6ecff106
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484903593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1484903593
Directory	/workspace/44.uart_intr/latest

Test location	/workspace/coverage/default/44.uart_long_xfer_wo_dly.1041159248
Short name	T265
Test name
Test status
Simulation time	133845456474 ps
CPU time	200.46 seconds
Started	Apr 15 02:53:47 PM PDT 24
Finished	Apr 15 02:57:08 PM PDT 24
Peak memory	200868 kb
Host	smart-8749db3a-87c7-4137-86d9-ef6853bc543c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1041159248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1041159248
Directory	/workspace/44.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/44.uart_loopback.1283994110
Short name	T934
Test name
Test status
Simulation time	3312969430 ps
CPU time	12.05 seconds
Started	Apr 15 02:53:46 PM PDT 24
Finished	Apr 15 02:53:58 PM PDT 24
Peak memory	200472 kb
Host	smart-e38ea53a-f969-456f-af63-d4a1dd2729fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283994110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1283994110
Directory	/workspace/44.uart_loopback/latest

Test location	/workspace/coverage/default/44.uart_noise_filter.2006460130
Short name	T985
Test name
Test status
Simulation time	14321543666 ps
CPU time	22.41 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:54:08 PM PDT 24
Peak memory	196536 kb
Host	smart-2b8ca63b-8ea5-4d2b-a364-a3bf83b05b9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006460130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2006460130
Directory	/workspace/44.uart_noise_filter/latest

Test location	/workspace/coverage/default/44.uart_perf.281081543
Short name	T806
Test name
Test status
Simulation time	20471260051 ps
CPU time	241.97 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:57:47 PM PDT 24
Peak memory	200848 kb
Host	smart-4d43c01d-0d93-4c28-95f4-a072bf10b35a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=281081543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.281081543
Directory	/workspace/44.uart_perf/latest

Test location	/workspace/coverage/default/44.uart_rx_oversample.1034844443
Short name	T557
Test name
Test status
Simulation time	4312291841 ps
CPU time	40.99 seconds
Started	Apr 15 02:53:40 PM PDT 24
Finished	Apr 15 02:54:22 PM PDT 24
Peak memory	199196 kb
Host	smart-7f467362-6448-4af5-9c31-a311c42e715b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1034844443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1034844443
Directory	/workspace/44.uart_rx_oversample/latest

Test location	/workspace/coverage/default/44.uart_rx_parity_err.4147099375
Short name	T172
Test name
Test status
Simulation time	197622884201 ps
CPU time	93.18 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:55:19 PM PDT 24
Peak memory	200832 kb
Host	smart-e59b1701-8729-4220-88df-84851673213a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4147099375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4147099375
Directory	/workspace/44.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/44.uart_rx_start_bit_filter.4057296941
Short name	T1116
Test name
Test status
Simulation time	2151257164 ps
CPU time	3.69 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:53:49 PM PDT 24
Peak memory	196648 kb
Host	smart-802c968c-aba9-4d29-ab51-3bd4c3583b6a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057296941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.4057296941
Directory	/workspace/44.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/44.uart_smoke.2396050503
Short name	T757
Test name
Test status
Simulation time	445146291 ps
CPU time	1.89 seconds
Started	Apr 15 02:53:41 PM PDT 24
Finished	Apr 15 02:53:44 PM PDT 24
Peak memory	199168 kb
Host	smart-fd2ea2f9-9b58-438b-8c7f-69a81938b4bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396050503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2396050503
Directory	/workspace/44.uart_smoke/latest

Test location	/workspace/coverage/default/44.uart_stress_all.546711391
Short name	T344
Test name
Test status
Simulation time	316255503585 ps
CPU time	610.8 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 03:03:56 PM PDT 24
Peak memory	200900 kb
Host	smart-c7735ac1-482c-41e1-b9ea-4251fc409837
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546711391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.546711391
Directory	/workspace/44.uart_stress_all/latest

Test location	/workspace/coverage/default/44.uart_stress_all_with_rand_reset.1259431837
Short name	T746
Test name
Test status
Simulation time	432518900945 ps
CPU time	983.42 seconds
Started	Apr 15 02:53:43 PM PDT 24
Finished	Apr 15 03:10:07 PM PDT 24
Peak memory	225712 kb
Host	smart-d671ff6a-7022-4472-bbdd-6241e7fb4ea4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259431837 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1259431837
Directory	/workspace/44.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.uart_tx_ovrd.1139013831
Short name	T552
Test name
Test status
Simulation time	2084719650 ps
CPU time	1.77 seconds
Started	Apr 15 02:53:44 PM PDT 24
Finished	Apr 15 02:53:46 PM PDT 24
Peak memory	199268 kb
Host	smart-b5b4e8ae-79d8-4742-a09f-84c836e64e12
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139013831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1139013831
Directory	/workspace/44.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/44.uart_tx_rx.176995953
Short name	T828
Test name
Test status
Simulation time	60000693436 ps
CPU time	41.83 seconds
Started	Apr 15 02:53:45 PM PDT 24
Finished	Apr 15 02:54:28 PM PDT 24
Peak memory	200824 kb
Host	smart-6c32cf7c-a393-4d6c-b37a-88f8354f9eef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176995953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.176995953
Directory	/workspace/44.uart_tx_rx/latest

Test location	/workspace/coverage/default/45.uart_alert_test.4230562194
Short name	T1111
Test name
Test status
Simulation time	11645576 ps
CPU time	0.58 seconds
Started	Apr 15 02:53:54 PM PDT 24
Finished	Apr 15 02:53:55 PM PDT 24
Peak memory	196364 kb
Host	smart-979a0c6b-9bc1-4455-a366-607b6b997587
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230562194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4230562194
Directory	/workspace/45.uart_alert_test/latest

Test location	/workspace/coverage/default/45.uart_fifo_full.2557600993
Short name	T969
Test name
Test status
Simulation time	75884499214 ps
CPU time	54.28 seconds
Started	Apr 15 02:53:51 PM PDT 24
Finished	Apr 15 02:54:46 PM PDT 24
Peak memory	200908 kb
Host	smart-3f47a09f-beaa-46fc-9dc5-4795358b238e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2557600993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2557600993
Directory	/workspace/45.uart_fifo_full/latest

Test location	/workspace/coverage/default/45.uart_fifo_overflow.2445105253
Short name	T955
Test name
Test status
Simulation time	182203242325 ps
CPU time	71.99 seconds
Started	Apr 15 02:53:50 PM PDT 24
Finished	Apr 15 02:55:03 PM PDT 24
Peak memory	200796 kb
Host	smart-f7dfaf7e-51fe-4c5b-81ce-3f3f10282e37
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445105253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2445105253
Directory	/workspace/45.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/45.uart_intr.2710427305
Short name	T346
Test name
Test status
Simulation time	51579993686 ps
CPU time	70.12 seconds
Started	Apr 15 02:53:51 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200908 kb
Host	smart-e45c12f5-e5a4-4548-84e9-5f5c6c97916d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710427305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2710427305
Directory	/workspace/45.uart_intr/latest

Test location	/workspace/coverage/default/45.uart_long_xfer_wo_dly.1486741236
Short name	T521
Test name
Test status
Simulation time	65802017114 ps
CPU time	266.67 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:58:25 PM PDT 24
Peak memory	200828 kb
Host	smart-827ab724-cc54-493e-b04b-6f8192ac94b2
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1486741236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1486741236
Directory	/workspace/45.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/45.uart_loopback.2715568299
Short name	T370
Test name
Test status
Simulation time	12970278440 ps
CPU time	22.61 seconds
Started	Apr 15 02:53:48 PM PDT 24
Finished	Apr 15 02:54:11 PM PDT 24
Peak memory	200560 kb
Host	smart-be4ab376-64e7-4382-8298-18365f3a0012
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715568299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2715568299
Directory	/workspace/45.uart_loopback/latest

Test location	/workspace/coverage/default/45.uart_noise_filter.1804308927
Short name	T600
Test name
Test status
Simulation time	45345354667 ps
CPU time	17.57 seconds
Started	Apr 15 02:53:47 PM PDT 24
Finished	Apr 15 02:54:05 PM PDT 24
Peak memory	201092 kb
Host	smart-0258f5a5-c1fa-4af9-92de-716abc9cce47
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1804308927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1804308927
Directory	/workspace/45.uart_noise_filter/latest

Test location	/workspace/coverage/default/45.uart_perf.3964514492
Short name	T633
Test name
Test status
Simulation time	8194978743 ps
CPU time	451.29 seconds
Started	Apr 15 02:53:49 PM PDT 24
Finished	Apr 15 03:01:21 PM PDT 24
Peak memory	200924 kb
Host	smart-b5cd5456-c2ea-4728-9408-f565fb362103
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3964514492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3964514492
Directory	/workspace/45.uart_perf/latest

Test location	/workspace/coverage/default/45.uart_rx_oversample.3262540735
Short name	T874
Test name
Test status
Simulation time	2018140178 ps
CPU time	3.75 seconds
Started	Apr 15 02:53:49 PM PDT 24
Finished	Apr 15 02:53:53 PM PDT 24
Peak memory	198808 kb
Host	smart-94132241-6468-456c-b2c5-ce5b190214a9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3262540735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3262540735
Directory	/workspace/45.uart_rx_oversample/latest

Test location	/workspace/coverage/default/45.uart_rx_parity_err.4074896586
Short name	T684
Test name
Test status
Simulation time	44990803373 ps
CPU time	42.35 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:54:39 PM PDT 24
Peak memory	200852 kb
Host	smart-0501286b-471c-4045-be46-fb880b18d342
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074896586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4074896586
Directory	/workspace/45.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/45.uart_rx_start_bit_filter.4045826858
Short name	T702
Test name
Test status
Simulation time	39923468915 ps
CPU time	5.64 seconds
Started	Apr 15 02:53:48 PM PDT 24
Finished	Apr 15 02:53:54 PM PDT 24
Peak memory	196624 kb
Host	smart-1faa23a8-9162-4b05-9f6f-e4abbeabe0e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045826858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.4045826858
Directory	/workspace/45.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/45.uart_smoke.3532865039
Short name	T1022
Test name
Test status
Simulation time	688190861 ps
CPU time	2.71 seconds
Started	Apr 15 02:53:44 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	199700 kb
Host	smart-c6c01aa5-4740-49b2-a7b9-ab4be4168a2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532865039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3532865039
Directory	/workspace/45.uart_smoke/latest

Test location	/workspace/coverage/default/45.uart_stress_all.73610422
Short name	T916
Test name
Test status
Simulation time	335662538047 ps
CPU time	1086.53 seconds
Started	Apr 15 02:53:54 PM PDT 24
Finished	Apr 15 03:12:01 PM PDT 24
Peak memory	209112 kb
Host	smart-4820ce22-a688-46bd-8ec9-271c3f7a98f2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73610422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.73610422
Directory	/workspace/45.uart_stress_all/latest

Test location	/workspace/coverage/default/45.uart_stress_all_with_rand_reset.2170511760
Short name	T50
Test name
Test status
Simulation time	58700064019 ps
CPU time	290.63 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:58:50 PM PDT 24
Peak memory	217336 kb
Host	smart-352291a1-503c-4770-a297-14b1cf48df89
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170511760 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2170511760
Directory	/workspace/45.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.uart_tx_ovrd.1067054685
Short name	T716
Test name
Test status
Simulation time	2050726043 ps
CPU time	2.37 seconds
Started	Apr 15 02:53:49 PM PDT 24
Finished	Apr 15 02:53:52 PM PDT 24
Peak memory	199736 kb
Host	smart-dc0670ff-8bc9-4142-a091-8bc5d59a6d44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067054685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1067054685
Directory	/workspace/45.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/45.uart_tx_rx.853744349
Short name	T988
Test name
Test status
Simulation time	14940590899 ps
CPU time	26.08 seconds
Started	Apr 15 02:53:47 PM PDT 24
Finished	Apr 15 02:54:13 PM PDT 24
Peak memory	200832 kb
Host	smart-65b642de-e653-4d9a-91ba-c80c0d0f53f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853744349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.853744349
Directory	/workspace/45.uart_tx_rx/latest

Test location	/workspace/coverage/default/46.uart_alert_test.3210036381
Short name	T1080
Test name
Test status
Simulation time	20327723 ps
CPU time	0.55 seconds
Started	Apr 15 02:53:57 PM PDT 24
Finished	Apr 15 02:53:58 PM PDT 24
Peak memory	195712 kb
Host	smart-7860843b-d8ee-4bba-aab7-86874bdd0b3c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210036381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3210036381
Directory	/workspace/46.uart_alert_test/latest

Test location	/workspace/coverage/default/46.uart_fifo_full.793846257
Short name	T845
Test name
Test status
Simulation time	34522904797 ps
CPU time	13.82 seconds
Started	Apr 15 02:53:52 PM PDT 24
Finished	Apr 15 02:54:07 PM PDT 24
Peak memory	200880 kb
Host	smart-70f73e03-0ca1-4f7c-8bb6-6ca9ba8b0299
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793846257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.793846257
Directory	/workspace/46.uart_fifo_full/latest

Test location	/workspace/coverage/default/46.uart_fifo_overflow.358536315
Short name	T159
Test name
Test status
Simulation time	17294244670 ps
CPU time	33.1 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:54:30 PM PDT 24
Peak memory	200884 kb
Host	smart-32c04609-d370-4444-965d-a68b546d6ac6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358536315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.358536315
Directory	/workspace/46.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/46.uart_intr.892321327
Short name	T595
Test name
Test status
Simulation time	13859001251 ps
CPU time	19.52 seconds
Started	Apr 15 02:53:55 PM PDT 24
Finished	Apr 15 02:54:15 PM PDT 24
Peak memory	197468 kb
Host	smart-1ddf4f21-de2b-4771-9d1e-6fc5e9bdfd4b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892321327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.892321327
Directory	/workspace/46.uart_intr/latest

Test location	/workspace/coverage/default/46.uart_long_xfer_wo_dly.3779863651
Short name	T415
Test name
Test status
Simulation time	170812003711 ps
CPU time	607.18 seconds
Started	Apr 15 02:53:57 PM PDT 24
Finished	Apr 15 03:04:04 PM PDT 24
Peak memory	200904 kb
Host	smart-7a5fb76f-6537-4815-91b0-52bdc319b045
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3779863651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3779863651
Directory	/workspace/46.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/46.uart_loopback.1188613288
Short name	T1139
Test name
Test status
Simulation time	3583520734 ps
CPU time	6.49 seconds
Started	Apr 15 02:53:57 PM PDT 24
Finished	Apr 15 02:54:04 PM PDT 24
Peak memory	198148 kb
Host	smart-0cc28452-a357-41ab-aae6-1605bb9c64a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188613288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1188613288
Directory	/workspace/46.uart_loopback/latest

Test location	/workspace/coverage/default/46.uart_noise_filter.205552525
Short name	T623
Test name
Test status
Simulation time	115451044369 ps
CPU time	98.97 seconds
Started	Apr 15 02:53:53 PM PDT 24
Finished	Apr 15 02:55:33 PM PDT 24
Peak memory	209236 kb
Host	smart-e76d510e-10a1-4088-92d7-4501a8844899
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205552525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.205552525
Directory	/workspace/46.uart_noise_filter/latest

Test location	/workspace/coverage/default/46.uart_perf.3626673519
Short name	T297
Test name
Test status
Simulation time	10949421590 ps
CPU time	153.83 seconds
Started	Apr 15 02:53:57 PM PDT 24
Finished	Apr 15 02:56:32 PM PDT 24
Peak memory	200868 kb
Host	smart-4888aaaf-cb0f-4ea3-a704-32604a2f50cf
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3626673519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3626673519
Directory	/workspace/46.uart_perf/latest

Test location	/workspace/coverage/default/46.uart_rx_oversample.2353413399
Short name	T722
Test name
Test status
Simulation time	2013715501 ps
CPU time	2.92 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:53:59 PM PDT 24
Peak memory	198920 kb
Host	smart-544fd71b-6fc6-4416-8e1d-2212850ba2a4
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2353413399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2353413399
Directory	/workspace/46.uart_rx_oversample/latest

Test location	/workspace/coverage/default/46.uart_rx_parity_err.2640284347
Short name	T892
Test name
Test status
Simulation time	49467715471 ps
CPU time	89.76 seconds
Started	Apr 15 02:53:54 PM PDT 24
Finished	Apr 15 02:55:24 PM PDT 24
Peak memory	200896 kb
Host	smart-e88d9980-be8c-4525-a662-57bd57b49968
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640284347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2640284347
Directory	/workspace/46.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/46.uart_rx_start_bit_filter.1574500122
Short name	T901
Test name
Test status
Simulation time	5908488552 ps
CPU time	4.57 seconds
Started	Apr 15 02:53:51 PM PDT 24
Finished	Apr 15 02:53:56 PM PDT 24
Peak memory	196940 kb
Host	smart-1e4cb339-1772-4820-ac96-e74774c823c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574500122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1574500122
Directory	/workspace/46.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/46.uart_smoke.3588121389
Short name	T772
Test name
Test status
Simulation time	526935893 ps
CPU time	1.51 seconds
Started	Apr 15 02:53:55 PM PDT 24
Finished	Apr 15 02:53:57 PM PDT 24
Peak memory	200188 kb
Host	smart-70b5d2dd-2001-44e3-8ff2-93d114f94003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588121389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3588121389
Directory	/workspace/46.uart_smoke/latest

Test location	/workspace/coverage/default/46.uart_stress_all.2532787797
Short name	T605
Test name
Test status
Simulation time	134125598155 ps
CPU time	385.67 seconds
Started	Apr 15 02:53:57 PM PDT 24
Finished	Apr 15 03:00:23 PM PDT 24
Peak memory	200788 kb
Host	smart-1a1c72a9-1e07-44f1-9031-1b364f2d7b8c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532787797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2532787797
Directory	/workspace/46.uart_stress_all/latest

Test location	/workspace/coverage/default/46.uart_stress_all_with_rand_reset.2984417394
Short name	T327
Test name
Test status
Simulation time	446510880791 ps
CPU time	786.84 seconds
Started	Apr 15 02:53:55 PM PDT 24
Finished	Apr 15 03:07:03 PM PDT 24
Peak memory	229936 kb
Host	smart-b93074d0-a710-49e9-8bcb-289f3c2fbcbc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984417394 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2984417394
Directory	/workspace/46.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.uart_tx_ovrd.3145985774
Short name	T773
Test name
Test status
Simulation time	13089107821 ps
CPU time	51.2 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:54:50 PM PDT 24
Peak memory	200684 kb
Host	smart-40b985ed-0ddb-4144-9e6d-f63197d64d91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145985774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3145985774
Directory	/workspace/46.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/46.uart_tx_rx.4281964488
Short name	T472
Test name
Test status
Simulation time	91805761349 ps
CPU time	42.16 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:54:38 PM PDT 24
Peak memory	200716 kb
Host	smart-ab696a89-ad0c-4cd9-a656-3d9c4e75e0d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281964488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.4281964488
Directory	/workspace/46.uart_tx_rx/latest

Test location	/workspace/coverage/default/47.uart_alert_test.1443914232
Short name	T1098
Test name
Test status
Simulation time	14800278 ps
CPU time	0.58 seconds
Started	Apr 15 02:54:01 PM PDT 24
Finished	Apr 15 02:54:02 PM PDT 24
Peak memory	196232 kb
Host	smart-0837210b-d041-4c00-82f8-d2c439caba07
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443914232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1443914232
Directory	/workspace/47.uart_alert_test/latest

Test location	/workspace/coverage/default/47.uart_fifo_overflow.1934508263
Short name	T140
Test name
Test status
Simulation time	44970388984 ps
CPU time	72.75 seconds
Started	Apr 15 02:53:55 PM PDT 24
Finished	Apr 15 02:55:08 PM PDT 24
Peak memory	200812 kb
Host	smart-df0141db-0941-4ebb-ad81-802eb1dfe972
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934508263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1934508263
Directory	/workspace/47.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/47.uart_fifo_reset.3186692167
Short name	T212
Test name
Test status
Simulation time	51698543592 ps
CPU time	95.73 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:55:32 PM PDT 24
Peak memory	200852 kb
Host	smart-3c9840fd-f8a9-4573-a354-8bc95562ab03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186692167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3186692167
Directory	/workspace/47.uart_fifo_reset/latest

Test location	/workspace/coverage/default/47.uart_intr.1202296864
Short name	T802
Test name
Test status
Simulation time	22939573020 ps
CPU time	5.31 seconds
Started	Apr 15 02:54:01 PM PDT 24
Finished	Apr 15 02:54:07 PM PDT 24
Peak memory	200732 kb
Host	smart-4d886553-8c46-49b9-b2af-ba8006145ca6
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202296864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1202296864
Directory	/workspace/47.uart_intr/latest

Test location	/workspace/coverage/default/47.uart_long_xfer_wo_dly.2428987065
Short name	T866
Test name
Test status
Simulation time	85053772754 ps
CPU time	88.44 seconds
Started	Apr 15 02:54:00 PM PDT 24
Finished	Apr 15 02:55:29 PM PDT 24
Peak memory	200876 kb
Host	smart-52143644-b798-4bd3-bc2b-ad7d0fd146a0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2428987065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2428987065
Directory	/workspace/47.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/47.uart_loopback.3497776871
Short name	T396
Test name
Test status
Simulation time	5530824564 ps
CPU time	12.77 seconds
Started	Apr 15 02:54:00 PM PDT 24
Finished	Apr 15 02:54:13 PM PDT 24
Peak memory	199372 kb
Host	smart-690a1a1d-1ff2-4e15-a128-a4375fbda2db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497776871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3497776871
Directory	/workspace/47.uart_loopback/latest

Test location	/workspace/coverage/default/47.uart_noise_filter.3541798866
Short name	T799
Test name
Test status
Simulation time	320467983687 ps
CPU time	68.96 seconds
Started	Apr 15 02:54:03 PM PDT 24
Finished	Apr 15 02:55:12 PM PDT 24
Peak memory	201200 kb
Host	smart-3dd2962f-ee8d-49de-8ba6-cef4ac103540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541798866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3541798866
Directory	/workspace/47.uart_noise_filter/latest

Test location	/workspace/coverage/default/47.uart_perf.1615211523
Short name	T839
Test name
Test status
Simulation time	12373753110 ps
CPU time	96.23 seconds
Started	Apr 15 02:54:00 PM PDT 24
Finished	Apr 15 02:55:37 PM PDT 24
Peak memory	200904 kb
Host	smart-d98b5e68-29b6-49bf-a2cd-9da855bff544
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1615211523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1615211523
Directory	/workspace/47.uart_perf/latest

Test location	/workspace/coverage/default/47.uart_rx_oversample.38701965
Short name	T919
Test name
Test status
Simulation time	6416061406 ps
CPU time	54.31 seconds
Started	Apr 15 02:53:56 PM PDT 24
Finished	Apr 15 02:54:51 PM PDT 24
Peak memory	200048 kb
Host	smart-5ad19eef-4fc0-4539-b08b-dc394161c470
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=38701965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.38701965
Directory	/workspace/47.uart_rx_oversample/latest

Test location	/workspace/coverage/default/47.uart_rx_parity_err.236736375
Short name	T345
Test name
Test status
Simulation time	15038164806 ps
CPU time	21.35 seconds
Started	Apr 15 02:54:00 PM PDT 24
Finished	Apr 15 02:54:22 PM PDT 24
Peak memory	200208 kb
Host	smart-3878eac6-e92e-48af-9595-09095ff74b25
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236736375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.236736375
Directory	/workspace/47.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/47.uart_rx_start_bit_filter.126674896
Short name	T508
Test name
Test status
Simulation time	69140002072 ps
CPU time	30.61 seconds
Started	Apr 15 02:54:06 PM PDT 24
Finished	Apr 15 02:54:37 PM PDT 24
Peak memory	196892 kb
Host	smart-44841e9b-457a-4523-b60d-69483618f5b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126674896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.126674896
Directory	/workspace/47.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/47.uart_smoke.4063077603
Short name	T490
Test name
Test status
Simulation time	5394291522 ps
CPU time	12.77 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:54:11 PM PDT 24
Peak memory	200972 kb
Host	smart-a32db872-5800-45c9-ab68-a507f3b36b3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063077603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4063077603
Directory	/workspace/47.uart_smoke/latest

Test location	/workspace/coverage/default/47.uart_stress_all.24711899
Short name	T1178
Test name
Test status
Simulation time	173070438711 ps
CPU time	103.27 seconds
Started	Apr 15 02:54:01 PM PDT 24
Finished	Apr 15 02:55:45 PM PDT 24
Peak memory	200840 kb
Host	smart-76515919-a407-4f6c-b419-35077103ad8b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24711899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.24711899
Directory	/workspace/47.uart_stress_all/latest

Test location	/workspace/coverage/default/47.uart_stress_all_with_rand_reset.2689259292
Short name	T108
Test name
Test status
Simulation time	104418838515 ps
CPU time	343.37 seconds
Started	Apr 15 02:54:00 PM PDT 24
Finished	Apr 15 02:59:44 PM PDT 24
Peak memory	217540 kb
Host	smart-98a7d76a-b359-4a35-8bfc-4047a95cde81
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689259292 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2689259292
Directory	/workspace/47.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.uart_tx_ovrd.205814500
Short name	T419
Test name
Test status
Simulation time	831276059 ps
CPU time	1.78 seconds
Started	Apr 15 02:54:01 PM PDT 24
Finished	Apr 15 02:54:04 PM PDT 24
Peak memory	199592 kb
Host	smart-75b9ec17-74b4-40a2-bfa6-97f921d8263c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205814500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.205814500
Directory	/workspace/47.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/47.uart_tx_rx.639301175
Short name	T314
Test name
Test status
Simulation time	124476582995 ps
CPU time	169.89 seconds
Started	Apr 15 02:53:58 PM PDT 24
Finished	Apr 15 02:56:48 PM PDT 24
Peak memory	200888 kb
Host	smart-490cf820-5741-4766-9028-9d3aadc9bca0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639301175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.639301175
Directory	/workspace/47.uart_tx_rx/latest

Test location	/workspace/coverage/default/48.uart_alert_test.1724508948
Short name	T993
Test name
Test status
Simulation time	16606583 ps
CPU time	0.57 seconds
Started	Apr 15 02:54:10 PM PDT 24
Finished	Apr 15 02:54:12 PM PDT 24
Peak memory	196220 kb
Host	smart-434a5dd9-1a89-4a62-8daf-45077d6b742d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724508948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1724508948
Directory	/workspace/48.uart_alert_test/latest

Test location	/workspace/coverage/default/48.uart_fifo_full.2410612086
Short name	T1034
Test name
Test status
Simulation time	261826213843 ps
CPU time	58.78 seconds
Started	Apr 15 02:54:05 PM PDT 24
Finished	Apr 15 02:55:05 PM PDT 24
Peak memory	200868 kb
Host	smart-df455040-939d-4b2c-8a4c-916b2dec3cd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410612086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2410612086
Directory	/workspace/48.uart_fifo_full/latest

Test location	/workspace/coverage/default/48.uart_fifo_overflow.257612670
Short name	T13
Test name
Test status
Simulation time	127025815305 ps
CPU time	197.62 seconds
Started	Apr 15 02:54:04 PM PDT 24
Finished	Apr 15 02:57:23 PM PDT 24
Peak memory	200908 kb
Host	smart-9be168cc-a705-4c67-984d-b1a6aaaa9255
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257612670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.257612670
Directory	/workspace/48.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/48.uart_fifo_reset.665254727
Short name	T687
Test name
Test status
Simulation time	149438538307 ps
CPU time	524.01 seconds
Started	Apr 15 02:54:05 PM PDT 24
Finished	Apr 15 03:02:50 PM PDT 24
Peak memory	200824 kb
Host	smart-08116f89-7cae-4890-a4b5-c2608991c6ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665254727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.665254727
Directory	/workspace/48.uart_fifo_reset/latest

Test location	/workspace/coverage/default/48.uart_intr.2478006711
Short name	T736
Test name
Test status
Simulation time	67523420996 ps
CPU time	52.88 seconds
Started	Apr 15 02:54:06 PM PDT 24
Finished	Apr 15 02:55:00 PM PDT 24
Peak memory	200952 kb
Host	smart-01ad6d39-aa42-4af9-af90-f30a9543db2d
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478006711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2478006711
Directory	/workspace/48.uart_intr/latest

Test location	/workspace/coverage/default/48.uart_long_xfer_wo_dly.3659194367
Short name	T1097
Test name
Test status
Simulation time	188322430537 ps
CPU time	1410.06 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 03:17:43 PM PDT 24
Peak memory	200860 kb
Host	smart-b96c33cf-53ad-4246-b14e-d20ce43c3822
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3659194367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3659194367
Directory	/workspace/48.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/48.uart_loopback.1689420174
Short name	T358
Test name
Test status
Simulation time	5752207106 ps
CPU time	12.44 seconds
Started	Apr 15 02:54:08 PM PDT 24
Finished	Apr 15 02:54:21 PM PDT 24
Peak memory	200736 kb
Host	smart-af4a3bc2-3a18-4710-979b-c87bde1e235d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689420174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1689420174
Directory	/workspace/48.uart_loopback/latest

Test location	/workspace/coverage/default/48.uart_noise_filter.1986983376
Short name	T544
Test name
Test status
Simulation time	55190689064 ps
CPU time	90.04 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 02:55:44 PM PDT 24
Peak memory	200860 kb
Host	smart-7a33c19c-3aec-4c0e-a61e-79a77532a49c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986983376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1986983376
Directory	/workspace/48.uart_noise_filter/latest

Test location	/workspace/coverage/default/48.uart_perf.476578801
Short name	T822
Test name
Test status
Simulation time	25204339276 ps
CPU time	1524.34 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 03:19:36 PM PDT 24
Peak memory	200876 kb
Host	smart-1ac0121d-05bc-4392-b5cd-b0e224a7f24d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=476578801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.476578801
Directory	/workspace/48.uart_perf/latest

Test location	/workspace/coverage/default/48.uart_rx_oversample.2741350672
Short name	T529
Test name
Test status
Simulation time	7536567958 ps
CPU time	70.39 seconds
Started	Apr 15 02:54:07 PM PDT 24
Finished	Apr 15 02:55:18 PM PDT 24
Peak memory	199944 kb
Host	smart-556b0dd2-a71b-4ab7-8ad1-4f569734ebad
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2741350672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2741350672
Directory	/workspace/48.uart_rx_oversample/latest

Test location	/workspace/coverage/default/48.uart_rx_parity_err.33994317
Short name	T350
Test name
Test status
Simulation time	17303064203 ps
CPU time	26.77 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 02:54:41 PM PDT 24
Peak memory	200864 kb
Host	smart-669db3d4-5373-47ae-ba09-794d70a564f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33994317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.33994317
Directory	/workspace/48.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/48.uart_rx_start_bit_filter.1136028411
Short name	T395
Test name
Test status
Simulation time	43212553740 ps
CPU time	53.21 seconds
Started	Apr 15 02:54:10 PM PDT 24
Finished	Apr 15 02:55:04 PM PDT 24
Peak memory	196728 kb
Host	smart-ef5e224a-ae66-46dd-804d-7845239c3a41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136028411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1136028411
Directory	/workspace/48.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/48.uart_smoke.3840176782
Short name	T449
Test name
Test status
Simulation time	6285933255 ps
CPU time	9.83 seconds
Started	Apr 15 02:54:02 PM PDT 24
Finished	Apr 15 02:54:12 PM PDT 24
Peak memory	200612 kb
Host	smart-e6d158b7-77d2-4eda-a0d9-a53da10793a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3840176782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3840176782
Directory	/workspace/48.uart_smoke/latest

Test location	/workspace/coverage/default/48.uart_stress_all.2609871955
Short name	T803
Test name
Test status
Simulation time	663715360891 ps
CPU time	148.17 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:56:40 PM PDT 24
Peak memory	200876 kb
Host	smart-a3181a72-4681-4229-ae99-b0ed91a83a42
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609871955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2609871955
Directory	/workspace/48.uart_stress_all/latest

Test location	/workspace/coverage/default/48.uart_stress_all_with_rand_reset.3265298242
Short name	T109
Test name
Test status
Simulation time	54324247794 ps
CPU time	284.04 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 02:58:57 PM PDT 24
Peak memory	217232 kb
Host	smart-c2f714d2-1857-49df-b466-e66299cbea89
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265298242 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3265298242
Directory	/workspace/48.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.uart_tx_ovrd.1785420236
Short name	T398
Test name
Test status
Simulation time	927756716 ps
CPU time	5.06 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:54:17 PM PDT 24
Peak memory	200540 kb
Host	smart-07d28702-9663-44a2-8348-ad14a53e436e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785420236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1785420236
Directory	/workspace/48.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/48.uart_tx_rx.2411332754
Short name	T558
Test name
Test status
Simulation time	64462472912 ps
CPU time	99.12 seconds
Started	Apr 15 02:54:01 PM PDT 24
Finished	Apr 15 02:55:40 PM PDT 24
Peak memory	200916 kb
Host	smart-2162e037-3fd8-4ed7-90ff-75de6f4799a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411332754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2411332754
Directory	/workspace/48.uart_tx_rx/latest

Test location	/workspace/coverage/default/49.uart_alert_test.778420132
Short name	T665
Test name
Test status
Simulation time	12350395 ps
CPU time	0.58 seconds
Started	Apr 15 02:54:17 PM PDT 24
Finished	Apr 15 02:54:18 PM PDT 24
Peak memory	196224 kb
Host	smart-f3f28125-4bff-4db7-8d1e-127dde9a3c8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778420132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.778420132
Directory	/workspace/49.uart_alert_test/latest

Test location	/workspace/coverage/default/49.uart_fifo_full.2107294196
Short name	T1129
Test name
Test status
Simulation time	74591068617 ps
CPU time	139.01 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 02:56:33 PM PDT 24
Peak memory	200884 kb
Host	smart-4e7ecccb-1481-49c0-957f-84f559888454
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107294196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2107294196
Directory	/workspace/49.uart_fifo_full/latest

Test location	/workspace/coverage/default/49.uart_fifo_overflow.2656334248
Short name	T177
Test name
Test status
Simulation time	120395489733 ps
CPU time	240.96 seconds
Started	Apr 15 02:54:09 PM PDT 24
Finished	Apr 15 02:58:10 PM PDT 24
Peak memory	200804 kb
Host	smart-b75673b3-26ef-4f07-8ab6-cf542bc9edf4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656334248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2656334248
Directory	/workspace/49.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/49.uart_fifo_reset.4173854297
Short name	T312
Test name
Test status
Simulation time	132887904376 ps
CPU time	28.55 seconds
Started	Apr 15 02:54:10 PM PDT 24
Finished	Apr 15 02:54:39 PM PDT 24
Peak memory	200944 kb
Host	smart-0fb0ecd2-b430-43d7-8157-57974c3d6b4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173854297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4173854297
Directory	/workspace/49.uart_fifo_reset/latest

Test location	/workspace/coverage/default/49.uart_intr.2051768521
Short name	T888
Test name
Test status
Simulation time	279441011014 ps
CPU time	131.74 seconds
Started	Apr 15 02:54:16 PM PDT 24
Finished	Apr 15 02:56:28 PM PDT 24
Peak memory	200816 kb
Host	smart-9168e13b-fd61-4faf-a859-07e667323510
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051768521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2051768521
Directory	/workspace/49.uart_intr/latest

Test location	/workspace/coverage/default/49.uart_long_xfer_wo_dly.509395274
Short name	T850
Test name
Test status
Simulation time	244650105881 ps
CPU time	249.05 seconds
Started	Apr 15 02:54:10 PM PDT 24
Finished	Apr 15 02:58:20 PM PDT 24
Peak memory	200904 kb
Host	smart-3d97e332-1178-4fe9-8a93-03889b8ac0fa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=509395274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.509395274
Directory	/workspace/49.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/49.uart_loopback.960345715
Short name	T693
Test name
Test status
Simulation time	1802378704 ps
CPU time	3.82 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:54:16 PM PDT 24
Peak memory	196472 kb
Host	smart-1ba677c0-3e98-47bb-b625-56a57960e8c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960345715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.960345715
Directory	/workspace/49.uart_loopback/latest

Test location	/workspace/coverage/default/49.uart_noise_filter.1561349238
Short name	T284
Test name
Test status
Simulation time	156924619931 ps
CPU time	77.47 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 02:55:30 PM PDT 24
Peak memory	199760 kb
Host	smart-6a953ff5-300d-4644-9ab0-6262d9f6c246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561349238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1561349238
Directory	/workspace/49.uart_noise_filter/latest

Test location	/workspace/coverage/default/49.uart_perf.2204455275
Short name	T293
Test name
Test status
Simulation time	8283002690 ps
CPU time	97.01 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:55:49 PM PDT 24
Peak memory	200924 kb
Host	smart-09ed4155-5b4b-4fb8-8634-0f637323c13c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2204455275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2204455275
Directory	/workspace/49.uart_perf/latest

Test location	/workspace/coverage/default/49.uart_rx_oversample.566916421
Short name	T1007
Test name
Test status
Simulation time	4692281608 ps
CPU time	10.05 seconds
Started	Apr 15 02:54:09 PM PDT 24
Finished	Apr 15 02:54:20 PM PDT 24
Peak memory	199040 kb
Host	smart-5a8d7c82-a309-4796-af78-2515dc21cbb5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=566916421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.566916421
Directory	/workspace/49.uart_rx_oversample/latest

Test location	/workspace/coverage/default/49.uart_rx_parity_err.3072451389
Short name	T1170
Test name
Test status
Simulation time	42595289969 ps
CPU time	15.15 seconds
Started	Apr 15 02:54:17 PM PDT 24
Finished	Apr 15 02:54:33 PM PDT 24
Peak memory	200152 kb
Host	smart-e499073d-c3ab-4bbc-a9b5-a43870a4eaba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072451389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3072451389
Directory	/workspace/49.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/49.uart_rx_start_bit_filter.941315091
Short name	T408
Test name
Test status
Simulation time	45552052126 ps
CPU time	9.12 seconds
Started	Apr 15 02:54:09 PM PDT 24
Finished	Apr 15 02:54:19 PM PDT 24
Peak memory	196908 kb
Host	smart-c0ad353c-39b6-4fd5-a9d9-c1afc952a0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941315091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.941315091
Directory	/workspace/49.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/49.uart_smoke.3092758970
Short name	T651
Test name
Test status
Simulation time	245913290 ps
CPU time	1.28 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:54:12 PM PDT 24
Peak memory	199272 kb
Host	smart-a05078b0-9457-4129-b98c-eb99674605aa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092758970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3092758970
Directory	/workspace/49.uart_smoke/latest

Test location	/workspace/coverage/default/49.uart_stress_all.3697859555
Short name	T1024
Test name
Test status
Simulation time	162615089975 ps
CPU time	304.55 seconds
Started	Apr 15 02:54:10 PM PDT 24
Finished	Apr 15 02:59:15 PM PDT 24
Peak memory	200936 kb
Host	smart-fcba1ace-599f-48e4-8ebd-56cbfb9f5ad3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697859555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3697859555
Directory	/workspace/49.uart_stress_all/latest

Test location	/workspace/coverage/default/49.uart_stress_all_with_rand_reset.4245177181
Short name	T569
Test name
Test status
Simulation time	12999029246 ps
CPU time	76.97 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:55:29 PM PDT 24
Peak memory	209384 kb
Host	smart-df307fbe-d773-426b-ad8e-9a5d61df5fc2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245177181 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4245177181
Directory	/workspace/49.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.uart_tx_ovrd.3034041264
Short name	T568
Test name
Test status
Simulation time	7072975834 ps
CPU time	20.16 seconds
Started	Apr 15 02:54:09 PM PDT 24
Finished	Apr 15 02:54:30 PM PDT 24
Peak memory	200232 kb
Host	smart-8c5ebfa2-acf0-4fac-b0a7-7573e0acc673
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034041264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3034041264
Directory	/workspace/49.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/49.uart_tx_rx.2324442914
Short name	T783
Test name
Test status
Simulation time	85514861503 ps
CPU time	219.43 seconds
Started	Apr 15 02:54:11 PM PDT 24
Finished	Apr 15 02:57:51 PM PDT 24
Peak memory	200896 kb
Host	smart-872018a8-704f-4967-ab8e-88a7223551fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324442914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2324442914
Directory	/workspace/49.uart_tx_rx/latest

Test location	/workspace/coverage/default/5.uart_alert_test.825020081
Short name	T604
Test name
Test status
Simulation time	33405243 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:32 PM PDT 24
Peak memory	196180 kb
Host	smart-afe25fef-92bc-4f33-96dd-6da15c73a025
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825020081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.825020081
Directory	/workspace/5.uart_alert_test/latest

Test location	/workspace/coverage/default/5.uart_fifo_full.1272412200
Short name	T1065
Test name
Test status
Simulation time	35531197178 ps
CPU time	61.22 seconds
Started	Apr 15 02:51:23 PM PDT 24
Finished	Apr 15 02:52:24 PM PDT 24
Peak memory	200788 kb
Host	smart-b85c6906-8763-48de-a5c5-fa21efcbf80d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272412200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1272412200
Directory	/workspace/5.uart_fifo_full/latest

Test location	/workspace/coverage/default/5.uart_fifo_overflow.1808850263
Short name	T954
Test name
Test status
Simulation time	93073400497 ps
CPU time	19.66 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:50 PM PDT 24
Peak memory	200820 kb
Host	smart-1b54e57c-c065-4179-89f5-95e01135e6e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808850263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1808850263
Directory	/workspace/5.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/5.uart_fifo_reset.3857778548
Short name	T983
Test name
Test status
Simulation time	116450011386 ps
CPU time	14.75 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:51:54 PM PDT 24
Peak memory	200888 kb
Host	smart-573ced07-5c95-488e-8580-fca82c786e05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857778548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3857778548
Directory	/workspace/5.uart_fifo_reset/latest

Test location	/workspace/coverage/default/5.uart_intr.1207584702
Short name	T981
Test name
Test status
Simulation time	178012060277 ps
CPU time	60.93 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:52:37 PM PDT 24
Peak memory	198480 kb
Host	smart-e21dc617-2d89-4f55-b237-cabfb2dc8f1b
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207584702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1207584702
Directory	/workspace/5.uart_intr/latest

Test location	/workspace/coverage/default/5.uart_long_xfer_wo_dly.173581762
Short name	T550
Test name
Test status
Simulation time	30559780083 ps
CPU time	75.19 seconds
Started	Apr 15 02:51:39 PM PDT 24
Finished	Apr 15 02:52:56 PM PDT 24
Peak memory	200852 kb
Host	smart-94a90a24-8c76-4a7d-a3d4-1b1443d7d3d9
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=173581762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.173581762
Directory	/workspace/5.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/5.uart_loopback.874147499
Short name	T26
Test name
Test status
Simulation time	2044799224 ps
CPU time	3.73 seconds
Started	Apr 15 02:51:24 PM PDT 24
Finished	Apr 15 02:51:28 PM PDT 24
Peak memory	196856 kb
Host	smart-58cfe160-c41f-4417-a920-ce49f17b5d41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874147499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.874147499
Directory	/workspace/5.uart_loopback/latest

Test location	/workspace/coverage/default/5.uart_noise_filter.4048553863
Short name	T1061
Test name
Test status
Simulation time	24522623452 ps
CPU time	11.82 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:51:56 PM PDT 24
Peak memory	199584 kb
Host	smart-ec421c5a-ce1d-4934-b470-1e03a79e42bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048553863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.4048553863
Directory	/workspace/5.uart_noise_filter/latest

Test location	/workspace/coverage/default/5.uart_perf.1773014369
Short name	T792
Test name
Test status
Simulation time	18026301168 ps
CPU time	730.58 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 03:03:50 PM PDT 24
Peak memory	200908 kb
Host	smart-e3e5b712-9744-4791-968b-c7b28367f638
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1773014369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1773014369
Directory	/workspace/5.uart_perf/latest

Test location	/workspace/coverage/default/5.uart_rx_oversample.3428752027
Short name	T663
Test name
Test status
Simulation time	4109517994 ps
CPU time	9.35 seconds
Started	Apr 15 02:51:26 PM PDT 24
Finished	Apr 15 02:51:36 PM PDT 24
Peak memory	198992 kb
Host	smart-b3f1a07b-1d0e-48db-805b-953c7d7287b8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3428752027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3428752027
Directory	/workspace/5.uart_rx_oversample/latest

Test location	/workspace/coverage/default/5.uart_rx_parity_err.3921089198
Short name	T876
Test name
Test status
Simulation time	12106751383 ps
CPU time	20.1 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	200852 kb
Host	smart-af8e87c6-90e5-43ba-9adf-15b02d21c866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921089198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3921089198
Directory	/workspace/5.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/5.uart_rx_start_bit_filter.3172748489
Short name	T622
Test name
Test status
Simulation time	5008851805 ps
CPU time	2.51 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:51:38 PM PDT 24
Peak memory	196912 kb
Host	smart-15cdf464-9bfa-40b9-a329-ddeeb32bb720
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172748489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3172748489
Directory	/workspace/5.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/5.uart_smoke.1313044681
Short name	T62
Test name
Test status
Simulation time	108790026 ps
CPU time	0.98 seconds
Started	Apr 15 02:51:31 PM PDT 24
Finished	Apr 15 02:51:33 PM PDT 24
Peak memory	197952 kb
Host	smart-44263676-fac0-4189-b7bf-d75c5bf3123a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313044681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1313044681
Directory	/workspace/5.uart_smoke/latest

Test location	/workspace/coverage/default/5.uart_stress_all_with_rand_reset.2429257486
Short name	T198
Test name
Test status
Simulation time	77838505170 ps
CPU time	686.59 seconds
Started	Apr 15 02:51:27 PM PDT 24
Finished	Apr 15 03:02:54 PM PDT 24
Peak memory	217324 kb
Host	smart-ab1b7c64-0b6f-492e-9133-96932101414d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429257486 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2429257486
Directory	/workspace/5.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.uart_tx_ovrd.1169630777
Short name	T1143
Test name
Test status
Simulation time	6893385596 ps
CPU time	22.01 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	200276 kb
Host	smart-2c0d2170-e19f-4393-befe-e6be3851e5cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169630777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1169630777
Directory	/workspace/5.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/5.uart_tx_rx.1131410560
Short name	T555
Test name
Test status
Simulation time	30097591230 ps
CPU time	54.08 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:52:30 PM PDT 24
Peak memory	200820 kb
Host	smart-6b1d1079-7f69-4676-8c29-1e56338bf284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1131410560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1131410560
Directory	/workspace/5.uart_tx_rx/latest

Test location	/workspace/coverage/default/51.uart_fifo_reset.14604830
Short name	T1093
Test name
Test status
Simulation time	120405791858 ps
CPU time	52.35 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 02:55:07 PM PDT 24
Peak memory	200932 kb
Host	smart-7e3bbfd1-2b81-4297-9680-7188490dcf7d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14604830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.14604830
Directory	/workspace/51.uart_fifo_reset/latest

Test location	/workspace/coverage/default/51.uart_stress_all_with_rand_reset.69405671
Short name	T247
Test name
Test status
Simulation time	58596797705 ps
CPU time	578.83 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 03:03:53 PM PDT 24
Peak memory	217460 kb
Host	smart-08c48cba-e8cb-46f3-9381-42ddcf42e413
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69405671 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.69405671
Directory	/workspace/51.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/52.uart_fifo_reset.834066000
Short name	T1153
Test name
Test status
Simulation time	57868687306 ps
CPU time	103.57 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 02:55:58 PM PDT 24
Peak memory	200924 kb
Host	smart-4ce0aae9-82a2-4fb5-963e-923c911b0c9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834066000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.834066000
Directory	/workspace/52.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_fifo_reset.4180586655
Short name	T1109
Test name
Test status
Simulation time	10845442423 ps
CPU time	4.52 seconds
Started	Apr 15 02:54:13 PM PDT 24
Finished	Apr 15 02:54:19 PM PDT 24
Peak memory	200820 kb
Host	smart-2b572f03-9115-4b38-a6df-fb5f3f4074eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180586655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4180586655
Directory	/workspace/53.uart_fifo_reset/latest

Test location	/workspace/coverage/default/53.uart_stress_all_with_rand_reset.1850194946
Short name	T455
Test name
Test status
Simulation time	85723697838 ps
CPU time	266.48 seconds
Started	Apr 15 02:54:15 PM PDT 24
Finished	Apr 15 02:58:42 PM PDT 24
Peak memory	217536 kb
Host	smart-82181d1e-958d-4602-b431-a964896f7170
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850194946 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1850194946
Directory	/workspace/53.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/54.uart_fifo_reset.1943252727
Short name	T250
Test name
Test status
Simulation time	68864532880 ps
CPU time	30.06 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 02:54:44 PM PDT 24
Peak memory	200860 kb
Host	smart-d3137a10-56e3-443a-a738-a24d41134107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1943252727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1943252727
Directory	/workspace/54.uart_fifo_reset/latest

Test location	/workspace/coverage/default/54.uart_stress_all_with_rand_reset.4156681532
Short name	T1006
Test name
Test status
Simulation time	102072760656 ps
CPU time	762.96 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 03:06:56 PM PDT 24
Peak memory	217472 kb
Host	smart-2020d89b-72c3-4ae6-9e58-dcb9fbeb4f11
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156681532 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.4156681532
Directory	/workspace/54.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/55.uart_stress_all_with_rand_reset.2990348872
Short name	T37
Test name
Test status
Simulation time	118756743687 ps
CPU time	805.95 seconds
Started	Apr 15 02:54:12 PM PDT 24
Finished	Apr 15 03:07:39 PM PDT 24
Peak memory	225820 kb
Host	smart-b5df15b7-c663-4892-9ac0-343f7904e175
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990348872 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2990348872
Directory	/workspace/55.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/56.uart_fifo_reset.2314494347
Short name	T1154
Test name
Test status
Simulation time	11912488449 ps
CPU time	22.39 seconds
Started	Apr 15 02:54:17 PM PDT 24
Finished	Apr 15 02:54:40 PM PDT 24
Peak memory	200772 kb
Host	smart-b1ddbdb6-a033-4bb1-8253-b6109b70b509
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314494347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2314494347
Directory	/workspace/56.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_fifo_reset.2845253395
Short name	T237
Test name
Test status
Simulation time	55354208336 ps
CPU time	27.48 seconds
Started	Apr 15 02:54:14 PM PDT 24
Finished	Apr 15 02:54:42 PM PDT 24
Peak memory	200908 kb
Host	smart-13befa8f-9eda-4ec6-b91c-03de2e3c938b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845253395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2845253395
Directory	/workspace/57.uart_fifo_reset/latest

Test location	/workspace/coverage/default/57.uart_stress_all_with_rand_reset.144706372
Short name	T841
Test name
Test status
Simulation time	70619841540 ps
CPU time	677.85 seconds
Started	Apr 15 02:54:19 PM PDT 24
Finished	Apr 15 03:05:38 PM PDT 24
Peak memory	217488 kb
Host	smart-55d7e58a-ab91-4199-a871-f58b6179fc75
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144706372 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.144706372
Directory	/workspace/57.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/58.uart_fifo_reset.2383145907
Short name	T549
Test name
Test status
Simulation time	49698280071 ps
CPU time	25.26 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 02:54:44 PM PDT 24
Peak memory	200888 kb
Host	smart-170da168-bb17-4da9-aa76-c17e1269a1bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383145907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2383145907
Directory	/workspace/58.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_fifo_reset.1551303418
Short name	T717
Test name
Test status
Simulation time	338820214039 ps
CPU time	148.61 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 02:56:48 PM PDT 24
Peak memory	200832 kb
Host	smart-73051bb2-9caf-44c8-84b2-c0c002830b2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551303418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1551303418
Directory	/workspace/59.uart_fifo_reset/latest

Test location	/workspace/coverage/default/59.uart_stress_all_with_rand_reset.1825684503
Short name	T63
Test name
Test status
Simulation time	117005015387 ps
CPU time	1337.21 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 03:16:36 PM PDT 24
Peak memory	226824 kb
Host	smart-44833150-9e61-4fd8-a432-787c54f7febd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825684503 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1825684503
Directory	/workspace/59.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_alert_test.632378296
Short name	T471
Test name
Test status
Simulation time	14571383 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:51:35 PM PDT 24
Peak memory	195144 kb
Host	smart-601c5dae-472f-4bef-96ab-6852d2cd79fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632378296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.632378296
Directory	/workspace/6.uart_alert_test/latest

Test location	/workspace/coverage/default/6.uart_fifo_full.4007525239
Short name	T285
Test name
Test status
Simulation time	147233403589 ps
CPU time	408.71 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 02:58:31 PM PDT 24
Peak memory	200836 kb
Host	smart-80827689-d382-49d6-b03d-318ae249e482
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007525239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.4007525239
Directory	/workspace/6.uart_fifo_full/latest

Test location	/workspace/coverage/default/6.uart_fifo_overflow.3071166798
Short name	T438
Test name
Test status
Simulation time	29743995736 ps
CPU time	7.7 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:38 PM PDT 24
Peak memory	200584 kb
Host	smart-5fa54ba8-b641-4218-8938-da8c034578d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071166798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3071166798
Directory	/workspace/6.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/6.uart_fifo_reset.1888107506
Short name	T1077
Test name
Test status
Simulation time	220931699477 ps
CPU time	335.83 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:57:13 PM PDT 24
Peak memory	200836 kb
Host	smart-2d05eb75-281c-4be3-b961-fc83dce39bc6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888107506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1888107506
Directory	/workspace/6.uart_fifo_reset/latest

Test location	/workspace/coverage/default/6.uart_intr.1869223357
Short name	T911
Test name
Test status
Simulation time	426801594096 ps
CPU time	377.9 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:58:01 PM PDT 24
Peak memory	199980 kb
Host	smart-3c45e91e-c628-4e3a-bba6-d1c9ce2ecea7
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869223357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1869223357
Directory	/workspace/6.uart_intr/latest

Test location	/workspace/coverage/default/6.uart_long_xfer_wo_dly.552773931
Short name	T591
Test name
Test status
Simulation time	75406871711 ps
CPU time	500.05 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 03:00:02 PM PDT 24
Peak memory	200884 kb
Host	smart-02869364-0a32-40a8-9e52-9e322e454c3a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=552773931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.552773931
Directory	/workspace/6.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/6.uart_loopback.508936525
Short name	T427
Test name
Test status
Simulation time	1438888458 ps
CPU time	0.9 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:32 PM PDT 24
Peak memory	196264 kb
Host	smart-df2feb90-78e3-4bc4-bea6-93b88a535c62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508936525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.508936525
Directory	/workspace/6.uart_loopback/latest

Test location	/workspace/coverage/default/6.uart_noise_filter.1869158528
Short name	T597
Test name
Test status
Simulation time	77334486429 ps
CPU time	137.24 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:53:48 PM PDT 24
Peak memory	201064 kb
Host	smart-b2adb390-a92d-46eb-88bc-89f84146340f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869158528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1869158528
Directory	/workspace/6.uart_noise_filter/latest

Test location	/workspace/coverage/default/6.uart_perf.3109275711
Short name	T263
Test name
Test status
Simulation time	29220102161 ps
CPU time	1495.22 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 03:16:33 PM PDT 24
Peak memory	200860 kb
Host	smart-7c0ae1ac-ce6d-4310-9d80-c87d07dc5ffe
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3109275711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3109275711
Directory	/workspace/6.uart_perf/latest

Test location	/workspace/coverage/default/6.uart_rx_oversample.1637444850
Short name	T1148
Test name
Test status
Simulation time	5686432361 ps
CPU time	53.5 seconds
Started	Apr 15 02:51:41 PM PDT 24
Finished	Apr 15 02:52:41 PM PDT 24
Peak memory	200124 kb
Host	smart-84d9f10e-ed3b-4d72-8dca-f16af87eda2f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1637444850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1637444850
Directory	/workspace/6.uart_rx_oversample/latest

Test location	/workspace/coverage/default/6.uart_rx_parity_err.3886347338
Short name	T775
Test name
Test status
Simulation time	72662165635 ps
CPU time	76.57 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:52:53 PM PDT 24
Peak memory	200932 kb
Host	smart-1597c003-5122-44e4-a87a-7413abebf757
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886347338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3886347338
Directory	/workspace/6.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/6.uart_rx_start_bit_filter.2684123075
Short name	T1168
Test name
Test status
Simulation time	3335929089 ps
CPU time	1.21 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:51:45 PM PDT 24
Peak memory	197200 kb
Host	smart-58f481f8-f505-4d61-b555-82a075db9cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2684123075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2684123075
Directory	/workspace/6.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/6.uart_smoke.1378456750
Short name	T40
Test name
Test status
Simulation time	474242114 ps
CPU time	1.88 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:51:36 PM PDT 24
Peak memory	199600 kb
Host	smart-dcc4a9eb-fd3d-423c-be1a-4fc7160bcdef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1378456750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1378456750
Directory	/workspace/6.uart_smoke/latest

Test location	/workspace/coverage/default/6.uart_stress_all.1821626421
Short name	T903
Test name
Test status
Simulation time	22936630915 ps
CPU time	34.51 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:52:08 PM PDT 24
Peak memory	200836 kb
Host	smart-f7c057a2-98fb-4c6c-9794-050949f23722
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821626421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1821626421
Directory	/workspace/6.uart_stress_all/latest

Test location	/workspace/coverage/default/6.uart_stress_all_with_rand_reset.1015336924
Short name	T816
Test name
Test status
Simulation time	135709014086 ps
CPU time	406.55 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:58:34 PM PDT 24
Peak memory	217564 kb
Host	smart-82fb2e14-e6f2-436f-bb55-047e9b669072
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015336924 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1015336924
Directory	/workspace/6.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.uart_tx_ovrd.1584964854
Short name	T646
Test name
Test status
Simulation time	1241504170 ps
CPU time	3.89 seconds
Started	Apr 15 02:51:30 PM PDT 24
Finished	Apr 15 02:51:35 PM PDT 24
Peak memory	199676 kb
Host	smart-38b841de-4b18-4379-9b33-6dfefa5b7101
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584964854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1584964854
Directory	/workspace/6.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/6.uart_tx_rx.2530012318
Short name	T674
Test name
Test status
Simulation time	95005161383 ps
CPU time	63.43 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:52:52 PM PDT 24
Peak memory	200840 kb
Host	smart-853138bf-da43-477d-acec-d4b4beb22d2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2530012318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2530012318
Directory	/workspace/6.uart_tx_rx/latest

Test location	/workspace/coverage/default/60.uart_fifo_reset.662431574
Short name	T115
Test name
Test status
Simulation time	20559469013 ps
CPU time	37.54 seconds
Started	Apr 15 02:54:22 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200868 kb
Host	smart-83ecc277-ac96-4f37-a852-dfb25f299bd5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662431574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.662431574
Directory	/workspace/60.uart_fifo_reset/latest

Test location	/workspace/coverage/default/60.uart_stress_all_with_rand_reset.1171642279
Short name	T336
Test name
Test status
Simulation time	28416995082 ps
CPU time	358.32 seconds
Started	Apr 15 02:54:22 PM PDT 24
Finished	Apr 15 03:00:21 PM PDT 24
Peak memory	217532 kb
Host	smart-0ccfc87e-836f-4d3a-96da-ca26d85685c9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171642279 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1171642279
Directory	/workspace/60.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/61.uart_fifo_reset.3405561253
Short name	T669
Test name
Test status
Simulation time	39102160835 ps
CPU time	63.34 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 02:55:22 PM PDT 24
Peak memory	200856 kb
Host	smart-d5479e68-ab4d-419b-acd2-00db8b5626b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405561253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3405561253
Directory	/workspace/61.uart_fifo_reset/latest

Test location	/workspace/coverage/default/61.uart_stress_all_with_rand_reset.1948686709
Short name	T221
Test name
Test status
Simulation time	123440435326 ps
CPU time	475.44 seconds
Started	Apr 15 02:54:22 PM PDT 24
Finished	Apr 15 03:02:18 PM PDT 24
Peak memory	227564 kb
Host	smart-9cbb2674-8922-4c3a-933a-7831284da103
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948686709 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1948686709
Directory	/workspace/61.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/62.uart_fifo_reset.2483399664
Short name	T1135
Test name
Test status
Simulation time	13324373112 ps
CPU time	12.46 seconds
Started	Apr 15 02:54:19 PM PDT 24
Finished	Apr 15 02:54:32 PM PDT 24
Peak memory	200944 kb
Host	smart-7320f2df-6208-4509-aa1c-ebd47aeab510
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483399664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2483399664
Directory	/workspace/62.uart_fifo_reset/latest

Test location	/workspace/coverage/default/62.uart_stress_all_with_rand_reset.3983859582
Short name	T417
Test name
Test status
Simulation time	143330935664 ps
CPU time	919.4 seconds
Started	Apr 15 02:54:21 PM PDT 24
Finished	Apr 15 03:09:41 PM PDT 24
Peak memory	217532 kb
Host	smart-d5dfac41-6b4b-439a-94b3-aef19e4f8992
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983859582 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3983859582
Directory	/workspace/62.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/63.uart_fifo_reset.501029364
Short name	T204
Test name
Test status
Simulation time	100526938719 ps
CPU time	41.31 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 02:55:00 PM PDT 24
Peak memory	200860 kb
Host	smart-61e3d28a-d32f-45c8-a0de-2b736a45a232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=501029364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.501029364
Directory	/workspace/63.uart_fifo_reset/latest

Test location	/workspace/coverage/default/63.uart_stress_all_with_rand_reset.3435169589
Short name	T1110
Test name
Test status
Simulation time	49138336978 ps
CPU time	103.95 seconds
Started	Apr 15 02:54:16 PM PDT 24
Finished	Apr 15 02:56:01 PM PDT 24
Peak memory	209168 kb
Host	smart-2d8d9748-9233-4f01-ad80-1cb816adfd08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435169589 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3435169589
Directory	/workspace/63.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/64.uart_fifo_reset.150936519
Short name	T230
Test name
Test status
Simulation time	212968572372 ps
CPU time	342.23 seconds
Started	Apr 15 02:54:17 PM PDT 24
Finished	Apr 15 03:00:00 PM PDT 24
Peak memory	200956 kb
Host	smart-b94f3fe0-438d-473a-ae17-f76406436956
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150936519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.150936519
Directory	/workspace/64.uart_fifo_reset/latest

Test location	/workspace/coverage/default/64.uart_stress_all_with_rand_reset.2876933013
Short name	T493
Test name
Test status
Simulation time	336216553916 ps
CPU time	575.06 seconds
Started	Apr 15 02:54:19 PM PDT 24
Finished	Apr 15 03:03:55 PM PDT 24
Peak memory	216364 kb
Host	smart-b2700dd0-08f4-4359-993f-403e7830d89f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876933013 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2876933013
Directory	/workspace/64.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/65.uart_fifo_reset.1739742383
Short name	T1155
Test name
Test status
Simulation time	48353506149 ps
CPU time	31.66 seconds
Started	Apr 15 02:54:18 PM PDT 24
Finished	Apr 15 02:54:51 PM PDT 24
Peak memory	200712 kb
Host	smart-7ee0984f-80a4-4ebd-8fd8-15b4aea4e22f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739742383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1739742383
Directory	/workspace/65.uart_fifo_reset/latest

Test location	/workspace/coverage/default/65.uart_stress_all_with_rand_reset.3644804062
Short name	T55
Test name
Test status
Simulation time	41287155295 ps
CPU time	1107.06 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 03:12:55 PM PDT 24
Peak memory	217252 kb
Host	smart-9cd4d225-367a-484e-9227-00c98e9607f2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644804062 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3644804062
Directory	/workspace/65.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/66.uart_fifo_reset.3590768340
Short name	T200
Test name
Test status
Simulation time	99259098833 ps
CPU time	167.85 seconds
Started	Apr 15 02:54:23 PM PDT 24
Finished	Apr 15 02:57:12 PM PDT 24
Peak memory	200836 kb
Host	smart-ce15a4a0-a90d-427e-a5cd-aa7074b9b58c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590768340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3590768340
Directory	/workspace/66.uart_fifo_reset/latest

Test location	/workspace/coverage/default/66.uart_stress_all_with_rand_reset.3860452539
Short name	T1108
Test name
Test status
Simulation time	48673006245 ps
CPU time	457.22 seconds
Started	Apr 15 02:54:21 PM PDT 24
Finished	Apr 15 03:01:59 PM PDT 24
Peak memory	217300 kb
Host	smart-2fdfde0b-154e-40f3-91ed-1993aee37325
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860452539 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3860452539
Directory	/workspace/66.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/67.uart_fifo_reset.2729595277
Short name	T1140
Test name
Test status
Simulation time	50922528104 ps
CPU time	78.23 seconds
Started	Apr 15 02:54:23 PM PDT 24
Finished	Apr 15 02:55:42 PM PDT 24
Peak memory	200764 kb
Host	smart-1213191a-17b8-4b2c-b038-1a3ccb690a1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2729595277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2729595277
Directory	/workspace/67.uart_fifo_reset/latest

Test location	/workspace/coverage/default/67.uart_stress_all_with_rand_reset.3741315144
Short name	T899
Test name
Test status
Simulation time	87321437112 ps
CPU time	705.68 seconds
Started	Apr 15 02:54:21 PM PDT 24
Finished	Apr 15 03:06:08 PM PDT 24
Peak memory	213904 kb
Host	smart-f9465326-c582-41d3-ae0f-3513f9a740da
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741315144 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3741315144
Directory	/workspace/67.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/68.uart_fifo_reset.2370989717
Short name	T942
Test name
Test status
Simulation time	29114762385 ps
CPU time	33.19 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200860 kb
Host	smart-12d07c17-1941-41b1-8d47-a1666bfecc0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370989717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2370989717
Directory	/workspace/68.uart_fifo_reset/latest

Test location	/workspace/coverage/default/68.uart_stress_all_with_rand_reset.1387451826
Short name	T1023
Test name
Test status
Simulation time	124295665929 ps
CPU time	354.87 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:00:24 PM PDT 24
Peak memory	217588 kb
Host	smart-0fa6655e-0886-456b-a40b-784176827cf7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387451826 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1387451826
Directory	/workspace/68.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_alert_test.2364732927
Short name	T367
Test name
Test status
Simulation time	14740080 ps
CPU time	0.55 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:51:37 PM PDT 24
Peak memory	196216 kb
Host	smart-09c4c2c4-eeb4-40f6-ac73-7edcd103db74
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364732927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2364732927
Directory	/workspace/7.uart_alert_test/latest

Test location	/workspace/coverage/default/7.uart_fifo_full.186475455
Short name	T829
Test name
Test status
Simulation time	20913766462 ps
CPU time	12.64 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:51:52 PM PDT 24
Peak memory	200728 kb
Host	smart-120c0801-4651-4c56-8db1-f7c1e3a90cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=186475455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.186475455
Directory	/workspace/7.uart_fifo_full/latest

Test location	/workspace/coverage/default/7.uart_fifo_overflow.3544981096
Short name	T170
Test name
Test status
Simulation time	113081387645 ps
CPU time	46.57 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:52:31 PM PDT 24
Peak memory	200796 kb
Host	smart-206ea18b-5c96-4225-8023-5e4a9e5eae0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544981096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3544981096
Directory	/workspace/7.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/7.uart_fifo_reset.171408730
Short name	T280
Test name
Test status
Simulation time	99998473091 ps
CPU time	186.7 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:54:41 PM PDT 24
Peak memory	200880 kb
Host	smart-1a561db4-e664-4f36-9ec9-e5dad8ef716f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171408730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.171408730
Directory	/workspace/7.uart_fifo_reset/latest

Test location	/workspace/coverage/default/7.uart_intr.3972235790
Short name	T583
Test name
Test status
Simulation time	34214437620 ps
CPU time	63.83 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:52:53 PM PDT 24
Peak memory	200916 kb
Host	smart-6e90ae28-c136-4e67-9d88-5c94b00c13af
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972235790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3972235790
Directory	/workspace/7.uart_intr/latest

Test location	/workspace/coverage/default/7.uart_long_xfer_wo_dly.3090286683
Short name	T767
Test name
Test status
Simulation time	126679549581 ps
CPU time	349.41 seconds
Started	Apr 15 02:51:29 PM PDT 24
Finished	Apr 15 02:57:19 PM PDT 24
Peak memory	200908 kb
Host	smart-bf6a86e3-53b7-4ac2-9dbc-6188719e38ef
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3090286683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3090286683
Directory	/workspace/7.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/7.uart_loopback.2676929283
Short name	T1145
Test name
Test status
Simulation time	534636919 ps
CPU time	1.32 seconds
Started	Apr 15 02:51:53 PM PDT 24
Finished	Apr 15 02:51:56 PM PDT 24
Peak memory	196248 kb
Host	smart-a1487618-7961-4ce1-a3d6-a3ac5c955e15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676929283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2676929283
Directory	/workspace/7.uart_loopback/latest

Test location	/workspace/coverage/default/7.uart_noise_filter.2843201588
Short name	T958
Test name
Test status
Simulation time	82073520966 ps
CPU time	85.73 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:53:08 PM PDT 24
Peak memory	201116 kb
Host	smart-06dc0cf6-8bd2-4c85-98a1-b847dbe05746
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843201588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2843201588
Directory	/workspace/7.uart_noise_filter/latest

Test location	/workspace/coverage/default/7.uart_perf.3964269047
Short name	T729
Test name
Test status
Simulation time	19505451212 ps
CPU time	1141.6 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 03:10:38 PM PDT 24
Peak memory	200896 kb
Host	smart-b0642889-7fb3-4988-9e64-4aaf454238e5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3964269047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3964269047
Directory	/workspace/7.uart_perf/latest

Test location	/workspace/coverage/default/7.uart_rx_oversample.2571283756
Short name	T880
Test name
Test status
Simulation time	6277557380 ps
CPU time	8.57 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:03 PM PDT 24
Peak memory	200760 kb
Host	smart-8f82954e-0894-4a31-bf63-1387847ac3d7
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2571283756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2571283756
Directory	/workspace/7.uart_rx_oversample/latest

Test location	/workspace/coverage/default/7.uart_rx_parity_err.2082623486
Short name	T871
Test name
Test status
Simulation time	81428638200 ps
CPU time	189.41 seconds
Started	Apr 15 02:51:45 PM PDT 24
Finished	Apr 15 02:54:56 PM PDT 24
Peak memory	200848 kb
Host	smart-ae6a400c-db91-4d9d-8da9-f42dd2531398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082623486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2082623486
Directory	/workspace/7.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/7.uart_rx_start_bit_filter.1298843892
Short name	T1016
Test name
Test status
Simulation time	3477292431 ps
CPU time	4.75 seconds
Started	Apr 15 02:51:52 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	197204 kb
Host	smart-c190a7b6-d03b-489d-968e-c030619025b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298843892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1298843892
Directory	/workspace/7.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/7.uart_smoke.2350725785
Short name	T1050
Test name
Test status
Simulation time	774628889 ps
CPU time	1.94 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:51:43 PM PDT 24
Peak memory	199168 kb
Host	smart-8432d455-6252-44a4-add8-daba3b74a314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350725785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2350725785
Directory	/workspace/7.uart_smoke/latest

Test location	/workspace/coverage/default/7.uart_stress_all.1008438239
Short name	T232
Test name
Test status
Simulation time	154209482443 ps
CPU time	150.43 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:54:13 PM PDT 24
Peak memory	200832 kb
Host	smart-379dd75b-862c-43e4-8dfc-8343f4796b5c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008438239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1008438239
Directory	/workspace/7.uart_stress_all/latest

Test location	/workspace/coverage/default/7.uart_stress_all_with_rand_reset.1342673804
Short name	T698
Test name
Test status
Simulation time	31802492442 ps
CPU time	381.86 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:58:04 PM PDT 24
Peak memory	216556 kb
Host	smart-4f6bb298-7dba-4e08-9b7b-5935189c0b02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342673804 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1342673804
Directory	/workspace/7.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.uart_tx_ovrd.1805928335
Short name	T328
Test name
Test status
Simulation time	2188464786 ps
CPU time	2.54 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:51:39 PM PDT 24
Peak memory	199980 kb
Host	smart-196520a2-d5c6-4353-aaee-e5035b37f456
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805928335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1805928335
Directory	/workspace/7.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/7.uart_tx_rx.1102768907
Short name	T805
Test name
Test status
Simulation time	41724818135 ps
CPU time	73.67 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:52:48 PM PDT 24
Peak memory	200836 kb
Host	smart-2b7b9f9b-89f1-4ba5-a24f-a2bead3bf057
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102768907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1102768907
Directory	/workspace/7.uart_tx_rx/latest

Test location	/workspace/coverage/default/70.uart_fifo_reset.372869462
Short name	T127
Test name
Test status
Simulation time	137997602371 ps
CPU time	156.91 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 02:57:05 PM PDT 24
Peak memory	200912 kb
Host	smart-690b16b1-a8dc-4a37-8ddd-4775d72078fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372869462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.372869462
Directory	/workspace/70.uart_fifo_reset/latest

Test location	/workspace/coverage/default/70.uart_stress_all_with_rand_reset.2978299444
Short name	T656
Test name
Test status
Simulation time	347078832662 ps
CPU time	737.68 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:06:47 PM PDT 24
Peak memory	225672 kb
Host	smart-25c2306b-dd29-4f7a-a421-6f6463a51f85
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978299444 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2978299444
Directory	/workspace/70.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/71.uart_fifo_reset.3658442665
Short name	T180
Test name
Test status
Simulation time	123531435665 ps
CPU time	101.92 seconds
Started	Apr 15 02:54:22 PM PDT 24
Finished	Apr 15 02:56:05 PM PDT 24
Peak memory	200552 kb
Host	smart-34717ae4-29b8-45bc-9893-d8c970550c4e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658442665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3658442665
Directory	/workspace/71.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_fifo_reset.2685977271
Short name	T878
Test name
Test status
Simulation time	88977196708 ps
CPU time	156.42 seconds
Started	Apr 15 02:55:09 PM PDT 24
Finished	Apr 15 02:57:46 PM PDT 24
Peak memory	200856 kb
Host	smart-381ef6da-14a3-498a-9d73-c2015fb7148f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685977271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2685977271
Directory	/workspace/72.uart_fifo_reset/latest

Test location	/workspace/coverage/default/72.uart_stress_all_with_rand_reset.2636181012
Short name	T53
Test name
Test status
Simulation time	238441643329 ps
CPU time	736.93 seconds
Started	Apr 15 02:54:22 PM PDT 24
Finished	Apr 15 03:06:40 PM PDT 24
Peak memory	217360 kb
Host	smart-55aaa8cb-cb30-44fd-bf2b-e99419b45850
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636181012 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2636181012
Directory	/workspace/72.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/73.uart_fifo_reset.621497185
Short name	T858
Test name
Test status
Simulation time	62974045284 ps
CPU time	27.85 seconds
Started	Apr 15 02:54:25 PM PDT 24
Finished	Apr 15 02:54:54 PM PDT 24
Peak memory	200688 kb
Host	smart-89eedfe8-5ffc-4a64-ba9f-902bbdf80e07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621497185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.621497185
Directory	/workspace/73.uart_fifo_reset/latest

Test location	/workspace/coverage/default/73.uart_stress_all_with_rand_reset.3428091768
Short name	T1107
Test name
Test status
Simulation time	50896231087 ps
CPU time	376.66 seconds
Started	Apr 15 02:54:21 PM PDT 24
Finished	Apr 15 03:00:39 PM PDT 24
Peak memory	217388 kb
Host	smart-f52fb41e-2dfd-4dd4-bc8e-361d67308208
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428091768 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3428091768
Directory	/workspace/73.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/74.uart_fifo_reset.383991688
Short name	T1026
Test name
Test status
Simulation time	143876651575 ps
CPU time	117.31 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:56:25 PM PDT 24
Peak memory	200788 kb
Host	smart-dc1586f9-4932-46f4-a83d-320394c06366
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383991688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.383991688
Directory	/workspace/74.uart_fifo_reset/latest

Test location	/workspace/coverage/default/74.uart_stress_all_with_rand_reset.4050189614
Short name	T157
Test name
Test status
Simulation time	190759582009 ps
CPU time	1687.19 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 03:22:35 PM PDT 24
Peak memory	227868 kb
Host	smart-b27b87e4-0485-4eb1-bcfc-71c9c1bc4c78
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050189614 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4050189614
Directory	/workspace/74.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/75.uart_fifo_reset.2504319319
Short name	T332
Test name
Test status
Simulation time	114149050871 ps
CPU time	95.79 seconds
Started	Apr 15 02:54:23 PM PDT 24
Finished	Apr 15 02:56:00 PM PDT 24
Peak memory	200900 kb
Host	smart-63ab8b5b-a9f6-4d6a-aa66-2a3b21371e75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504319319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2504319319
Directory	/workspace/75.uart_fifo_reset/latest

Test location	/workspace/coverage/default/75.uart_stress_all_with_rand_reset.885111860
Short name	T36
Test name
Test status
Simulation time	28232665429 ps
CPU time	227.68 seconds
Started	Apr 15 02:54:23 PM PDT 24
Finished	Apr 15 02:58:11 PM PDT 24
Peak memory	212940 kb
Host	smart-8458c824-286b-4cfc-98c4-0d91a6099085
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885111860 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.885111860
Directory	/workspace/75.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/76.uart_fifo_reset.2505325089
Short name	T826
Test name
Test status
Simulation time	104070220077 ps
CPU time	23.72 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 02:54:52 PM PDT 24
Peak memory	200532 kb
Host	smart-f7a8ad53-1119-4de9-8a3d-087211a0d6a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505325089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2505325089
Directory	/workspace/76.uart_fifo_reset/latest

Test location	/workspace/coverage/default/76.uart_stress_all_with_rand_reset.2445916413
Short name	T921
Test name
Test status
Simulation time	687021031966 ps
CPU time	535.73 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 03:03:24 PM PDT 24
Peak memory	211624 kb
Host	smart-a660288b-7b70-4265-a26f-1ca63bf1624e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445916413 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2445916413
Directory	/workspace/76.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/77.uart_fifo_reset.3159142852
Short name	T404
Test name
Test status
Simulation time	13222961603 ps
CPU time	5.34 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:54:32 PM PDT 24
Peak memory	200904 kb
Host	smart-1b68005e-388e-4ea7-833c-69add03d3d71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159142852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3159142852
Directory	/workspace/77.uart_fifo_reset/latest

Test location	/workspace/coverage/default/77.uart_stress_all_with_rand_reset.4223642796
Short name	T202
Test name
Test status
Simulation time	45623986049 ps
CPU time	416.85 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:01:26 PM PDT 24
Peak memory	217320 kb
Host	smart-0ee6f05c-63dc-4c5a-bc88-238fe1de519e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223642796 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4223642796
Directory	/workspace/77.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/78.uart_fifo_reset.1503066509
Short name	T253
Test name
Test status
Simulation time	97260646933 ps
CPU time	116.35 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:56:24 PM PDT 24
Peak memory	200912 kb
Host	smart-ac3eb0ed-3273-4e62-9806-65880ddccd3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1503066509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1503066509
Directory	/workspace/78.uart_fifo_reset/latest

Test location	/workspace/coverage/default/78.uart_stress_all_with_rand_reset.1573922001
Short name	T1089
Test name
Test status
Simulation time	13630758807 ps
CPU time	372.02 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:00:41 PM PDT 24
Peak memory	216600 kb
Host	smart-331c5180-11f8-4400-a01e-d7fbcdd055a0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573922001 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1573922001
Directory	/workspace/78.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/79.uart_fifo_reset.1276609076
Short name	T194
Test name
Test status
Simulation time	18294493697 ps
CPU time	36.94 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:55:04 PM PDT 24
Peak memory	200852 kb
Host	smart-de78cc6a-bb9b-4836-b721-5819af8cdc7c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1276609076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1276609076
Directory	/workspace/79.uart_fifo_reset/latest

Test location	/workspace/coverage/default/79.uart_stress_all_with_rand_reset.3366154344
Short name	T1063
Test name
Test status
Simulation time	78110629417 ps
CPU time	552.96 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 03:03:42 PM PDT 24
Peak memory	217388 kb
Host	smart-43ce4c2e-1137-4c37-9612-013f8c93933c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366154344 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3366154344
Directory	/workspace/79.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_alert_test.3017097439
Short name	T680
Test name
Test status
Simulation time	10778275 ps
CPU time	0.54 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 02:51:57 PM PDT 24
Peak memory	195192 kb
Host	smart-7a096e97-acc1-43b5-bec1-9207e46bbff9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017097439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3017097439
Directory	/workspace/8.uart_alert_test/latest

Test location	/workspace/coverage/default/8.uart_fifo_full.1726893833
Short name	T167
Test name
Test status
Simulation time	34160194647 ps
CPU time	28.31 seconds
Started	Apr 15 02:51:38 PM PDT 24
Finished	Apr 15 02:52:13 PM PDT 24
Peak memory	200980 kb
Host	smart-8bea0f5f-9401-4fe5-9a33-fd1bb91e5507
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726893833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1726893833
Directory	/workspace/8.uart_fifo_full/latest

Test location	/workspace/coverage/default/8.uart_fifo_overflow.2565853632
Short name	T166
Test name
Test status
Simulation time	124347700215 ps
CPU time	45.57 seconds
Started	Apr 15 02:51:33 PM PDT 24
Finished	Apr 15 02:52:19 PM PDT 24
Peak memory	200860 kb
Host	smart-3c819061-ffbb-4fca-bce4-62b80f683803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565853632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2565853632
Directory	/workspace/8.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/8.uart_fifo_reset.1521763864
Short name	T105
Test name
Test status
Simulation time	36758853339 ps
CPU time	33.74 seconds
Started	Apr 15 02:51:31 PM PDT 24
Finished	Apr 15 02:52:05 PM PDT 24
Peak memory	200852 kb
Host	smart-736afe41-f283-424b-be85-b91412977f58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521763864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1521763864
Directory	/workspace/8.uart_fifo_reset/latest

Test location	/workspace/coverage/default/8.uart_intr.336538023
Short name	T459
Test name
Test status
Simulation time	31342437239 ps
CPU time	5.71 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 02:51:38 PM PDT 24
Peak memory	200808 kb
Host	smart-ead5307c-2e0d-4f6e-8210-44f383443bc0
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336538023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.336538023
Directory	/workspace/8.uart_intr/latest

Test location	/workspace/coverage/default/8.uart_long_xfer_wo_dly.1205452388
Short name	T875
Test name
Test status
Simulation time	233842195597 ps
CPU time	267.8 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:56:03 PM PDT 24
Peak memory	200928 kb
Host	smart-1bdd80f4-0d98-4e8e-b820-460082175b47
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1205452388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1205452388
Directory	/workspace/8.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/8.uart_loopback.2104360201
Short name	T371
Test name
Test status
Simulation time	7058904275 ps
CPU time	5.18 seconds
Started	Apr 15 02:51:43 PM PDT 24
Finished	Apr 15 02:51:49 PM PDT 24
Peak memory	200508 kb
Host	smart-1b34e931-0cbb-4004-9578-3766f2d30b24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104360201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2104360201
Directory	/workspace/8.uart_loopback/latest

Test location	/workspace/coverage/default/8.uart_noise_filter.1531003544
Short name	T999
Test name
Test status
Simulation time	39581993461 ps
CPU time	68.6 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 02:52:45 PM PDT 24
Peak memory	200160 kb
Host	smart-45842aba-bdc7-42cd-a408-ecb9c35ada52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1531003544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1531003544
Directory	/workspace/8.uart_noise_filter/latest

Test location	/workspace/coverage/default/8.uart_perf.2195940703
Short name	T476
Test name
Test status
Simulation time	14012661409 ps
CPU time	834.82 seconds
Started	Apr 15 02:51:27 PM PDT 24
Finished	Apr 15 03:05:23 PM PDT 24
Peak memory	200848 kb
Host	smart-22e8b737-b9e0-430a-9717-5a693a3f0492
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2195940703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2195940703
Directory	/workspace/8.uart_perf/latest

Test location	/workspace/coverage/default/8.uart_rx_oversample.3382107709
Short name	T1174
Test name
Test status
Simulation time	5357191227 ps
CPU time	13.39 seconds
Started	Apr 15 02:51:36 PM PDT 24
Finished	Apr 15 02:51:51 PM PDT 24
Peak memory	200864 kb
Host	smart-479f38a2-37aa-4138-b336-0c05e5c2f790
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3382107709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3382107709
Directory	/workspace/8.uart_rx_oversample/latest

Test location	/workspace/coverage/default/8.uart_rx_parity_err.4252935065
Short name	T754
Test name
Test status
Simulation time	164093481811 ps
CPU time	27.76 seconds
Started	Apr 15 02:51:39 PM PDT 24
Finished	Apr 15 02:52:08 PM PDT 24
Peak memory	200968 kb
Host	smart-8fcff625-4051-4b7d-bb8f-2698226beab8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252935065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4252935065
Directory	/workspace/8.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/8.uart_rx_start_bit_filter.1889938089
Short name	T1030
Test name
Test status
Simulation time	1670863662 ps
CPU time	1.36 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:51:47 PM PDT 24
Peak memory	196244 kb
Host	smart-564a6d3b-5a9a-4523-899e-b275fb8a14b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889938089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1889938089
Directory	/workspace/8.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/8.uart_smoke.3518284639
Short name	T1125
Test name
Test status
Simulation time	690069260 ps
CPU time	2.03 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 02:51:35 PM PDT 24
Peak memory	199640 kb
Host	smart-43e3552f-6d5b-455b-b656-8b2764f4a680
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3518284639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3518284639
Directory	/workspace/8.uart_smoke/latest

Test location	/workspace/coverage/default/8.uart_stress_all.2090365305
Short name	T968
Test name
Test status
Simulation time	44468535833 ps
CPU time	85.43 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 02:52:58 PM PDT 24
Peak memory	200912 kb
Host	smart-792ff06c-acf1-42cf-94d0-fa8cf1c6353c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090365305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2090365305
Directory	/workspace/8.uart_stress_all/latest

Test location	/workspace/coverage/default/8.uart_stress_all_with_rand_reset.2145539846
Short name	T904
Test name
Test status
Simulation time	117467391447 ps
CPU time	367.37 seconds
Started	Apr 15 02:51:32 PM PDT 24
Finished	Apr 15 02:57:40 PM PDT 24
Peak memory	217516 kb
Host	smart-d4a71354-8ee7-48ac-a9ca-210753d82551
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145539846 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2145539846
Directory	/workspace/8.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.uart_tx_ovrd.3368028507
Short name	T412
Test name
Test status
Simulation time	611104220 ps
CPU time	2.26 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:51:38 PM PDT 24
Peak memory	200160 kb
Host	smart-cc818521-5619-4fab-bf56-35248b77776d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368028507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3368028507
Directory	/workspace/8.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/8.uart_tx_rx.4210669136
Short name	T835
Test name
Test status
Simulation time	37833851365 ps
CPU time	71.14 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:52:47 PM PDT 24
Peak memory	200804 kb
Host	smart-d1d390e3-f4d7-4e63-baf5-4446d4d90c52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4210669136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4210669136
Directory	/workspace/8.uart_tx_rx/latest

Test location	/workspace/coverage/default/80.uart_fifo_reset.2242444591
Short name	T356
Test name
Test status
Simulation time	59691823515 ps
CPU time	19.98 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 02:54:49 PM PDT 24
Peak memory	200756 kb
Host	smart-4b798a23-1be2-4774-84a5-9b26b998756a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242444591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2242444591
Directory	/workspace/80.uart_fifo_reset/latest

Test location	/workspace/coverage/default/80.uart_stress_all_with_rand_reset.3509730591
Short name	T77
Test name
Test status
Simulation time	67841573634 ps
CPU time	697.01 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 03:06:07 PM PDT 24
Peak memory	217284 kb
Host	smart-ea530ba6-efda-4799-97a9-859d62b52460
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509730591 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3509730591
Directory	/workspace/80.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/81.uart_fifo_reset.891289692
Short name	T1165
Test name
Test status
Simulation time	29361875040 ps
CPU time	39.55 seconds
Started	Apr 15 02:54:26 PM PDT 24
Finished	Apr 15 02:55:07 PM PDT 24
Peak memory	200896 kb
Host	smart-d3533fa1-0862-4bc1-b9aa-12f058e1eb3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891289692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.891289692
Directory	/workspace/81.uart_fifo_reset/latest

Test location	/workspace/coverage/default/81.uart_stress_all_with_rand_reset.1496969029
Short name	T238
Test name
Test status
Simulation time	97713565403 ps
CPU time	307.03 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 02:59:36 PM PDT 24
Peak memory	217388 kb
Host	smart-a33b185f-654b-4932-b1ec-0ea605c5b08b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496969029 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1496969029
Directory	/workspace/81.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/82.uart_fifo_reset.504380059
Short name	T1103
Test name
Test status
Simulation time	43266524158 ps
CPU time	93.45 seconds
Started	Apr 15 02:54:30 PM PDT 24
Finished	Apr 15 02:56:04 PM PDT 24
Peak memory	200884 kb
Host	smart-d9bb1cea-d055-42ce-9318-0a1391f28c7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504380059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.504380059
Directory	/workspace/82.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_fifo_reset.3829985472
Short name	T191
Test name
Test status
Simulation time	40929976951 ps
CPU time	23.36 seconds
Started	Apr 15 02:54:27 PM PDT 24
Finished	Apr 15 02:54:51 PM PDT 24
Peak memory	200832 kb
Host	smart-72cfafc9-e15c-49f2-8202-8f7717374c65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829985472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3829985472
Directory	/workspace/83.uart_fifo_reset/latest

Test location	/workspace/coverage/default/83.uart_stress_all_with_rand_reset.1002124711
Short name	T1049
Test name
Test status
Simulation time	33450636143 ps
CPU time	168.29 seconds
Started	Apr 15 02:54:28 PM PDT 24
Finished	Apr 15 02:57:17 PM PDT 24
Peak memory	209196 kb
Host	smart-76d4552b-0b46-4026-bb06-fbb97352cac9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002124711 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1002124711
Directory	/workspace/83.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/84.uart_fifo_reset.909563411
Short name	T995
Test name
Test status
Simulation time	92934629002 ps
CPU time	30.47 seconds
Started	Apr 15 02:54:30 PM PDT 24
Finished	Apr 15 02:55:01 PM PDT 24
Peak memory	200860 kb
Host	smart-92018c39-d5d8-4a3d-a0ef-50c0bc49df84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909563411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.909563411
Directory	/workspace/84.uart_fifo_reset/latest

Test location	/workspace/coverage/default/84.uart_stress_all_with_rand_reset.200457781
Short name	T190
Test name
Test status
Simulation time	84730239477 ps
CPU time	1236.14 seconds
Started	Apr 15 02:54:32 PM PDT 24
Finished	Apr 15 03:15:09 PM PDT 24
Peak memory	217608 kb
Host	smart-20dedb19-e549-4e1d-b6d9-fe19e38510a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200457781 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.200457781
Directory	/workspace/84.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/85.uart_fifo_reset.660453194
Short name	T500
Test name
Test status
Simulation time	150565736081 ps
CPU time	32.36 seconds
Started	Apr 15 02:54:30 PM PDT 24
Finished	Apr 15 02:55:03 PM PDT 24
Peak memory	200788 kb
Host	smart-b131dee2-201f-4fa5-a9f6-3b31e9c0181b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=660453194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.660453194
Directory	/workspace/85.uart_fifo_reset/latest

Test location	/workspace/coverage/default/85.uart_stress_all_with_rand_reset.3389258696
Short name	T1082
Test name
Test status
Simulation time	31165371762 ps
CPU time	184.39 seconds
Started	Apr 15 02:54:31 PM PDT 24
Finished	Apr 15 02:57:37 PM PDT 24
Peak memory	217588 kb
Host	smart-08270c3e-b190-47f0-80be-0c361516f407
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389258696 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3389258696
Directory	/workspace/85.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/86.uart_fifo_reset.915415938
Short name	T207
Test name
Test status
Simulation time	152041494467 ps
CPU time	36.51 seconds
Started	Apr 15 02:54:31 PM PDT 24
Finished	Apr 15 02:55:08 PM PDT 24
Peak memory	200916 kb
Host	smart-2cb98fd1-f537-47ac-a68e-75c5d1a71bfc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915415938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.915415938
Directory	/workspace/86.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_fifo_reset.2194720344
Short name	T782
Test name
Test status
Simulation time	25301837428 ps
CPU time	12.82 seconds
Started	Apr 15 02:54:31 PM PDT 24
Finished	Apr 15 02:54:44 PM PDT 24
Peak memory	200916 kb
Host	smart-3cca787f-abce-4e4b-be0e-4e1fa50642eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194720344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2194720344
Directory	/workspace/87.uart_fifo_reset/latest

Test location	/workspace/coverage/default/87.uart_stress_all_with_rand_reset.3751338473
Short name	T54
Test name
Test status
Simulation time	418520849222 ps
CPU time	1532.64 seconds
Started	Apr 15 02:54:30 PM PDT 24
Finished	Apr 15 03:20:04 PM PDT 24
Peak memory	233936 kb
Host	smart-5caa5aed-d2d3-4575-97e6-24b6b3b79ac4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751338473 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3751338473
Directory	/workspace/87.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/88.uart_fifo_reset.2461850936
Short name	T228
Test name
Test status
Simulation time	9555525498 ps
CPU time	17.39 seconds
Started	Apr 15 02:54:37 PM PDT 24
Finished	Apr 15 02:54:55 PM PDT 24
Peak memory	200848 kb
Host	smart-c38dd140-ee72-4572-8a6f-79e7c0528b66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461850936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2461850936
Directory	/workspace/88.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_fifo_reset.3984735492
Short name	T246
Test name
Test status
Simulation time	36974995352 ps
CPU time	18.79 seconds
Started	Apr 15 02:54:31 PM PDT 24
Finished	Apr 15 02:54:50 PM PDT 24
Peak memory	200916 kb
Host	smart-254280f7-20da-41e6-8912-b11788dd8fe7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984735492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3984735492
Directory	/workspace/89.uart_fifo_reset/latest

Test location	/workspace/coverage/default/89.uart_stress_all_with_rand_reset.2334805564
Short name	T39
Test name
Test status
Simulation time	15758201173 ps
CPU time	149.08 seconds
Started	Apr 15 02:54:42 PM PDT 24
Finished	Apr 15 02:57:11 PM PDT 24
Peak memory	216860 kb
Host	smart-10813be4-6164-476f-8dd8-77de8944da6b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334805564 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2334805564
Directory	/workspace/89.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_alert_test.1758899112
Short name	T379
Test name
Test status
Simulation time	38065355 ps
CPU time	0.56 seconds
Started	Apr 15 02:51:40 PM PDT 24
Finished	Apr 15 02:51:42 PM PDT 24
Peak memory	196180 kb
Host	smart-27bc8c6c-03a4-4a7c-8b09-60a09eb35401
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758899112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1758899112
Directory	/workspace/9.uart_alert_test/latest

Test location	/workspace/coverage/default/9.uart_fifo_full.3447227806
Short name	T1052
Test name
Test status
Simulation time	89042846635 ps
CPU time	52.62 seconds
Started	Apr 15 02:51:37 PM PDT 24
Finished	Apr 15 02:52:31 PM PDT 24
Peak memory	200784 kb
Host	smart-6a28d816-f0ce-425d-b22a-f36ef3d22cba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3447227806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3447227806
Directory	/workspace/9.uart_fifo_full/latest

Test location	/workspace/coverage/default/9.uart_fifo_overflow.244587597
Short name	T288
Test name
Test status
Simulation time	54144329995 ps
CPU time	25.53 seconds
Started	Apr 15 02:51:58 PM PDT 24
Finished	Apr 15 02:52:24 PM PDT 24
Peak memory	200840 kb
Host	smart-07523827-76ce-4f94-a704-3913564691b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=244587597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.244587597
Directory	/workspace/9.uart_fifo_overflow/latest

Test location	/workspace/coverage/default/9.uart_fifo_reset.4062231782
Short name	T768
Test name
Test status
Simulation time	89620797337 ps
CPU time	230.79 seconds
Started	Apr 15 02:51:48 PM PDT 24
Finished	Apr 15 02:55:40 PM PDT 24
Peak memory	200916 kb
Host	smart-a36ab307-9d57-440f-a50b-58ebaaf8404c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4062231782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4062231782
Directory	/workspace/9.uart_fifo_reset/latest

Test location	/workspace/coverage/default/9.uart_intr.2231008257
Short name	T592
Test name
Test status
Simulation time	334344330470 ps
CPU time	589.26 seconds
Started	Apr 15 02:51:35 PM PDT 24
Finished	Apr 15 03:01:25 PM PDT 24
Peak memory	200912 kb
Host	smart-edc79b54-434f-4b7d-8b3e-75e3dcd82553
User	root
Command	/workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231008257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2231008257
Directory	/workspace/9.uart_intr/latest

Test location	/workspace/coverage/default/9.uart_long_xfer_wo_dly.4109832977
Short name	T790
Test name
Test status
Simulation time	32357824266 ps
CPU time	63.41 seconds
Started	Apr 15 02:51:44 PM PDT 24
Finished	Apr 15 02:52:49 PM PDT 24
Peak memory	200860 kb
Host	smart-72bb7627-ecd8-4ea9-924f-083a72a2ec23
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4109832977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4109832977
Directory	/workspace/9.uart_long_xfer_wo_dly/latest

Test location	/workspace/coverage/default/9.uart_loopback.833466874
Short name	T1051
Test name
Test status
Simulation time	2539422145 ps
CPU time	1.56 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:51:48 PM PDT 24
Peak memory	197220 kb
Host	smart-5afd48cf-f00e-46f5-91ab-88c69ea73c60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=833466874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.833466874
Directory	/workspace/9.uart_loopback/latest

Test location	/workspace/coverage/default/9.uart_noise_filter.2609816740
Short name	T466
Test name
Test status
Simulation time	252912319641 ps
CPU time	96.26 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 02:53:24 PM PDT 24
Peak memory	201248 kb
Host	smart-bdf050d0-07f9-49c1-a858-0ad4b191dd39
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609816740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2609816740
Directory	/workspace/9.uart_noise_filter/latest

Test location	/workspace/coverage/default/9.uart_perf.1278547596
Short name	T801
Test name
Test status
Simulation time	17712478349 ps
CPU time	982.58 seconds
Started	Apr 15 02:51:46 PM PDT 24
Finished	Apr 15 03:08:09 PM PDT 24
Peak memory	200868 kb
Host	smart-eb2f3259-40e7-4f69-b851-96433b8f2b3c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1278547596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1278547596
Directory	/workspace/9.uart_perf/latest

Test location	/workspace/coverage/default/9.uart_rx_oversample.4147002301
Short name	T750
Test name
Test status
Simulation time	1377975292 ps
CPU time	2.82 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:51:46 PM PDT 24
Peak memory	198764 kb
Host	smart-d9b40cd6-f7b7-4b28-96c9-4eb1c9689ef6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4147002301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.4147002301
Directory	/workspace/9.uart_rx_oversample/latest

Test location	/workspace/coverage/default/9.uart_rx_parity_err.1594019374
Short name	T1150
Test name
Test status
Simulation time	20379527287 ps
CPU time	15.27 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:11 PM PDT 24
Peak memory	200904 kb
Host	smart-a88a691c-0c4c-4c8e-8770-05cfaabba0e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594019374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1594019374
Directory	/workspace/9.uart_rx_parity_err/latest

Test location	/workspace/coverage/default/9.uart_rx_start_bit_filter.760670896
Short name	T294
Test name
Test status
Simulation time	3629774434 ps
CPU time	5.68 seconds
Started	Apr 15 02:51:54 PM PDT 24
Finished	Apr 15 02:52:02 PM PDT 24
Peak memory	197204 kb
Host	smart-7d605a21-2a2d-4703-91fe-960f9eb3676f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760670896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.760670896
Directory	/workspace/9.uart_rx_start_bit_filter/latest

Test location	/workspace/coverage/default/9.uart_smoke.551478955
Short name	T898
Test name
Test status
Simulation time	6004488608 ps
CPU time	20.28 seconds
Started	Apr 15 02:51:42 PM PDT 24
Finished	Apr 15 02:52:03 PM PDT 24
Peak memory	200720 kb
Host	smart-9042c0d9-5f6f-4826-91ee-264f4eae9e5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551478955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.551478955
Directory	/workspace/9.uart_smoke/latest

Test location	/workspace/coverage/default/9.uart_stress_all.826629579
Short name	T742
Test name
Test status
Simulation time	186028354266 ps
CPU time	333.94 seconds
Started	Apr 15 02:51:52 PM PDT 24
Finished	Apr 15 02:57:27 PM PDT 24
Peak memory	217008 kb
Host	smart-f691cb59-1459-46b4-9ee5-e749f55ae2ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826629579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.826629579
Directory	/workspace/9.uart_stress_all/latest

Test location	/workspace/coverage/default/9.uart_stress_all_with_rand_reset.1772870919
Short name	T629
Test name
Test status
Simulation time	59497683290 ps
CPU time	848.62 seconds
Started	Apr 15 02:51:55 PM PDT 24
Finished	Apr 15 03:06:05 PM PDT 24
Peak memory	217572 kb
Host	smart-3c2df10f-fc4b-49b8-968c-2b7b21105254
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772870919 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1772870919
Directory	/workspace/9.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.uart_tx_ovrd.1201280602
Short name	T813
Test name
Test status
Simulation time	1116059577 ps
CPU time	3.84 seconds
Started	Apr 15 02:51:34 PM PDT 24
Finished	Apr 15 02:51:39 PM PDT 24
Peak memory	200436 kb
Host	smart-417a5215-13d1-4259-8a4b-3bd9ab972866
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201280602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1201280602
Directory	/workspace/9.uart_tx_ovrd/latest

Test location	/workspace/coverage/default/9.uart_tx_rx.3114616050
Short name	T947
Test name
Test status
Simulation time	106413363252 ps
CPU time	230.4 seconds
Started	Apr 15 02:51:47 PM PDT 24
Finished	Apr 15 02:55:38 PM PDT 24
Peak memory	200856 kb
Host	smart-6c5801a5-15d5-44eb-a6c5-5df6fe2ddead
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3114616050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3114616050
Directory	/workspace/9.uart_tx_rx/latest

Test location	/workspace/coverage/default/90.uart_fifo_reset.3795749967
Short name	T143
Test name
Test status
Simulation time	95419458052 ps
CPU time	255.49 seconds
Started	Apr 15 02:54:33 PM PDT 24
Finished	Apr 15 02:58:50 PM PDT 24
Peak memory	200888 kb
Host	smart-ea06ce17-c2bb-4118-851c-904cd33f7942
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795749967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3795749967
Directory	/workspace/90.uart_fifo_reset/latest

Test location	/workspace/coverage/default/90.uart_stress_all_with_rand_reset.324444823
Short name	T1037
Test name
Test status
Simulation time	1043227957353 ps
CPU time	594.31 seconds
Started	Apr 15 02:54:35 PM PDT 24
Finished	Apr 15 03:04:30 PM PDT 24
Peak memory	225820 kb
Host	smart-edeb5b0d-6598-414c-a0e7-823de18de395
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324444823 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.324444823
Directory	/workspace/90.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/91.uart_fifo_reset.3178162552
Short name	T1136
Test name
Test status
Simulation time	13155029631 ps
CPU time	11.55 seconds
Started	Apr 15 02:54:34 PM PDT 24
Finished	Apr 15 02:54:47 PM PDT 24
Peak memory	200564 kb
Host	smart-7de11879-1a15-4aad-9280-00f469286884
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178162552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3178162552
Directory	/workspace/91.uart_fifo_reset/latest

Test location	/workspace/coverage/default/91.uart_stress_all_with_rand_reset.1185919469
Short name	T49
Test name
Test status
Simulation time	80230362907 ps
CPU time	726.48 seconds
Started	Apr 15 02:54:41 PM PDT 24
Finished	Apr 15 03:06:48 PM PDT 24
Peak memory	217548 kb
Host	smart-93652d5b-3eba-4dc5-96f3-f8464f2b890a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185919469 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1185919469
Directory	/workspace/91.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/92.uart_fifo_reset.4163888223
Short name	T144
Test name
Test status
Simulation time	45738227087 ps
CPU time	24.4 seconds
Started	Apr 15 02:54:34 PM PDT 24
Finished	Apr 15 02:54:59 PM PDT 24
Peak memory	200924 kb
Host	smart-d6388510-3b6a-40d6-8366-74966eaf5527
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4163888223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4163888223
Directory	/workspace/92.uart_fifo_reset/latest

Test location	/workspace/coverage/default/92.uart_stress_all_with_rand_reset.4239926426
Short name	T107
Test name
Test status
Simulation time	18532016867 ps
CPU time	122.69 seconds
Started	Apr 15 02:54:42 PM PDT 24
Finished	Apr 15 02:56:45 PM PDT 24
Peak memory	216428 kb
Host	smart-80c06067-81a0-463d-b423-5459fec63423
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239926426 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4239926426
Directory	/workspace/92.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/93.uart_fifo_reset.1502756537
Short name	T1147
Test name
Test status
Simulation time	25786217729 ps
CPU time	19.65 seconds
Started	Apr 15 02:54:38 PM PDT 24
Finished	Apr 15 02:54:58 PM PDT 24
Peak memory	200080 kb
Host	smart-062ff59e-eced-4307-91db-fd7f9ef77624
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502756537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1502756537
Directory	/workspace/93.uart_fifo_reset/latest

Test location	/workspace/coverage/default/93.uart_stress_all_with_rand_reset.2620488624
Short name	T1032
Test name
Test status
Simulation time	85390828847 ps
CPU time	564.16 seconds
Started	Apr 15 02:54:42 PM PDT 24
Finished	Apr 15 03:04:07 PM PDT 24
Peak memory	216888 kb
Host	smart-a8ca312e-12e7-450e-aa5d-775c6c4bfc63
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620488624 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2620488624
Directory	/workspace/93.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/94.uart_fifo_reset.818477782
Short name	T226
Test name
Test status
Simulation time	117878163206 ps
CPU time	100.61 seconds
Started	Apr 15 02:54:40 PM PDT 24
Finished	Apr 15 02:56:22 PM PDT 24
Peak memory	200836 kb
Host	smart-51a38efc-c045-49b5-97fe-a5cce2a7babb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818477782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.818477782
Directory	/workspace/94.uart_fifo_reset/latest

Test location	/workspace/coverage/default/94.uart_stress_all_with_rand_reset.2821637425
Short name	T543
Test name
Test status
Simulation time	183649106025 ps
CPU time	384.74 seconds
Started	Apr 15 02:54:35 PM PDT 24
Finished	Apr 15 03:01:00 PM PDT 24
Peak memory	217564 kb
Host	smart-74db05cb-ee49-40c4-b343-e6a6376e25a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821637425 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2821637425
Directory	/workspace/94.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/95.uart_fifo_reset.350118006
Short name	T619
Test name
Test status
Simulation time	29069999139 ps
CPU time	47.93 seconds
Started	Apr 15 02:54:40 PM PDT 24
Finished	Apr 15 02:55:28 PM PDT 24
Peak memory	200736 kb
Host	smart-27b5c443-dbd5-4380-872a-bca4fbe091ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350118006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.350118006
Directory	/workspace/95.uart_fifo_reset/latest

Test location	/workspace/coverage/default/95.uart_stress_all_with_rand_reset.2005339319
Short name	T931
Test name
Test status
Simulation time	278003324482 ps
CPU time	692.65 seconds
Started	Apr 15 02:54:39 PM PDT 24
Finished	Apr 15 03:06:13 PM PDT 24
Peak memory	225760 kb
Host	smart-5997e265-791b-40b5-a16a-16327d01ff20
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005339319 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2005339319
Directory	/workspace/95.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/96.uart_fifo_reset.1340444966
Short name	T965
Test name
Test status
Simulation time	120327150536 ps
CPU time	49.2 seconds
Started	Apr 15 02:54:40 PM PDT 24
Finished	Apr 15 02:55:30 PM PDT 24
Peak memory	200892 kb
Host	smart-ef8d0597-690e-438c-843f-a06c095465b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340444966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1340444966
Directory	/workspace/96.uart_fifo_reset/latest

Test location	/workspace/coverage/default/96.uart_stress_all_with_rand_reset.3370613019
Short name	T692
Test name
Test status
Simulation time	38903436970 ps
CPU time	316.73 seconds
Started	Apr 15 02:54:39 PM PDT 24
Finished	Apr 15 02:59:57 PM PDT 24
Peak memory	217396 kb
Host	smart-7fe5276d-4c84-4215-a1fe-500a6f65d9d3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370613019 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3370613019
Directory	/workspace/96.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/97.uart_fifo_reset.834389132
Short name	T477
Test name
Test status
Simulation time	30863772674 ps
CPU time	21.95 seconds
Started	Apr 15 02:54:39 PM PDT 24
Finished	Apr 15 02:55:02 PM PDT 24
Peak memory	200788 kb
Host	smart-38f0c20b-2b24-4e83-8e87-c34b246430b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834389132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.834389132
Directory	/workspace/97.uart_fifo_reset/latest

Test location	/workspace/coverage/default/97.uart_stress_all_with_rand_reset.895687546
Short name	T763
Test name
Test status
Simulation time	45237874493 ps
CPU time	116.49 seconds
Started	Apr 15 02:54:40 PM PDT 24
Finished	Apr 15 02:56:37 PM PDT 24
Peak memory	217236 kb
Host	smart-774dde33-872a-43c5-afea-ba2ce728d43b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895687546 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.895687546
Directory	/workspace/97.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/98.uart_stress_all_with_rand_reset.3842799583
Short name	T512
Test name
Test status
Simulation time	29688452502 ps
CPU time	348.77 seconds
Started	Apr 15 02:54:50 PM PDT 24
Finished	Apr 15 03:00:39 PM PDT 24
Peak memory	209100 kb
Host	smart-9dfe9ff4-031c-46a7-bc03-3b4c220f0ec0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842799583 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3842799583
Directory	/workspace/98.uart_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/99.uart_fifo_reset.2789539730
Short name	T241
Test name
Test status
Simulation time	54324066406 ps
CPU time	44.09 seconds
Started	Apr 15 02:54:43 PM PDT 24
Finished	Apr 15 02:55:27 PM PDT 24
Peak memory	200944 kb
Host	smart-9229daa0-cb3c-4206-8ca9-98bb54b741f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789539730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2789539730
Directory	/workspace/99.uart_fifo_reset/latest

Test location	/workspace/coverage/default/99.uart_stress_all_with_rand_reset.1593899164
Short name	T701
Test name
Test status
Simulation time	116493472446 ps
CPU time	488.55 seconds
Started	Apr 15 02:54:49 PM PDT 24
Finished	Apr 15 03:02:58 PM PDT 24
Peak memory	217172 kb
Host	smart-96ce46dc-7c56-4b55-a2a3-ed50f381f69c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593899164 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1593899164
Directory	/workspace/99.uart_stress_all_with_rand_reset/latest