Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	109833	1			T1	51		T2	18		T4	15
all_values[1]	109833	1			T1	51		T2	18		T4	15
all_values[2]	109833	1			T1	51		T2	18		T4	15
all_values[3]	109833	1			T1	51		T2	18		T4	15
all_values[4]	109833	1			T1	51		T2	18		T4	15
all_values[5]	109833	1			T1	51		T2	18		T4	15
all_values[6]	109833	1			T1	51		T2	18		T4	15
all_values[7]	109833	1			T1	51		T2	18		T4	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430866

1

T1

204

T2

61

T4

58

auto[1]

447798

1

T1

204

T2

83

T4

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

820798

1

T1

345

T2

125

T4

98

auto[1]

57866

1

T1

63

T2

19

T4

22

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29056	1			T1	4		T8	9		T10	3
all_values[0]	auto[0]	auto[1]	22089	1			T1	44		T2	8		T4	2
all_values[0]	auto[1]	auto[0]	34713	1			T2	8		T6	4		T8	11
all_values[0]	auto[1]	auto[1]	23975	1			T1	3		T2	2		T4	13
all_values[1]	auto[0]	auto[0]	52802	1			T2	12		T4	15		T5	19
all_values[1]	auto[0]	auto[1]	1780	1			T12	2		T15	1		T13	17
all_values[1]	auto[1]	auto[0]	53525	1			T1	46		T2	6		T6	16
all_values[1]	auto[1]	auto[1]	1726	1			T1	5		T11	3		T125	5
all_values[2]	auto[0]	auto[0]	49642	1			T1	51		T2	5		T4	6
all_values[2]	auto[0]	auto[1]	2804	1			T2	2		T4	7		T6	4
all_values[2]	auto[1]	auto[0]	54774	1			T2	4		T4	2		T5	13
all_values[2]	auto[1]	auto[1]	2613	1			T2	7		T5	6		T6	3
all_values[3]	auto[0]	auto[0]	53732	1			T1	3		T2	18		T4	2
all_values[3]	auto[0]	auto[1]	278	1			T12	2		T13	1		T122	2
all_values[3]	auto[1]	auto[0]	55515	1			T1	48		T4	13		T5	9
all_values[3]	auto[1]	auto[1]	308	1			T12	3		T15	1		T13	3
all_values[4]	auto[0]	auto[0]	53931	1			T1	39		T2	2		T5	10
all_values[4]	auto[0]	auto[1]	447	1			T1	9		T12	1		T13	1
all_values[4]	auto[1]	auto[0]	55020	1			T1	1		T2	16		T4	15
all_values[4]	auto[1]	auto[1]	435	1			T1	2		T13	5		T36	3
all_values[5]	auto[0]	auto[0]	53893	1			T1	3		T2	2		T4	13
all_values[5]	auto[0]	auto[1]	200	1			T15	1		T13	2		T36	1
all_values[5]	auto[1]	auto[0]	55591	1			T1	48		T2	16		T4	2
all_values[5]	auto[1]	auto[1]	149	1			T12	2		T15	1		T36	1
all_values[6]	auto[0]	auto[0]	55641	1			T1	51		T2	3		T4	2
all_values[6]	auto[0]	auto[1]	163	1			T13	1		T129	2		T124	2
all_values[6]	auto[1]	auto[0]	53849	1			T2	15		T4	13		T5	19
all_values[6]	auto[1]	auto[1]	180	1			T13	2		T36	1		T129	1
all_values[7]	auto[0]	auto[0]	54060	1			T2	9		T4	11		T6	7
all_values[7]	auto[0]	auto[1]	348	1			T17	2		T12	2		T13	3
all_values[7]	auto[1]	auto[0]	55054	1			T1	51		T2	9		T4	4
all_values[7]	auto[1]	auto[1]	371	1			T12	5		T15	3		T13	10