Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2555

1

T1

1

T2

1

T3

1

auto[UartRx]

2555

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4485	1			T1	2		T2	2		T3	2
values[1]	58	1			T24	1		T35	1		T129	1
values[2]	40	1			T15	1		T36	1		T130	1
values[3]	44	1			T18	1		T13	1		T129	3
values[4]	60	1			T18	2		T24	1		T15	1
values[5]	59	1			T18	1		T13	2		T35	1
values[6]	71	1			T18	2		T24	1		T15	1
values[7]	70	1			T22	1		T18	2		T15	2
values[8]	47	1			T22	3		T129	1		T130	4
values[9]	70	1			T22	1		T13	1		T37	1
values[10]	71	1			T15	1		T13	1		T34	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2337	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	16	1			T24	1		T35	1		T113	2
auto[UartTx]	values[2]	12	1			T55	1		T315	1		T165	1
auto[UartTx]	values[3]	10	1			T13	1		T129	1		T114	1
auto[UartTx]	values[4]	25	1			T18	2		T316	1		T114	1
auto[UartTx]	values[5]	20	1			T18	1		T129	1		T115	1
auto[UartTx]	values[6]	28	1			T18	1		T24	1		T35	1
auto[UartTx]	values[7]	25	1			T18	1		T15	1		T13	1
auto[UartTx]	values[8]	17	1			T22	2		T129	1		T130	1
auto[UartTx]	values[9]	24	1			T22	1		T317	1		T130	2
auto[UartTx]	values[10]	29	1			T34	1		T299	1		T113	1
auto[UartRx]	values[0]	2148	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	42	1			T129	1		T55	2		T115	2
auto[UartRx]	values[2]	28	1			T15	1		T36	1		T130	1
auto[UartRx]	values[3]	34	1			T18	1		T129	2		T317	1
auto[UartRx]	values[4]	35	1			T24	1		T15	1		T34	1
auto[UartRx]	values[5]	39	1			T13	2		T35	1		T37	2
auto[UartRx]	values[6]	43	1			T18	1		T15	1		T35	1
auto[UartRx]	values[7]	45	1			T22	1		T18	1		T15	1
auto[UartRx]	values[8]	30	1			T22	1		T130	3		T68	1
auto[UartRx]	values[9]	46	1			T13	1		T37	1		T38	1
auto[UartRx]	values[10]	42	1			T15	1		T13	1		T34	1