Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2486	1			T5	1		T6	1		T7	3
auto[BaudRate115200]	2241	1			T2	3		T4	1		T6	1
auto[BaudRate230400]	2120	1			T1	2		T2	2		T4	3
auto[BaudRate128Kbps]	2045	1			T2	2		T7	9		T9	1
auto[BaudRate256Kbps]	2361	1			T2	4		T4	1		T6	2
auto[BaudRate1Mbps]	1805	1			T2	4		T4	1		T5	1
auto[BaudRate1p5Mbps]	1391	1			T2	4		T4	1		T5	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1572	1			T1	2		T4	7		T7	48
freqs[25]	1338	1			T6	6		T43	5		T44	9
freqs[48]	661	1			T118	7		T137	6		T37	82
freqs[50]	438	1			T41	4		T15	11		T148	8
freqs[100]	1137	1			T25	2		T22	11		T24	13

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	249	1			T7	3		T11	1		T12	3
auto[BaudRate9600]	freqs[25]	232	1			T6	1		T267	2		T34	2
auto[BaudRate9600]	freqs[48]	104	1			T37	13		T129	2		T55	5
auto[BaudRate9600]	freqs[50]	83	1			T15	1		T124	4		T318	1
auto[BaudRate9600]	freqs[100]	181	1			T22	2		T24	2		T269	2
auto[BaudRate115200]	freqs[24]	230	1			T4	1		T7	9		T11	1
auto[BaudRate115200]	freqs[25]	205	1			T6	1		T267	3		T34	1
auto[BaudRate115200]	freqs[48]	68	1			T118	1		T137	1		T37	1
auto[BaudRate115200]	freqs[50]	63	1			T41	2		T15	1		T148	4
auto[BaudRate115200]	freqs[100]	185	1			T22	2		T24	1		T269	2
auto[BaudRate230400]	freqs[24]	239	1			T1	2		T4	3		T7	12
auto[BaudRate230400]	freqs[25]	186	1			T34	5		T49	2		T110	3
auto[BaudRate230400]	freqs[48]	102	1			T118	2		T137	1		T37	16
auto[BaudRate230400]	freqs[50]	69	1			T15	3		T148	1		T319	1
auto[BaudRate230400]	freqs[100]	144	1			T22	1		T132	2		T269	1
auto[BaudRate128Kbps]	freqs[24]	228	1			T7	9		T9	1		T11	1
auto[BaudRate128Kbps]	freqs[25]	174	1			T267	2		T34	4		T123	3
auto[BaudRate128Kbps]	freqs[48]	98	1			T118	1		T37	10		T107	1
auto[BaudRate128Kbps]	freqs[50]	60	1			T41	1		T15	2		T124	6
auto[BaudRate128Kbps]	freqs[100]	149	1			T25	1		T22	1		T24	1
auto[BaudRate256Kbps]	freqs[24]	226	1			T4	1		T7	6		T11	2
auto[BaudRate256Kbps]	freqs[25]	221	1			T6	2		T43	1		T44	5
auto[BaudRate256Kbps]	freqs[48]	88	1			T137	1		T37	12		T107	3
auto[BaudRate256Kbps]	freqs[50]	61	1			T41	1		T15	2		T148	1
auto[BaudRate256Kbps]	freqs[100]	156	1			T25	1		T24	2		T132	1
auto[BaudRate1Mbps]	freqs[24]	264	1			T4	1		T7	3		T125	1
auto[BaudRate1Mbps]	freqs[25]	187	1			T43	3		T44	3		T34	3
auto[BaudRate1Mbps]	freqs[48]	115	1			T118	1		T137	1		T37	17
auto[BaudRate1Mbps]	freqs[50]	62	1			T148	1		T319	1		T124	9
auto[BaudRate1Mbps]	freqs[100]	155	1			T22	3		T24	3		T132	4
auto[BaudRate1p5Mbps]	freqs[25]	133	1			T6	2		T43	1		T44	1
auto[BaudRate1p5Mbps]	freqs[48]	86	1			T118	2		T137	2		T37	13
auto[BaudRate1p5Mbps]	freqs[50]	40	1			T15	2		T148	1		T124	5
auto[BaudRate1p5Mbps]	freqs[100]	167	1			T22	2		T24	4		T132	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded