Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29652867	1			T1	560		T2	399		T4	22
all_levels[1]	200858	1			T2	45		T4	2		T5	19
all_levels[2]	2696	1			T2	3		T4	2		T5	5
all_levels[3]	1130	1			T2	2		T5	3		T6	6
all_levels[4]	778	1			T2	2		T5	3		T6	4
all_levels[5]	535	1			T2	1		T5	1		T6	3
all_levels[6]	401	1			T4	1		T17	1		T12	1
all_levels[7]	353	1			T6	1		T10	1		T131	4
all_levels[8]	314	1			T2	1		T17	1		T33	1
all_levels[9]	242	1			T10	2		T32	1		T118	3
all_levels[10]	200	1			T32	1		T13	1		T132	2
all_levels[11]	187	1			T10	1		T18	1		T13	2
all_levels[12]	156	1			T10	1		T13	1		T34	2
all_levels[13]	156	1			T4	1		T13	1		T118	1
all_levels[14]	147	1			T17	1		T18	1		T13	1
all_levels[15]	116	1			T4	2		T32	1		T13	1
all_levels[16]	94	1			T11	1		T34	1		T35	1
all_levels[17]	87	1			T6	1		T17	3		T32	1
all_levels[18]	98	1			T17	2		T33	1		T13	1
all_levels[19]	74	1			T11	3		T125	1		T17	1
all_levels[20]	63	1			T125	1		T33	1		T15	1
all_levels[21]	95	1			T4	1		T6	3		T10	1
all_levels[22]	62	1			T33	1		T118	1		T49	1
all_levels[23]	57	1			T133	1		T134	1		T135	1
all_levels[24]	58	1			T13	1		T118	1		T35	1
all_levels[25]	50	1			T45	1		T15	1		T136	1
all_levels[26]	51	1			T4	1		T34	1		T119	1
all_levels[27]	50	1			T4	1		T15	2		T137	1
all_levels[28]	31	1			T125	1		T132	1		T118	1
all_levels[29]	22	1			T125	1		T135	1		T138	1
all_levels[30]	35	1			T45	1		T15	1		T139	1
all_levels[31]	45	1			T12	1		T35	1		T38	3
all_levels[32]	31	1			T140	1		T141	2		T128	1
all_levels[33]	31	1			T13	1		T38	1		T142	1
all_levels[34]	28	1			T35	1		T143	1		T144	1
all_levels[35]	22	1			T145	1		T128	1		T71	1
all_levels[36]	22	1			T68	1		T146	1		T147	2
all_levels[37]	24	1			T10	1		T148	1		T65	1
all_levels[38]	28	1			T11	1		T149	1		T150	1
all_levels[39]	23	1			T11	1		T135	1		T151	1
all_levels[40]	21	1			T142	1		T71	1		T149	1
all_levels[41]	12	1			T32	1		T13	1		T51	1
all_levels[42]	13	1			T11	1		T35	1		T134	1
all_levels[43]	19	1			T152	1		T153	1		T154	1
all_levels[44]	13	1			T132	1		T155	1		T65	1
all_levels[45]	12	1			T35	1		T109	1		T156	2
all_levels[46]	11	1			T157	1		T158	1		T159	1
all_levels[47]	6	1			T70	1		T160	1		T161	2
all_levels[48]	14	1			T71	1		T162	1		T163	1
all_levels[49]	11	1			T145	1		T136	1		T164	2
all_levels[50]	10	1			T128	1		T70	1		T165	1
all_levels[51]	6	1			T136	1		T166	1		T165	1
all_levels[52]	13	1			T68	3		T167	1		T168	2
all_levels[53]	14	1			T109	2		T134	2		T70	1
all_levels[54]	12	1			T35	1		T169	1		T170	1
all_levels[55]	8	1			T125	1		T136	1		T167	1
all_levels[56]	11	1			T152	1		T136	1		T171	1
all_levels[57]	18	1			T13	2		T136	1		T172	1
all_levels[58]	8	1			T173	3		T174	3		T175	1
all_levels[59]	12	1			T13	1		T124	1		T140	1
all_levels[60]	4	1			T136	1		T176	1		T177	1
all_levels[61]	8	1			T120	2		T178	1		T179	1
all_levels[62]	12	1			T139	4		T142	1		T180	1
all_levels[63]	7	1			T158	1		T169	2		T181	1
all_levels[64]	112	1			T12	2		T13	3		T36	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29858062

1

T1

542

T2

453

T4

33

auto[1]

4642

1

T1

18

T6

5

T7

9

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40] , all_levels[41] , all_levels[42]]	[auto[1]]	--	--	4
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29648695	1			T1	542		T2	399		T4	22
all_levels[0]	auto[1]	4172	1			T1	18		T6	4		T7	9
all_levels[1]	auto[0]	200791	1			T2	45		T4	2		T5	19
all_levels[1]	auto[1]	67	1			T133	3		T134	1		T182	2
all_levels[2]	auto[0]	2675	1			T2	3		T4	2		T5	5
all_levels[2]	auto[1]	21	1			T131	1		T183	1		T184	2
all_levels[3]	auto[0]	1105	1			T2	2		T5	3		T6	6
all_levels[3]	auto[1]	25	1			T51	1		T185	4		T168	1
all_levels[4]	auto[0]	753	1			T2	2		T5	3		T6	4
all_levels[4]	auto[1]	25	1			T131	1		T186	2		T134	1
all_levels[5]	auto[0]	516	1			T2	1		T5	1		T6	3
all_levels[5]	auto[1]	19	1			T139	1		T187	2		T188	1
all_levels[6]	auto[0]	383	1			T4	1		T17	1		T12	1
all_levels[6]	auto[1]	18	1			T154	1		T65	2		T189	3
all_levels[7]	auto[0]	332	1			T6	1		T10	1		T131	3
all_levels[7]	auto[1]	21	1			T131	1		T184	1		T187	3
all_levels[8]	auto[0]	301	1			T2	1		T17	1		T33	1
all_levels[8]	auto[1]	13	1			T132	1		T190	3		T164	1
all_levels[9]	auto[0]	230	1			T10	2		T32	1		T118	3
all_levels[9]	auto[1]	12	1			T36	1		T182	1		T191	1
all_levels[10]	auto[0]	194	1			T32	1		T13	1		T132	2
all_levels[10]	auto[1]	6	1			T192	2		T173	1		T193	1
all_levels[11]	auto[0]	176	1			T10	1		T18	1		T13	2
all_levels[11]	auto[1]	11	1			T182	2		T194	2		T195	1
all_levels[12]	auto[0]	145	1			T10	1		T13	1		T34	2
all_levels[12]	auto[1]	11	1			T196	1		T197	2		T198	2
all_levels[13]	auto[0]	136	1			T4	1		T13	1		T118	1
all_levels[13]	auto[1]	20	1			T133	2		T139	1		T199	1
all_levels[14]	auto[0]	134	1			T17	1		T18	1		T13	1
all_levels[14]	auto[1]	13	1			T200	1		T201	1		T202	3
all_levels[15]	auto[0]	101	1			T4	2		T32	1		T13	1
all_levels[15]	auto[1]	15	1			T53	3		T72	1		T203	1
all_levels[16]	auto[0]	88	1			T11	1		T34	1		T35	1
all_levels[16]	auto[1]	6	1			T204	2		T205	2		T206	1
all_levels[17]	auto[0]	82	1			T6	1		T17	3		T32	1
all_levels[17]	auto[1]	5	1			T146	1		T201	2		T207	1
all_levels[18]	auto[0]	83	1			T17	2		T33	1		T13	1
all_levels[18]	auto[1]	15	1			T183	1		T154	1		T146	1
all_levels[19]	auto[0]	68	1			T11	1		T125	1		T17	1
all_levels[19]	auto[1]	6	1			T11	2		T53	1		T208	1
all_levels[20]	auto[0]	60	1			T125	1		T33	1		T15	1
all_levels[20]	auto[1]	3	1			T69	2		T209	1		-	-
all_levels[21]	auto[0]	84	1			T4	1		T6	2		T10	1
all_levels[21]	auto[1]	11	1			T6	1		T11	1		T210	1
all_levels[22]	auto[0]	49	1			T33	1		T118	1		T49	1
all_levels[22]	auto[1]	13	1			T134	3		T211	1		T212	2
all_levels[23]	auto[0]	55	1			T133	1		T134	1		T135	1
all_levels[23]	auto[1]	2	1			T72	1		T213	1		-	-
all_levels[24]	auto[0]	47	1			T13	1		T118	1		T35	1
all_levels[24]	auto[1]	11	1			T214	1		T167	1		T215	3
all_levels[25]	auto[0]	44	1			T45	1		T15	1		T136	1
all_levels[25]	auto[1]	6	1			T182	1		T161	1		T198	1
all_levels[26]	auto[0]	42	1			T4	1		T34	1		T119	1
all_levels[26]	auto[1]	9	1			T203	1		T216	2		T217	3
all_levels[27]	auto[0]	48	1			T4	1		T15	2		T137	1
all_levels[27]	auto[1]	2	1			T218	1		T219	1		-	-
all_levels[28]	auto[0]	30	1			T125	1		T132	1		T118	1
all_levels[28]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[29]	auto[0]	21	1			T125	1		T135	1		T138	1
all_levels[29]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[30]	auto[0]	32	1			T45	1		T15	1		T139	1
all_levels[30]	auto[1]	3	1			T69	1		T216	1		T222	1
all_levels[31]	auto[0]	34	1			T12	1		T35	1		T38	1
all_levels[31]	auto[1]	11	1			T38	2		T135	2		T149	1
all_levels[32]	auto[0]	29	1			T140	1		T141	2		T128	1
all_levels[32]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[33]	auto[0]	26	1			T13	1		T38	1		T142	1
all_levels[33]	auto[1]	5	1			T187	1		T195	1		T225	1
all_levels[34]	auto[0]	26	1			T35	1		T143	1		T144	1
all_levels[34]	auto[1]	2	1			T226	2		-	-		-	-
all_levels[35]	auto[0]	21	1			T145	1		T128	1		T71	1
all_levels[35]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[36]	auto[0]	18	1			T68	1		T146	1		T147	1
all_levels[36]	auto[1]	4	1			T147	1		T218	2		T228	1
all_levels[37]	auto[0]	24	1			T10	1		T148	1		T65	1
all_levels[38]	auto[0]	24	1			T11	1		T149	1		T150	1
all_levels[38]	auto[1]	4	1			T229	1		T230	1		T231	2
all_levels[39]	auto[0]	23	1			T11	1		T135	1		T151	1
all_levels[40]	auto[0]	21	1			T142	1		T71	1		T149	1
all_levels[41]	auto[0]	12	1			T32	1		T13	1		T51	1
all_levels[42]	auto[0]	13	1			T11	1		T35	1		T134	1
all_levels[43]	auto[0]	17	1			T152	1		T153	1		T154	1
all_levels[43]	auto[1]	2	1			T232	2		-	-		-	-
all_levels[44]	auto[0]	11	1			T132	1		T155	1		T65	1
all_levels[44]	auto[1]	2	1			T233	1		T234	1		-	-
all_levels[45]	auto[0]	11	1			T35	1		T109	1		T156	1
all_levels[45]	auto[1]	1	1			T156	1		-	-		-	-
all_levels[46]	auto[0]	10	1			T157	1		T158	1		T159	1
all_levels[46]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[47]	auto[0]	5	1			T70	1		T160	1		T161	1
all_levels[47]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[48]	auto[0]	12	1			T71	1		T162	1		T163	1
all_levels[48]	auto[1]	2	1			T236	1		T237	1		-	-
all_levels[49]	auto[0]	9	1			T145	1		T136	1		T164	1
all_levels[49]	auto[1]	2	1			T164	1		T238	1		-	-
all_levels[50]	auto[0]	9	1			T128	1		T70	1		T165	1
all_levels[50]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[51]	auto[0]	6	1			T136	1		T166	1		T165	1
all_levels[52]	auto[0]	12	1			T68	3		T167	1		T168	1
all_levels[52]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[53]	auto[0]	12	1			T109	1		T134	1		T70	1
all_levels[53]	auto[1]	2	1			T109	1		T134	1		-	-
all_levels[54]	auto[0]	10	1			T35	1		T169	1		T170	1
all_levels[54]	auto[1]	2	1			T240	1		T241	1		-	-
all_levels[55]	auto[0]	8	1			T125	1		T136	1		T167	1
all_levels[56]	auto[0]	7	1			T152	1		T136	1		T171	1
all_levels[56]	auto[1]	4	1			T242	2		T243	2		-	-
all_levels[57]	auto[0]	16	1			T13	2		T136	1		T172	1
all_levels[57]	auto[1]	2	1			T244	1		T245	1		-	-
all_levels[58]	auto[0]	4	1			T173	1		T174	1		T175	1
all_levels[58]	auto[1]	4	1			T173	2		T174	2		-	-
all_levels[59]	auto[0]	10	1			T13	1		T124	1		T140	1
all_levels[59]	auto[1]	2	1			T246	1		T247	1		-	-
all_levels[60]	auto[0]	4	1			T136	1		T176	1		T177	1
all_levels[61]	auto[0]	8	1			T120	2		T178	1		T179	1
all_levels[62]	auto[0]	8	1			T139	1		T142	1		T180	1
all_levels[62]	auto[1]	4	1			T139	3		T248	1		-	-
all_levels[63]	auto[0]	7	1			T158	1		T169	2		T181	1
all_levels[64]	auto[0]	95	1			T12	2		T13	3		T36	1
all_levels[64]	auto[1]	17	1			T152	1		T249	1		T214	2