Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1465 |
1 |
|
|
T11 |
2 |
|
T17 |
2 |
|
T12 |
17 |
all_levels[1] |
718 |
1 |
|
|
T15 |
2 |
|
T34 |
12 |
|
T14 |
15 |
all_levels[2] |
547 |
1 |
|
|
T11 |
1 |
|
T34 |
4 |
|
T118 |
15 |
all_levels[3] |
379 |
1 |
|
|
T125 |
5 |
|
T45 |
3 |
|
T13 |
16 |
all_levels[4] |
160 |
1 |
|
|
T35 |
1 |
|
T38 |
5 |
|
T126 |
6 |
all_levels[5] |
115 |
1 |
|
|
T1 |
5 |
|
T36 |
2 |
|
T65 |
1 |
all_levels[6] |
99 |
1 |
|
|
T37 |
8 |
|
T68 |
8 |
|
T127 |
2 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |