Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	109833	1			T1	51		T2	18		T4	15
all_pins[1]	109833	1			T1	51		T2	18		T4	15
all_pins[2]	109833	1			T1	51		T2	18		T4	15
all_pins[3]	109833	1			T1	51		T2	18		T4	15
all_pins[4]	109833	1			T1	51		T2	18		T4	15
all_pins[5]	109833	1			T1	51		T2	18		T4	15
all_pins[6]	109833	1			T1	51		T2	18		T4	15
all_pins[7]	109833	1			T1	51		T2	18		T4	15

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	847985	1			T1	396		T2	132		T4	107
values[0x1]	30679	1			T1	12		T2	12		T4	13
transitions[0x0=>0x1]	29480	1			T1	12		T2	12		T4	13
transitions[0x1=>0x0]	29033	1			T1	11		T2	11		T4	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85793	1			T1	48		T2	16		T4	2
all_pins[0]	values[0x1]	24040	1			T1	3		T2	2		T4	13
all_pins[0]	transitions[0x0=>0x1]	23349	1			T1	3		T2	2		T4	13
all_pins[0]	transitions[0x1=>0x0]	1030	1			T1	5		T11	3		T17	2
all_pins[1]	values[0x0]	108112	1			T1	46		T2	18		T4	15
all_pins[1]	values[0x1]	1721	1			T1	5		T11	3		T125	5
all_pins[1]	transitions[0x0=>0x1]	1613	1			T1	5		T11	2		T125	5
all_pins[1]	transitions[0x1=>0x0]	2567	1			T2	7		T5	6		T6	3
all_pins[2]	values[0x0]	107158	1			T1	51		T2	11		T4	15
all_pins[2]	values[0x1]	2675	1			T2	7		T5	6		T6	3
all_pins[2]	transitions[0x0=>0x1]	2614	1			T2	7		T5	6		T6	3
all_pins[2]	transitions[0x1=>0x0]	247	1			T12	3		T15	1		T13	3
all_pins[3]	values[0x0]	109525	1			T1	51		T2	18		T4	15
all_pins[3]	values[0x1]	308	1			T12	3		T15	1		T13	3
all_pins[3]	transitions[0x0=>0x1]	276	1			T12	3		T15	1		T13	3
all_pins[3]	transitions[0x1=>0x0]	403	1			T1	2		T13	5		T36	2
all_pins[4]	values[0x0]	109398	1			T1	49		T2	18		T4	15
all_pins[4]	values[0x1]	435	1			T1	2		T13	5		T36	3
all_pins[4]	transitions[0x0=>0x1]	388	1			T1	2		T13	4		T36	2
all_pins[4]	transitions[0x1=>0x0]	158	1			T1	2		T12	2		T15	1
all_pins[5]	values[0x0]	109628	1			T1	49		T2	18		T4	15
all_pins[5]	values[0x1]	205	1			T1	2		T12	2		T15	1
all_pins[5]	transitions[0x0=>0x1]	167	1			T1	2		T12	2		T15	1
all_pins[5]	transitions[0x1=>0x0]	886	1			T2	3		T5	4		T11	1
all_pins[6]	values[0x0]	108909	1			T1	51		T2	15		T4	15
all_pins[6]	values[0x1]	924	1			T2	3		T5	4		T11	1
all_pins[6]	transitions[0x0=>0x1]	867	1			T2	3		T5	4		T11	1
all_pins[6]	transitions[0x1=>0x0]	314	1			T12	2		T15	3		T13	10
all_pins[7]	values[0x0]	109462	1			T1	51		T2	18		T4	15
all_pins[7]	values[0x1]	371	1			T12	5		T15	3		T13	10
all_pins[7]	transitions[0x0=>0x1]	206	1			T12	2		T15	2		T13	10
all_pins[7]	transitions[0x1=>0x0]	23428	1			T1	2		T2	1		T4	13