Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7723638	1			T1	6		T2	227		T4	19
all_levels[1]	1643019	1			T2	8		T4	4		T5	64
all_levels[2]	434816	1			T2	14		T5	17		T6	1
all_levels[3]	219732	1			T2	6		T4	5		T5	17
all_levels[4]	218112	1			T5	14		T8	11		T17	7
all_levels[5]	335898	1			T5	26		T6	1		T8	8
all_levels[6]	203036	1			T4	2		T5	18		T6	1
all_levels[7]	194437	1			T1	11		T5	21		T8	8
all_levels[8]	458724	1			T1	541		T2	3		T5	12
all_levels[9]	232903	1			T8	8		T17	1		T43	10
all_levels[10]	433347	1			T8	7		T17	1		T43	8
all_levels[11]	337097	1			T2	6		T4	2		T8	11
all_levels[12]	186318	1			T2	3		T4	1		T6	1
all_levels[13]	185778	1			T2	4		T8	8		T17	2
all_levels[14]	250519	1			T2	5		T8	8		T10	1
all_levels[15]	199373	1			T6	1		T8	8		T10	1
all_levels[16]	427956	1			T2	23		T8	8		T17	3
all_levels[17]	518758	1			T2	8		T8	10		T10	1
all_levels[18]	247129	1			T2	1		T8	7		T10	3
all_levels[19]	168898	1			T8	8		T10	3		T125	2
all_levels[20]	317070	1			T2	1		T8	10		T17	3
all_levels[21]	165879	1			T8	11		T43	8		T12	1375
all_levels[22]	193963	1			T2	64		T8	6		T17	7
all_levels[23]	163524	1			T2	12		T6	1		T8	9
all_levels[24]	239298	1			T8	13		T17	1		T43	11
all_levels[25]	175842	1			T8	13		T11	9		T17	3
all_levels[26]	293779	1			T8	11		T17	3		T43	7
all_levels[27]	184857	1			T2	67		T6	1		T8	9
all_levels[28]	236838	1			T2	2		T8	10		T17	2
all_levels[29]	199571	1			T8	12		T17	1		T43	7
all_levels[30]	285048	1			T8	8		T11	5		T17	3
all_levels[31]	529214	1			T8	396		T10	1		T17	5
all_levels[32]	12257817	1			T8	42277		T10	13		T11	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29858062

1

T1

542

T2

453

T4

33

auto[1]

4126

1

T1

16

T2

1

T6

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7721552	1			T2	227		T4	19		T5	130
all_levels[0]	auto[1]	2086	1			T1	6		T6	3		T11	2
all_levels[1]	auto[0]	1642658	1			T2	8		T4	4		T5	64
all_levels[1]	auto[1]	361	1			T131	2		T269	3		T122	1
all_levels[2]	auto[0]	434776	1			T2	14		T5	17		T6	1
all_levels[2]	auto[1]	40	1			T152	1		T273	1		T66	1
all_levels[3]	auto[0]	219623	1			T2	6		T4	5		T5	17
all_levels[3]	auto[1]	109	1			T132	1		T264	1		T51	2
all_levels[4]	auto[0]	218072	1			T5	14		T8	11		T17	7
all_levels[4]	auto[1]	40	1			T131	1		T126	1		T214	3
all_levels[5]	auto[0]	335883	1			T5	26		T6	1		T8	8
all_levels[5]	auto[1]	15	1			T269	1		T124	1		T72	2
all_levels[6]	auto[0]	203012	1			T4	2		T5	18		T6	1
all_levels[6]	auto[1]	24	1			T139	1		T200	1		T154	3
all_levels[7]	auto[0]	194251	1			T1	1		T5	21		T8	8
all_levels[7]	auto[1]	186	1			T1	10		T12	1		T299	6
all_levels[8]	auto[0]	458687	1			T1	541		T2	3		T5	12
all_levels[8]	auto[1]	37	1			T66	1		T324	1		T325	1
all_levels[9]	auto[0]	232873	1			T8	8		T17	1		T43	10
all_levels[9]	auto[1]	30	1			T178	1		T152	3		T65	1
all_levels[10]	auto[0]	433322	1			T8	7		T17	1		T43	8
all_levels[10]	auto[1]	25	1			T109	1		T200	1		T199	2
all_levels[11]	auto[0]	337071	1			T2	6		T4	2		T8	11
all_levels[11]	auto[1]	26	1			T132	1		T186	1		T278	2
all_levels[12]	auto[0]	186284	1			T2	3		T4	1		T6	1
all_levels[12]	auto[1]	34	1			T112	2		T135	1		T326	1
all_levels[13]	auto[0]	185756	1			T2	4		T8	8		T17	2
all_levels[13]	auto[1]	22	1			T264	1		T302	3		T327	1
all_levels[14]	auto[0]	250484	1			T2	5		T8	8		T10	1
all_levels[14]	auto[1]	35	1			T278	4		T328	1		T147	1
all_levels[15]	auto[0]	199176	1			T6	1		T8	8		T10	1
all_levels[15]	auto[1]	197	1			T273	1		T167	3		T329	16
all_levels[16]	auto[0]	427928	1			T2	23		T8	8		T17	3
all_levels[16]	auto[1]	28	1			T53	1		T152	1		T185	1
all_levels[17]	auto[0]	518744	1			T2	8		T8	10		T10	1
all_levels[17]	auto[1]	14	1			T261	3		T203	1		T57	1
all_levels[18]	auto[0]	247108	1			T2	1		T8	7		T10	3
all_levels[18]	auto[1]	21	1			T300	1		T330	2		T331	3
all_levels[19]	auto[0]	168881	1			T8	8		T10	3		T125	2
all_levels[19]	auto[1]	17	1			T250	1		T134	2		T66	3
all_levels[20]	auto[0]	317054	1			T2	1		T8	10		T17	3
all_levels[20]	auto[1]	16	1			T293	2		T146	2		T151	2
all_levels[21]	auto[0]	165857	1			T8	11		T43	8		T12	1375
all_levels[21]	auto[1]	22	1			T109	2		T210	4		T70	1
all_levels[22]	auto[0]	193936	1			T2	64		T8	6		T17	7
all_levels[22]	auto[1]	27	1			T184	2		T69	2		T332	1
all_levels[23]	auto[0]	163510	1			T2	11		T6	1		T8	9
all_levels[23]	auto[1]	14	1			T2	1		T126	1		T70	1
all_levels[24]	auto[0]	239238	1			T8	13		T17	1		T43	11
all_levels[24]	auto[1]	60	1			T132	2		T191	1		T325	1
all_levels[25]	auto[0]	175828	1			T8	13		T11	6		T17	3
all_levels[25]	auto[1]	14	1			T11	3		T327	1		T203	1
all_levels[26]	auto[0]	293761	1			T8	11		T17	3		T43	7
all_levels[26]	auto[1]	18	1			T255	2		T185	2		T72	1
all_levels[27]	auto[0]	184843	1			T2	67		T6	1		T8	9
all_levels[27]	auto[1]	14	1			T293	1		T327	1		T161	1
all_levels[28]	auto[0]	236813	1			T2	2		T8	10		T17	2
all_levels[28]	auto[1]	25	1			T53	1		T109	1		T262	1
all_levels[29]	auto[0]	199554	1			T8	12		T17	1		T43	7
all_levels[29]	auto[1]	17	1			T109	2		T293	2		T195	1
all_levels[30]	auto[0]	285032	1			T8	8		T11	5		T17	3
all_levels[30]	auto[1]	16	1			T122	3		T333	1		T195	1
all_levels[31]	auto[0]	529186	1			T8	396		T10	1		T17	5
all_levels[31]	auto[1]	28	1			T132	1		T133	2		T126	2
all_levels[32]	auto[0]	12257309	1			T8	42276		T10	13		T11	1
all_levels[32]	auto[1]	508	1			T8	1		T11	2		T125	1