Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	737	1			T12	4		T15	4		T13	4
all_values[1]	737	1			T12	4		T15	4		T13	4
all_values[2]	737	1			T12	4		T15	4		T13	4
all_values[3]	737	1			T12	4		T15	4		T13	4
all_values[4]	737	1			T12	4		T15	4		T13	4
all_values[5]	737	1			T12	4		T15	4		T13	4
all_values[6]	737	1			T12	4		T15	4		T13	4
all_values[7]	737	1			T12	4		T15	4		T13	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3215

1

T12

14

T15

16

T13

23

auto[1]

2681

1

T12

18

T15

16

T13

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2204

1

T12

8

T15

12

T13

16

auto[1]

3692

1

T12

24

T15

20

T13

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3515

1

T12

13

T15

18

T13

23

auto[1]

2381

1

T12

19

T15

14

T13

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	243	1			T12	2		T13	3		T36	2
all_values[0]	auto[0]	auto[1]	auto[1]	202	1			T15	2		T124	1		T128	9
all_values[0]	auto[1]	auto[0]	auto[1]	143	1			T15	2		T13	1		T129	2
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T12	2		T36	2		T124	1
all_values[1]	auto[0]	auto[0]	auto[0]	241	1			T13	2		T36	2		T129	1
all_values[1]	auto[0]	auto[1]	auto[0]	199	1			T12	1		T15	3		T13	1
all_values[1]	auto[1]	auto[0]	auto[1]	169	1			T15	1		T36	1		T124	2
all_values[1]	auto[1]	auto[1]	auto[1]	128	1			T12	3		T13	1		T36	1
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T12	1		T13	2		T36	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T15	1		T36	1		T124	1
all_values[2]	auto[0]	auto[1]	auto[0]	138	1			T13	2		T129	3		T124	1
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T124	1		T128	1		T55	2
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T12	3		T15	3		T36	2
all_values[2]	auto[1]	auto[1]	auto[1]	130	1			T124	2		T128	2		T55	4
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T15	2		T13	2		T124	4
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T15	1		T130	1		T55	1
all_values[3]	auto[0]	auto[1]	auto[0]	144	1			T12	1		T36	2		T129	2
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T12	1		T13	1		T124	1
all_values[3]	auto[1]	auto[0]	auto[1]	160	1			T13	1		T129	2		T124	1
all_values[3]	auto[1]	auto[1]	auto[1]	127	1			T12	2		T15	1		T36	2
all_values[4]	auto[0]	auto[0]	auto[0]	181	1			T15	1		T13	2		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T128	3		T55	3		T114	1
all_values[4]	auto[0]	auto[1]	auto[0]	140	1			T12	1		T15	2		T13	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T36	2		T130	1		T128	1
all_values[4]	auto[1]	auto[0]	auto[1]	172	1			T15	1		T13	1		T124	2
all_values[4]	auto[1]	auto[1]	auto[1]	118	1			T12	3		T36	1		T129	2
all_values[5]	auto[0]	auto[0]	auto[0]	137	1			T12	2		T13	1		T124	3
all_values[5]	auto[0]	auto[0]	auto[1]	92	1			T13	1		T129	1		T124	1
all_values[5]	auto[0]	auto[1]	auto[0]	135	1			T15	1		T13	1		T36	1
all_values[5]	auto[0]	auto[1]	auto[1]	56	1			T12	1		T15	1		T36	1
all_values[5]	auto[1]	auto[0]	auto[1]	180	1			T15	1		T129	2		T124	2
all_values[5]	auto[1]	auto[1]	auto[1]	137	1			T12	1		T15	1		T13	1
all_values[6]	auto[0]	auto[0]	auto[0]	165	1			T12	2		T13	1		T36	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T36	1		T129	1		T124	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T15	2		T36	1		T124	4
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T13	1		T129	1		T130	1
all_values[6]	auto[1]	auto[0]	auto[1]	153	1			T12	2		T15	2		T13	2
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T36	1		T124	1		T130	1
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T13	1		T36	1		T129	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T12	1		T13	1		T128	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T15	1		T36	1		T129	2
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T15	1		T36	1		T130	1
all_values[7]	auto[1]	auto[0]	auto[1]	183	1			T12	1		T15	1		T13	2
all_values[7]	auto[1]	auto[1]	auto[1]	127	1			T12	2		T15	1		T36	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal