Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.27 99.27 97.95 100.00 98.80 100.00 99.59


Total test records in report: 1320
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T1255 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3379273328 Apr 16 02:18:35 PM PDT 24 Apr 16 02:18:37 PM PDT 24 240538642 ps
T1256 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2063586513 Apr 16 02:18:35 PM PDT 24 Apr 16 02:18:36 PM PDT 24 21589498 ps
T1257 /workspace/coverage/cover_reg_top/39.uart_intr_test.1462805160 Apr 16 02:19:14 PM PDT 24 Apr 16 02:19:17 PM PDT 24 15136302 ps
T1258 /workspace/coverage/cover_reg_top/16.uart_intr_test.2600393642 Apr 16 02:19:06 PM PDT 24 Apr 16 02:19:10 PM PDT 24 38103490 ps
T80 /workspace/coverage/cover_reg_top/15.uart_csr_rw.3959964987 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 14190391 ps
T1259 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3911237509 Apr 16 02:18:38 PM PDT 24 Apr 16 02:18:39 PM PDT 24 43863187 ps
T1260 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3778805285 Apr 16 02:19:06 PM PDT 24 Apr 16 02:19:10 PM PDT 24 94360921 ps
T81 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2600619774 Apr 16 02:18:46 PM PDT 24 Apr 16 02:18:48 PM PDT 24 17530747 ps
T1261 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1633787330 Apr 16 02:19:13 PM PDT 24 Apr 16 02:19:16 PM PDT 24 30971860 ps
T1262 /workspace/coverage/cover_reg_top/6.uart_intr_test.4128321211 Apr 16 02:18:47 PM PDT 24 Apr 16 02:18:49 PM PDT 24 14032178 ps
T1263 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3621003336 Apr 16 02:18:40 PM PDT 24 Apr 16 02:18:42 PM PDT 24 191378085 ps
T1264 /workspace/coverage/cover_reg_top/15.uart_intr_test.153733661 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 14951570 ps
T1265 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.674644856 Apr 16 02:19:10 PM PDT 24 Apr 16 02:19:14 PM PDT 24 35433268 ps
T1266 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.810560146 Apr 16 02:18:42 PM PDT 24 Apr 16 02:18:44 PM PDT 24 39715916 ps
T1267 /workspace/coverage/cover_reg_top/46.uart_intr_test.3201684441 Apr 16 02:19:17 PM PDT 24 Apr 16 02:19:19 PM PDT 24 11383062 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4241585408 Apr 16 02:18:48 PM PDT 24 Apr 16 02:18:50 PM PDT 24 78738726 ps
T1269 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3244491639 Apr 16 02:18:32 PM PDT 24 Apr 16 02:18:34 PM PDT 24 46574577 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2219179699 Apr 16 02:18:37 PM PDT 24 Apr 16 02:18:38 PM PDT 24 13344977 ps
T1271 /workspace/coverage/cover_reg_top/34.uart_intr_test.600490709 Apr 16 02:19:12 PM PDT 24 Apr 16 02:19:16 PM PDT 24 14275151 ps
T1272 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4103417677 Apr 16 02:18:32 PM PDT 24 Apr 16 02:18:33 PM PDT 24 21461249 ps
T1273 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.890637057 Apr 16 02:19:04 PM PDT 24 Apr 16 02:19:07 PM PDT 24 84322536 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.775881694 Apr 16 02:19:11 PM PDT 24 Apr 16 02:19:15 PM PDT 24 70964781 ps
T1275 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3468715421 Apr 16 02:18:37 PM PDT 24 Apr 16 02:18:38 PM PDT 24 17455721 ps
T1276 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2853940734 Apr 16 02:18:54 PM PDT 24 Apr 16 02:18:56 PM PDT 24 18802086 ps
T1277 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1448210747 Apr 16 02:19:07 PM PDT 24 Apr 16 02:19:11 PM PDT 24 384587285 ps
T1278 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3854352991 Apr 16 02:19:06 PM PDT 24 Apr 16 02:19:10 PM PDT 24 40535416 ps
T1279 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1308034944 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 63604068 ps
T1280 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2259835443 Apr 16 02:18:37 PM PDT 24 Apr 16 02:18:39 PM PDT 24 66013082 ps
T1281 /workspace/coverage/cover_reg_top/19.uart_intr_test.446099964 Apr 16 02:19:10 PM PDT 24 Apr 16 02:19:14 PM PDT 24 34812840 ps
T1282 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3793153103 Apr 16 02:18:43 PM PDT 24 Apr 16 02:18:45 PM PDT 24 16022064 ps
T1283 /workspace/coverage/cover_reg_top/26.uart_intr_test.2590294 Apr 16 02:19:11 PM PDT 24 Apr 16 02:19:15 PM PDT 24 42491178 ps
T1284 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2811517143 Apr 16 02:19:07 PM PDT 24 Apr 16 02:19:11 PM PDT 24 17596530 ps
T1285 /workspace/coverage/cover_reg_top/21.uart_intr_test.4161691119 Apr 16 02:19:12 PM PDT 24 Apr 16 02:19:16 PM PDT 24 15430205 ps
T97 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1461751592 Apr 16 02:19:11 PM PDT 24 Apr 16 02:19:15 PM PDT 24 555477275 ps
T1286 /workspace/coverage/cover_reg_top/12.uart_csr_rw.338750543 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:01 PM PDT 24 43972846 ps
T1287 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2030368118 Apr 16 02:18:58 PM PDT 24 Apr 16 02:19:00 PM PDT 24 42137644 ps
T1288 /workspace/coverage/cover_reg_top/37.uart_intr_test.844327794 Apr 16 02:19:13 PM PDT 24 Apr 16 02:19:16 PM PDT 24 13150923 ps
T1289 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2848962928 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 52853306 ps
T82 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.896610476 Apr 16 02:18:41 PM PDT 24 Apr 16 02:18:43 PM PDT 24 18735560 ps
T1290 /workspace/coverage/cover_reg_top/30.uart_intr_test.3363388938 Apr 16 02:19:12 PM PDT 24 Apr 16 02:19:16 PM PDT 24 129365721 ps
T1291 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3134125168 Apr 16 02:18:58 PM PDT 24 Apr 16 02:19:01 PM PDT 24 82235751 ps
T1292 /workspace/coverage/cover_reg_top/33.uart_intr_test.1176236107 Apr 16 02:19:12 PM PDT 24 Apr 16 02:19:16 PM PDT 24 13319287 ps
T1293 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3650072259 Apr 16 02:18:54 PM PDT 24 Apr 16 02:18:56 PM PDT 24 82458543 ps
T1294 /workspace/coverage/cover_reg_top/32.uart_intr_test.2433862678 Apr 16 02:19:14 PM PDT 24 Apr 16 02:19:18 PM PDT 24 16144352 ps
T1295 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.887836194 Apr 16 02:18:33 PM PDT 24 Apr 16 02:18:34 PM PDT 24 64126331 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1856634141 Apr 16 02:19:06 PM PDT 24 Apr 16 02:19:11 PM PDT 24 169032508 ps
T1297 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1075076658 Apr 16 02:19:10 PM PDT 24 Apr 16 02:19:14 PM PDT 24 71448590 ps
T1298 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2761381293 Apr 16 02:18:54 PM PDT 24 Apr 16 02:18:56 PM PDT 24 30311058 ps
T1299 /workspace/coverage/cover_reg_top/44.uart_intr_test.1219706895 Apr 16 02:19:16 PM PDT 24 Apr 16 02:19:18 PM PDT 24 41141225 ps
T1300 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2814104281 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 329234526 ps
T1301 /workspace/coverage/cover_reg_top/11.uart_intr_test.2770222213 Apr 16 02:19:00 PM PDT 24 Apr 16 02:19:03 PM PDT 24 17391965 ps
T1302 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3498213145 Apr 16 02:19:06 PM PDT 24 Apr 16 02:19:09 PM PDT 24 97667323 ps
T1303 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3500143784 Apr 16 02:18:58 PM PDT 24 Apr 16 02:19:00 PM PDT 24 18753951 ps
T1304 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2553645061 Apr 16 02:18:49 PM PDT 24 Apr 16 02:18:51 PM PDT 24 52045166 ps
T1305 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3249116630 Apr 16 02:18:41 PM PDT 24 Apr 16 02:18:43 PM PDT 24 47531562 ps
T1306 /workspace/coverage/cover_reg_top/48.uart_intr_test.2685293500 Apr 16 02:19:15 PM PDT 24 Apr 16 02:19:18 PM PDT 24 13848454 ps
T1307 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3896964058 Apr 16 02:18:53 PM PDT 24 Apr 16 02:18:55 PM PDT 24 36886204 ps
T1308 /workspace/coverage/cover_reg_top/43.uart_intr_test.3124988962 Apr 16 02:19:13 PM PDT 24 Apr 16 02:19:17 PM PDT 24 34576852 ps
T1309 /workspace/coverage/cover_reg_top/20.uart_intr_test.1480179616 Apr 16 02:19:11 PM PDT 24 Apr 16 02:19:15 PM PDT 24 52687703 ps
T1310 /workspace/coverage/cover_reg_top/38.uart_intr_test.3852169712 Apr 16 02:19:13 PM PDT 24 Apr 16 02:19:17 PM PDT 24 14721551 ps
T1311 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3787822487 Apr 16 02:18:59 PM PDT 24 Apr 16 02:19:02 PM PDT 24 60833573 ps
T1312 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3735697111 Apr 16 02:18:47 PM PDT 24 Apr 16 02:18:49 PM PDT 24 21333606 ps
T1313 /workspace/coverage/cover_reg_top/8.uart_tl_errors.983025358 Apr 16 02:18:54 PM PDT 24 Apr 16 02:18:57 PM PDT 24 194693448 ps
T1314 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4020887370 Apr 16 02:19:11 PM PDT 24 Apr 16 02:19:14 PM PDT 24 113186527 ps
T1315 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2415091292 Apr 16 02:18:54 PM PDT 24 Apr 16 02:18:57 PM PDT 24 50689447 ps
T1316 /workspace/coverage/cover_reg_top/13.uart_intr_test.3420683775 Apr 16 02:18:58 PM PDT 24 Apr 16 02:18:59 PM PDT 24 13267842 ps
T1317 /workspace/coverage/cover_reg_top/5.uart_intr_test.1053227589 Apr 16 02:18:49 PM PDT 24 Apr 16 02:18:51 PM PDT 24 40213014 ps
T1318 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.902231844 Apr 16 02:18:42 PM PDT 24 Apr 16 02:18:45 PM PDT 24 240241128 ps
T1319 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2789335688 Apr 16 02:18:40 PM PDT 24 Apr 16 02:18:41 PM PDT 24 30347398 ps
T1320 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2515823497 Apr 16 02:18:58 PM PDT 24 Apr 16 02:19:01 PM PDT 24 14132793 ps

Test location /workspace/coverage/default/16.uart_fifo_full.2563723600
Short name T4
Test name
Test status
Simulation time 29632214004 ps
CPU time 12.97 seconds
Started Apr 16 02:39:25 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 200836 kb
Host smart-7b732e59-18df-4d26-97d0-04ecbafe930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563723600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2563723600
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3708562154
Short name T13
Test name
Test status
Simulation time 1264106486999 ps
CPU time 519.18 seconds
Started Apr 16 02:40:42 PM PDT 24
Finished Apr 16 02:49:22 PM PDT 24
Peak memory 217556 kb
Host smart-ac818162-06f1-4342-9751-49af7a160103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708562154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3708562154
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1808996862
Short name T37
Test name
Test status
Simulation time 135053093759 ps
CPU time 637.27 seconds
Started Apr 16 02:41:47 PM PDT 24
Finished Apr 16 02:52:26 PM PDT 24
Peak memory 217544 kb
Host smart-2f4bdbec-ab43-4c76-9f3a-e6591f4d977b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808996862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1808996862
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.122614920
Short name T68
Test name
Test status
Simulation time 1202900399065 ps
CPU time 1037.8 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:58:34 PM PDT 24
Peak memory 225696 kb
Host smart-7bd8637c-3055-40b8-bbf9-58ba06219a10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122614920 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.122614920
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.3210148226
Short name T12
Test name
Test status
Simulation time 199925547370 ps
CPU time 252.93 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:44:46 PM PDT 24
Peak memory 217468 kb
Host smart-2bf43b41-7409-4de4-b231-0a38b0c35e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210148226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3210148226
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all.786938034
Short name T124
Test name
Test status
Simulation time 295178648553 ps
CPU time 684.04 seconds
Started Apr 16 02:39:25 PM PDT 24
Finished Apr 16 02:50:51 PM PDT 24
Peak memory 200908 kb
Host smart-fe6a1b77-f3f1-47b2-9c7e-923c2590c330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786938034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.786938034
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3260357134
Short name T42
Test name
Test status
Simulation time 104086155268 ps
CPU time 199.79 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:43:22 PM PDT 24
Peak memory 200860 kb
Host smart-8315d0d3-9eaf-46b3-a179-4d3cd3c78084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260357134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3260357134
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_fifo_full.72356674
Short name T148
Test name
Test status
Simulation time 45899626177 ps
CPU time 56.83 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:40:15 PM PDT 24
Peak memory 200908 kb
Host smart-72d2c985-f712-4e6a-954b-424a1a89662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72356674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.72356674
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2775197571
Short name T55
Test name
Test status
Simulation time 193906986808 ps
CPU time 745.35 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:52:23 PM PDT 24
Peak memory 216744 kb
Host smart-796b647b-5868-4ab2-9c07-aca684de6927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775197571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2775197571
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3167761193
Short name T29
Test name
Test status
Simulation time 166451958 ps
CPU time 0.79 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:08 PM PDT 24
Peak memory 219016 kb
Host smart-866f149a-f1a0-4d11-81a1-357facc3c8f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167761193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3167761193
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2988418008
Short name T35
Test name
Test status
Simulation time 111161662138 ps
CPU time 581.27 seconds
Started Apr 16 02:39:32 PM PDT 24
Finished Apr 16 02:49:14 PM PDT 24
Peak memory 225768 kb
Host smart-5c9c338f-cfac-4f4b-bf7f-afc39b6c3611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988418008 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2988418008
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.932614036
Short name T11
Test name
Test status
Simulation time 65558280254 ps
CPU time 28.52 seconds
Started Apr 16 02:43:23 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200836 kb
Host smart-e78b5a5f-5cbc-42e1-82d4-71728e31fbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932614036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.932614036
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2054765575
Short name T38
Test name
Test status
Simulation time 148354065302 ps
CPU time 988.42 seconds
Started Apr 16 02:39:02 PM PDT 24
Finished Apr 16 02:55:31 PM PDT 24
Peak memory 217380 kb
Host smart-2f24e92c-098b-42af-a044-e846664d0d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054765575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2054765575
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1166674487
Short name T34
Test name
Test status
Simulation time 79725787594 ps
CPU time 305.78 seconds
Started Apr 16 02:40:54 PM PDT 24
Finished Apr 16 02:46:01 PM PDT 24
Peak memory 217520 kb
Host smart-d085b9a3-e3ab-40da-a941-fd0051be5402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166674487 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1166674487
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.400307469
Short name T70
Test name
Test status
Simulation time 742349561678 ps
CPU time 1056.7 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:56:57 PM PDT 24
Peak memory 217388 kb
Host smart-b459a40d-a17b-4517-a8ab-b81158152dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400307469 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.400307469
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.162377448
Short name T99
Test name
Test status
Simulation time 273039591 ps
CPU time 1.32 seconds
Started Apr 16 02:18:56 PM PDT 24
Finished Apr 16 02:18:59 PM PDT 24
Peak memory 199336 kb
Host smart-d07c60ca-7e41-4903-9960-a6a8f0f14ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162377448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.162377448
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4183868940
Short name T306
Test name
Test status
Simulation time 128840792232 ps
CPU time 216.4 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:42:56 PM PDT 24
Peak memory 200916 kb
Host smart-c428ff1e-8694-4b77-aab4-8e8bfd1c1c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183868940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4183868940
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_alert_test.759754056
Short name T340
Test name
Test status
Simulation time 33955373 ps
CPU time 0.55 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 196228 kb
Host smart-2d52dd0b-3545-4531-a56a-276178e5f41e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759754056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.759754056
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1819628174
Short name T136
Test name
Test status
Simulation time 177511706081 ps
CPU time 169.48 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 200912 kb
Host smart-15249cc8-2c21-4a10-8c6c-20d473af3b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819628174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1819628174
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.605867721
Short name T76
Test name
Test status
Simulation time 87037902 ps
CPU time 0.57 seconds
Started Apr 16 02:18:36 PM PDT 24
Finished Apr 16 02:18:38 PM PDT 24
Peak memory 195448 kb
Host smart-848c5505-699a-4336-9183-f37b36c2bbad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605867721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.605867721
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.4214223117
Short name T128
Test name
Test status
Simulation time 229254549962 ps
CPU time 426.59 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:47:03 PM PDT 24
Peak memory 217548 kb
Host smart-b0a6fce8-b769-4d4e-9ef7-db4a07fdcb73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214223117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.4214223117
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1665072362
Short name T139
Test name
Test status
Simulation time 122560797876 ps
CPU time 54.11 seconds
Started Apr 16 02:42:10 PM PDT 24
Finished Apr 16 02:43:05 PM PDT 24
Peak memory 200868 kb
Host smart-9cc0c9c5-ae5b-4f75-8d22-ecd4775aae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665072362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1665072362
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_noise_filter.342427563
Short name T2
Test name
Test status
Simulation time 56502446961 ps
CPU time 99.45 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:41:45 PM PDT 24
Peak memory 200204 kb
Host smart-399a4eaa-d3bf-43c1-8cb6-64bb7b59d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342427563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.342427563
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1860271029
Short name T154
Test name
Test status
Simulation time 40039451026 ps
CPU time 68.51 seconds
Started Apr 16 02:42:53 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200860 kb
Host smart-5e587d9a-167f-4719-bf55-b5289e5a8cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860271029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1860271029
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.4131406419
Short name T132
Test name
Test status
Simulation time 22051614644 ps
CPU time 35.1 seconds
Started Apr 16 02:43:12 PM PDT 24
Finished Apr 16 02:43:48 PM PDT 24
Peak memory 200808 kb
Host smart-6311a5fc-4c54-480b-87d5-2c3e05abb178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131406419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.4131406419
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3802976002
Short name T179
Test name
Test status
Simulation time 131078674842 ps
CPU time 489.53 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:50:07 PM PDT 24
Peak memory 225760 kb
Host smart-13f3ae1a-fb08-446b-92ea-9f096b4b12e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802976002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3802976002
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3078480746
Short name T167
Test name
Test status
Simulation time 196709738671 ps
CPU time 82.61 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:43:21 PM PDT 24
Peak memory 200844 kb
Host smart-98e00125-0ffd-4bd7-b28b-02495a2c9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078480746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3078480746
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.4272085453
Short name T53
Test name
Test status
Simulation time 62926373287 ps
CPU time 142.26 seconds
Started Apr 16 02:42:18 PM PDT 24
Finished Apr 16 02:44:41 PM PDT 24
Peak memory 200856 kb
Host smart-c3abdb2b-5d17-4326-99b0-214c08b6c07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272085453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4272085453
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1155549073
Short name T96
Test name
Test status
Simulation time 4492113198 ps
CPU time 1.44 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 199984 kb
Host smart-7901aea4-ec3b-4045-92be-1578817e0902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155549073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1155549073
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3418275282
Short name T129
Test name
Test status
Simulation time 121165793725 ps
CPU time 880.08 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:54:06 PM PDT 24
Peak memory 225768 kb
Host smart-8598a582-d23f-44ed-9981-7ee8d3572b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418275282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3418275282
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.3429529230
Short name T158
Test name
Test status
Simulation time 288333816375 ps
CPU time 572.27 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:49:18 PM PDT 24
Peak memory 200844 kb
Host smart-d1dcb3c5-7170-42c3-b83d-96dac11ebb31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429529230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3429529230
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all.3620825043
Short name T153
Test name
Test status
Simulation time 173879437235 ps
CPU time 111.38 seconds
Started Apr 16 02:41:31 PM PDT 24
Finished Apr 16 02:43:23 PM PDT 24
Peak memory 200852 kb
Host smart-ed537ec8-4b4f-4d51-996b-9ed26481546b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620825043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3620825043
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.935186966
Short name T202
Test name
Test status
Simulation time 151479893655 ps
CPU time 63.47 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:42:40 PM PDT 24
Peak memory 200880 kb
Host smart-b0a77648-1eac-4ac2-8e64-24dce379e9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935186966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.935186966
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3984466179
Short name T93
Test name
Test status
Simulation time 86808202 ps
CPU time 1.32 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 199492 kb
Host smart-d88706b7-2ebe-40f3-b736-24880b5ec9f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984466179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3984466179
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1790839727
Short name T308
Test name
Test status
Simulation time 211726771703 ps
CPU time 180.52 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:42:06 PM PDT 24
Peak memory 200852 kb
Host smart-e3844cc1-0e47-418f-8c71-f35fc454ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790839727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1790839727
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3981063087
Short name T133
Test name
Test status
Simulation time 180045408499 ps
CPU time 311.81 seconds
Started Apr 16 02:43:03 PM PDT 24
Finished Apr 16 02:48:15 PM PDT 24
Peak memory 200856 kb
Host smart-8e16b04c-cfb1-46bc-83a9-df446bf8eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981063087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3981063087
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1795999729
Short name T173
Test name
Test status
Simulation time 11151321541 ps
CPU time 16.23 seconds
Started Apr 16 02:43:06 PM PDT 24
Finished Apr 16 02:43:23 PM PDT 24
Peak memory 200916 kb
Host smart-a09b5d7b-03a2-4b2d-ae24-9632c3690104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795999729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1795999729
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all.2687635481
Short name T565
Test name
Test status
Simulation time 227820705461 ps
CPU time 375.34 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:47:05 PM PDT 24
Peak memory 209276 kb
Host smart-ad9f02e6-3fc2-4a80-91f0-7b5efdca33a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687635481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2687635481
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.161100089
Short name T134
Test name
Test status
Simulation time 114231830752 ps
CPU time 184.69 seconds
Started Apr 16 02:42:59 PM PDT 24
Finished Apr 16 02:46:04 PM PDT 24
Peak memory 200884 kb
Host smart-d1e50139-a0ed-413e-b50f-2b9007767d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161100089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.161100089
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.123007137
Short name T182
Test name
Test status
Simulation time 59865492217 ps
CPU time 95.6 seconds
Started Apr 16 02:42:16 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200856 kb
Host smart-e979a896-c588-451a-b578-a41b21e207fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123007137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.123007137
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1921817626
Short name T411
Test name
Test status
Simulation time 94251407281 ps
CPU time 137.32 seconds
Started Apr 16 02:42:38 PM PDT 24
Finished Apr 16 02:44:56 PM PDT 24
Peak memory 200852 kb
Host smart-e4489939-8560-46d7-bdd6-fe118a1c9d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921817626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1921817626
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.2678799824
Short name T497
Test name
Test status
Simulation time 208444674252 ps
CPU time 236.69 seconds
Started Apr 16 02:39:50 PM PDT 24
Finished Apr 16 02:43:48 PM PDT 24
Peak memory 200876 kb
Host smart-033cf4d0-7336-48ed-8376-a125d90a5675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678799824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2678799824
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.886610340
Short name T819
Test name
Test status
Simulation time 117189377469 ps
CPU time 105.84 seconds
Started Apr 16 02:43:15 PM PDT 24
Finished Apr 16 02:45:01 PM PDT 24
Peak memory 200764 kb
Host smart-e904628d-4a45-49fe-8e3e-ace25eff4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886610340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.886610340
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_perf.3022358242
Short name T275
Test name
Test status
Simulation time 23108331171 ps
CPU time 591.36 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:49:03 PM PDT 24
Peak memory 200932 kb
Host smart-5b7c4c43-fa76-48c8-89d5-211172787ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022358242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3022358242
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4238024882
Short name T218
Test name
Test status
Simulation time 123253981202 ps
CPU time 37.03 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:42:50 PM PDT 24
Peak memory 200828 kb
Host smart-acaef75a-9388-48ff-ab58-6b42502aea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238024882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4238024882
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1899282056
Short name T72
Test name
Test status
Simulation time 36241535490 ps
CPU time 58.79 seconds
Started Apr 16 02:42:10 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200828 kb
Host smart-6be53eb0-16f4-472c-b993-d7c0aa317d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899282056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1899282056
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2872552451
Short name T230
Test name
Test status
Simulation time 192596953942 ps
CPU time 323.73 seconds
Started Apr 16 02:42:43 PM PDT 24
Finished Apr 16 02:48:08 PM PDT 24
Peak memory 200920 kb
Host smart-bfdd87ab-a099-412f-b50e-4bcd940a12f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872552451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2872552451
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3385346206
Short name T233
Test name
Test status
Simulation time 128813550593 ps
CPU time 75.31 seconds
Started Apr 16 02:42:46 PM PDT 24
Finished Apr 16 02:44:02 PM PDT 24
Peak memory 200868 kb
Host smart-d49a3902-1a73-4e9f-9c2a-aaa255b1147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385346206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3385346206
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2714535295
Short name T69
Test name
Test status
Simulation time 115680096586 ps
CPU time 107.71 seconds
Started Apr 16 02:42:49 PM PDT 24
Finished Apr 16 02:44:37 PM PDT 24
Peak memory 200848 kb
Host smart-82c81018-cd04-483f-92e1-5db940a1ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714535295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2714535295
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.4097724175
Short name T156
Test name
Test status
Simulation time 79351771017 ps
CPU time 753.31 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:52:48 PM PDT 24
Peak memory 200912 kb
Host smart-40718902-e07e-4e8c-9a80-4dc083f3315a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097724175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.4097724175
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1382022261
Short name T245
Test name
Test status
Simulation time 58590672244 ps
CPU time 160.71 seconds
Started Apr 16 02:42:02 PM PDT 24
Finished Apr 16 02:44:43 PM PDT 24
Peak memory 200880 kb
Host smart-f822105f-95f1-43d1-8292-0807c48f40e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382022261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1382022261
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1334180309
Short name T591
Test name
Test status
Simulation time 263508007959 ps
CPU time 731.28 seconds
Started Apr 16 02:42:05 PM PDT 24
Finished Apr 16 02:54:17 PM PDT 24
Peak memory 230916 kb
Host smart-a8c134a1-506a-419b-a4a9-6eccc7c23c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334180309 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1334180309
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2115257419
Short name T671
Test name
Test status
Simulation time 34196110937 ps
CPU time 20.45 seconds
Started Apr 16 02:39:03 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 199904 kb
Host smart-e9572ad7-ecae-404e-b7eb-06b11b460045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115257419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2115257419
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1912830551
Short name T204
Test name
Test status
Simulation time 116724376660 ps
CPU time 40.94 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:42:53 PM PDT 24
Peak memory 200828 kb
Host smart-0364ba32-ab08-4c42-bd60-7c2ffb033ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912830551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1912830551
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3398997359
Short name T253
Test name
Test status
Simulation time 335729207694 ps
CPU time 54.3 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 201048 kb
Host smart-7126f0d6-b51c-4dce-9ce6-fd21f4e93718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398997359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3398997359
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4068075005
Short name T226
Test name
Test status
Simulation time 57726342678 ps
CPU time 22.69 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 200664 kb
Host smart-527733a3-df38-42ba-aec7-82191a41508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068075005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4068075005
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2909474043
Short name T246
Test name
Test status
Simulation time 121295617044 ps
CPU time 44.5 seconds
Started Apr 16 02:42:20 PM PDT 24
Finished Apr 16 02:43:05 PM PDT 24
Peak memory 200852 kb
Host smart-63b8208d-758d-42e0-8b95-ccebf53cf38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909474043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2909474043
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1920733995
Short name T243
Test name
Test status
Simulation time 90005768898 ps
CPU time 73.33 seconds
Started Apr 16 02:42:17 PM PDT 24
Finished Apr 16 02:43:31 PM PDT 24
Peak memory 200812 kb
Host smart-c0a18314-d219-482e-b32a-a84204739322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920733995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1920733995
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3480041131
Short name T1114
Test name
Test status
Simulation time 87598048487 ps
CPU time 413.58 seconds
Started Apr 16 02:42:19 PM PDT 24
Finished Apr 16 02:49:13 PM PDT 24
Peak memory 200856 kb
Host smart-93e5f6be-15b3-4a02-87d5-59fbbbbdf213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480041131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3480041131
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.727462218
Short name T548
Test name
Test status
Simulation time 27381374100 ps
CPU time 565.37 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:48:49 PM PDT 24
Peak memory 215096 kb
Host smart-f2ab433a-a3c0-4d01-aa4d-0b7be6ee6c99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727462218 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.727462218
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.869692082
Short name T237
Test name
Test status
Simulation time 34783513914 ps
CPU time 58.4 seconds
Started Apr 16 02:42:26 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 200876 kb
Host smart-a4c704b0-47e4-4550-83e7-92f7c8bc7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869692082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.869692082
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3844937205
Short name T217
Test name
Test status
Simulation time 236145834830 ps
CPU time 189.45 seconds
Started Apr 16 02:42:39 PM PDT 24
Finished Apr 16 02:45:49 PM PDT 24
Peak memory 200932 kb
Host smart-aca7ae52-c8e4-4308-a270-b6495a686b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844937205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3844937205
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1788670960
Short name T221
Test name
Test status
Simulation time 26262269527 ps
CPU time 12.54 seconds
Started Apr 16 02:42:42 PM PDT 24
Finished Apr 16 02:42:55 PM PDT 24
Peak memory 200920 kb
Host smart-55557f78-6469-43a7-a2ce-ab4f1fbae065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788670960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1788670960
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2160151760
Short name T168
Test name
Test status
Simulation time 115166624981 ps
CPU time 256.52 seconds
Started Apr 16 02:42:55 PM PDT 24
Finished Apr 16 02:47:12 PM PDT 24
Peak memory 200884 kb
Host smart-23d968f0-0e5d-49e1-a341-bb2c317193d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160151760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2160151760
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2747281618
Short name T269
Test name
Test status
Simulation time 122460097519 ps
CPU time 224.58 seconds
Started Apr 16 02:42:53 PM PDT 24
Finished Apr 16 02:46:38 PM PDT 24
Peak memory 200920 kb
Host smart-398a60ef-181d-4671-9eb8-b078abb1bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747281618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2747281618
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1089193163
Short name T164
Test name
Test status
Simulation time 43534790022 ps
CPU time 62.79 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:59 PM PDT 24
Peak memory 200828 kb
Host smart-b3422460-a18d-44a1-b56a-15c7e3f25dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089193163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1089193163
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.922406218
Short name T224
Test name
Test status
Simulation time 263724066861 ps
CPU time 42.82 seconds
Started Apr 16 02:43:02 PM PDT 24
Finished Apr 16 02:43:46 PM PDT 24
Peak memory 200852 kb
Host smart-7a652151-89fc-4252-871c-fa70282e1088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922406218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.922406218
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3860576803
Short name T220
Test name
Test status
Simulation time 92347011604 ps
CPU time 40.49 seconds
Started Apr 16 02:43:07 PM PDT 24
Finished Apr 16 02:43:48 PM PDT 24
Peak memory 200872 kb
Host smart-77c0fd0b-835c-4453-841b-bdebb55e5963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860576803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3860576803
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1731016969
Short name T278
Test name
Test status
Simulation time 160391665799 ps
CPU time 104.66 seconds
Started Apr 16 02:43:07 PM PDT 24
Finished Apr 16 02:44:52 PM PDT 24
Peak memory 200736 kb
Host smart-b1182082-f67f-4e3d-803b-9cead28b9cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731016969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1731016969
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1400813908
Short name T161
Test name
Test status
Simulation time 139881134870 ps
CPU time 32.91 seconds
Started Apr 16 02:43:19 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200840 kb
Host smart-ecf2be5c-9e9b-4825-89ed-12f3061cfcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400813908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1400813908
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2123597320
Short name T232
Test name
Test status
Simulation time 52053680807 ps
CPU time 30.51 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:43:55 PM PDT 24
Peak memory 200844 kb
Host smart-5657af24-6773-4a24-8df9-1ab385cee373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123597320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2123597320
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.258708613
Short name T235
Test name
Test status
Simulation time 49105286958 ps
CPU time 28.73 seconds
Started Apr 16 02:40:50 PM PDT 24
Finished Apr 16 02:41:19 PM PDT 24
Peak memory 200904 kb
Host smart-db9eea3e-333d-4e38-844e-fee97f6b13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258708613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.258708613
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.2431924557
Short name T239
Test name
Test status
Simulation time 373123481484 ps
CPU time 229.66 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:44:55 PM PDT 24
Peak memory 200832 kb
Host smart-1da845a8-ffe2-4509-8b9e-6e4f384ceece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431924557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2431924557
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1656312011
Short name T241
Test name
Test status
Simulation time 48146287379 ps
CPU time 20.35 seconds
Started Apr 16 02:41:25 PM PDT 24
Finished Apr 16 02:41:46 PM PDT 24
Peak memory 200832 kb
Host smart-69680ca0-a526-43f3-ba15-86eab2eafd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656312011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1656312011
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2297344421
Short name T227
Test name
Test status
Simulation time 285573137926 ps
CPU time 772.43 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:54:55 PM PDT 24
Peak memory 217280 kb
Host smart-4ba47640-28ff-43a7-b561-e36fe568a54a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297344421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2297344421
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.359177898
Short name T1196
Test name
Test status
Simulation time 18550340 ps
CPU time 0.67 seconds
Started Apr 16 02:18:33 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 195408 kb
Host smart-f289ffe0-9674-4b4b-814e-d83eba9d6ad2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359177898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.359177898
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4223005193
Short name T1217
Test name
Test status
Simulation time 211046542 ps
CPU time 1.44 seconds
Started Apr 16 02:18:33 PM PDT 24
Finished Apr 16 02:18:35 PM PDT 24
Peak memory 198008 kb
Host smart-8ead229f-2ec2-4615-842e-cd8bd48d0bca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223005193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4223005193
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4103417677
Short name T1272
Test name
Test status
Simulation time 21461249 ps
CPU time 0.57 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:33 PM PDT 24
Peak memory 195476 kb
Host smart-fc54ab2d-38b3-49af-95c3-44dbf81be233
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103417677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4103417677
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.887836194
Short name T1295
Test name
Test status
Simulation time 64126331 ps
CPU time 0.63 seconds
Started Apr 16 02:18:33 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 197896 kb
Host smart-9e578a64-e92b-445d-b4e7-408c0c054da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887836194 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.887836194
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1432404717
Short name T90
Test name
Test status
Simulation time 20137726 ps
CPU time 0.57 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:33 PM PDT 24
Peak memory 195376 kb
Host smart-6bb4c7f0-9c19-4467-a9d4-16a9a2c32848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432404717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1432404717
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1018017207
Short name T1216
Test name
Test status
Simulation time 24687831 ps
CPU time 0.57 seconds
Started Apr 16 02:18:33 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 194384 kb
Host smart-d0bf031b-746b-4064-9036-f8d1cacd23ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018017207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1018017207
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1926128815
Short name T1226
Test name
Test status
Simulation time 84267443 ps
CPU time 0.62 seconds
Started Apr 16 02:18:33 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 195460 kb
Host smart-da965af6-d459-4b90-952f-185b40148c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926128815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1926128815
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3379273328
Short name T1255
Test name
Test status
Simulation time 240538642 ps
CPU time 1.39 seconds
Started Apr 16 02:18:35 PM PDT 24
Finished Apr 16 02:18:37 PM PDT 24
Peak memory 200104 kb
Host smart-8522f6ad-f49d-4a65-a00a-19e738a24800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379273328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3379273328
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1883661840
Short name T1220
Test name
Test status
Simulation time 20738387 ps
CPU time 0.63 seconds
Started Apr 16 02:18:38 PM PDT 24
Finished Apr 16 02:18:40 PM PDT 24
Peak memory 194936 kb
Host smart-08f2d5a2-1835-4bb1-95ae-5807a705437f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883661840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1883661840
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3678664811
Short name T1184
Test name
Test status
Simulation time 738661743 ps
CPU time 1.5 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 197780 kb
Host smart-57879605-a119-4a60-a476-98f67a905677
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678664811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3678664811
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2346632810
Short name T78
Test name
Test status
Simulation time 54235056 ps
CPU time 0.56 seconds
Started Apr 16 02:18:37 PM PDT 24
Finished Apr 16 02:18:39 PM PDT 24
Peak memory 195416 kb
Host smart-78214af4-d365-4ecc-ac6c-db442f792f7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346632810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2346632810
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3468715421
Short name T1275
Test name
Test status
Simulation time 17455721 ps
CPU time 0.66 seconds
Started Apr 16 02:18:37 PM PDT 24
Finished Apr 16 02:18:38 PM PDT 24
Peak memory 197860 kb
Host smart-e9be91d8-d98a-4b0a-ad17-5e50ea99357a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468715421 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3468715421
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1824702110
Short name T1254
Test name
Test status
Simulation time 31969303 ps
CPU time 0.56 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:33 PM PDT 24
Peak memory 194384 kb
Host smart-e4c55c77-e13f-43f0-b58f-0660fb78dd9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824702110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1824702110
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.628212638
Short name T85
Test name
Test status
Simulation time 53919389 ps
CPU time 0.67 seconds
Started Apr 16 02:18:36 PM PDT 24
Finished Apr 16 02:18:37 PM PDT 24
Peak memory 194632 kb
Host smart-f1f6ef5a-7368-4b9a-b96e-6467021f0ee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628212638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.628212638
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.692560997
Short name T1193
Test name
Test status
Simulation time 22448851 ps
CPU time 1.06 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 199872 kb
Host smart-498a389b-ee73-4df8-9eff-3e69da0eef3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692560997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.692560997
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3244491639
Short name T1269
Test name
Test status
Simulation time 46574577 ps
CPU time 0.91 seconds
Started Apr 16 02:18:32 PM PDT 24
Finished Apr 16 02:18:34 PM PDT 24
Peak memory 199004 kb
Host smart-7a796a50-3a47-4a03-aa87-8dfdeba0b028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244491639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3244491639
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2761381293
Short name T1298
Test name
Test status
Simulation time 30311058 ps
CPU time 0.85 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 199840 kb
Host smart-56840535-94d3-476e-a990-d5ff5da41144
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761381293 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2761381293
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2515823497
Short name T1320
Test name
Test status
Simulation time 14132793 ps
CPU time 0.59 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:19:01 PM PDT 24
Peak memory 195436 kb
Host smart-9a07a792-f956-47da-9f60-dd448b4a190b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515823497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2515823497
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2752190252
Short name T1192
Test name
Test status
Simulation time 20614123 ps
CPU time 0.57 seconds
Started Apr 16 02:18:53 PM PDT 24
Finished Apr 16 02:18:55 PM PDT 24
Peak memory 194460 kb
Host smart-f66a889e-2429-4f0b-a1e7-2a1234eb6a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752190252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2752190252
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.64629913
Short name T1241
Test name
Test status
Simulation time 123882472 ps
CPU time 0.76 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 196884 kb
Host smart-d03eb4ae-bdde-4fef-999b-8350a5de173b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64629913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_
outstanding.64629913
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3785276140
Short name T1228
Test name
Test status
Simulation time 49917205 ps
CPU time 1.24 seconds
Started Apr 16 02:18:53 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 200116 kb
Host smart-6d21e301-394d-4023-869f-d7055ddf50a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785276140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3785276140
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2848962928
Short name T1289
Test name
Test status
Simulation time 52853306 ps
CPU time 1.01 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 199188 kb
Host smart-02a627ff-4830-4b3a-80a3-4aba6505babd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848962928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2848962928
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2642354603
Short name T1197
Test name
Test status
Simulation time 113417917 ps
CPU time 0.92 seconds
Started Apr 16 02:19:08 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 199808 kb
Host smart-3f4e2c98-c9cf-4a7a-81cd-d7de716f80d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642354603 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2642354603
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3299894452
Short name T1218
Test name
Test status
Simulation time 14844456 ps
CPU time 0.58 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:01 PM PDT 24
Peak memory 195528 kb
Host smart-a3e443de-5f7e-44ea-841c-b2e8332cb68c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299894452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3299894452
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2770222213
Short name T1301
Test name
Test status
Simulation time 17391965 ps
CPU time 0.58 seconds
Started Apr 16 02:19:00 PM PDT 24
Finished Apr 16 02:19:03 PM PDT 24
Peak memory 194384 kb
Host smart-d6a295f9-b743-4934-bc84-6b232a11e2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770222213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2770222213
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2573244470
Short name T91
Test name
Test status
Simulation time 31543913 ps
CPU time 0.63 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 195544 kb
Host smart-cbb6d7f9-7763-45cd-8e63-50abbff5aab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573244470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2573244470
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.618059802
Short name T1239
Test name
Test status
Simulation time 104360630 ps
CPU time 1.81 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:57 PM PDT 24
Peak memory 200144 kb
Host smart-920dc8ee-aded-48c9-9abb-68b0adde047c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618059802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.618059802
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3854352991
Short name T1278
Test name
Test status
Simulation time 40535416 ps
CPU time 0.86 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:10 PM PDT 24
Peak memory 199816 kb
Host smart-6a5a740e-db6e-4287-aa27-f9835f36d0ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854352991 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3854352991
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.338750543
Short name T1286
Test name
Test status
Simulation time 43972846 ps
CPU time 0.63 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:01 PM PDT 24
Peak memory 195684 kb
Host smart-6d28dcdf-616b-4349-a365-1cd24ed1214c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338750543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.338750543
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2804796403
Short name T1203
Test name
Test status
Simulation time 17916718 ps
CPU time 0.62 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 194392 kb
Host smart-e826aad2-f8f3-4937-b45a-7b8eb5b2651f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804796403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2804796403
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3239030481
Short name T1234
Test name
Test status
Simulation time 13877437 ps
CPU time 0.67 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 195736 kb
Host smart-e2b92504-39ec-4127-8552-36e911702d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239030481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3239030481
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.602290348
Short name T1238
Test name
Test status
Simulation time 294309907 ps
CPU time 1.95 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 200132 kb
Host smart-b0c2eb80-5c02-4842-8a36-928d75d744a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602290348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.602290348
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2030368118
Short name T1287
Test name
Test status
Simulation time 42137644 ps
CPU time 0.92 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:19:00 PM PDT 24
Peak memory 198952 kb
Host smart-8a6f698f-e070-4e44-ad7a-88cd6f5394ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030368118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2030368118
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3787822487
Short name T1311
Test name
Test status
Simulation time 60833573 ps
CPU time 0.73 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 197900 kb
Host smart-5b476efa-c4b0-475f-be65-d27161c10263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787822487 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3787822487
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2811517143
Short name T1284
Test name
Test status
Simulation time 17596530 ps
CPU time 0.64 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 195560 kb
Host smart-10942e92-728e-4b2c-8f11-61db24b1a967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811517143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2811517143
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3420683775
Short name T1316
Test name
Test status
Simulation time 13267842 ps
CPU time 0.54 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:18:59 PM PDT 24
Peak memory 194320 kb
Host smart-cc6077bc-b2bf-4526-9849-ff2caf61d04c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420683775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3420683775
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1219392823
Short name T84
Test name
Test status
Simulation time 17076316 ps
CPU time 0.67 seconds
Started Apr 16 02:19:02 PM PDT 24
Finished Apr 16 02:19:05 PM PDT 24
Peak memory 195876 kb
Host smart-9f52a9f0-0e76-4a41-a1da-84263126578f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219392823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1219392823
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.476886133
Short name T1194
Test name
Test status
Simulation time 122271153 ps
CPU time 2.16 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 200116 kb
Host smart-ef3950db-a43e-4089-ae35-09bded102ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476886133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.476886133
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.890637057
Short name T1273
Test name
Test status
Simulation time 84322536 ps
CPU time 0.92 seconds
Started Apr 16 02:19:04 PM PDT 24
Finished Apr 16 02:19:07 PM PDT 24
Peak memory 199364 kb
Host smart-2417f3ee-824a-4ae7-bddf-dc7cee137a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890637057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.890637057
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3134125168
Short name T1291
Test name
Test status
Simulation time 82235751 ps
CPU time 0.8 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:19:01 PM PDT 24
Peak memory 199868 kb
Host smart-f625abbe-e33c-4a88-a75c-0ea2a3a60189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134125168 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3134125168
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1653337929
Short name T75
Test name
Test status
Simulation time 51628533 ps
CPU time 0.62 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:19:00 PM PDT 24
Peak memory 195476 kb
Host smart-b1a7a0b9-1342-498e-ab4d-732db5d850d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653337929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1653337929
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2360356881
Short name T1187
Test name
Test status
Simulation time 13964346 ps
CPU time 0.57 seconds
Started Apr 16 02:19:01 PM PDT 24
Finished Apr 16 02:19:05 PM PDT 24
Peak memory 194408 kb
Host smart-cd66d656-09f7-4475-9a4c-d71864b0f627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360356881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2360356881
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3397765510
Short name T1221
Test name
Test status
Simulation time 46898052 ps
CPU time 0.65 seconds
Started Apr 16 02:19:00 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 196480 kb
Host smart-0eb2c76a-fd73-4acf-9b71-7faa006d4ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397765510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3397765510
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3215367431
Short name T1237
Test name
Test status
Simulation time 270784751 ps
CPU time 2.35 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:03 PM PDT 24
Peak memory 200156 kb
Host smart-6ee59eba-01fd-4a40-ab30-18e9622603d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215367431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3215367431
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2814104281
Short name T1300
Test name
Test status
Simulation time 329234526 ps
CPU time 0.95 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 198928 kb
Host smart-12642920-795e-409c-a143-1aebb550a7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814104281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2814104281
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4108507902
Short name T1205
Test name
Test status
Simulation time 83862451 ps
CPU time 0.72 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 198352 kb
Host smart-eafd6cfb-cf43-4064-ad9f-f4914f86a35e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108507902 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4108507902
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.3959964987
Short name T80
Test name
Test status
Simulation time 14190391 ps
CPU time 0.57 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 195460 kb
Host smart-058b55e9-3caa-461d-afe9-e179a1b14914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959964987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3959964987
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.153733661
Short name T1264
Test name
Test status
Simulation time 14951570 ps
CPU time 0.59 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 194320 kb
Host smart-c3132589-69d5-49c7-b253-bfeed3e6e307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153733661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.153733661
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3498213145
Short name T1302
Test name
Test status
Simulation time 97667323 ps
CPU time 0.74 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:09 PM PDT 24
Peak memory 195896 kb
Host smart-3a45125e-2979-42ac-96c2-33716cff6a0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498213145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3498213145
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1308034944
Short name T1279
Test name
Test status
Simulation time 63604068 ps
CPU time 1.4 seconds
Started Apr 16 02:18:59 PM PDT 24
Finished Apr 16 02:19:02 PM PDT 24
Peak memory 200116 kb
Host smart-7872370b-5e47-4400-a07d-26c9d29a6c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308034944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1308034944
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1856634141
Short name T1296
Test name
Test status
Simulation time 169032508 ps
CPU time 0.81 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 199876 kb
Host smart-acf2a59c-6eab-4faa-83c9-0945b8f0e8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856634141 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1856634141
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2419875655
Short name T89
Test name
Test status
Simulation time 21669951 ps
CPU time 0.58 seconds
Started Apr 16 02:19:10 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 195556 kb
Host smart-d6809297-8c72-43c0-9dd1-cc748c72337e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419875655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2419875655
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2600393642
Short name T1258
Test name
Test status
Simulation time 38103490 ps
CPU time 0.55 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:10 PM PDT 24
Peak memory 194432 kb
Host smart-09a1e960-28f7-4277-86e1-74193429074f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600393642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2600393642
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.308717079
Short name T87
Test name
Test status
Simulation time 60552912 ps
CPU time 0.8 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 197076 kb
Host smart-2ac1ed2e-cf3f-45d3-bb45-726151892861
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308717079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.308717079
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1448210747
Short name T1277
Test name
Test status
Simulation time 384587285 ps
CPU time 1.18 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 199852 kb
Host smart-758134bd-110d-49f4-9090-bd93a223b1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448210747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1448210747
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3778805285
Short name T1260
Test name
Test status
Simulation time 94360921 ps
CPU time 1.32 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:10 PM PDT 24
Peak memory 199416 kb
Host smart-1d8850a9-13b1-4c13-8bc0-ca29b8b0d6a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778805285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3778805285
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1857526761
Short name T1199
Test name
Test status
Simulation time 113838221 ps
CPU time 0.83 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:11 PM PDT 24
Peak memory 199848 kb
Host smart-d108545d-71d3-4917-a57c-41752c762c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857526761 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1857526761
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1152241599
Short name T1224
Test name
Test status
Simulation time 22964147 ps
CPU time 0.62 seconds
Started Apr 16 02:19:08 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 195468 kb
Host smart-1b5c8727-3d3f-484b-aa4f-18d2023d4c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152241599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1152241599
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2553799907
Short name T1232
Test name
Test status
Simulation time 18224629 ps
CPU time 0.6 seconds
Started Apr 16 02:19:07 PM PDT 24
Finished Apr 16 02:19:10 PM PDT 24
Peak memory 194432 kb
Host smart-cc0ca603-54b1-4ca3-bb14-580cf6fa972d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553799907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2553799907
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3111802504
Short name T1229
Test name
Test status
Simulation time 19931740 ps
CPU time 0.64 seconds
Started Apr 16 02:19:08 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 195448 kb
Host smart-5b6e3ffa-6350-4091-8f3d-ccc032ecb70e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111802504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3111802504
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3032764602
Short name T1223
Test name
Test status
Simulation time 93745270 ps
CPU time 2.06 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:10 PM PDT 24
Peak memory 200168 kb
Host smart-34c2f83a-ee0c-41b2-bf1e-2d589d5e5e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032764602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3032764602
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3677480608
Short name T94
Test name
Test status
Simulation time 511328924 ps
CPU time 0.94 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 198948 kb
Host smart-5b107d74-f7bd-46b1-91a5-a7cec269db90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677480608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3677480608
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.775881694
Short name T1274
Test name
Test status
Simulation time 70964781 ps
CPU time 1.08 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 200104 kb
Host smart-e59adb15-b09c-443d-9b67-2fae0503ec47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775881694 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.775881694
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2102121386
Short name T83
Test name
Test status
Simulation time 33198271 ps
CPU time 0.59 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 195584 kb
Host smart-8c6e446a-8c10-4a76-9455-e2bc65963655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102121386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2102121386
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3487456726
Short name T1212
Test name
Test status
Simulation time 13622753 ps
CPU time 0.57 seconds
Started Apr 16 02:19:08 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 194452 kb
Host smart-77fc0ec1-328d-4794-851f-32afae9fd37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487456726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3487456726
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.624718653
Short name T88
Test name
Test status
Simulation time 21113214 ps
CPU time 0.66 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 195756 kb
Host smart-9414a010-12ab-4af6-b022-637e5303c640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624718653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.624718653
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2256076063
Short name T1252
Test name
Test status
Simulation time 198384336 ps
CPU time 1.25 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 200128 kb
Host smart-b62146e7-0c49-40a7-a15d-6b334fb87bde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256076063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2256076063
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1075076658
Short name T1297
Test name
Test status
Simulation time 71448590 ps
CPU time 1.32 seconds
Started Apr 16 02:19:10 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 199576 kb
Host smart-6cba1336-2bd8-4a22-895e-8328cb1dd1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075076658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1075076658
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4020887370
Short name T1314
Test name
Test status
Simulation time 113186527 ps
CPU time 0.67 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 197496 kb
Host smart-b28a2108-2ab4-413a-8c01-1ef27c8bfda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020887370 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4020887370
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1633787330
Short name T1261
Test name
Test status
Simulation time 30971860 ps
CPU time 0.6 seconds
Started Apr 16 02:19:13 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 195488 kb
Host smart-bd55dd8a-c5e5-42f2-9936-a66f3466bd32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633787330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1633787330
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.446099964
Short name T1281
Test name
Test status
Simulation time 34812840 ps
CPU time 0.55 seconds
Started Apr 16 02:19:10 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 194376 kb
Host smart-edcfc523-852a-444d-9ddb-dabaf17adabf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446099964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.446099964
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.674644856
Short name T1265
Test name
Test status
Simulation time 35433268 ps
CPU time 0.62 seconds
Started Apr 16 02:19:10 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 195832 kb
Host smart-2fa37092-830b-4652-82bc-5f6782a70f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674644856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.674644856
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1508691938
Short name T1233
Test name
Test status
Simulation time 132190951 ps
CPU time 2.38 seconds
Started Apr 16 02:19:06 PM PDT 24
Finished Apr 16 02:19:12 PM PDT 24
Peak memory 200096 kb
Host smart-c3b17b87-61b9-4fd1-a4f7-4aac9150c72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508691938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1508691938
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1461751592
Short name T97
Test name
Test status
Simulation time 555477275 ps
CPU time 0.94 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 199108 kb
Host smart-0ed51d0a-296e-43b3-9a32-8db7c28e43a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461751592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1461751592
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1729806607
Short name T74
Test name
Test status
Simulation time 63940934 ps
CPU time 0.68 seconds
Started Apr 16 02:18:46 PM PDT 24
Finished Apr 16 02:18:48 PM PDT 24
Peak memory 195180 kb
Host smart-6fc31844-cff7-48eb-80e9-f6fa847a9d17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729806607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1729806607
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2259835443
Short name T1280
Test name
Test status
Simulation time 66013082 ps
CPU time 1.44 seconds
Started Apr 16 02:18:37 PM PDT 24
Finished Apr 16 02:18:39 PM PDT 24
Peak memory 198224 kb
Host smart-efc493cc-1682-4a19-adea-70bf1a862e93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259835443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2259835443
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2789335688
Short name T1319
Test name
Test status
Simulation time 30347398 ps
CPU time 0.6 seconds
Started Apr 16 02:18:40 PM PDT 24
Finished Apr 16 02:18:41 PM PDT 24
Peak memory 195480 kb
Host smart-d4d2bfae-eb6a-4aae-9c7d-cc39bb56c9d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789335688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2789335688
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2063586513
Short name T1256
Test name
Test status
Simulation time 21589498 ps
CPU time 0.78 seconds
Started Apr 16 02:18:35 PM PDT 24
Finished Apr 16 02:18:36 PM PDT 24
Peak memory 199468 kb
Host smart-ff188888-655d-486e-a92d-95c825b18161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063586513 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2063586513
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3911237509
Short name T1259
Test name
Test status
Simulation time 43863187 ps
CPU time 0.6 seconds
Started Apr 16 02:18:38 PM PDT 24
Finished Apr 16 02:18:39 PM PDT 24
Peak memory 195460 kb
Host smart-21fd5f6a-80b7-4066-b7b7-8a9662e7f0e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911237509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3911237509
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.809523383
Short name T1195
Test name
Test status
Simulation time 10978576 ps
CPU time 0.58 seconds
Started Apr 16 02:18:38 PM PDT 24
Finished Apr 16 02:18:39 PM PDT 24
Peak memory 194460 kb
Host smart-0335e3a5-d664-4831-af6c-d82a29387f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809523383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.809523383
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3488514059
Short name T1242
Test name
Test status
Simulation time 33059245 ps
CPU time 0.76 seconds
Started Apr 16 02:18:39 PM PDT 24
Finished Apr 16 02:18:40 PM PDT 24
Peak memory 197228 kb
Host smart-505311b4-905e-4595-b8ae-c77bb074583f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488514059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3488514059
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2553645061
Short name T1304
Test name
Test status
Simulation time 52045166 ps
CPU time 1.37 seconds
Started Apr 16 02:18:49 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 200360 kb
Host smart-f3fd5ac9-ce19-4edb-b403-879d92fe70ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553645061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2553645061
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2517882957
Short name T92
Test name
Test status
Simulation time 49193554 ps
CPU time 0.99 seconds
Started Apr 16 02:18:49 PM PDT 24
Finished Apr 16 02:18:50 PM PDT 24
Peak memory 199284 kb
Host smart-7dd5d98b-9f78-4ef0-baac-6a5ff50bb928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517882957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2517882957
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1480179616
Short name T1309
Test name
Test status
Simulation time 52687703 ps
CPU time 0.54 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 194436 kb
Host smart-5867642f-2dd6-4249-bcf1-848b10175ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480179616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1480179616
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.4161691119
Short name T1285
Test name
Test status
Simulation time 15430205 ps
CPU time 0.56 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194428 kb
Host smart-e17afac6-41ef-4082-914c-b30a44a82880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161691119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.4161691119
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2841088765
Short name T1235
Test name
Test status
Simulation time 35707806 ps
CPU time 0.57 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:14 PM PDT 24
Peak memory 194392 kb
Host smart-a1fe6763-3539-4f61-952e-f80cc667c808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841088765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2841088765
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.54872754
Short name T1207
Test name
Test status
Simulation time 36899930 ps
CPU time 0.56 seconds
Started Apr 16 02:19:09 PM PDT 24
Finished Apr 16 02:19:13 PM PDT 24
Peak memory 194464 kb
Host smart-db6f7937-0add-4bd4-9a14-777dfe0728d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54872754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.54872754
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2308848550
Short name T1208
Test name
Test status
Simulation time 10721105 ps
CPU time 0.57 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 194340 kb
Host smart-6c5bc803-77dc-4253-9562-eab98d030ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308848550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2308848550
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2871454732
Short name T1230
Test name
Test status
Simulation time 15792279 ps
CPU time 0.57 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 194372 kb
Host smart-b1d0eceb-a6f5-48da-87fb-e26ab9183693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871454732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2871454732
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2590294
Short name T1283
Test name
Test status
Simulation time 42491178 ps
CPU time 0.64 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 194380 kb
Host smart-c1f496c6-25ef-4114-b468-38d6a1a11006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2590294
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.411390514
Short name T1209
Test name
Test status
Simulation time 11959050 ps
CPU time 0.59 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194440 kb
Host smart-970c14c8-0a85-47ec-9f45-3b6de681e8cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411390514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.411390514
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2601180306
Short name T1198
Test name
Test status
Simulation time 12515687 ps
CPU time 0.63 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194440 kb
Host smart-5062f769-daa9-4e5d-82c0-5ef23c717efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601180306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2601180306
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.11431641
Short name T1202
Test name
Test status
Simulation time 13594529 ps
CPU time 0.58 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194364 kb
Host smart-f1119ea5-d8d5-4550-a8b8-e4c08549a3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.11431641
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.896610476
Short name T82
Test name
Test status
Simulation time 18735560 ps
CPU time 0.77 seconds
Started Apr 16 02:18:41 PM PDT 24
Finished Apr 16 02:18:43 PM PDT 24
Peak memory 196788 kb
Host smart-1361a1c2-b099-4488-9a6d-5c1ab61d25cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896610476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.896610476
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.720696676
Short name T1190
Test name
Test status
Simulation time 394416192 ps
CPU time 1.56 seconds
Started Apr 16 02:18:48 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 197940 kb
Host smart-38c9727f-eb8b-472c-9676-5aeabe434c3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720696676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.720696676
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2219179699
Short name T1270
Test name
Test status
Simulation time 13344977 ps
CPU time 0.58 seconds
Started Apr 16 02:18:37 PM PDT 24
Finished Apr 16 02:18:38 PM PDT 24
Peak memory 195448 kb
Host smart-8ead00e8-2a50-4fde-9b74-9524d1d3fe6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219179699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2219179699
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3249116630
Short name T1305
Test name
Test status
Simulation time 47531562 ps
CPU time 1.1 seconds
Started Apr 16 02:18:41 PM PDT 24
Finished Apr 16 02:18:43 PM PDT 24
Peak memory 200136 kb
Host smart-d6c7a2fa-5f2b-482e-b939-6319125407c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249116630 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3249116630
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2600619774
Short name T81
Test name
Test status
Simulation time 17530747 ps
CPU time 0.63 seconds
Started Apr 16 02:18:46 PM PDT 24
Finished Apr 16 02:18:48 PM PDT 24
Peak memory 195712 kb
Host smart-e629d6f7-e718-4bf9-b35a-2f199872c375
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600619774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2600619774
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3587492399
Short name T1225
Test name
Test status
Simulation time 14851427 ps
CPU time 0.62 seconds
Started Apr 16 02:18:38 PM PDT 24
Finished Apr 16 02:18:40 PM PDT 24
Peak memory 194360 kb
Host smart-56242707-5a71-469f-b937-6ec65d711fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587492399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3587492399
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3616730615
Short name T1215
Test name
Test status
Simulation time 33342589 ps
CPU time 0.78 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 195864 kb
Host smart-3873bcec-151e-44dc-8d4a-3dde40a3788e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616730615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3616730615
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3684621775
Short name T1248
Test name
Test status
Simulation time 710962457 ps
CPU time 1.26 seconds
Started Apr 16 02:18:37 PM PDT 24
Finished Apr 16 02:18:39 PM PDT 24
Peak memory 200088 kb
Host smart-59e4c0fe-d39c-4f01-a860-56f4dda3cf3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684621775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3684621775
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3269305702
Short name T101
Test name
Test status
Simulation time 41469931 ps
CPU time 0.9 seconds
Started Apr 16 02:18:36 PM PDT 24
Finished Apr 16 02:18:37 PM PDT 24
Peak memory 198928 kb
Host smart-9b91cc2e-92fb-443e-b692-0dc375622bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269305702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3269305702
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3363388938
Short name T1290
Test name
Test status
Simulation time 129365721 ps
CPU time 0.58 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194436 kb
Host smart-8f02a633-bf2a-4999-8961-64c5052c7d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363388938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3363388938
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3786925151
Short name T1214
Test name
Test status
Simulation time 12585442 ps
CPU time 0.58 seconds
Started Apr 16 02:19:13 PM PDT 24
Finished Apr 16 02:19:17 PM PDT 24
Peak memory 194392 kb
Host smart-739fd9e3-89a1-4cf5-a9f2-42df4a97c079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786925151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3786925151
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2433862678
Short name T1294
Test name
Test status
Simulation time 16144352 ps
CPU time 0.65 seconds
Started Apr 16 02:19:14 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194388 kb
Host smart-534ad2a4-db62-4fe6-9505-37c57746c945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433862678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2433862678
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1176236107
Short name T1292
Test name
Test status
Simulation time 13319287 ps
CPU time 0.56 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194316 kb
Host smart-db1f1041-1b0b-4ac1-b7cb-ca48efdcb04f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176236107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1176236107
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.600490709
Short name T1271
Test name
Test status
Simulation time 14275151 ps
CPU time 0.59 seconds
Started Apr 16 02:19:12 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194460 kb
Host smart-fdb78fbc-6697-4251-bf63-ed07cd8ad46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600490709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.600490709
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1964047092
Short name T1253
Test name
Test status
Simulation time 13406320 ps
CPU time 0.56 seconds
Started Apr 16 02:19:15 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194328 kb
Host smart-a6ee7c01-43c5-4359-8761-0e4f0155acc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964047092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1964047092
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2895873025
Short name T1201
Test name
Test status
Simulation time 18770962 ps
CPU time 0.55 seconds
Started Apr 16 02:19:11 PM PDT 24
Finished Apr 16 02:19:15 PM PDT 24
Peak memory 194368 kb
Host smart-d6eb1a86-9c3a-4a44-856e-84eae32ee6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895873025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2895873025
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.844327794
Short name T1288
Test name
Test status
Simulation time 13150923 ps
CPU time 0.56 seconds
Started Apr 16 02:19:13 PM PDT 24
Finished Apr 16 02:19:16 PM PDT 24
Peak memory 194364 kb
Host smart-8570e52c-3d7f-4adf-88c9-a20afc58cdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844327794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.844327794
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3852169712
Short name T1310
Test name
Test status
Simulation time 14721551 ps
CPU time 0.58 seconds
Started Apr 16 02:19:13 PM PDT 24
Finished Apr 16 02:19:17 PM PDT 24
Peak memory 194456 kb
Host smart-e14a81ea-da5a-4432-9b21-e03193b00b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852169712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3852169712
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1462805160
Short name T1257
Test name
Test status
Simulation time 15136302 ps
CPU time 0.59 seconds
Started Apr 16 02:19:14 PM PDT 24
Finished Apr 16 02:19:17 PM PDT 24
Peak memory 194452 kb
Host smart-ebe4af52-39a9-4071-972e-492f827b56a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462805160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1462805160
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1492006076
Short name T79
Test name
Test status
Simulation time 120491822 ps
CPU time 0.77 seconds
Started Apr 16 02:18:46 PM PDT 24
Finished Apr 16 02:18:48 PM PDT 24
Peak memory 196364 kb
Host smart-43aa578d-360d-4ad3-94bd-8f622cd4bad9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492006076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1492006076
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.902231844
Short name T1318
Test name
Test status
Simulation time 240241128 ps
CPU time 1.66 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:45 PM PDT 24
Peak memory 197752 kb
Host smart-c6fd56fc-db7d-4936-892c-ad59a6b7b1ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902231844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.902231844
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.810560146
Short name T1266
Test name
Test status
Simulation time 39715916 ps
CPU time 0.59 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 195456 kb
Host smart-6dd163ee-34ea-47b7-a381-3d78e005b585
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810560146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.810560146
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3726889466
Short name T1204
Test name
Test status
Simulation time 32070400 ps
CPU time 0.94 seconds
Started Apr 16 02:18:49 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 200100 kb
Host smart-d4cbdd5c-e89d-473d-b67c-6d2a13ec9b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726889466 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3726889466
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3174697804
Short name T1211
Test name
Test status
Simulation time 30951538 ps
CPU time 0.61 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 195440 kb
Host smart-ccf75d0e-3fe8-4c86-a0ef-3b42344086d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174697804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3174697804
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1987404322
Short name T1245
Test name
Test status
Simulation time 45368355 ps
CPU time 0.59 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 194472 kb
Host smart-9bbf5e14-afb4-47d6-8ffd-7c748381bc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987404322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1987404322
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3793153103
Short name T1282
Test name
Test status
Simulation time 16022064 ps
CPU time 0.65 seconds
Started Apr 16 02:18:43 PM PDT 24
Finished Apr 16 02:18:45 PM PDT 24
Peak memory 196488 kb
Host smart-dd2ac3ed-18b1-44bd-ba72-6d1d9825339c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793153103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3793153103
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2686545604
Short name T1191
Test name
Test status
Simulation time 42361181 ps
CPU time 1.2 seconds
Started Apr 16 02:18:42 PM PDT 24
Finished Apr 16 02:18:44 PM PDT 24
Peak memory 199884 kb
Host smart-30cea22f-dc24-4157-b04b-bd9f5c056b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686545604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2686545604
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3621003336
Short name T1263
Test name
Test status
Simulation time 191378085 ps
CPU time 0.99 seconds
Started Apr 16 02:18:40 PM PDT 24
Finished Apr 16 02:18:42 PM PDT 24
Peak memory 199160 kb
Host smart-3fe4ee83-e4e5-493d-89a7-e284b28f721f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621003336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3621003336
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3835677248
Short name T1243
Test name
Test status
Simulation time 24029927 ps
CPU time 0.58 seconds
Started Apr 16 02:19:15 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194312 kb
Host smart-842d00bd-c8b3-4437-b1d3-8092818cc6d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835677248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3835677248
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2621833156
Short name T1231
Test name
Test status
Simulation time 38896779 ps
CPU time 0.58 seconds
Started Apr 16 02:19:15 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194452 kb
Host smart-d59d077a-5e1f-4706-a114-71e69ac4641a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621833156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2621833156
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2482209383
Short name T1246
Test name
Test status
Simulation time 46067685 ps
CPU time 0.58 seconds
Started Apr 16 02:19:16 PM PDT 24
Finished Apr 16 02:19:19 PM PDT 24
Peak memory 194388 kb
Host smart-8a452252-9e72-46f9-bcaa-c5bb3e42ddf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482209383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2482209383
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3124988962
Short name T1308
Test name
Test status
Simulation time 34576852 ps
CPU time 0.53 seconds
Started Apr 16 02:19:13 PM PDT 24
Finished Apr 16 02:19:17 PM PDT 24
Peak memory 194360 kb
Host smart-8b96e475-2627-46cb-ac24-8bcec19ecfdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124988962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3124988962
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1219706895
Short name T1299
Test name
Test status
Simulation time 41141225 ps
CPU time 0.57 seconds
Started Apr 16 02:19:16 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194440 kb
Host smart-334e4aa8-b684-44bf-b198-69fa839c91be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219706895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1219706895
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3867717167
Short name T1236
Test name
Test status
Simulation time 30781273 ps
CPU time 0.61 seconds
Started Apr 16 02:19:16 PM PDT 24
Finished Apr 16 02:19:19 PM PDT 24
Peak memory 194356 kb
Host smart-5f088351-d0d3-4667-8f03-efb9fa72734d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867717167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3867717167
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3201684441
Short name T1267
Test name
Test status
Simulation time 11383062 ps
CPU time 0.58 seconds
Started Apr 16 02:19:17 PM PDT 24
Finished Apr 16 02:19:19 PM PDT 24
Peak memory 194324 kb
Host smart-010b2970-983a-4089-8fe8-ee6c569f973b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201684441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3201684441
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2069234699
Short name T1240
Test name
Test status
Simulation time 50392564 ps
CPU time 0.58 seconds
Started Apr 16 02:19:16 PM PDT 24
Finished Apr 16 02:19:19 PM PDT 24
Peak memory 194380 kb
Host smart-5d445b66-dafe-4f5d-9471-5440f73d42ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069234699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2069234699
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2685293500
Short name T1306
Test name
Test status
Simulation time 13848454 ps
CPU time 0.58 seconds
Started Apr 16 02:19:15 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194428 kb
Host smart-17a1aff2-28ff-44af-8929-82b4d4c2c4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685293500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2685293500
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3892732692
Short name T1210
Test name
Test status
Simulation time 17382901 ps
CPU time 0.6 seconds
Started Apr 16 02:19:16 PM PDT 24
Finished Apr 16 02:19:18 PM PDT 24
Peak memory 194396 kb
Host smart-22c4044a-92aa-45da-ac02-c6d19f4feaf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892732692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3892732692
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4241585408
Short name T1268
Test name
Test status
Simulation time 78738726 ps
CPU time 0.74 seconds
Started Apr 16 02:18:48 PM PDT 24
Finished Apr 16 02:18:50 PM PDT 24
Peak memory 198380 kb
Host smart-5424a6ea-76e2-4ea9-9b8b-b98287c4ae85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241585408 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4241585408
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3857753595
Short name T86
Test name
Test status
Simulation time 45313667 ps
CPU time 0.62 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 195636 kb
Host smart-04a44d1a-938c-49b8-93a8-8ab3f824fff0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857753595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3857753595
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1053227589
Short name T1317
Test name
Test status
Simulation time 40213014 ps
CPU time 0.62 seconds
Started Apr 16 02:18:49 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 194464 kb
Host smart-052e8b85-f880-47fa-b137-02c45fb8c038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053227589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1053227589
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2656728613
Short name T1251
Test name
Test status
Simulation time 22344803 ps
CPU time 0.65 seconds
Started Apr 16 02:18:48 PM PDT 24
Finished Apr 16 02:18:50 PM PDT 24
Peak memory 196488 kb
Host smart-620b617e-9251-4c80-b504-1135c71faa6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656728613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2656728613
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.82992947
Short name T1189
Test name
Test status
Simulation time 47346153 ps
CPU time 1.15 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 200120 kb
Host smart-d33a5d27-18b8-4cde-8a45-e1f47399e583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82992947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.82992947
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2254655009
Short name T1250
Test name
Test status
Simulation time 137471052 ps
CPU time 1.24 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 199272 kb
Host smart-6fc3066b-fcb2-4794-820b-9dc15b904ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254655009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2254655009
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3735697111
Short name T1312
Test name
Test status
Simulation time 21333606 ps
CPU time 0.78 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 198512 kb
Host smart-fb1a5428-b308-4e21-9aaf-9438cc50eb16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735697111 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3735697111
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3657828764
Short name T1186
Test name
Test status
Simulation time 15745365 ps
CPU time 0.65 seconds
Started Apr 16 02:18:46 PM PDT 24
Finished Apr 16 02:18:47 PM PDT 24
Peak memory 195508 kb
Host smart-f36783dd-4a47-4747-a1db-b38acc2129d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657828764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3657828764
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4128321211
Short name T1262
Test name
Test status
Simulation time 14032178 ps
CPU time 0.57 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 194360 kb
Host smart-2228d9dd-5ca9-4426-bef2-c4f0fe297047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128321211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4128321211
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1318395894
Short name T1249
Test name
Test status
Simulation time 69092904 ps
CPU time 0.67 seconds
Started Apr 16 02:18:48 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 195564 kb
Host smart-2f6aa40d-2307-4c4b-9928-3c8196eac3b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318395894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1318395894
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.707227395
Short name T1200
Test name
Test status
Simulation time 94536133 ps
CPU time 2.03 seconds
Started Apr 16 02:18:52 PM PDT 24
Finished Apr 16 02:18:55 PM PDT 24
Peak memory 200104 kb
Host smart-72f37a07-2f4b-450c-844f-c4343ff2990e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707227395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.707227395
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1967001392
Short name T98
Test name
Test status
Simulation time 47978410 ps
CPU time 0.94 seconds
Started Apr 16 02:18:48 PM PDT 24
Finished Apr 16 02:18:50 PM PDT 24
Peak memory 198952 kb
Host smart-cf32ae8a-4d07-4381-982f-25cd65c0539e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967001392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1967001392
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3650072259
Short name T1293
Test name
Test status
Simulation time 82458543 ps
CPU time 0.74 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 198712 kb
Host smart-ac4ccd6a-d522-479c-a80a-ad169b637252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650072259 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3650072259
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.234936625
Short name T1206
Test name
Test status
Simulation time 18701666 ps
CPU time 0.59 seconds
Started Apr 16 02:18:50 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 195468 kb
Host smart-437d7910-eb75-4388-a0d0-09ae8f499b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234936625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.234936625
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3750585843
Short name T1185
Test name
Test status
Simulation time 45887481 ps
CPU time 0.57 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:48 PM PDT 24
Peak memory 194360 kb
Host smart-8671a77d-512d-4da0-ac08-f922c714ea90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750585843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3750585843
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3500143784
Short name T1303
Test name
Test status
Simulation time 18753951 ps
CPU time 0.63 seconds
Started Apr 16 02:18:58 PM PDT 24
Finished Apr 16 02:19:00 PM PDT 24
Peak memory 195588 kb
Host smart-bb8d3958-8d82-4456-b05b-ef21250dea49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500143784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3500143784
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4071592752
Short name T1227
Test name
Test status
Simulation time 24810155 ps
CPU time 1.27 seconds
Started Apr 16 02:18:47 PM PDT 24
Finished Apr 16 02:18:50 PM PDT 24
Peak memory 200072 kb
Host smart-a9cf9446-bcd6-43be-837a-d102aa16114d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071592752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4071592752
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1048847563
Short name T100
Test name
Test status
Simulation time 160406860 ps
CPU time 1.32 seconds
Started Apr 16 02:18:46 PM PDT 24
Finished Apr 16 02:18:47 PM PDT 24
Peak memory 199480 kb
Host smart-a73c6ec2-977d-4096-98ca-c69b192a5410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048847563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1048847563
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2853940734
Short name T1276
Test name
Test status
Simulation time 18802086 ps
CPU time 0.69 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 198020 kb
Host smart-ba26f2c2-240d-4de8-88f6-c2e1d7f4223d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853940734 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2853940734
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1879905815
Short name T77
Test name
Test status
Simulation time 59160957 ps
CPU time 0.62 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 195536 kb
Host smart-aaa9b0e3-11fb-42d0-9db3-1932bd0203d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879905815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1879905815
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1130522421
Short name T1244
Test name
Test status
Simulation time 53501683 ps
CPU time 0.58 seconds
Started Apr 16 02:18:53 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 194364 kb
Host smart-1b0a42cf-07bf-4106-af13-8c49f31def9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130522421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1130522421
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4192529150
Short name T1222
Test name
Test status
Simulation time 13731235 ps
CPU time 0.63 seconds
Started Apr 16 02:18:52 PM PDT 24
Finished Apr 16 02:18:53 PM PDT 24
Peak memory 194652 kb
Host smart-9a5a5f5f-b40d-43e9-8267-d0fb86c176aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192529150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4192529150
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.983025358
Short name T1313
Test name
Test status
Simulation time 194693448 ps
CPU time 1.86 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:57 PM PDT 24
Peak memory 200120 kb
Host smart-e30f2900-495a-4b74-9beb-b0813130d554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983025358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.983025358
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2415091292
Short name T1315
Test name
Test status
Simulation time 50689447 ps
CPU time 0.98 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:57 PM PDT 24
Peak memory 198868 kb
Host smart-934e3470-c987-48ea-a682-9e7d383bc4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415091292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2415091292
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3896964058
Short name T1307
Test name
Test status
Simulation time 36886204 ps
CPU time 0.7 seconds
Started Apr 16 02:18:53 PM PDT 24
Finished Apr 16 02:18:55 PM PDT 24
Peak memory 197772 kb
Host smart-1dd72887-ee43-4c6d-b6ee-b2c65366ff07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896964058 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3896964058
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2853106323
Short name T1213
Test name
Test status
Simulation time 15103745 ps
CPU time 0.62 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 195480 kb
Host smart-291a34e2-adf6-455d-a9a5-fcca0fea009c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853106323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2853106323
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3366233199
Short name T1188
Test name
Test status
Simulation time 12188956 ps
CPU time 0.56 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 194360 kb
Host smart-3e28268d-8404-4592-aef7-6be49e84e60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366233199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3366233199
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.986251281
Short name T1247
Test name
Test status
Simulation time 21418893 ps
CPU time 0.75 seconds
Started Apr 16 02:18:54 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 197056 kb
Host smart-3878be12-f14d-47a1-a64f-e83162fe9812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986251281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.986251281
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1936250258
Short name T1219
Test name
Test status
Simulation time 1112253205 ps
CPU time 1.48 seconds
Started Apr 16 02:18:52 PM PDT 24
Finished Apr 16 02:18:55 PM PDT 24
Peak memory 200056 kb
Host smart-c7c98d7e-180d-4a4a-953e-7a8699e85e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936250258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1936250258
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.604720028
Short name T95
Test name
Test status
Simulation time 246516582 ps
CPU time 1.41 seconds
Started Apr 16 02:18:53 PM PDT 24
Finished Apr 16 02:18:56 PM PDT 24
Peak memory 199440 kb
Host smart-b2bc229a-d327-4c2f-ad41-4eef7d5fd016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604720028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.604720028
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1905175768
Short name T419
Test name
Test status
Simulation time 23131195 ps
CPU time 0.58 seconds
Started Apr 16 02:38:59 PM PDT 24
Finished Apr 16 02:39:01 PM PDT 24
Peak memory 196224 kb
Host smart-433095cc-11e8-424f-b315-5990a914bba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905175768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1905175768
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.4237332001
Short name T879
Test name
Test status
Simulation time 302463976376 ps
CPU time 42.42 seconds
Started Apr 16 02:39:00 PM PDT 24
Finished Apr 16 02:39:44 PM PDT 24
Peak memory 200932 kb
Host smart-263e218a-3f82-47fd-89c8-ac5a3007e26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237332001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4237332001
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2093978093
Short name T1025
Test name
Test status
Simulation time 18385752326 ps
CPU time 34.91 seconds
Started Apr 16 02:39:02 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 200680 kb
Host smart-6ab94c70-060d-405f-98d4-0eae3fc728e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093978093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2093978093
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.437894137
Short name T531
Test name
Test status
Simulation time 43035736914 ps
CPU time 10.01 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:39:11 PM PDT 24
Peak memory 200412 kb
Host smart-f8be9406-ebad-4ca4-8cdf-84f6e6d66219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437894137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.437894137
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2570582019
Short name T929
Test name
Test status
Simulation time 251526054609 ps
CPU time 211.8 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:42:33 PM PDT 24
Peak memory 200944 kb
Host smart-8e1b67de-db66-464b-8f12-017fe55774d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570582019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2570582019
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1368536844
Short name T271
Test name
Test status
Simulation time 136568733577 ps
CPU time 343.05 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:44:45 PM PDT 24
Peak memory 200664 kb
Host smart-c627c64d-531f-4639-9465-38af220a6872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368536844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1368536844
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3910922052
Short name T644
Test name
Test status
Simulation time 3123780848 ps
CPU time 2.62 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:39:05 PM PDT 24
Peak memory 199392 kb
Host smart-c30edf83-4ec3-4076-b219-5616ed4c0caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910922052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3910922052
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.4097788809
Short name T260
Test name
Test status
Simulation time 255373583853 ps
CPU time 29.77 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:39:32 PM PDT 24
Peak memory 198556 kb
Host smart-dfa1aa64-1d67-4926-8cb3-477e48ae4e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097788809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.4097788809
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.449761523
Short name T509
Test name
Test status
Simulation time 17660440884 ps
CPU time 65.22 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:40:07 PM PDT 24
Peak memory 200876 kb
Host smart-ed3ce11f-ac94-40a3-99a0-c5dc62e2b24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449761523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.449761523
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4212051423
Short name T482
Test name
Test status
Simulation time 4642882756 ps
CPU time 19.03 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 199544 kb
Host smart-c37407cb-cafa-4251-ab0a-d38debb8a502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212051423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4212051423
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1708538263
Short name T584
Test name
Test status
Simulation time 28170789068 ps
CPU time 26.12 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 200876 kb
Host smart-ca58f5f9-fcfe-402c-b1da-cd154b998f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708538263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1708538263
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4156924508
Short name T604
Test name
Test status
Simulation time 3815317931 ps
CPU time 3.83 seconds
Started Apr 16 02:38:59 PM PDT 24
Finished Apr 16 02:39:04 PM PDT 24
Peak memory 196896 kb
Host smart-e8f8f901-c945-4110-b739-2dc784b46198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156924508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4156924508
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2048533606
Short name T31
Test name
Test status
Simulation time 32675615 ps
CPU time 0.77 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:08 PM PDT 24
Peak memory 218876 kb
Host smart-c6c2e2fa-89b4-4dab-a700-c0b891930e7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048533606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2048533606
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2567058506
Short name T285
Test name
Test status
Simulation time 1028731514 ps
CPU time 1.31 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:39:04 PM PDT 24
Peak memory 199552 kb
Host smart-fed2c552-cf02-41c6-b608-c8ed3bf5de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567058506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2567058506
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.830488714
Short name T553
Test name
Test status
Simulation time 205381893180 ps
CPU time 160.99 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:41:46 PM PDT 24
Peak memory 200880 kb
Host smart-abb2a974-b4b1-4366-848d-7a97b42a8811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830488714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.830488714
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2058750333
Short name T514
Test name
Test status
Simulation time 1465488282 ps
CPU time 2.7 seconds
Started Apr 16 02:39:00 PM PDT 24
Finished Apr 16 02:39:03 PM PDT 24
Peak memory 199848 kb
Host smart-8e103b80-1224-45e6-ba35-e8f315831c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058750333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2058750333
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.4083311731
Short name T1013
Test name
Test status
Simulation time 39933317 ps
CPU time 0.63 seconds
Started Apr 16 02:39:07 PM PDT 24
Finished Apr 16 02:39:08 PM PDT 24
Peak memory 196232 kb
Host smart-5d63fc7b-e4b8-45c9-b670-566129579555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083311731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4083311731
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1772219207
Short name T659
Test name
Test status
Simulation time 333274000399 ps
CPU time 66.79 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 200924 kb
Host smart-4d32c4ac-fcb5-46f4-a726-7a13d64254fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772219207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1772219207
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2825597236
Short name T459
Test name
Test status
Simulation time 41287095098 ps
CPU time 71.29 seconds
Started Apr 16 02:39:01 PM PDT 24
Finished Apr 16 02:40:14 PM PDT 24
Peak memory 200860 kb
Host smart-5cda337a-31ca-4a3f-8e3c-77f39cd4ef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825597236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2825597236
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3646554569
Short name T324
Test name
Test status
Simulation time 36004024269 ps
CPU time 15.3 seconds
Started Apr 16 02:39:02 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 200832 kb
Host smart-e3baf5d3-93c4-4df5-b14b-38ff77b9e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646554569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3646554569
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3982876066
Short name T570
Test name
Test status
Simulation time 62685892394 ps
CPU time 105.25 seconds
Started Apr 16 02:39:02 PM PDT 24
Finished Apr 16 02:40:48 PM PDT 24
Peak memory 200732 kb
Host smart-9700e11e-3786-4038-b669-335d97249d9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982876066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3982876066
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3993831148
Short name T414
Test name
Test status
Simulation time 300446252032 ps
CPU time 490.17 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:47:24 PM PDT 24
Peak memory 200920 kb
Host smart-e1e74826-d4c7-4a62-ac89-52ac42d4f98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993831148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3993831148
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3421789660
Short name T492
Test name
Test status
Simulation time 3625415400 ps
CPU time 11.08 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 200744 kb
Host smart-02981ce0-0c94-458c-916b-99b2a1505a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421789660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3421789660
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1093631886
Short name T998
Test name
Test status
Simulation time 55518490515 ps
CPU time 42.61 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 200724 kb
Host smart-8abd110a-1a88-4685-b80f-d90574048274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093631886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1093631886
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.241929033
Short name T1135
Test name
Test status
Simulation time 10556548125 ps
CPU time 253.65 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:43:21 PM PDT 24
Peak memory 200844 kb
Host smart-d39781ca-5a56-42bc-93fe-7c678f088b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241929033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.241929033
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1539054777
Short name T356
Test name
Test status
Simulation time 4347500650 ps
CPU time 6.47 seconds
Started Apr 16 02:38:59 PM PDT 24
Finished Apr 16 02:39:06 PM PDT 24
Peak memory 199836 kb
Host smart-666c0242-af81-43d2-a08c-6423f7ac8adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539054777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1539054777
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3042551740
Short name T1115
Test name
Test status
Simulation time 44541925399 ps
CPU time 6.45 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:39:12 PM PDT 24
Peak memory 196932 kb
Host smart-e3f48a53-da96-426e-a16e-191762eba8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042551740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3042551740
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.901249159
Short name T394
Test name
Test status
Simulation time 691984960 ps
CPU time 2.6 seconds
Started Apr 16 02:39:00 PM PDT 24
Finished Apr 16 02:39:04 PM PDT 24
Peak memory 200584 kb
Host smart-3c895507-530d-484b-8c86-eaf4e05604d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901249159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.901249159
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.526413469
Short name T284
Test name
Test status
Simulation time 309109926817 ps
CPU time 442.32 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:46:33 PM PDT 24
Peak memory 209320 kb
Host smart-51d5acef-1b2a-42a3-9c5a-e8b005866b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526413469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.526413469
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1598501334
Short name T700
Test name
Test status
Simulation time 80677223790 ps
CPU time 632.55 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:49:39 PM PDT 24
Peak memory 217524 kb
Host smart-06200b62-8839-4195-aec0-924f5daba79f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598501334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1598501334
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2824913039
Short name T274
Test name
Test status
Simulation time 6805962177 ps
CPU time 9.78 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:39:15 PM PDT 24
Peak memory 200088 kb
Host smart-753d038e-9155-40a0-b1f9-d04b112b8a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824913039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2824913039
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.4278087289
Short name T840
Test name
Test status
Simulation time 72828487765 ps
CPU time 121.92 seconds
Started Apr 16 02:39:02 PM PDT 24
Finished Apr 16 02:41:05 PM PDT 24
Peak memory 200912 kb
Host smart-55e0d535-9d8a-47d4-ac9a-cb31bda0b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278087289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4278087289
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.781039973
Short name T403
Test name
Test status
Simulation time 10993038 ps
CPU time 0.59 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:39:19 PM PDT 24
Peak memory 195200 kb
Host smart-f6a57d1c-b3ab-4112-85b6-eb9b00239217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781039973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.781039973
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.241269394
Short name T493
Test name
Test status
Simulation time 182805779510 ps
CPU time 101.53 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:40:56 PM PDT 24
Peak memory 200944 kb
Host smart-8bf39625-d2e8-4ecc-a6ba-b402f51cfdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241269394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.241269394
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3520878244
Short name T468
Test name
Test status
Simulation time 146383151843 ps
CPU time 35.14 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:52 PM PDT 24
Peak memory 200872 kb
Host smart-957479c4-40ae-42c0-a1a1-8cec1b56e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520878244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3520878244
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2081187084
Short name T684
Test name
Test status
Simulation time 88128181741 ps
CPU time 27.08 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:46 PM PDT 24
Peak memory 200896 kb
Host smart-c6a1c8ef-fbd7-4fdf-9669-357045c45b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081187084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2081187084
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1044394495
Short name T1061
Test name
Test status
Simulation time 332125792243 ps
CPU time 528.7 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:48:08 PM PDT 24
Peak memory 200864 kb
Host smart-1bc605f2-0938-4948-9ac7-5460d9c17335
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044394495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1044394495
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3387044600
Short name T441
Test name
Test status
Simulation time 275392153380 ps
CPU time 231.24 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:43:08 PM PDT 24
Peak memory 200880 kb
Host smart-48b9a9b3-24bf-49b3-8839-9be8743e06da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387044600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3387044600
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1861903293
Short name T813
Test name
Test status
Simulation time 8037209844 ps
CPU time 7.44 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 200288 kb
Host smart-c3e583b3-8b78-454f-905e-05877782b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861903293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1861903293
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.2012529559
Short name T107
Test name
Test status
Simulation time 86983737708 ps
CPU time 72.06 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:40:32 PM PDT 24
Peak memory 200396 kb
Host smart-2ad5174c-8bb5-4a24-aa32-f5c58d902bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012529559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2012529559
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.697410706
Short name T471
Test name
Test status
Simulation time 11107068522 ps
CPU time 623.48 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:49:43 PM PDT 24
Peak memory 200720 kb
Host smart-e6d51d7f-ed70-44ac-bbfb-1421371f0947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697410706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.697410706
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2723687024
Short name T449
Test name
Test status
Simulation time 2949574689 ps
CPU time 22.03 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:42 PM PDT 24
Peak memory 199728 kb
Host smart-e9161698-afe2-443a-b261-53c780eae641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2723687024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2723687024
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2888463675
Short name T693
Test name
Test status
Simulation time 72638102915 ps
CPU time 24.28 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:48 PM PDT 24
Peak memory 200576 kb
Host smart-b3e97a64-2a65-438b-9b7d-81f52e243d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888463675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2888463675
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.771613231
Short name T396
Test name
Test status
Simulation time 3206123449 ps
CPU time 3.12 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 196932 kb
Host smart-f5b6e311-968f-4eba-a922-58abab13467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771613231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.771613231
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3587018214
Short name T372
Test name
Test status
Simulation time 823481617 ps
CPU time 2.92 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:23 PM PDT 24
Peak memory 199820 kb
Host smart-464c884f-38a3-4dc8-b410-457da127648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587018214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3587018214
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.286838277
Short name T752
Test name
Test status
Simulation time 232277952742 ps
CPU time 386.85 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:45:51 PM PDT 24
Peak memory 200852 kb
Host smart-07a5b8f7-9a32-4db3-8c69-9cb5b06a28cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286838277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.286838277
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3067718266
Short name T116
Test name
Test status
Simulation time 22099395794 ps
CPU time 293.34 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:44:17 PM PDT 24
Peak memory 216768 kb
Host smart-56adaef9-208a-4965-a93f-a014c4163990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067718266 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3067718266
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3376581900
Short name T837
Test name
Test status
Simulation time 6190828537 ps
CPU time 18.77 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 200868 kb
Host smart-a351a63d-04f1-4fb6-83ac-1088da1ccca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376581900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3376581900
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.355381885
Short name T1168
Test name
Test status
Simulation time 31539795325 ps
CPU time 49.71 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:40:13 PM PDT 24
Peak memory 200836 kb
Host smart-6a55a9c8-c949-40de-899c-8a3a42470688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355381885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.355381885
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3013657324
Short name T1162
Test name
Test status
Simulation time 52705361437 ps
CPU time 94.56 seconds
Started Apr 16 02:42:11 PM PDT 24
Finished Apr 16 02:43:47 PM PDT 24
Peak memory 200948 kb
Host smart-505f75be-bd80-40d2-af46-5ba2c71d7c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013657324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3013657324
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.532466143
Short name T112
Test name
Test status
Simulation time 119738091111 ps
CPU time 236.93 seconds
Started Apr 16 02:42:11 PM PDT 24
Finished Apr 16 02:46:08 PM PDT 24
Peak memory 200832 kb
Host smart-9ed65a71-cdfe-4364-85e4-ba9dceac3611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532466143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.532466143
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2493118729
Short name T261
Test name
Test status
Simulation time 17122942561 ps
CPU time 16.16 seconds
Started Apr 16 02:42:13 PM PDT 24
Finished Apr 16 02:42:29 PM PDT 24
Peak memory 200884 kb
Host smart-6ada1022-93de-400a-a2b0-a6ec2a2d8b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493118729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2493118729
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3117364897
Short name T300
Test name
Test status
Simulation time 31920028688 ps
CPU time 59.18 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:43:12 PM PDT 24
Peak memory 200852 kb
Host smart-35150ab5-486d-4ccd-9e1a-6e7c3176411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117364897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3117364897
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3558977075
Short name T1182
Test name
Test status
Simulation time 26316814346 ps
CPU time 24.7 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:42:38 PM PDT 24
Peak memory 200864 kb
Host smart-20be7a2b-dad6-464a-ac59-05c0d8291831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558977075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3558977075
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4055618519
Short name T313
Test name
Test status
Simulation time 50561363302 ps
CPU time 23.31 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:42:36 PM PDT 24
Peak memory 200656 kb
Host smart-22898a26-63ba-4858-9b3a-0da2432e9f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055618519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4055618519
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.98487937
Short name T1010
Test name
Test status
Simulation time 102425469 ps
CPU time 0.55 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:20 PM PDT 24
Peak memory 196048 kb
Host smart-f6b44974-9c19-4634-b4dd-b490594b5dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98487937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.98487937
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3333080047
Short name T797
Test name
Test status
Simulation time 213849907433 ps
CPU time 88.24 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:40:53 PM PDT 24
Peak memory 200744 kb
Host smart-a5a22304-cb4a-4745-b4d4-3cd126e8d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333080047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3333080047
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1238276571
Short name T743
Test name
Test status
Simulation time 93571914267 ps
CPU time 279.53 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:44:04 PM PDT 24
Peak memory 200820 kb
Host smart-add5db94-91de-4f3c-9848-8e74e01afdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238276571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1238276571
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1311658367
Short name T788
Test name
Test status
Simulation time 163563916785 ps
CPU time 86.67 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:40:47 PM PDT 24
Peak memory 200848 kb
Host smart-6d182596-ef69-4f49-8a22-618610387654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311658367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1311658367
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2743961769
Short name T831
Test name
Test status
Simulation time 289045023953 ps
CPU time 432.7 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:46:33 PM PDT 24
Peak memory 200900 kb
Host smart-b4bc3b7f-6a89-4968-b95b-10a554217881
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743961769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2743961769
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1272317764
Short name T869
Test name
Test status
Simulation time 67591374075 ps
CPU time 305.17 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:44:23 PM PDT 24
Peak memory 200804 kb
Host smart-feac74db-b17b-4dc6-9c10-fafc0edc8705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272317764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1272317764
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2114504013
Short name T566
Test name
Test status
Simulation time 8877293027 ps
CPU time 5.18 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 199636 kb
Host smart-3b66ac06-0100-4c85-bfbc-db61a57e65df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114504013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2114504013
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.206897599
Short name T52
Test name
Test status
Simulation time 14088104858 ps
CPU time 338.71 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:44:56 PM PDT 24
Peak memory 200852 kb
Host smart-89887475-7703-438a-9fef-884a1786ea7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=206897599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.206897599
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.709673005
Short name T429
Test name
Test status
Simulation time 2427295451 ps
CPU time 2.95 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 198792 kb
Host smart-663bfef3-0520-43a9-891b-b57a254b6396
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709673005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.709673005
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.273519485
Short name T17
Test name
Test status
Simulation time 110248856647 ps
CPU time 198.95 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:42:39 PM PDT 24
Peak memory 200868 kb
Host smart-1a0bfc5b-8ee3-42b2-8020-66f4ca4c968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273519485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.273519485
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2828199132
Short name T615
Test name
Test status
Simulation time 1133216032 ps
CPU time 2.73 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 196192 kb
Host smart-9882f1cd-3bf6-4623-b15c-c271366c4b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828199132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2828199132
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.1472761592
Short name T480
Test name
Test status
Simulation time 11169814670 ps
CPU time 7.66 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:27 PM PDT 24
Peak memory 200728 kb
Host smart-af4ccca4-f48a-4b5c-b214-395110a8c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472761592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1472761592
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2706724768
Short name T977
Test name
Test status
Simulation time 319164338729 ps
CPU time 144.6 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:41:44 PM PDT 24
Peak memory 200908 kb
Host smart-8dea1ad7-67e4-45f9-91d8-9004380bef37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706724768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2706724768
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3104368403
Short name T650
Test name
Test status
Simulation time 127303971725 ps
CPU time 375.03 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:45:37 PM PDT 24
Peak memory 217576 kb
Host smart-d4b957bb-d282-47be-a5d8-0aeaf8226cbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104368403 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3104368403
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1507393600
Short name T830
Test name
Test status
Simulation time 613893887 ps
CPU time 2.1 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:17 PM PDT 24
Peak memory 200128 kb
Host smart-996abed2-3c36-4d4f-b440-fed38f40a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507393600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1507393600
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3692151215
Short name T1006
Test name
Test status
Simulation time 140261590582 ps
CPU time 12.1 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:32 PM PDT 24
Peak memory 200084 kb
Host smart-a9f41ed9-b54f-4008-8350-a178bf94ee5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692151215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3692151215
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2581266161
Short name T325
Test name
Test status
Simulation time 23743086259 ps
CPU time 14.52 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:42:27 PM PDT 24
Peak memory 200836 kb
Host smart-679dc496-d587-4a57-a083-4b0bafb4ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581266161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2581266161
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1124151438
Short name T846
Test name
Test status
Simulation time 138109344015 ps
CPU time 56.41 seconds
Started Apr 16 02:42:13 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200920 kb
Host smart-f1e948b1-0f81-4896-9b69-7fd7ef1ab460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124151438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1124151438
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.920859205
Short name T49
Test name
Test status
Simulation time 17746453299 ps
CPU time 7.18 seconds
Started Apr 16 02:42:11 PM PDT 24
Finished Apr 16 02:42:19 PM PDT 24
Peak memory 200476 kb
Host smart-ebb353eb-7473-49c0-8acf-90a598091cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920859205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.920859205
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3120946487
Short name T1076
Test name
Test status
Simulation time 85809567682 ps
CPU time 128.04 seconds
Started Apr 16 02:42:13 PM PDT 24
Finished Apr 16 02:44:21 PM PDT 24
Peak memory 200892 kb
Host smart-1da24a5e-d767-4ded-8990-7eccadce48f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120946487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3120946487
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1369463686
Short name T1138
Test name
Test status
Simulation time 71100215073 ps
CPU time 28.57 seconds
Started Apr 16 02:42:15 PM PDT 24
Finished Apr 16 02:42:45 PM PDT 24
Peak memory 200752 kb
Host smart-12578c12-ba65-493d-b49f-3742396cc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369463686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1369463686
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1391373522
Short name T736
Test name
Test status
Simulation time 29991546026 ps
CPU time 47.36 seconds
Started Apr 16 02:42:12 PM PDT 24
Finished Apr 16 02:43:00 PM PDT 24
Peak memory 200928 kb
Host smart-75be96e8-7d2d-498b-b566-f0d4047dde33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391373522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1391373522
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3111228334
Short name T267
Test name
Test status
Simulation time 101091899217 ps
CPU time 47.92 seconds
Started Apr 16 02:42:21 PM PDT 24
Finished Apr 16 02:43:09 PM PDT 24
Peak memory 200792 kb
Host smart-eab92723-f0c7-4cdb-b938-c48ee21fbbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111228334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3111228334
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2139201016
Short name T891
Test name
Test status
Simulation time 32331470087 ps
CPU time 54.26 seconds
Started Apr 16 02:42:19 PM PDT 24
Finished Apr 16 02:43:14 PM PDT 24
Peak memory 200904 kb
Host smart-0acead10-1b34-4a61-ba69-578de3bfc602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139201016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2139201016
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2703133311
Short name T964
Test name
Test status
Simulation time 33013073474 ps
CPU time 16.65 seconds
Started Apr 16 02:42:15 PM PDT 24
Finished Apr 16 02:42:33 PM PDT 24
Peak memory 200820 kb
Host smart-8682f1b4-e513-4aec-8650-460872e3e321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703133311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2703133311
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.859980856
Short name T661
Test name
Test status
Simulation time 58158727119 ps
CPU time 29.34 seconds
Started Apr 16 02:42:17 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200828 kb
Host smart-aedf6f8d-334a-4a51-a98d-5c1bff70f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859980856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.859980856
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3824406769
Short name T608
Test name
Test status
Simulation time 26334157 ps
CPU time 0.58 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 196248 kb
Host smart-0228fc31-cfad-40d3-a5e1-d994b4552406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824406769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3824406769
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2323327472
Short name T825
Test name
Test status
Simulation time 118112927585 ps
CPU time 300.16 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:44:25 PM PDT 24
Peak memory 200860 kb
Host smart-8831cf08-76ce-40ed-b64b-4666458303ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323327472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2323327472
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1683260729
Short name T405
Test name
Test status
Simulation time 87698373105 ps
CPU time 143.02 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:41:44 PM PDT 24
Peak memory 200880 kb
Host smart-53cec008-4eb4-42af-b248-991fde64a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683260729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1683260729
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1548125550
Short name T791
Test name
Test status
Simulation time 31243627554 ps
CPU time 6.54 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 200596 kb
Host smart-bb682bdc-dda9-4737-b14a-aab092e8703a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548125550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1548125550
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.586916447
Short name T1063
Test name
Test status
Simulation time 265072234167 ps
CPU time 138.49 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:41:38 PM PDT 24
Peak memory 200808 kb
Host smart-46b2d2fc-7dcd-424e-95b3-c0a352e78e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586916447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.586916447
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1779336143
Short name T7
Test name
Test status
Simulation time 8108533795 ps
CPU time 4.44 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 199376 kb
Host smart-c2ac2eca-d1ec-4249-b51a-c7ba8e6c5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779336143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1779336143
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1166522909
Short name T589
Test name
Test status
Simulation time 23920790283 ps
CPU time 42.05 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:59 PM PDT 24
Peak memory 198192 kb
Host smart-de0ca15f-9f9e-4383-ad28-d6756ec4a93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166522909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1166522909
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2088647828
Short name T469
Test name
Test status
Simulation time 25667700055 ps
CPU time 83.93 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:40:48 PM PDT 24
Peak memory 200416 kb
Host smart-23c15c5c-379a-49cf-9548-385a87130437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088647828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2088647828
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4261928443
Short name T842
Test name
Test status
Simulation time 1822923837 ps
CPU time 2.07 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 198872 kb
Host smart-1a312431-0e64-4aae-85d3-8b30a62c5b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261928443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4261928443
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3066838254
Short name T1051
Test name
Test status
Simulation time 131613790701 ps
CPU time 125.94 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:41:25 PM PDT 24
Peak memory 200632 kb
Host smart-422e9d9d-9d01-48cd-802d-5d089c4e78e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066838254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3066838254
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1413987176
Short name T642
Test name
Test status
Simulation time 5032881583 ps
CPU time 1.38 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 196380 kb
Host smart-28d3133a-4181-4ab2-b1ad-078725a26317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413987176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1413987176
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3567513528
Short name T397
Test name
Test status
Simulation time 5355920600 ps
CPU time 20.01 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 200632 kb
Host smart-a4e56775-d6e1-408d-92e1-804c487930b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567513528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3567513528
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2381952712
Short name T690
Test name
Test status
Simulation time 60143489532 ps
CPU time 101.87 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:41:05 PM PDT 24
Peak memory 200872 kb
Host smart-ea113641-c6c1-4fda-acf2-3f6b8897e3b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381952712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2381952712
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1909514104
Short name T1164
Test name
Test status
Simulation time 82655757885 ps
CPU time 1168.41 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:58:53 PM PDT 24
Peak memory 217328 kb
Host smart-ca664609-45e9-4727-818b-44d469e70d75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909514104 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1909514104
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3903660521
Short name T404
Test name
Test status
Simulation time 353780787 ps
CPU time 1.79 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:25 PM PDT 24
Peak memory 199656 kb
Host smart-fae2cb81-554e-408e-b3fe-a7135de6026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903660521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3903660521
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1450050467
Short name T491
Test name
Test status
Simulation time 66936194926 ps
CPU time 62.08 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:40:27 PM PDT 24
Peak memory 200860 kb
Host smart-fde62ab0-316e-4572-be6a-7d36258d7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450050467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1450050467
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.43543974
Short name T283
Test name
Test status
Simulation time 103619019681 ps
CPU time 261.38 seconds
Started Apr 16 02:42:20 PM PDT 24
Finished Apr 16 02:46:42 PM PDT 24
Peak memory 200864 kb
Host smart-63c2fc2e-7945-4bc3-a8d9-71cd8731413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43543974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.43543974
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3969182435
Short name T1067
Test name
Test status
Simulation time 25367925751 ps
CPU time 29.66 seconds
Started Apr 16 02:42:16 PM PDT 24
Finished Apr 16 02:42:46 PM PDT 24
Peak memory 200908 kb
Host smart-338308d3-73c8-47f5-a825-2ecfce6217a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969182435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3969182435
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1758776620
Short name T464
Test name
Test status
Simulation time 66974600089 ps
CPU time 30.7 seconds
Started Apr 16 02:42:19 PM PDT 24
Finished Apr 16 02:42:51 PM PDT 24
Peak memory 200872 kb
Host smart-d9c417b3-3a96-4e67-994e-1c99f7b48503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758776620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1758776620
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1168103582
Short name T1146
Test name
Test status
Simulation time 21453679583 ps
CPU time 10.75 seconds
Started Apr 16 02:42:13 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 200208 kb
Host smart-fe4a1739-020e-402e-a66f-74184558ed48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168103582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1168103582
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3489588980
Short name T176
Test name
Test status
Simulation time 131461903393 ps
CPU time 59.06 seconds
Started Apr 16 02:42:13 PM PDT 24
Finished Apr 16 02:43:13 PM PDT 24
Peak memory 200856 kb
Host smart-4eab5170-f522-4514-aba9-cec10d1a4754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489588980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3489588980
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.880196330
Short name T1002
Test name
Test status
Simulation time 17567182424 ps
CPU time 34.94 seconds
Started Apr 16 02:42:21 PM PDT 24
Finished Apr 16 02:42:57 PM PDT 24
Peak memory 200908 kb
Host smart-dbd07dd3-da4a-4ac9-9eda-51133dd1b7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880196330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.880196330
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1019880443
Short name T1032
Test name
Test status
Simulation time 5293933419 ps
CPU time 10.32 seconds
Started Apr 16 02:42:18 PM PDT 24
Finished Apr 16 02:42:29 PM PDT 24
Peak memory 200912 kb
Host smart-51e0fd5e-6cfd-4cff-a1ac-27c680bf064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019880443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1019880443
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3767907980
Short name T1088
Test name
Test status
Simulation time 157494336583 ps
CPU time 33.8 seconds
Started Apr 16 02:42:18 PM PDT 24
Finished Apr 16 02:42:53 PM PDT 24
Peak memory 200864 kb
Host smart-02e72558-dcf9-4110-bdb8-c3507751ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767907980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3767907980
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3466426199
Short name T716
Test name
Test status
Simulation time 13506816 ps
CPU time 0.59 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 196208 kb
Host smart-a64bbf9a-4782-4e32-a56a-5a4d92b3c41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466426199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3466426199
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3353701146
Short name T159
Test name
Test status
Simulation time 84627349850 ps
CPU time 37.7 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:40:02 PM PDT 24
Peak memory 200796 kb
Host smart-17a786d4-aa89-43d8-9ea6-cd032783bff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353701146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3353701146
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2855614369
Short name T1156
Test name
Test status
Simulation time 37740782262 ps
CPU time 69.43 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:40:32 PM PDT 24
Peak memory 200824 kb
Host smart-d9cbd59f-62c7-4bdd-89e8-38b27e451fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855614369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2855614369
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.3750868471
Short name T632
Test name
Test status
Simulation time 104499763004 ps
CPU time 48.63 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:40:11 PM PDT 24
Peak memory 200892 kb
Host smart-66649f0a-8ba0-4614-8cc8-ccf2226ba081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750868471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3750868471
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2965449394
Short name T517
Test name
Test status
Simulation time 19303870555 ps
CPU time 33.08 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 198676 kb
Host smart-098cf942-9ff0-4d5d-bf2b-984e6a17e464
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965449394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2965449394
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1104805044
Short name T578
Test name
Test status
Simulation time 306101167128 ps
CPU time 222.38 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:43:07 PM PDT 24
Peak memory 200828 kb
Host smart-16a23924-8ae9-423f-ba29-5e1210f77c54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104805044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1104805044
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3741137296
Short name T123
Test name
Test status
Simulation time 763762557 ps
CPU time 0.97 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 196952 kb
Host smart-3a201b4a-7cf9-4c26-bc5f-e01d8368bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741137296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3741137296
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3535697634
Short name T39
Test name
Test status
Simulation time 196664353166 ps
CPU time 39.65 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:40:05 PM PDT 24
Peak memory 201000 kb
Host smart-3185f668-36c1-46dc-aa3c-b50012e36584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535697634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3535697634
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.411803268
Short name T664
Test name
Test status
Simulation time 25491895982 ps
CPU time 1388.64 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 03:02:28 PM PDT 24
Peak memory 200860 kb
Host smart-49db85a2-854d-415c-9b3d-b4a886360f18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411803268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.411803268
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3144904080
Short name T374
Test name
Test status
Simulation time 7328440675 ps
CPU time 32.66 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 199984 kb
Host smart-458394e2-1114-4421-a5d8-746f58ae2b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3144904080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3144904080
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1412526728
Short name T160
Test name
Test status
Simulation time 82746043969 ps
CPU time 84.18 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 200836 kb
Host smart-2ae6b522-e01d-4093-b0ef-277dc74b6099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412526728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1412526728
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2597454435
Short name T1175
Test name
Test status
Simulation time 5605300877 ps
CPU time 2.91 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 196884 kb
Host smart-91403a40-838e-46b6-95c8-16f7c2f357f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597454435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2597454435
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3070135780
Short name T965
Test name
Test status
Simulation time 292097662 ps
CPU time 1.26 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 199052 kb
Host smart-9f0c67fe-305e-4780-a4d7-18a1f532eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070135780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3070135780
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1164613612
Short name T1047
Test name
Test status
Simulation time 162473954363 ps
CPU time 67.3 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:40:30 PM PDT 24
Peak memory 200908 kb
Host smart-114bd188-7d4c-425b-9177-0035eee64dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164613612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1164613612
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.1997692873
Short name T855
Test name
Test status
Simulation time 918969021 ps
CPU time 1.43 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 199180 kb
Host smart-90106700-6249-4654-a214-fb52d50024bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997692873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1997692873
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1046412231
Short name T586
Test name
Test status
Simulation time 118811689259 ps
CPU time 23.52 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:41 PM PDT 24
Peak memory 200796 kb
Host smart-3169dd34-5ae0-48f9-af4a-be6406cf674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046412231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1046412231
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3513633287
Short name T461
Test name
Test status
Simulation time 66377316418 ps
CPU time 50.91 seconds
Started Apr 16 02:42:21 PM PDT 24
Finished Apr 16 02:43:13 PM PDT 24
Peak memory 200856 kb
Host smart-de44116a-d3c6-432d-ace7-73a64e738d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513633287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3513633287
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.208732604
Short name T923
Test name
Test status
Simulation time 54231411885 ps
CPU time 39.65 seconds
Started Apr 16 02:42:18 PM PDT 24
Finished Apr 16 02:42:58 PM PDT 24
Peak memory 200864 kb
Host smart-3114276e-80e7-454d-b227-59c9f6eafd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208732604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.208732604
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.215648022
Short name T187
Test name
Test status
Simulation time 189577455136 ps
CPU time 55.5 seconds
Started Apr 16 02:42:18 PM PDT 24
Finished Apr 16 02:43:15 PM PDT 24
Peak memory 200840 kb
Host smart-21450dce-c93c-4c26-8da7-75bdda5b65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215648022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.215648022
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1129326178
Short name T742
Test name
Test status
Simulation time 16948015381 ps
CPU time 16.36 seconds
Started Apr 16 02:42:20 PM PDT 24
Finished Apr 16 02:42:37 PM PDT 24
Peak memory 200624 kb
Host smart-fcdd31b6-185c-4e9d-9d2b-ecc26777ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129326178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1129326178
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4036702218
Short name T760
Test name
Test status
Simulation time 51434631808 ps
CPU time 48.53 seconds
Started Apr 16 02:42:19 PM PDT 24
Finished Apr 16 02:43:08 PM PDT 24
Peak memory 200908 kb
Host smart-334070f3-f60f-48a8-be73-19aae85a89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036702218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4036702218
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2285335805
Short name T1019
Test name
Test status
Simulation time 138818743197 ps
CPU time 67.2 seconds
Started Apr 16 02:42:16 PM PDT 24
Finished Apr 16 02:43:24 PM PDT 24
Peak memory 200676 kb
Host smart-0b77cbbd-b700-448f-bad8-bf6ad23ab665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285335805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2285335805
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3465781753
Short name T358
Test name
Test status
Simulation time 9643913485 ps
CPU time 19.02 seconds
Started Apr 16 02:42:19 PM PDT 24
Finished Apr 16 02:42:38 PM PDT 24
Peak memory 200824 kb
Host smart-f2de076a-d850-4681-a03f-fbc717a433ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465781753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3465781753
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2120502230
Short name T435
Test name
Test status
Simulation time 44893852 ps
CPU time 0.55 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 195628 kb
Host smart-07054bef-7384-4ca0-a28e-c9e4928a761d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120502230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2120502230
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3200203635
Short name T689
Test name
Test status
Simulation time 291867118734 ps
CPU time 307.76 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:44:30 PM PDT 24
Peak memory 200832 kb
Host smart-834671ee-ad7d-437f-93c6-6ec2c9b154b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200203635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3200203635
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.610103633
Short name T898
Test name
Test status
Simulation time 43356044171 ps
CPU time 27.45 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:48 PM PDT 24
Peak memory 200844 kb
Host smart-7b4b9bd5-1d9d-4517-a9f9-e37571ec1e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610103633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.610103633
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2731270746
Short name T1181
Test name
Test status
Simulation time 56787336548 ps
CPU time 28.08 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:50 PM PDT 24
Peak memory 200820 kb
Host smart-5580765e-ee0f-47da-89db-498151626a4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731270746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2731270746
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4036151663
Short name T782
Test name
Test status
Simulation time 234841167336 ps
CPU time 243.46 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:43:26 PM PDT 24
Peak memory 200872 kb
Host smart-7c565478-b474-4517-b291-6b3be791bd86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036151663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4036151663
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.389316329
Short name T466
Test name
Test status
Simulation time 822179965 ps
CPU time 2.23 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:23 PM PDT 24
Peak memory 196948 kb
Host smart-9ac020a6-8257-45dd-8762-e94d3b47e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389316329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.389316329
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.450525883
Short name T383
Test name
Test status
Simulation time 61949392380 ps
CPU time 96.42 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:40:57 PM PDT 24
Peak memory 209208 kb
Host smart-6f558f74-572a-440c-a3a2-ffbcd7b0631a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450525883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.450525883
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2944609201
Short name T906
Test name
Test status
Simulation time 9612258584 ps
CPU time 93.89 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:40:57 PM PDT 24
Peak memory 200948 kb
Host smart-ed3ddf9c-8464-4fd4-be61-201f0067febe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944609201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2944609201
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1238636372
Short name T603
Test name
Test status
Simulation time 5853507731 ps
CPU time 27.12 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:50 PM PDT 24
Peak memory 199572 kb
Host smart-ce8e8a61-3b52-49ef-8ad1-7925f699ae4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238636372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1238636372
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2042360027
Short name T458
Test name
Test status
Simulation time 20513850179 ps
CPU time 18.53 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:41 PM PDT 24
Peak memory 200744 kb
Host smart-fb3b5374-3c62-4688-a0be-2f1870be830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042360027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2042360027
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1222864532
Short name T769
Test name
Test status
Simulation time 77059066214 ps
CPU time 17.73 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 196904 kb
Host smart-0f177ae3-e0f0-426f-8545-1a34ff4b440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222864532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1222864532
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.156491968
Short name T948
Test name
Test status
Simulation time 130000278 ps
CPU time 0.87 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:23 PM PDT 24
Peak memory 197800 kb
Host smart-b9b5ea03-ae24-4dda-8205-d4e225ce953b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156491968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.156491968
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1092934729
Short name T436
Test name
Test status
Simulation time 23458646719 ps
CPU time 36.09 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 200904 kb
Host smart-053a736f-3f9b-45a6-ba01-cb7cb4a23cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092934729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1092934729
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.81030698
Short name T1075
Test name
Test status
Simulation time 1372710728 ps
CPU time 2.11 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 200292 kb
Host smart-26655191-a606-4d44-923e-fd2c96ab6606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81030698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.81030698
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1548699219
Short name T877
Test name
Test status
Simulation time 21712862816 ps
CPU time 16.92 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 200804 kb
Host smart-6ce03471-3417-4aa9-a8bc-ab87bdf3f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548699219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1548699219
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3454993349
Short name T1015
Test name
Test status
Simulation time 100233287323 ps
CPU time 81.29 seconds
Started Apr 16 02:42:25 PM PDT 24
Finished Apr 16 02:43:47 PM PDT 24
Peak memory 200868 kb
Host smart-4a5ac0a9-0fb9-47d6-8e39-cf6a2373ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454993349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3454993349
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3497877686
Short name T1163
Test name
Test status
Simulation time 260265943372 ps
CPU time 77.49 seconds
Started Apr 16 02:42:24 PM PDT 24
Finished Apr 16 02:43:42 PM PDT 24
Peak memory 200908 kb
Host smart-7a4204e4-13fe-4baf-b33a-d952fa726b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497877686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3497877686
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3020915515
Short name T225
Test name
Test status
Simulation time 74443781549 ps
CPU time 204.58 seconds
Started Apr 16 02:42:25 PM PDT 24
Finished Apr 16 02:45:50 PM PDT 24
Peak memory 200816 kb
Host smart-a1a92a0f-bf9a-4fdc-b2da-5d73bc29753d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020915515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3020915515
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3416840567
Short name T109
Test name
Test status
Simulation time 30948918349 ps
CPU time 35.57 seconds
Started Apr 16 02:42:24 PM PDT 24
Finished Apr 16 02:43:00 PM PDT 24
Peak memory 200912 kb
Host smart-19bbad69-6ab7-4c6f-b2f9-d2ff7b8a28d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416840567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3416840567
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2112976951
Short name T428
Test name
Test status
Simulation time 72972690322 ps
CPU time 28.83 seconds
Started Apr 16 02:42:24 PM PDT 24
Finished Apr 16 02:42:53 PM PDT 24
Peak memory 200624 kb
Host smart-2cc6f821-ba00-4baf-adc5-03426be46903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112976951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2112976951
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.99156013
Short name T582
Test name
Test status
Simulation time 116016312534 ps
CPU time 61.39 seconds
Started Apr 16 02:42:22 PM PDT 24
Finished Apr 16 02:43:23 PM PDT 24
Peak memory 200884 kb
Host smart-dac70853-1f85-4d3e-81c1-6370bc668cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99156013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.99156013
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1792758248
Short name T311
Test name
Test status
Simulation time 24441646638 ps
CPU time 70.43 seconds
Started Apr 16 02:42:24 PM PDT 24
Finished Apr 16 02:43:35 PM PDT 24
Peak memory 200936 kb
Host smart-fefd25fb-0fb8-46e8-9e06-faca14e2bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792758248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1792758248
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1231518986
Short name T551
Test name
Test status
Simulation time 115447121888 ps
CPU time 47.72 seconds
Started Apr 16 02:42:22 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200684 kb
Host smart-4ceacce4-5547-43d5-aff9-6281cc77e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231518986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1231518986
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1581635099
Short name T926
Test name
Test status
Simulation time 219932646797 ps
CPU time 31.16 seconds
Started Apr 16 02:42:22 PM PDT 24
Finished Apr 16 02:42:54 PM PDT 24
Peak memory 200864 kb
Host smart-7d1e4861-db62-4857-b437-e985f6073d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581635099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1581635099
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1817729404
Short name T905
Test name
Test status
Simulation time 68074068706 ps
CPU time 15.9 seconds
Started Apr 16 02:42:23 PM PDT 24
Finished Apr 16 02:42:39 PM PDT 24
Peak memory 200836 kb
Host smart-2b29b342-68fa-401f-9614-3fabc2e2abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817729404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1817729404
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4164061103
Short name T682
Test name
Test status
Simulation time 12254691 ps
CPU time 0.58 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:39:30 PM PDT 24
Peak memory 196208 kb
Host smart-99bcaea5-b254-4431-9059-f9d62b33b1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164061103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4164061103
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1890433199
Short name T950
Test name
Test status
Simulation time 8422008941 ps
CPU time 12.42 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:33 PM PDT 24
Peak memory 200884 kb
Host smart-41aa28ce-b945-4d96-9c0f-603a7b8f407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890433199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1890433199
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.64089907
Short name T696
Test name
Test status
Simulation time 50420616559 ps
CPU time 81.85 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:40:46 PM PDT 24
Peak memory 200792 kb
Host smart-37c9207e-4896-49ed-bb77-8204169af262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64089907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.64089907
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4018472239
Short name T447
Test name
Test status
Simulation time 14766821076 ps
CPU time 22.5 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:39:48 PM PDT 24
Peak memory 200660 kb
Host smart-5760140a-e51e-41be-884d-0396d224f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018472239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4018472239
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3993087527
Short name T1049
Test name
Test status
Simulation time 21899761843 ps
CPU time 41.58 seconds
Started Apr 16 02:39:26 PM PDT 24
Finished Apr 16 02:40:08 PM PDT 24
Peak memory 200576 kb
Host smart-a282cae4-4291-4927-815c-a150cd5b4323
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993087527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3993087527
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2335227484
Short name T629
Test name
Test status
Simulation time 148562959388 ps
CPU time 207 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:42:53 PM PDT 24
Peak memory 200888 kb
Host smart-d4429bae-7a87-418a-b8ee-3afc666580e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335227484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2335227484
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.484136087
Short name T359
Test name
Test status
Simulation time 14774663550 ps
CPU time 4.18 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 200828 kb
Host smart-2d5b421b-addd-4aa1-9d5c-ef3aac6b0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484136087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.484136087
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1595599410
Short name T1072
Test name
Test status
Simulation time 86383837351 ps
CPU time 168.75 seconds
Started Apr 16 02:39:26 PM PDT 24
Finished Apr 16 02:42:15 PM PDT 24
Peak memory 208956 kb
Host smart-33d09fb7-6796-45bf-824d-b6bcbf0a899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595599410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1595599410
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.152641919
Short name T500
Test name
Test status
Simulation time 27476795235 ps
CPU time 73.66 seconds
Started Apr 16 02:39:25 PM PDT 24
Finished Apr 16 02:40:40 PM PDT 24
Peak memory 200828 kb
Host smart-62e2a843-54bd-4f0b-810d-17d8faf93e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152641919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.152641919
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3525555148
Short name T1131
Test name
Test status
Simulation time 2406009796 ps
CPU time 15.71 seconds
Started Apr 16 02:39:28 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 198772 kb
Host smart-ef9bc0fc-3cd1-4634-856b-f2d8d1525a00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525555148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3525555148
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1460262095
Short name T912
Test name
Test status
Simulation time 52901013476 ps
CPU time 88.23 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:40:53 PM PDT 24
Peak memory 200856 kb
Host smart-b47346b6-6dfc-4ada-a819-80a97ccf2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460262095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1460262095
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2944626918
Short name T351
Test name
Test status
Simulation time 1684979300 ps
CPU time 3.11 seconds
Started Apr 16 02:39:26 PM PDT 24
Finished Apr 16 02:39:30 PM PDT 24
Peak memory 196268 kb
Host smart-eac30f35-edb1-464d-9674-942fd327788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944626918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2944626918
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3461437008
Short name T501
Test name
Test status
Simulation time 811009495 ps
CPU time 1.31 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 199568 kb
Host smart-575ce132-f288-4d55-9fb0-f974049ee737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461437008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3461437008
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2644847732
Short name T903
Test name
Test status
Simulation time 2929093719 ps
CPU time 2.01 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:39:27 PM PDT 24
Peak memory 199880 kb
Host smart-3a892020-3eca-45ee-92e5-6bbf84baaa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644847732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2644847732
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2856767096
Short name T371
Test name
Test status
Simulation time 8523637878 ps
CPU time 7.12 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:27 PM PDT 24
Peak memory 199656 kb
Host smart-535aa0e2-4621-49b9-b064-a7d893cf34f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856767096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2856767096
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4182617903
Short name T137
Test name
Test status
Simulation time 25348189011 ps
CPU time 26.06 seconds
Started Apr 16 02:42:22 PM PDT 24
Finished Apr 16 02:42:49 PM PDT 24
Peak memory 200872 kb
Host smart-01c76150-1177-49dc-a4e6-25155e982813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182617903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4182617903
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.668883426
Short name T181
Test name
Test status
Simulation time 32937758012 ps
CPU time 15.86 seconds
Started Apr 16 02:42:24 PM PDT 24
Finished Apr 16 02:42:40 PM PDT 24
Peak memory 200848 kb
Host smart-e9efe7f6-ee0e-407b-8bc9-3cc5af099f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668883426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.668883426
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2225690696
Short name T211
Test name
Test status
Simulation time 127495274454 ps
CPU time 202.12 seconds
Started Apr 16 02:42:22 PM PDT 24
Finished Apr 16 02:45:44 PM PDT 24
Peak memory 200892 kb
Host smart-bafb3a5b-f32b-4b0a-ba61-b5acf984fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225690696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2225690696
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.1094843667
Short name T259
Test name
Test status
Simulation time 44056365566 ps
CPU time 73.71 seconds
Started Apr 16 02:42:27 PM PDT 24
Finished Apr 16 02:43:42 PM PDT 24
Peak memory 200872 kb
Host smart-9b9e32da-5e13-434d-bf80-65b9e57e6cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094843667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1094843667
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2839331928
Short name T523
Test name
Test status
Simulation time 89777560096 ps
CPU time 162.78 seconds
Started Apr 16 02:42:28 PM PDT 24
Finished Apr 16 02:45:12 PM PDT 24
Peak memory 200892 kb
Host smart-50e2b8ba-e5c5-4962-a8b9-7e48c2d7ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839331928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2839331928
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.114231851
Short name T1024
Test name
Test status
Simulation time 146552355923 ps
CPU time 67.42 seconds
Started Apr 16 02:42:28 PM PDT 24
Finished Apr 16 02:43:36 PM PDT 24
Peak memory 200836 kb
Host smart-2ec205bb-9a44-4b57-9776-7573c7290799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114231851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.114231851
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1672693674
Short name T1117
Test name
Test status
Simulation time 157729682723 ps
CPU time 29.3 seconds
Started Apr 16 02:42:30 PM PDT 24
Finished Apr 16 02:43:00 PM PDT 24
Peak memory 200868 kb
Host smart-80044980-8ceb-4f29-9127-af20c0b57037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672693674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1672693674
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2600454987
Short name T330
Test name
Test status
Simulation time 210264698299 ps
CPU time 142.97 seconds
Started Apr 16 02:42:33 PM PDT 24
Finished Apr 16 02:44:57 PM PDT 24
Peak memory 200796 kb
Host smart-ae5dfc87-ec76-418b-af6f-621eda2e6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600454987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2600454987
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1263209408
Short name T208
Test name
Test status
Simulation time 105677945836 ps
CPU time 72.48 seconds
Started Apr 16 02:42:32 PM PDT 24
Finished Apr 16 02:43:45 PM PDT 24
Peak memory 200860 kb
Host smart-7f3af65e-612a-44e3-978a-bd79973b16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263209408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1263209408
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2641658566
Short name T670
Test name
Test status
Simulation time 13377887 ps
CPU time 0.55 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:39:34 PM PDT 24
Peak memory 196192 kb
Host smart-015f6950-4df9-4bc6-b639-7eda8d9d8dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641658566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2641658566
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1526315574
Short name T822
Test name
Test status
Simulation time 13823235653 ps
CPU time 7.72 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:39:33 PM PDT 24
Peak memory 200400 kb
Host smart-9b895401-d768-4510-a765-1b827d24bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526315574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1526315574
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3173795722
Short name T635
Test name
Test status
Simulation time 55862646284 ps
CPU time 25.15 seconds
Started Apr 16 02:39:27 PM PDT 24
Finished Apr 16 02:39:53 PM PDT 24
Peak memory 200908 kb
Host smart-5a49296b-6175-49a2-8ca6-9b08679d3363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173795722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3173795722
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2527460147
Short name T1034
Test name
Test status
Simulation time 64381911200 ps
CPU time 30.53 seconds
Started Apr 16 02:39:37 PM PDT 24
Finished Apr 16 02:40:08 PM PDT 24
Peak memory 200792 kb
Host smart-ac9dc100-61ea-4e4d-b33d-91cadc890436
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527460147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2527460147
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1524218869
Short name T426
Test name
Test status
Simulation time 93811796320 ps
CPU time 631.67 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:50:13 PM PDT 24
Peak memory 200880 kb
Host smart-709778c3-8226-481e-9c66-8ddc0f083dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524218869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1524218869
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.781350628
Short name T337
Test name
Test status
Simulation time 11350726069 ps
CPU time 12.09 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 200800 kb
Host smart-1dcef790-d0f7-4b29-955f-bc7ce4896968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781350628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.781350628
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2061614316
Short name T433
Test name
Test status
Simulation time 134547216590 ps
CPU time 54.16 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:40:27 PM PDT 24
Peak memory 200936 kb
Host smart-2f5e99fb-42ee-4c50-8dc9-775680eeab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061614316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2061614316
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.4267656632
Short name T685
Test name
Test status
Simulation time 21119510111 ps
CPU time 1250.3 seconds
Started Apr 16 02:39:35 PM PDT 24
Finished Apr 16 03:00:26 PM PDT 24
Peak memory 200932 kb
Host smart-49523e2f-d0f9-452c-88ee-8f55b67c0e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267656632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4267656632
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3266407108
Short name T653
Test name
Test status
Simulation time 4323463899 ps
CPU time 2.76 seconds
Started Apr 16 02:39:24 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 198764 kb
Host smart-de582142-818d-47d2-ba54-452c207ecf81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266407108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3266407108
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.876603110
Short name T852
Test name
Test status
Simulation time 149176756849 ps
CPU time 63.42 seconds
Started Apr 16 02:39:36 PM PDT 24
Finished Apr 16 02:40:40 PM PDT 24
Peak memory 200820 kb
Host smart-1e8e38d0-c6e0-4919-950d-af7653fb9652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876603110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.876603110
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2831038173
Short name T399
Test name
Test status
Simulation time 4451940291 ps
CPU time 2.37 seconds
Started Apr 16 02:39:28 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 196888 kb
Host smart-6bbd20a4-e0f7-4ca7-bb1e-602efcda5fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831038173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2831038173
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1327953205
Short name T1037
Test name
Test status
Simulation time 646879461 ps
CPU time 1.46 seconds
Started Apr 16 02:39:25 PM PDT 24
Finished Apr 16 02:39:27 PM PDT 24
Peak memory 199208 kb
Host smart-dc16c666-ef14-4003-91fb-08a2412e6765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327953205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1327953205
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2343156743
Short name T968
Test name
Test status
Simulation time 160061843108 ps
CPU time 120.08 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:41:46 PM PDT 24
Peak memory 200856 kb
Host smart-a43d01b1-00f0-4fd2-89ff-463312d81574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343156743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2343156743
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.771610130
Short name T1026
Test name
Test status
Simulation time 734880343748 ps
CPU time 776.35 seconds
Started Apr 16 02:39:31 PM PDT 24
Finished Apr 16 02:52:28 PM PDT 24
Peak memory 225800 kb
Host smart-40df1560-5f2b-4815-b640-2d68e6827de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771610130 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.771610130
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2521395579
Short name T432
Test name
Test status
Simulation time 1321246155 ps
CPU time 4 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:39:43 PM PDT 24
Peak memory 199232 kb
Host smart-030ce555-fa3c-406a-b694-9bbe8bb6fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521395579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2521395579
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.716108575
Short name T289
Test name
Test status
Simulation time 7815580717 ps
CPU time 14.84 seconds
Started Apr 16 02:39:25 PM PDT 24
Finished Apr 16 02:39:41 PM PDT 24
Peak memory 200864 kb
Host smart-af5ad280-7317-47f9-9d13-5ff06461425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716108575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.716108575
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.636709130
Short name T1071
Test name
Test status
Simulation time 15923103212 ps
CPU time 32.46 seconds
Started Apr 16 02:42:31 PM PDT 24
Finished Apr 16 02:43:04 PM PDT 24
Peak memory 200880 kb
Host smart-657625f7-9d2d-4f52-b75e-8e98be1211ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636709130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.636709130
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1812703427
Short name T633
Test name
Test status
Simulation time 172484064570 ps
CPU time 81.54 seconds
Started Apr 16 02:42:30 PM PDT 24
Finished Apr 16 02:43:52 PM PDT 24
Peak memory 200816 kb
Host smart-8ae516fc-0924-483c-8a67-ff72d367c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812703427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1812703427
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2159752493
Short name T244
Test name
Test status
Simulation time 167792888276 ps
CPU time 50.68 seconds
Started Apr 16 02:42:31 PM PDT 24
Finished Apr 16 02:43:23 PM PDT 24
Peak memory 200888 kb
Host smart-de4d1723-2f5b-4795-a858-5309e7953b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159752493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2159752493
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1884390595
Short name T1077
Test name
Test status
Simulation time 133450602998 ps
CPU time 99 seconds
Started Apr 16 02:42:32 PM PDT 24
Finished Apr 16 02:44:12 PM PDT 24
Peak memory 200832 kb
Host smart-af25b7f4-db29-4ff3-91dd-b111cec9572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884390595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1884390595
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.139525145
Short name T717
Test name
Test status
Simulation time 20991385555 ps
CPU time 10.56 seconds
Started Apr 16 02:42:31 PM PDT 24
Finished Apr 16 02:42:42 PM PDT 24
Peak memory 200596 kb
Host smart-34eb253c-2991-4647-ab16-fff2521c42da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139525145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.139525145
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2533555666
Short name T1139
Test name
Test status
Simulation time 188187456301 ps
CPU time 77.7 seconds
Started Apr 16 02:42:31 PM PDT 24
Finished Apr 16 02:43:50 PM PDT 24
Peak memory 200712 kb
Host smart-a066e0a1-cdee-4b21-831a-8a78fbc22600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533555666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2533555666
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1539108080
Short name T707
Test name
Test status
Simulation time 121385152369 ps
CPU time 57.43 seconds
Started Apr 16 02:42:31 PM PDT 24
Finished Apr 16 02:43:29 PM PDT 24
Peak memory 200916 kb
Host smart-d29c54e5-5d39-4bae-a663-8e907b2957da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539108080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1539108080
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1643221607
Short name T1179
Test name
Test status
Simulation time 39858040661 ps
CPU time 16.95 seconds
Started Apr 16 02:42:32 PM PDT 24
Finished Apr 16 02:42:49 PM PDT 24
Peak memory 200524 kb
Host smart-3ece0d45-baf6-4cb5-96f0-d378c420ae1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643221607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1643221607
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1043894721
Short name T144
Test name
Test status
Simulation time 143104832059 ps
CPU time 57.59 seconds
Started Apr 16 02:42:37 PM PDT 24
Finished Apr 16 02:43:35 PM PDT 24
Peak memory 200892 kb
Host smart-e3743ffa-a7b4-4ec0-87d3-8ab22fb0a325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043894721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1043894721
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.255213918
Short name T183
Test name
Test status
Simulation time 136646673426 ps
CPU time 65.11 seconds
Started Apr 16 02:42:37 PM PDT 24
Finished Apr 16 02:43:43 PM PDT 24
Peak memory 200816 kb
Host smart-01c03916-ca75-4298-b4cb-0ae6b3a9098d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255213918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.255213918
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.821782924
Short name T1045
Test name
Test status
Simulation time 12420392 ps
CPU time 0.6 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:39:35 PM PDT 24
Peak memory 196192 kb
Host smart-4fe71e2a-005b-4ace-9b63-81a5d698d6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821782924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.821782924
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1690078369
Short name T1070
Test name
Test status
Simulation time 103755065212 ps
CPU time 98.81 seconds
Started Apr 16 02:39:31 PM PDT 24
Finished Apr 16 02:41:10 PM PDT 24
Peak memory 200904 kb
Host smart-ba535dc9-4006-44c3-9293-0dd50d2ba99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690078369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1690078369
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1003915442
Short name T155
Test name
Test status
Simulation time 89463185171 ps
CPU time 80.14 seconds
Started Apr 16 02:39:30 PM PDT 24
Finished Apr 16 02:40:51 PM PDT 24
Peak memory 200744 kb
Host smart-b3561a63-c903-4bcb-92a6-05fe13a8a594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003915442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1003915442
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3432794498
Short name T194
Test name
Test status
Simulation time 20219175140 ps
CPU time 41.62 seconds
Started Apr 16 02:39:30 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 200844 kb
Host smart-35214c71-9d6c-4c4f-9038-36dba78b01af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432794498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3432794498
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2099078123
Short name T909
Test name
Test status
Simulation time 11793873872 ps
CPU time 11.66 seconds
Started Apr 16 02:39:28 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 200792 kb
Host smart-348e39b6-9992-441f-9f26-927d5bded7e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099078123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2099078123
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3725816115
Short name T1022
Test name
Test status
Simulation time 92071946251 ps
CPU time 360.26 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:45:35 PM PDT 24
Peak memory 200728 kb
Host smart-33a4d253-9790-4cd8-a4ab-3b106b73fb4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725816115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3725816115
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1089263675
Short name T355
Test name
Test status
Simulation time 2404258695 ps
CPU time 2.7 seconds
Started Apr 16 02:39:28 PM PDT 24
Finished Apr 16 02:39:32 PM PDT 24
Peak memory 199400 kb
Host smart-7f187a90-819f-425c-bc92-1440e53962fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089263675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1089263675
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3744312043
Short name T827
Test name
Test status
Simulation time 151144364270 ps
CPU time 72.79 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:40:43 PM PDT 24
Peak memory 201140 kb
Host smart-5fa6f5e3-5a98-4c77-b921-5260d8fd8a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744312043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3744312043
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1131173776
Short name T766
Test name
Test status
Simulation time 6637152190 ps
CPU time 375.34 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:45:46 PM PDT 24
Peak memory 200864 kb
Host smart-bf942fa2-9fa7-48bf-bf8c-45590cd43238
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131173776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1131173776
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3435835272
Short name T643
Test name
Test status
Simulation time 6523095016 ps
CPU time 63.97 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:40:34 PM PDT 24
Peak memory 199196 kb
Host smart-8730a9a3-a47b-4afc-8654-c205fe225f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3435835272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3435835272
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.441513862
Short name T162
Test name
Test status
Simulation time 23084609288 ps
CPU time 56.64 seconds
Started Apr 16 02:39:32 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 200812 kb
Host smart-89368156-ea59-4a0f-9560-985284bb39df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441513862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.441513862
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3878750137
Short name T25
Test name
Test status
Simulation time 4317239334 ps
CPU time 7.27 seconds
Started Apr 16 02:39:30 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 196828 kb
Host smart-51bb6b3d-46d0-4e77-b207-52a2ce14f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878750137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3878750137
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2929583449
Short name T1035
Test name
Test status
Simulation time 6200530683 ps
CPU time 10.3 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 200460 kb
Host smart-4b9808a5-49cf-46df-9779-e85006acd786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929583449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2929583449
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2414620509
Short name T847
Test name
Test status
Simulation time 106430156520 ps
CPU time 404.93 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:46:26 PM PDT 24
Peak memory 200908 kb
Host smart-5a3a38e9-bfa0-4d61-8ae3-43e5adf506c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414620509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2414620509
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.60753585
Short name T115
Test name
Test status
Simulation time 78432285192 ps
CPU time 886.81 seconds
Started Apr 16 02:39:35 PM PDT 24
Finished Apr 16 02:54:23 PM PDT 24
Peak memory 225424 kb
Host smart-929f76ed-6f28-4f1f-9dee-d6b2aa844e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60753585 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.60753585
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.923578400
Short name T952
Test name
Test status
Simulation time 1337040312 ps
CPU time 2.28 seconds
Started Apr 16 02:39:30 PM PDT 24
Finished Apr 16 02:39:33 PM PDT 24
Peak memory 199916 kb
Host smart-cbde0f6b-d71b-4c8d-a8b5-391435c13ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923578400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.923578400
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2993793396
Short name T757
Test name
Test status
Simulation time 9816503586 ps
CPU time 1.54 seconds
Started Apr 16 02:39:29 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 198524 kb
Host smart-0a778824-03b7-44c1-b8f6-bf3997824842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993793396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2993793396
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.680604121
Short name T634
Test name
Test status
Simulation time 78717624752 ps
CPU time 18.62 seconds
Started Apr 16 02:42:38 PM PDT 24
Finished Apr 16 02:42:58 PM PDT 24
Peak memory 200876 kb
Host smart-df5e6d9d-d8bd-41e5-8677-7cbfb92b96ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680604121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.680604121
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.966717386
Short name T192
Test name
Test status
Simulation time 180070617762 ps
CPU time 66.75 seconds
Started Apr 16 02:42:38 PM PDT 24
Finished Apr 16 02:43:46 PM PDT 24
Peak memory 200816 kb
Host smart-cedf5c26-72e4-45f3-b91a-cea7d9b99644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966717386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.966717386
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.428111
Short name T200
Test name
Test status
Simulation time 19454889262 ps
CPU time 30.92 seconds
Started Apr 16 02:42:38 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200880 kb
Host smart-6267beb9-92b1-4b0d-9dfd-b127752c8b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.428111
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3273818684
Short name T1098
Test name
Test status
Simulation time 132755012584 ps
CPU time 52.43 seconds
Started Apr 16 02:42:38 PM PDT 24
Finished Apr 16 02:43:32 PM PDT 24
Peak memory 200832 kb
Host smart-343f71c3-140a-46aa-8d24-cffb96393909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273818684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3273818684
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1508155394
Short name T222
Test name
Test status
Simulation time 11098761383 ps
CPU time 17.52 seconds
Started Apr 16 02:42:40 PM PDT 24
Finished Apr 16 02:42:59 PM PDT 24
Peak memory 200868 kb
Host smart-e20cb486-dbef-4556-8e58-dfb15f88ecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508155394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1508155394
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1590495949
Short name T1052
Test name
Test status
Simulation time 73052042720 ps
CPU time 110.13 seconds
Started Apr 16 02:42:36 PM PDT 24
Finished Apr 16 02:44:27 PM PDT 24
Peak memory 200864 kb
Host smart-5139ea49-60b4-4f0c-bb94-d5c656bd479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590495949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1590495949
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1723496121
Short name T213
Test name
Test status
Simulation time 99900272100 ps
CPU time 32.89 seconds
Started Apr 16 02:42:41 PM PDT 24
Finished Apr 16 02:43:15 PM PDT 24
Peak memory 200844 kb
Host smart-401f4e25-7e75-4d7c-88af-3d368f6712fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723496121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1723496121
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3231444383
Short name T843
Test name
Test status
Simulation time 45053013 ps
CPU time 0.57 seconds
Started Apr 16 02:39:39 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 196184 kb
Host smart-f4c69adc-1f3c-46dd-aa1d-93b28e6703ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231444383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3231444383
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3731218880
Short name T989
Test name
Test status
Simulation time 78212045395 ps
CPU time 37.8 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:40:11 PM PDT 24
Peak memory 200808 kb
Host smart-b51722c1-28a8-4372-b615-c0ecf9a01804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731218880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3731218880
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.503144168
Short name T951
Test name
Test status
Simulation time 7907019144 ps
CPU time 15.69 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:39:57 PM PDT 24
Peak memory 200844 kb
Host smart-86fcf0de-1e1a-4aea-9da9-e6b03d398939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503144168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.503144168
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2593289723
Short name T205
Test name
Test status
Simulation time 20950948903 ps
CPU time 37.16 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 200808 kb
Host smart-32a06416-b771-4c3f-aeb2-0142fbd7eb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593289723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2593289723
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4125136445
Short name T416
Test name
Test status
Simulation time 12098800858 ps
CPU time 23.17 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 200240 kb
Host smart-62d58f88-3748-4d9a-a1e9-1d3db14ce3c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125136445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4125136445
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.487033076
Short name T587
Test name
Test status
Simulation time 260889546828 ps
CPU time 186.01 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200916 kb
Host smart-db1c554c-41d4-4da2-b2a8-0036f2426e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487033076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.487033076
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3431608724
Short name T104
Test name
Test status
Simulation time 7768148234 ps
CPU time 13.25 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:39:47 PM PDT 24
Peak memory 199656 kb
Host smart-c9338c16-17bf-4000-9bb4-f9dd2460107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431608724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3431608724
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2821720366
Short name T1141
Test name
Test status
Simulation time 105992659239 ps
CPU time 243.26 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:43:42 PM PDT 24
Peak memory 209276 kb
Host smart-cdba10ad-7d52-4efc-9211-50b861888cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821720366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2821720366
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2103393938
Short name T418
Test name
Test status
Simulation time 21812989626 ps
CPU time 282.9 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:44:30 PM PDT 24
Peak memory 200936 kb
Host smart-7a52d3ff-be95-460a-85da-909973957439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2103393938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2103393938
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3715421834
Short name T336
Test name
Test status
Simulation time 6997294799 ps
CPU time 56.99 seconds
Started Apr 16 02:39:37 PM PDT 24
Finished Apr 16 02:40:34 PM PDT 24
Peak memory 199096 kb
Host smart-f383a67e-fc45-4d32-b791-9f3af8e644ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3715421834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3715421834
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2458635291
Short name T312
Test name
Test status
Simulation time 37271688561 ps
CPU time 34.91 seconds
Started Apr 16 02:39:35 PM PDT 24
Finished Apr 16 02:40:10 PM PDT 24
Peak memory 200784 kb
Host smart-f9cd5897-e1bb-4827-86f0-5000fbe32335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458635291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2458635291
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.33364616
Short name T303
Test name
Test status
Simulation time 5879716839 ps
CPU time 1.88 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:39:36 PM PDT 24
Peak memory 196896 kb
Host smart-707e535b-45bf-4b8f-8b73-c205cb205755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33364616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.33364616
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.181968478
Short name T734
Test name
Test status
Simulation time 112212386 ps
CPU time 0.96 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 198184 kb
Host smart-e8a59636-81da-4da5-8373-1e65356a0171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181968478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.181968478
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.686608791
Short name T1093
Test name
Test status
Simulation time 488149839497 ps
CPU time 471.51 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:47:26 PM PDT 24
Peak memory 201104 kb
Host smart-121f8519-fd8f-4ad5-a0f5-3ddea4d3591d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686608791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.686608791
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1662349221
Short name T657
Test name
Test status
Simulation time 6442027592 ps
CPU time 11.47 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:39:54 PM PDT 24
Peak memory 200840 kb
Host smart-53a21b49-da28-41c8-af7c-b155d112d5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662349221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1662349221
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2455154302
Short name T375
Test name
Test status
Simulation time 132033620703 ps
CPU time 52.76 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:40:34 PM PDT 24
Peak memory 200788 kb
Host smart-1a674218-b159-46b1-b5b9-8b12f51c564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455154302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2455154302
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2638876567
Short name T186
Test name
Test status
Simulation time 141317452743 ps
CPU time 58.85 seconds
Started Apr 16 02:42:43 PM PDT 24
Finished Apr 16 02:43:43 PM PDT 24
Peak memory 200796 kb
Host smart-ef8aeeb4-97de-48d7-9edb-8f44f218a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638876567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2638876567
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2913721973
Short name T215
Test name
Test status
Simulation time 97338017511 ps
CPU time 75.46 seconds
Started Apr 16 02:42:40 PM PDT 24
Finished Apr 16 02:43:57 PM PDT 24
Peak memory 200732 kb
Host smart-930440d0-4d9f-4ee1-b0e0-3e79aeca9f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913721973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2913721973
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.865611835
Short name T1003
Test name
Test status
Simulation time 59252493043 ps
CPU time 77.26 seconds
Started Apr 16 02:42:41 PM PDT 24
Finished Apr 16 02:43:59 PM PDT 24
Peak memory 200808 kb
Host smart-2c6ae1c9-7a66-47ae-9acb-b7db2f4fb925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865611835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.865611835
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1857181477
Short name T174
Test name
Test status
Simulation time 28731270143 ps
CPU time 15.2 seconds
Started Apr 16 02:42:43 PM PDT 24
Finished Apr 16 02:42:59 PM PDT 24
Peak memory 200924 kb
Host smart-2b9056ff-d024-4902-bd74-147c1cbcc3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857181477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1857181477
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.131651976
Short name T249
Test name
Test status
Simulation time 38987779124 ps
CPU time 17.18 seconds
Started Apr 16 02:42:42 PM PDT 24
Finished Apr 16 02:43:00 PM PDT 24
Peak memory 200580 kb
Host smart-59379afc-2d96-40ce-a4ae-a1640a06b75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131651976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.131651976
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3175896990
Short name T1080
Test name
Test status
Simulation time 134529228704 ps
CPU time 218.27 seconds
Started Apr 16 02:42:43 PM PDT 24
Finished Apr 16 02:46:22 PM PDT 24
Peak memory 200792 kb
Host smart-bf364510-cb69-46f4-a8fe-933c0094b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175896990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3175896990
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4178707915
Short name T277
Test name
Test status
Simulation time 101290676688 ps
CPU time 43.17 seconds
Started Apr 16 02:42:41 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 200900 kb
Host smart-c3102a71-7f74-4d90-90e0-c1458d1c6294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178707915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4178707915
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3409644992
Short name T189
Test name
Test status
Simulation time 18340711603 ps
CPU time 28.92 seconds
Started Apr 16 02:42:42 PM PDT 24
Finished Apr 16 02:43:11 PM PDT 24
Peak memory 200920 kb
Host smart-a73d9f0b-6acd-405a-8202-5dc64e8797a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409644992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3409644992
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3014510841
Short name T264
Test name
Test status
Simulation time 37383989865 ps
CPU time 36.44 seconds
Started Apr 16 02:42:44 PM PDT 24
Finished Apr 16 02:43:21 PM PDT 24
Peak memory 200888 kb
Host smart-6ee89b86-4b04-4450-8e0a-fd4c3cc9230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014510841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3014510841
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2635040086
Short name T150
Test name
Test status
Simulation time 108194306365 ps
CPU time 41.18 seconds
Started Apr 16 02:42:43 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 200908 kb
Host smart-f60c9e5c-dabe-4241-ae99-1a47c018ed51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635040086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2635040086
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4225419087
Short name T986
Test name
Test status
Simulation time 14345199 ps
CPU time 0.59 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:39:48 PM PDT 24
Peak memory 196200 kb
Host smart-e89ef34d-4322-4f62-865c-ee5942fe1a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225419087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4225419087
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2071990190
Short name T933
Test name
Test status
Simulation time 89402144278 ps
CPU time 66.27 seconds
Started Apr 16 02:39:36 PM PDT 24
Finished Apr 16 02:40:43 PM PDT 24
Peak memory 200852 kb
Host smart-4e52597b-8c1c-4e96-aa10-e20be4c179d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071990190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2071990190
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3085101175
Short name T863
Test name
Test status
Simulation time 89128386864 ps
CPU time 173.59 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:42:28 PM PDT 24
Peak memory 200732 kb
Host smart-e78dfa71-ea11-46c0-914a-c572036d06cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085101175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3085101175
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3503895883
Short name T1062
Test name
Test status
Simulation time 18615244427 ps
CPU time 32.86 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 200836 kb
Host smart-061473c9-b89d-4cca-99a4-2b462c4afbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503895883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3503895883
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4088762460
Short name T511
Test name
Test status
Simulation time 20416719797 ps
CPU time 40.67 seconds
Started Apr 16 02:39:35 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 200848 kb
Host smart-36b61cb0-19c0-4974-8562-a58ebf9aa0d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088762460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4088762460
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2792583236
Short name T43
Test name
Test status
Simulation time 47434693256 ps
CPU time 53.2 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:40:35 PM PDT 24
Peak memory 200856 kb
Host smart-878eaf03-8a04-410e-a341-5f35bd6bf2ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792583236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2792583236
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2288487830
Short name T960
Test name
Test status
Simulation time 12216193633 ps
CPU time 22.91 seconds
Started Apr 16 02:39:36 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 200712 kb
Host smart-f72434cb-5235-4ace-8856-9d9141942a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288487830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2288487830
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2645461041
Short name T944
Test name
Test status
Simulation time 96278359432 ps
CPU time 79.39 seconds
Started Apr 16 02:39:39 PM PDT 24
Finished Apr 16 02:40:59 PM PDT 24
Peak memory 201032 kb
Host smart-fec4e01f-6c9d-44e9-9cdb-359a00b4e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645461041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2645461041
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.783091459
Short name T400
Test name
Test status
Simulation time 9227114707 ps
CPU time 268.08 seconds
Started Apr 16 02:39:43 PM PDT 24
Finished Apr 16 02:44:12 PM PDT 24
Peak memory 200928 kb
Host smart-1875cb33-c7a5-4221-a8a1-03614d175c7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783091459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.783091459
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.325930768
Short name T1040
Test name
Test status
Simulation time 7527139486 ps
CPU time 15.96 seconds
Started Apr 16 02:39:35 PM PDT 24
Finished Apr 16 02:39:51 PM PDT 24
Peak memory 198852 kb
Host smart-6b89706e-9d58-44e3-ac33-2a248413e8e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325930768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.325930768
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4263735706
Short name T142
Test name
Test status
Simulation time 72096008868 ps
CPU time 32.74 seconds
Started Apr 16 02:39:32 PM PDT 24
Finished Apr 16 02:40:05 PM PDT 24
Peak memory 200796 kb
Host smart-481c4110-d4fd-4cbd-9a98-6d47ac881271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263735706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4263735706
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1519228935
Short name T940
Test name
Test status
Simulation time 4798543027 ps
CPU time 8.42 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:39:51 PM PDT 24
Peak memory 196936 kb
Host smart-04f61000-264c-4530-b45f-1d75eb842987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519228935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1519228935
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.390189561
Short name T465
Test name
Test status
Simulation time 647876870 ps
CPU time 2.12 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:39:37 PM PDT 24
Peak memory 200740 kb
Host smart-8a2dd7ce-2ab9-4c5b-88f5-f7e0ae24fa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390189561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.390189561
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2187528374
Short name T694
Test name
Test status
Simulation time 260812142832 ps
CPU time 490.21 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:47:56 PM PDT 24
Peak memory 200832 kb
Host smart-36ad5c58-b244-42fc-9526-2425705eaa4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187528374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2187528374
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3115115641
Short name T762
Test name
Test status
Simulation time 284369489294 ps
CPU time 874.3 seconds
Started Apr 16 02:39:37 PM PDT 24
Finished Apr 16 02:54:12 PM PDT 24
Peak memory 228848 kb
Host smart-a88713d3-0286-4867-9e57-0e0db364b827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115115641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3115115641
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1008191272
Short name T941
Test name
Test status
Simulation time 902046614 ps
CPU time 4.28 seconds
Started Apr 16 02:39:33 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 199360 kb
Host smart-a4aa62dc-2424-4129-86f9-235c5453b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008191272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1008191272
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2448945025
Short name T631
Test name
Test status
Simulation time 87277085597 ps
CPU time 186.72 seconds
Started Apr 16 02:39:39 PM PDT 24
Finished Apr 16 02:42:46 PM PDT 24
Peak memory 200848 kb
Host smart-41646596-8dc6-4825-9fc3-8711704d896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448945025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2448945025
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3161269010
Short name T613
Test name
Test status
Simulation time 79286464116 ps
CPU time 39.32 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:43:28 PM PDT 24
Peak memory 200648 kb
Host smart-c5c844c5-1660-4b69-b49a-56e794057256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161269010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3161269010
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2139073398
Short name T789
Test name
Test status
Simulation time 181196982493 ps
CPU time 73.9 seconds
Started Apr 16 02:42:49 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200824 kb
Host smart-9ac351b0-b946-4e22-8966-38b6649a7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139073398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2139073398
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.108634863
Short name T1171
Test name
Test status
Simulation time 58461751551 ps
CPU time 94.21 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:44:22 PM PDT 24
Peak memory 200848 kb
Host smart-8d4f7403-3a09-43f4-ae38-60f4e9576b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108634863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.108634863
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3968135163
Short name T219
Test name
Test status
Simulation time 311160982399 ps
CPU time 35.32 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:43:24 PM PDT 24
Peak memory 200884 kb
Host smart-0d068b5a-3c57-4d86-9b2e-1a237a4dfc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968135163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3968135163
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.907248840
Short name T296
Test name
Test status
Simulation time 119190027683 ps
CPU time 360.68 seconds
Started Apr 16 02:42:47 PM PDT 24
Finished Apr 16 02:48:48 PM PDT 24
Peak memory 200820 kb
Host smart-c5af6c4e-b704-4720-b830-f9c34b11d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907248840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.907248840
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2626222759
Short name T563
Test name
Test status
Simulation time 170567069142 ps
CPU time 37.65 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:43:26 PM PDT 24
Peak memory 200860 kb
Host smart-aec18219-d3a9-435f-aa78-025bf851f85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626222759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2626222759
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2319317901
Short name T195
Test name
Test status
Simulation time 72760055756 ps
CPU time 96.42 seconds
Started Apr 16 02:42:45 PM PDT 24
Finished Apr 16 02:44:22 PM PDT 24
Peak memory 200812 kb
Host smart-a79c38dd-f01c-4cd2-8e5a-86986a755039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319317901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2319317901
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3356697495
Short name T1140
Test name
Test status
Simulation time 46949358 ps
CPU time 0.62 seconds
Started Apr 16 02:39:07 PM PDT 24
Finished Apr 16 02:39:08 PM PDT 24
Peak memory 196184 kb
Host smart-23deeffc-5407-4360-b1d6-5961a14d4641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356697495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3356697495
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.156140670
Short name T170
Test name
Test status
Simulation time 128859777584 ps
CPU time 77.57 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:40:25 PM PDT 24
Peak memory 200908 kb
Host smart-77e0a0fc-0533-4af0-8dfc-36eafe6543b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156140670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.156140670
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.740572290
Short name T590
Test name
Test status
Simulation time 25146154500 ps
CPU time 38.54 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:52 PM PDT 24
Peak memory 200844 kb
Host smart-33cbcfb0-2648-449a-a5c7-dc1b6470fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740572290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.740572290
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2148737233
Short name T327
Test name
Test status
Simulation time 51242749235 ps
CPU time 17.04 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 200816 kb
Host smart-8f0b171c-bae3-4716-8cac-1606aa8eef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148737233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2148737233
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3943117149
Short name T14
Test name
Test status
Simulation time 389914622380 ps
CPU time 82.93 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 198732 kb
Host smart-4ff72b26-339f-46b3-bf83-49daebe25151
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943117149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3943117149
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.4279590736
Short name T861
Test name
Test status
Simulation time 96280087577 ps
CPU time 407.48 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:46:05 PM PDT 24
Peak memory 200772 kb
Host smart-d3ccb13b-2bd8-45f1-a37b-83cc1307e52d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279590736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.4279590736
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.547487164
Short name T627
Test name
Test status
Simulation time 3881427389 ps
CPU time 8.83 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 199724 kb
Host smart-a011e198-a8aa-41fa-ab9b-47404066a063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547487164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.547487164
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1391710448
Short name T326
Test name
Test status
Simulation time 126581473132 ps
CPU time 447.25 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:46:38 PM PDT 24
Peak memory 201012 kb
Host smart-b605c318-7338-4cfc-9737-a74c4bb9047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391710448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1391710448
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3983673167
Short name T391
Test name
Test status
Simulation time 13610417218 ps
CPU time 835.16 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:53:00 PM PDT 24
Peak memory 200756 kb
Host smart-cc09b2aa-cda4-4cfa-9e43-4345d58ecb78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983673167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3983673167
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3977771388
Short name T536
Test name
Test status
Simulation time 5879884841 ps
CPU time 54.08 seconds
Started Apr 16 02:39:05 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 200096 kb
Host smart-69c0bcad-0a4c-4274-a6c5-d98ada80807e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977771388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3977771388
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.164349381
Short name T515
Test name
Test status
Simulation time 96086020518 ps
CPU time 46.44 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:03 PM PDT 24
Peak memory 200764 kb
Host smart-ec8fa32f-e952-4c93-9577-dfd774a59989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164349381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.164349381
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1054234900
Short name T420
Test name
Test status
Simulation time 38053276145 ps
CPU time 33.91 seconds
Started Apr 16 02:39:05 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 196672 kb
Host smart-9eec67c2-920c-489c-a0fe-5e5873e69fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054234900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1054234900
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.765125017
Short name T30
Test name
Test status
Simulation time 55630203 ps
CPU time 0.75 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 218776 kb
Host smart-f3b72c35-32d9-43a7-9639-c2365687cfc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765125017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.765125017
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.876199134
Short name T534
Test name
Test status
Simulation time 248129001 ps
CPU time 1.33 seconds
Started Apr 16 02:39:04 PM PDT 24
Finished Apr 16 02:39:07 PM PDT 24
Peak memory 199296 kb
Host smart-728be81b-4598-406a-b49e-7333854c33f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876199134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.876199134
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2654016145
Short name T1176
Test name
Test status
Simulation time 90739412981 ps
CPU time 44.99 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:52 PM PDT 24
Peak memory 201116 kb
Host smart-a3396bb9-8b15-48ba-bbc4-92fb4d8a1c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654016145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2654016145
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2921692845
Short name T305
Test name
Test status
Simulation time 81791711472 ps
CPU time 637.95 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:49:48 PM PDT 24
Peak memory 217348 kb
Host smart-39b7e1c8-709e-415a-ad4a-a6bc5da3422e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921692845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2921692845
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2977519132
Short name T1153
Test name
Test status
Simulation time 1145793327 ps
CPU time 2.37 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 199588 kb
Host smart-180ea567-ab0c-4672-98aa-422aab7436af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977519132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2977519132
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.751962879
Short name T1116
Test name
Test status
Simulation time 6687865694 ps
CPU time 12.46 seconds
Started Apr 16 02:39:08 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 200840 kb
Host smart-a1b2d6c6-4d6e-4740-a1e8-1b6ba5d17331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751962879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.751962879
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2805219393
Short name T920
Test name
Test status
Simulation time 21170221 ps
CPU time 0.53 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:39:43 PM PDT 24
Peak memory 195160 kb
Host smart-0ad62bfc-7e72-4a02-84c9-17287816f827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805219393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2805219393
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3319601239
Short name T560
Test name
Test status
Simulation time 115258559190 ps
CPU time 194.66 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:42:54 PM PDT 24
Peak memory 200856 kb
Host smart-8d44cc04-9ffe-4014-89ec-e77999d3f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319601239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3319601239
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.586251412
Short name T1048
Test name
Test status
Simulation time 36999372943 ps
CPU time 16.76 seconds
Started Apr 16 02:39:43 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 200832 kb
Host smart-5d649541-75b5-45d5-b873-14eeeaaf2fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586251412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.586251412
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3254978942
Short name T1165
Test name
Test status
Simulation time 143113271408 ps
CPU time 280.98 seconds
Started Apr 16 02:39:47 PM PDT 24
Finished Apr 16 02:44:29 PM PDT 24
Peak memory 200952 kb
Host smart-af932cb9-a729-43a1-892e-90ffec0297c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254978942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3254978942
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2149138549
Short name T365
Test name
Test status
Simulation time 15500693750 ps
CPU time 7.77 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 198508 kb
Host smart-9656b895-3490-4cb1-bd48-2c8308f74da1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149138549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2149138549
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.770708004
Short name T600
Test name
Test status
Simulation time 139507585815 ps
CPU time 1043.58 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:57:04 PM PDT 24
Peak memory 200732 kb
Host smart-3490deb9-1ed4-448e-ad13-b4bdbd235dc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770708004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.770708004
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2718391352
Short name T875
Test name
Test status
Simulation time 2879095126 ps
CPU time 2.21 seconds
Started Apr 16 02:39:36 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 199772 kb
Host smart-ff2abc80-34f4-4c35-8e27-eb681dacd7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718391352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2718391352
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.399635383
Short name T1132
Test name
Test status
Simulation time 62233305564 ps
CPU time 113.91 seconds
Started Apr 16 02:39:47 PM PDT 24
Finished Apr 16 02:41:42 PM PDT 24
Peak memory 201048 kb
Host smart-116a9c1f-331e-40cb-b6e7-c8827a88ea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399635383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.399635383
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1958196914
Short name T410
Test name
Test status
Simulation time 20143980420 ps
CPU time 1222.99 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 03:00:02 PM PDT 24
Peak memory 200916 kb
Host smart-a44737b8-4f87-466c-aab1-61d74a2a369f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958196914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1958196914
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.367499672
Short name T479
Test name
Test status
Simulation time 7239133173 ps
CPU time 63.85 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 199492 kb
Host smart-3a7b1095-8e15-4605-bab4-8bf2a5b5ad31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=367499672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.367499672
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1408176113
Short name T1123
Test name
Test status
Simulation time 63192324709 ps
CPU time 107.21 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:41:33 PM PDT 24
Peak memory 200852 kb
Host smart-f189103f-02d6-47b4-81a3-6bdf65a96236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408176113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1408176113
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2015798149
Short name T688
Test name
Test status
Simulation time 1754145533 ps
CPU time 2.06 seconds
Started Apr 16 02:39:38 PM PDT 24
Finished Apr 16 02:39:41 PM PDT 24
Peak memory 196292 kb
Host smart-037c05bb-7849-49f7-bfd3-e9c69f183b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015798149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2015798149
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2731652583
Short name T445
Test name
Test status
Simulation time 576567732 ps
CPU time 1.37 seconds
Started Apr 16 02:39:36 PM PDT 24
Finished Apr 16 02:39:38 PM PDT 24
Peak memory 200364 kb
Host smart-e861dd9f-dabd-416b-9ae1-48a9f6723228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731652583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2731652583
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3493471454
Short name T942
Test name
Test status
Simulation time 589228989206 ps
CPU time 632.71 seconds
Started Apr 16 02:39:41 PM PDT 24
Finished Apr 16 02:50:15 PM PDT 24
Peak memory 200820 kb
Host smart-31559f3f-9e45-4f81-8aee-75eb0f756bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493471454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3493471454
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1034137352
Short name T478
Test name
Test status
Simulation time 45612406006 ps
CPU time 163.37 seconds
Started Apr 16 02:39:43 PM PDT 24
Finished Apr 16 02:42:27 PM PDT 24
Peak memory 209164 kb
Host smart-7bb26185-4003-4531-8beb-4cbf2ba17f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034137352 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1034137352
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2673719856
Short name T19
Test name
Test status
Simulation time 1146219277 ps
CPU time 1.86 seconds
Started Apr 16 02:39:34 PM PDT 24
Finished Apr 16 02:39:37 PM PDT 24
Peak memory 199124 kb
Host smart-7d5e52ff-aea2-4518-abd2-df0a09c69715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673719856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2673719856
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3612036543
Short name T364
Test name
Test status
Simulation time 20429907591 ps
CPU time 8.39 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 199004 kb
Host smart-72dd4110-e280-4765-910e-9ff941445d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612036543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3612036543
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3292674079
Short name T333
Test name
Test status
Simulation time 31144997272 ps
CPU time 59.16 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:43:48 PM PDT 24
Peak memory 200840 kb
Host smart-602699ff-5e83-4095-8bec-8ebf5b87a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292674079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3292674079
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3154982748
Short name T1056
Test name
Test status
Simulation time 23121009320 ps
CPU time 9.93 seconds
Started Apr 16 02:42:46 PM PDT 24
Finished Apr 16 02:42:56 PM PDT 24
Peak memory 200792 kb
Host smart-c054731c-fb01-4ae7-a791-c6a76e562aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154982748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3154982748
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1563600415
Short name T844
Test name
Test status
Simulation time 19305192823 ps
CPU time 39.41 seconds
Started Apr 16 02:42:47 PM PDT 24
Finished Apr 16 02:43:26 PM PDT 24
Peak memory 201084 kb
Host smart-8a1d8745-8003-473e-ac24-779c4b7152a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563600415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1563600415
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3222634319
Short name T630
Test name
Test status
Simulation time 114217036574 ps
CPU time 75.2 seconds
Started Apr 16 02:42:49 PM PDT 24
Finished Apr 16 02:44:05 PM PDT 24
Peak memory 200904 kb
Host smart-e2c9d5f1-721c-4443-a5f5-670736eda559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222634319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3222634319
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2844409213
Short name T273
Test name
Test status
Simulation time 43850836233 ps
CPU time 83.84 seconds
Started Apr 16 02:42:47 PM PDT 24
Finished Apr 16 02:44:11 PM PDT 24
Peak memory 200816 kb
Host smart-900bdbd5-d3ae-4682-a83b-9f8d428aceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844409213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2844409213
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2298456092
Short name T455
Test name
Test status
Simulation time 182139839401 ps
CPU time 33.9 seconds
Started Apr 16 02:42:45 PM PDT 24
Finished Apr 16 02:43:20 PM PDT 24
Peak memory 200808 kb
Host smart-2871864d-7969-4d3e-ad96-aea6dd5ab175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298456092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2298456092
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1769378486
Short name T773
Test name
Test status
Simulation time 53560046165 ps
CPU time 51.63 seconds
Started Apr 16 02:42:49 PM PDT 24
Finished Apr 16 02:43:41 PM PDT 24
Peak memory 200916 kb
Host smart-ac44368c-8827-4e0f-84db-33191abc3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769378486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1769378486
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1904809452
Short name T184
Test name
Test status
Simulation time 38254235441 ps
CPU time 43.15 seconds
Started Apr 16 02:42:48 PM PDT 24
Finished Apr 16 02:43:32 PM PDT 24
Peak memory 200856 kb
Host smart-4c2dcca0-3179-4250-a924-d17e103285f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904809452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1904809452
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.331749058
Short name T818
Test name
Test status
Simulation time 86672714347 ps
CPU time 104.75 seconds
Started Apr 16 02:42:53 PM PDT 24
Finished Apr 16 02:44:39 PM PDT 24
Peak memory 200756 kb
Host smart-9e004c92-e36c-4f6e-8baf-af2b4cc9f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331749058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.331749058
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2509138699
Short name T473
Test name
Test status
Simulation time 14341596 ps
CPU time 0.57 seconds
Started Apr 16 02:39:48 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 196208 kb
Host smart-1673084b-2ab2-4d58-8e47-8978f921e26e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509138699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2509138699
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.119408882
Short name T157
Test name
Test status
Simulation time 60637136907 ps
CPU time 23.1 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:40:06 PM PDT 24
Peak memory 200796 kb
Host smart-02ef5345-3c49-4053-af8a-d39dffd225ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119408882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.119408882
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2525480624
Short name T1085
Test name
Test status
Simulation time 156264059675 ps
CPU time 235.9 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:43:39 PM PDT 24
Peak memory 200852 kb
Host smart-534dd1b7-aae1-48ec-83fe-b817ca7275b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525480624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2525480624
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.777052612
Short name T956
Test name
Test status
Simulation time 120835564310 ps
CPU time 50.12 seconds
Started Apr 16 02:39:40 PM PDT 24
Finished Apr 16 02:40:31 PM PDT 24
Peak memory 200816 kb
Host smart-b6f0efbe-09b8-4d7d-81ab-bd23dc591d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777052612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.777052612
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1425868864
Short name T917
Test name
Test status
Simulation time 20836643734 ps
CPU time 38.4 seconds
Started Apr 16 02:39:41 PM PDT 24
Finished Apr 16 02:40:20 PM PDT 24
Peak memory 200804 kb
Host smart-502c85a0-dcbe-4d07-97a3-3ca3f8fafb45
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425868864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1425868864
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3194934229
Short name T454
Test name
Test status
Simulation time 148248418762 ps
CPU time 899.08 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:54:45 PM PDT 24
Peak memory 200852 kb
Host smart-5063331a-6b1e-4a81-8d5a-f5c9b8acfa43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194934229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3194934229
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2596896848
Short name T1103
Test name
Test status
Simulation time 11623451150 ps
CPU time 7.98 seconds
Started Apr 16 02:39:50 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 200844 kb
Host smart-8bd8d5c6-53e2-4329-ac21-9bfb7d3e7737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596896848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2596896848
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4289378494
Short name T427
Test name
Test status
Simulation time 66099441357 ps
CPU time 133.67 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:42:00 PM PDT 24
Peak memory 200832 kb
Host smart-8836f55f-a0b9-43e6-909c-dccdef2afbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289378494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4289378494
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1714053838
Short name T625
Test name
Test status
Simulation time 2532108220 ps
CPU time 72.61 seconds
Started Apr 16 02:39:48 PM PDT 24
Finished Apr 16 02:41:02 PM PDT 24
Peak memory 200900 kb
Host smart-a0584214-8cac-4a75-b57d-ae3e7f56a2d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714053838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1714053838
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.828871864
Short name T994
Test name
Test status
Simulation time 5731987681 ps
CPU time 11.96 seconds
Started Apr 16 02:39:47 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 199904 kb
Host smart-030e9d71-150b-47f4-9dc0-2d4f5b013807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828871864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.828871864
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2375101516
Short name T954
Test name
Test status
Simulation time 26703332500 ps
CPU time 15.21 seconds
Started Apr 16 02:39:44 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 200840 kb
Host smart-ac7de67a-62e1-45b4-845a-545db696d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375101516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2375101516
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.4245024103
Short name T40
Test name
Test status
Simulation time 698747424 ps
CPU time 0.89 seconds
Started Apr 16 02:39:47 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 196296 kb
Host smart-fb7dbe0f-b946-408c-851c-7cdeb05b403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245024103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4245024103
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1996928794
Short name T279
Test name
Test status
Simulation time 460580531 ps
CPU time 1.7 seconds
Started Apr 16 02:39:42 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 199156 kb
Host smart-1e847bbb-558b-435d-afc6-68505032ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996928794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1996928794
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.842035306
Short name T937
Test name
Test status
Simulation time 90343631306 ps
CPU time 1093.27 seconds
Started Apr 16 02:39:45 PM PDT 24
Finished Apr 16 02:57:59 PM PDT 24
Peak memory 226128 kb
Host smart-8d7016da-1ef3-4af9-8e5c-e38d8453cffd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842035306 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.842035306
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2656737123
Short name T730
Test name
Test status
Simulation time 962078269 ps
CPU time 3.8 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:39:50 PM PDT 24
Peak memory 200584 kb
Host smart-73d552ca-e4f4-4475-a01d-f994117bd5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656737123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2656737123
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2220906176
Short name T639
Test name
Test status
Simulation time 9970774844 ps
CPU time 17.28 seconds
Started Apr 16 02:39:53 PM PDT 24
Finished Apr 16 02:40:11 PM PDT 24
Peak memory 200788 kb
Host smart-a06f246d-647c-476c-ba4f-883d79fef1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220906176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2220906176
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1193196649
Short name T214
Test name
Test status
Simulation time 242188065493 ps
CPU time 86.74 seconds
Started Apr 16 02:42:52 PM PDT 24
Finished Apr 16 02:44:19 PM PDT 24
Peak memory 200924 kb
Host smart-d29baa5b-fc38-4e01-aa9e-cae994220294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193196649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1193196649
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4265977989
Short name T231
Test name
Test status
Simulation time 421354462783 ps
CPU time 36.37 seconds
Started Apr 16 02:42:53 PM PDT 24
Finished Apr 16 02:43:29 PM PDT 24
Peak memory 200840 kb
Host smart-96e552dc-1ff2-4174-ba95-75f58f17001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265977989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4265977989
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3805821294
Short name T228
Test name
Test status
Simulation time 34309649509 ps
CPU time 15.65 seconds
Started Apr 16 02:42:53 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200920 kb
Host smart-665429a1-2167-478b-bec0-b0e3e346d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805821294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3805821294
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3377237369
Short name T131
Test name
Test status
Simulation time 118793806470 ps
CPU time 169.02 seconds
Started Apr 16 02:42:52 PM PDT 24
Finished Apr 16 02:45:42 PM PDT 24
Peak memory 200900 kb
Host smart-e72cb0ee-e665-443d-8f46-e12146c0822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377237369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3377237369
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2484632710
Short name T302
Test name
Test status
Simulation time 115050507601 ps
CPU time 20.81 seconds
Started Apr 16 02:42:52 PM PDT 24
Finished Apr 16 02:43:13 PM PDT 24
Peak memory 199860 kb
Host smart-65347f38-0bcc-4985-a3c3-1d75f77abbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484632710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2484632710
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1420308528
Short name T1073
Test name
Test status
Simulation time 15963122900 ps
CPU time 12.96 seconds
Started Apr 16 02:42:56 PM PDT 24
Finished Apr 16 02:43:10 PM PDT 24
Peak memory 200836 kb
Host smart-e1288e37-5bc3-45ca-9c31-bb7ab0169417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420308528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1420308528
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3530420386
Short name T199
Test name
Test status
Simulation time 7249164715 ps
CPU time 7.73 seconds
Started Apr 16 02:42:55 PM PDT 24
Finished Apr 16 02:43:03 PM PDT 24
Peak memory 200868 kb
Host smart-f656844e-a83b-4933-ba98-edc799253d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530420386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3530420386
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1274509761
Short name T910
Test name
Test status
Simulation time 27573613376 ps
CPU time 21.79 seconds
Started Apr 16 02:42:56 PM PDT 24
Finished Apr 16 02:43:18 PM PDT 24
Peak memory 200824 kb
Host smart-1696e7fd-d430-442e-9479-ea28ab9c979e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274509761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1274509761
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2964565385
Short name T525
Test name
Test status
Simulation time 137724265748 ps
CPU time 27.09 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:40:14 PM PDT 24
Peak memory 200912 kb
Host smart-f206be55-a7e5-43b1-81ca-996271f91666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964565385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2964565385
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1480666677
Short name T138
Test name
Test status
Simulation time 137303493176 ps
CPU time 49.28 seconds
Started Apr 16 02:39:46 PM PDT 24
Finished Apr 16 02:40:36 PM PDT 24
Peak memory 200660 kb
Host smart-a87e7342-6c97-478e-857c-ba2d9b23c448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480666677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1480666677
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4041849412
Short name T152
Test name
Test status
Simulation time 46631889869 ps
CPU time 24.39 seconds
Started Apr 16 02:39:51 PM PDT 24
Finished Apr 16 02:40:16 PM PDT 24
Peak memory 200812 kb
Host smart-7ee8729d-5b02-45b7-ada2-ce648316a79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041849412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4041849412
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.631637151
Short name T323
Test name
Test status
Simulation time 38697391150 ps
CPU time 64.77 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200456 kb
Host smart-787c55d3-fcd9-4196-8ac8-037d56e066fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631637151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.631637151
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1227694209
Short name T254
Test name
Test status
Simulation time 239928615830 ps
CPU time 355.32 seconds
Started Apr 16 02:39:52 PM PDT 24
Finished Apr 16 02:45:48 PM PDT 24
Peak memory 200672 kb
Host smart-aca6e99b-3eb7-4abd-825c-82b5c068ae9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227694209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1227694209
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1074253428
Short name T712
Test name
Test status
Simulation time 7559913090 ps
CPU time 2.52 seconds
Started Apr 16 02:39:52 PM PDT 24
Finished Apr 16 02:39:55 PM PDT 24
Peak memory 199396 kb
Host smart-f844b7dd-3f58-405d-8434-26f3b769a6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074253428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1074253428
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3247045143
Short name T286
Test name
Test status
Simulation time 50861670288 ps
CPU time 58.81 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:56 PM PDT 24
Peak memory 199936 kb
Host smart-dd57891f-fcf4-406a-99fd-e261cbffcba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247045143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3247045143
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2428706950
Short name T398
Test name
Test status
Simulation time 19747453254 ps
CPU time 107.42 seconds
Started Apr 16 02:39:52 PM PDT 24
Finished Apr 16 02:41:40 PM PDT 24
Peak memory 200840 kb
Host smart-fe236648-cc1c-4844-b5d7-c5af08bc30b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428706950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2428706950
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3812155381
Short name T585
Test name
Test status
Simulation time 7448624052 ps
CPU time 32.26 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 198892 kb
Host smart-27c2305c-8ae6-4a11-bb14-9511d499e9a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812155381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3812155381
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.380636438
Short name T588
Test name
Test status
Simulation time 158915928036 ps
CPU time 251.26 seconds
Started Apr 16 02:39:51 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200852 kb
Host smart-95e76a2f-54d3-43ce-92d9-ce447cd1ba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380636438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.380636438
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1414045904
Short name T823
Test name
Test status
Simulation time 51884202536 ps
CPU time 20.79 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:40:16 PM PDT 24
Peak memory 196632 kb
Host smart-37a88182-08f2-421b-a92e-b41fa8ff0fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414045904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1414045904
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1596204350
Short name T833
Test name
Test status
Simulation time 645151709 ps
CPU time 2.61 seconds
Started Apr 16 02:39:53 PM PDT 24
Finished Apr 16 02:39:56 PM PDT 24
Peak memory 199576 kb
Host smart-0bb0b3f8-5a26-4041-b96d-a9a2842708c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596204350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1596204350
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.606838301
Short name T658
Test name
Test status
Simulation time 1407699108 ps
CPU time 1.81 seconds
Started Apr 16 02:39:53 PM PDT 24
Finished Apr 16 02:39:56 PM PDT 24
Peak memory 199664 kb
Host smart-a7305e35-266f-49b8-92f5-784bc60c3cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606838301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.606838301
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1736368036
Short name T251
Test name
Test status
Simulation time 79049292371 ps
CPU time 71.56 seconds
Started Apr 16 02:39:48 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200848 kb
Host smart-3ff9c85b-5d61-4c22-8754-c677e73280c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736368036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1736368036
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2989334079
Short name T393
Test name
Test status
Simulation time 9940589272 ps
CPU time 16.89 seconds
Started Apr 16 02:42:57 PM PDT 24
Finished Apr 16 02:43:14 PM PDT 24
Peak memory 200648 kb
Host smart-cf4d5e04-7592-48f4-bd3d-7ff7223af07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989334079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2989334079
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2733336797
Short name T745
Test name
Test status
Simulation time 38410914205 ps
CPU time 64.85 seconds
Started Apr 16 02:42:56 PM PDT 24
Finished Apr 16 02:44:02 PM PDT 24
Peak memory 200852 kb
Host smart-03f1d1da-a743-4645-a5e3-dde181804b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733336797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2733336797
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3516209233
Short name T710
Test name
Test status
Simulation time 194272854644 ps
CPU time 91.86 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:44:33 PM PDT 24
Peak memory 200948 kb
Host smart-ecddcc8b-b410-4f9e-8a9d-dd1c9f178812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516209233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3516209233
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1952269365
Short name T939
Test name
Test status
Simulation time 199344168101 ps
CPU time 53.53 seconds
Started Apr 16 02:42:56 PM PDT 24
Finished Apr 16 02:43:50 PM PDT 24
Peak memory 200884 kb
Host smart-e2a5cca9-5e68-44d5-b552-db8310baed6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952269365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1952269365
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3776386583
Short name T280
Test name
Test status
Simulation time 16060224623 ps
CPU time 28.63 seconds
Started Apr 16 02:42:55 PM PDT 24
Finished Apr 16 02:43:24 PM PDT 24
Peak memory 200708 kb
Host smart-7c146630-7a76-451e-a1e1-08d3459e8ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776386583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3776386583
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.514650357
Short name T248
Test name
Test status
Simulation time 25268569121 ps
CPU time 50.52 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200908 kb
Host smart-9828f696-8660-47d8-94bc-43b62df90b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514650357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.514650357
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.632526151
Short name T779
Test name
Test status
Simulation time 191554719668 ps
CPU time 111.08 seconds
Started Apr 16 02:42:55 PM PDT 24
Finished Apr 16 02:44:46 PM PDT 24
Peak memory 200864 kb
Host smart-fcb9a2ad-59d2-4d84-ac28-72b453c9364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632526151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.632526151
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1751634893
Short name T1044
Test name
Test status
Simulation time 19270261430 ps
CPU time 28.98 seconds
Started Apr 16 02:42:56 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 200780 kb
Host smart-9a323d29-33f0-4969-a641-37e0a4754392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751634893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1751634893
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1085063581
Short name T610
Test name
Test status
Simulation time 28126065478 ps
CPU time 47.74 seconds
Started Apr 16 02:42:55 PM PDT 24
Finished Apr 16 02:43:43 PM PDT 24
Peak memory 201080 kb
Host smart-b4e03a61-f6a3-4574-80f8-54262b866473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085063581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1085063581
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3402015444
Short name T678
Test name
Test status
Simulation time 12353013 ps
CPU time 0.56 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:39:57 PM PDT 24
Peak memory 196224 kb
Host smart-bf7a2474-3e10-4981-aa06-65cb355c75ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402015444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3402015444
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1230612130
Short name T790
Test name
Test status
Simulation time 109622174699 ps
CPU time 99.32 seconds
Started Apr 16 02:39:50 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 200772 kb
Host smart-fb745faf-99f0-48f2-bfeb-cf4e69ca9cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230612130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1230612130
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2300252382
Short name T304
Test name
Test status
Simulation time 17512003940 ps
CPU time 14.35 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:40:09 PM PDT 24
Peak memory 199896 kb
Host smart-d25b76fe-5387-4ec8-b42d-97ea207cd3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300252382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2300252382
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.1346346310
Short name T674
Test name
Test status
Simulation time 15873593449 ps
CPU time 26.73 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 02:40:25 PM PDT 24
Peak memory 200620 kb
Host smart-6978cbe0-8321-4610-8bf6-0d7a215e53c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346346310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1346346310
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1426982829
Short name T935
Test name
Test status
Simulation time 44974902355 ps
CPU time 99.32 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:41:35 PM PDT 24
Peak memory 200832 kb
Host smart-eee8b9bb-052a-440c-9857-12023e4856eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426982829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1426982829
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.783979231
Short name T23
Test name
Test status
Simulation time 8628091546 ps
CPU time 16.12 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 02:40:15 PM PDT 24
Peak memory 200800 kb
Host smart-76456ef6-5c30-4cc3-8186-c37359eb33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783979231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.783979231
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.852755034
Short name T1011
Test name
Test status
Simulation time 96922517985 ps
CPU time 69.92 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:41:05 PM PDT 24
Peak memory 200424 kb
Host smart-c86beae4-81a1-4d98-b7ce-4d2e60261305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852755034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.852755034
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3407251292
Short name T849
Test name
Test status
Simulation time 27518808759 ps
CPU time 1332.88 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 03:02:11 PM PDT 24
Peak memory 200932 kb
Host smart-528efdd0-5657-41c1-b8aa-647012f8b6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407251292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3407251292
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3386504205
Short name T680
Test name
Test status
Simulation time 3647905457 ps
CPU time 5.13 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 198916 kb
Host smart-d03c64be-25ad-47c0-9dbc-a0a60e632d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386504205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3386504205
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2610936860
Short name T268
Test name
Test status
Simulation time 44484377685 ps
CPU time 23.44 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 200792 kb
Host smart-462c90d3-85bb-4cad-9c63-448f402a2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610936860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2610936860
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1470587922
Short name T692
Test name
Test status
Simulation time 4802839740 ps
CPU time 4.96 seconds
Started Apr 16 02:39:52 PM PDT 24
Finished Apr 16 02:39:57 PM PDT 24
Peak memory 196764 kb
Host smart-860a89bb-3597-4d32-b081-a4be0067171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470587922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1470587922
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1675628711
Short name T1126
Test name
Test status
Simulation time 839231586 ps
CPU time 4.55 seconds
Started Apr 16 02:39:53 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 199244 kb
Host smart-a6bb3e08-a8f9-4f32-964c-c8e38e29bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675628711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1675628711
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.335441574
Short name T490
Test name
Test status
Simulation time 192292338046 ps
CPU time 281.62 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 02:44:40 PM PDT 24
Peak memory 200856 kb
Host smart-23eac989-83d9-4a27-a9b0-2d5900499bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335441574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.335441574
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1852465297
Short name T647
Test name
Test status
Simulation time 33081223174 ps
CPU time 199.22 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:43:17 PM PDT 24
Peak memory 217512 kb
Host smart-22ae184a-ef8f-4a94-a8cc-447c4b1edb32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852465297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1852465297
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3579731125
Short name T362
Test name
Test status
Simulation time 1720587966 ps
CPU time 1.68 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 199584 kb
Host smart-12472910-e80d-4162-84a7-0a4f249d6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579731125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3579731125
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.554963236
Short name T489
Test name
Test status
Simulation time 29259083230 ps
CPU time 54.17 seconds
Started Apr 16 02:39:50 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 200884 kb
Host smart-da3cfafa-483a-43cc-86d7-bc3d9ddde2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554963236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.554963236
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4201162887
Short name T820
Test name
Test status
Simulation time 36892049938 ps
CPU time 17.13 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:43:19 PM PDT 24
Peak memory 200820 kb
Host smart-e02d6d24-3aad-40ea-9669-ab1ffdb4b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201162887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4201162887
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3899771524
Short name T151
Test name
Test status
Simulation time 34487015948 ps
CPU time 16.2 seconds
Started Apr 16 02:43:02 PM PDT 24
Finished Apr 16 02:43:19 PM PDT 24
Peak memory 200824 kb
Host smart-05f3badc-a35f-46f8-a3b0-9a57f941bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899771524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3899771524
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1160458320
Short name T705
Test name
Test status
Simulation time 189315899954 ps
CPU time 83.18 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:44:25 PM PDT 24
Peak memory 200872 kb
Host smart-a84fc74a-fdce-412e-abbd-f0d6cde2a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160458320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1160458320
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4191356997
Short name T895
Test name
Test status
Simulation time 46877647390 ps
CPU time 18.78 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:43:21 PM PDT 24
Peak memory 200836 kb
Host smart-73d3c431-2546-4012-a2ec-56c84a62737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191356997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4191356997
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1131248174
Short name T945
Test name
Test status
Simulation time 127087330858 ps
CPU time 341.79 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:48:44 PM PDT 24
Peak memory 200836 kb
Host smart-e855e990-b9e4-4ad2-a543-7afd17029d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131248174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1131248174
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1336319391
Short name T1121
Test name
Test status
Simulation time 78400695931 ps
CPU time 30.63 seconds
Started Apr 16 02:43:03 PM PDT 24
Finished Apr 16 02:43:34 PM PDT 24
Peak memory 200892 kb
Host smart-575c45d1-4983-4033-b257-7052123ccb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336319391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1336319391
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.47636831
Short name T780
Test name
Test status
Simulation time 39203153302 ps
CPU time 16.21 seconds
Started Apr 16 02:43:07 PM PDT 24
Finished Apr 16 02:43:24 PM PDT 24
Peak memory 200824 kb
Host smart-35828e3d-38ed-45cd-a236-ac7ec4310f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47636831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.47636831
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.328681208
Short name T981
Test name
Test status
Simulation time 12442475844 ps
CPU time 17.9 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:43:19 PM PDT 24
Peak memory 200692 kb
Host smart-f4dab736-46c5-4820-89b9-c8580f821575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328681208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.328681208
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2311323940
Short name T679
Test name
Test status
Simulation time 35395218 ps
CPU time 0.54 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:04 PM PDT 24
Peak memory 196172 kb
Host smart-21a88017-59b3-40f4-8d0d-589f862c5bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311323940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2311323940
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.196409619
Short name T990
Test name
Test status
Simulation time 121660768878 ps
CPU time 196.87 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 02:43:15 PM PDT 24
Peak memory 200832 kb
Host smart-929fb0f5-6f16-4998-ae1f-e9c1823f4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196409619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.196409619
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2048213096
Short name T32
Test name
Test status
Simulation time 18749805418 ps
CPU time 30.86 seconds
Started Apr 16 02:39:57 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 200604 kb
Host smart-1a9e8af4-a5e1-4943-a578-f8acb9b2423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048213096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2048213096
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3960370447
Short name T198
Test name
Test status
Simulation time 128738384884 ps
CPU time 25.77 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:40:22 PM PDT 24
Peak memory 200836 kb
Host smart-88cd2d4e-c014-4336-8c5c-e2abfbddf890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960370447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3960370447
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2270066229
Short name T1
Test name
Test status
Simulation time 18556808064 ps
CPU time 12 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:40:08 PM PDT 24
Peak memory 200788 kb
Host smart-58ee5c5a-ab76-43e1-8699-9111f2839aae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270066229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2270066229
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.649260225
Short name T785
Test name
Test status
Simulation time 106317983203 ps
CPU time 342.14 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:45:39 PM PDT 24
Peak memory 200872 kb
Host smart-88975280-4a7a-4613-a26f-1a4bc18d6dbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649260225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.649260225
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3590912083
Short name T908
Test name
Test status
Simulation time 4318840946 ps
CPU time 8.33 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:06 PM PDT 24
Peak memory 199056 kb
Host smart-ef6b0208-ade5-4bb0-abb8-b02a067d1890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590912083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3590912083
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.837513349
Short name T266
Test name
Test status
Simulation time 149444957328 ps
CPU time 76.37 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 209016 kb
Host smart-0f58aaa5-79b3-41da-99b9-aa51d2c6a2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837513349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.837513349
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2548767785
Short name T669
Test name
Test status
Simulation time 13143186946 ps
CPU time 591.09 seconds
Started Apr 16 02:39:55 PM PDT 24
Finished Apr 16 02:49:47 PM PDT 24
Peak memory 200860 kb
Host smart-52b47618-6851-406b-855c-b3dadec60a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2548767785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2548767785
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3108235635
Short name T958
Test name
Test status
Simulation time 7182054360 ps
CPU time 30.8 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:28 PM PDT 24
Peak memory 198912 kb
Host smart-51a6c657-1aa6-4e85-b4d0-01531d4918d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108235635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3108235635
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1948692639
Short name T706
Test name
Test status
Simulation time 150573046237 ps
CPU time 28.42 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:26 PM PDT 24
Peak memory 200820 kb
Host smart-f43e4edb-6d78-492f-9b4b-7596eed15764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948692639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1948692639
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2028892486
Short name T406
Test name
Test status
Simulation time 4606482714 ps
CPU time 2.5 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 196908 kb
Host smart-6569b9fb-9589-43f4-942e-33fc19c6c0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028892486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2028892486
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2159421733
Short name T828
Test name
Test status
Simulation time 6072795028 ps
CPU time 17.91 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:15 PM PDT 24
Peak memory 200720 kb
Host smart-6cacca81-ea0b-4d49-8154-23abf3dc138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159421733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2159421733
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.805788818
Short name T1183
Test name
Test status
Simulation time 376174489603 ps
CPU time 175.05 seconds
Started Apr 16 02:39:58 PM PDT 24
Finished Apr 16 02:42:54 PM PDT 24
Peak memory 200816 kb
Host smart-769578ba-ebec-4863-b537-0dfde936eeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805788818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.805788818
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2651439589
Short name T1155
Test name
Test status
Simulation time 1593951565 ps
CPU time 2.8 seconds
Started Apr 16 02:39:54 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 199792 kb
Host smart-e63b4399-92c0-431f-b6cd-e27b323c3ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651439589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2651439589
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.795910026
Short name T250
Test name
Test status
Simulation time 92226534311 ps
CPU time 17.98 seconds
Started Apr 16 02:39:56 PM PDT 24
Finished Apr 16 02:40:15 PM PDT 24
Peak memory 200880 kb
Host smart-165eceaa-7cfc-4164-a1fb-c79afb4f9c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795910026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.795910026
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1907238581
Short name T1020
Test name
Test status
Simulation time 84896919707 ps
CPU time 37.26 seconds
Started Apr 16 02:43:02 PM PDT 24
Finished Apr 16 02:43:40 PM PDT 24
Peak memory 200792 kb
Host smart-8c841b38-065b-4d29-9544-0984fb19ca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907238581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1907238581
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3538616780
Short name T1127
Test name
Test status
Simulation time 114467348689 ps
CPU time 43.79 seconds
Started Apr 16 02:43:05 PM PDT 24
Finished Apr 16 02:43:49 PM PDT 24
Peak memory 200836 kb
Host smart-47789b0e-68e5-4a5b-a766-59cc3a8b86a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538616780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3538616780
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.773128736
Short name T516
Test name
Test status
Simulation time 152044859188 ps
CPU time 118.44 seconds
Started Apr 16 02:43:02 PM PDT 24
Finished Apr 16 02:45:01 PM PDT 24
Peak memory 200812 kb
Host smart-d2d608ea-5ec6-43d2-b58c-039f24167796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773128736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.773128736
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.4173784792
Short name T1108
Test name
Test status
Simulation time 18345518156 ps
CPU time 33.25 seconds
Started Apr 16 02:43:01 PM PDT 24
Finished Apr 16 02:43:36 PM PDT 24
Peak memory 200904 kb
Host smart-a2d20879-5023-4ae8-9608-2021d3dc33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173784792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.4173784792
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2070582738
Short name T889
Test name
Test status
Simulation time 117809160997 ps
CPU time 48.53 seconds
Started Apr 16 02:43:06 PM PDT 24
Finished Apr 16 02:43:55 PM PDT 24
Peak memory 200904 kb
Host smart-0b52a14a-9a4f-4c03-848c-fd602203479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070582738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2070582738
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1340985343
Short name T1159
Test name
Test status
Simulation time 8164138955 ps
CPU time 14.11 seconds
Started Apr 16 02:43:08 PM PDT 24
Finished Apr 16 02:43:23 PM PDT 24
Peak memory 200796 kb
Host smart-49e5ceec-5288-4e7a-8b55-6f0493353355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340985343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1340985343
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.551029791
Short name T236
Test name
Test status
Simulation time 10635244324 ps
CPU time 18.95 seconds
Started Apr 16 02:43:05 PM PDT 24
Finished Apr 16 02:43:25 PM PDT 24
Peak memory 200744 kb
Host smart-bba3db6e-f29c-47da-b249-48bee19219d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551029791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.551029791
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3476006251
Short name T594
Test name
Test status
Simulation time 192366227717 ps
CPU time 351.57 seconds
Started Apr 16 02:43:05 PM PDT 24
Finished Apr 16 02:48:57 PM PDT 24
Peak memory 200756 kb
Host smart-8855f785-e07c-4a79-8341-b95b5c51ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476006251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3476006251
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3054847461
Short name T793
Test name
Test status
Simulation time 78763869896 ps
CPU time 24.66 seconds
Started Apr 16 02:43:05 PM PDT 24
Finished Apr 16 02:43:30 PM PDT 24
Peak memory 200856 kb
Host smart-08f39b73-d3d3-4b9b-9d00-bc4e53544de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054847461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3054847461
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4290085192
Short name T370
Test name
Test status
Simulation time 14355380 ps
CPU time 0.58 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:02 PM PDT 24
Peak memory 196232 kb
Host smart-e2dc0e4d-58aa-46c2-a850-37df8df454ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290085192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4290085192
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1925634784
Short name T961
Test name
Test status
Simulation time 116880125840 ps
CPU time 20.45 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:24 PM PDT 24
Peak memory 199680 kb
Host smart-2333639b-b698-40bc-b406-af12222a9a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925634784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1925634784
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1679217381
Short name T141
Test name
Test status
Simulation time 84567210859 ps
CPU time 13.64 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 200332 kb
Host smart-6839158c-d456-403d-838d-e67c47f5b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679217381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1679217381
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1845840610
Short name T637
Test name
Test status
Simulation time 107682693691 ps
CPU time 82.34 seconds
Started Apr 16 02:39:58 PM PDT 24
Finished Apr 16 02:41:21 PM PDT 24
Peak memory 200796 kb
Host smart-9d6a2ea5-851a-41c0-ac06-18eaf7f8fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845840610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1845840610
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3727908408
Short name T1145
Test name
Test status
Simulation time 32202085326 ps
CPU time 56.93 seconds
Started Apr 16 02:39:59 PM PDT 24
Finished Apr 16 02:40:57 PM PDT 24
Peak memory 200720 kb
Host smart-4bc898cf-d9f4-42a7-b275-c3e35b024fad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727908408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3727908408
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_loopback.1166872
Short name T865
Test name
Test status
Simulation time 944690751 ps
CPU time 1.36 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:40:06 PM PDT 24
Peak memory 196288 kb
Host smart-f48b0801-213d-472e-9efb-c33c5812c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1166872
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3839984815
Short name T652
Test name
Test status
Simulation time 52506035731 ps
CPU time 53.61 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:41:02 PM PDT 24
Peak memory 200388 kb
Host smart-30cb75d8-b970-4a82-9d27-3b14e500781d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839984815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3839984815
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2997027955
Short name T925
Test name
Test status
Simulation time 15333189517 ps
CPU time 139.48 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:42:23 PM PDT 24
Peak memory 200876 kb
Host smart-2a5a8951-e1d7-40a2-8bb4-431c9a8102f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997027955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2997027955
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.23309241
Short name T911
Test name
Test status
Simulation time 1336446049 ps
CPU time 0.73 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:03 PM PDT 24
Peak memory 196548 kb
Host smart-5d986f2d-913f-4e09-9516-f910a83538ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23309241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.23309241
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1659530315
Short name T143
Test name
Test status
Simulation time 151260263173 ps
CPU time 153.37 seconds
Started Apr 16 02:39:58 PM PDT 24
Finished Apr 16 02:42:32 PM PDT 24
Peak memory 200728 kb
Host smart-428540f8-90fa-49d6-acfe-7c3b8ac8e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659530315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1659530315
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2936960410
Short name T854
Test name
Test status
Simulation time 5549651197 ps
CPU time 2.77 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:07 PM PDT 24
Peak memory 196872 kb
Host smart-17ce050f-bc1c-4d6a-87bf-f78534e89bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936960410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2936960410
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2681169889
Short name T862
Test name
Test status
Simulation time 653300083 ps
CPU time 1.76 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:03 PM PDT 24
Peak memory 200152 kb
Host smart-1ca9ce3d-8c3c-496f-8867-91af67dcd002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681169889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2681169889
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.803352282
Short name T1018
Test name
Test status
Simulation time 9383299244 ps
CPU time 13.44 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:40:22 PM PDT 24
Peak memory 200804 kb
Host smart-a30d5b68-2f50-44ac-a3d6-99f44ecb20cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803352282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.803352282
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3970322253
Short name T24
Test name
Test status
Simulation time 60407255086 ps
CPU time 1014.97 seconds
Started Apr 16 02:40:00 PM PDT 24
Finished Apr 16 02:56:56 PM PDT 24
Peak memory 217552 kb
Host smart-5351f778-c14b-4ca5-8218-7c15ec68472a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970322253 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3970322253
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1116670869
Short name T541
Test name
Test status
Simulation time 7112258195 ps
CPU time 15.12 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 200240 kb
Host smart-740a56ae-4ae5-4154-bdd4-e993264c6c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116670869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1116670869
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3021027314
Short name T522
Test name
Test status
Simulation time 34921042348 ps
CPU time 61.53 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:41:03 PM PDT 24
Peak memory 200920 kb
Host smart-1bb4b4a1-162a-4144-96b0-c9539717b871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021027314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3021027314
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1151653991
Short name T1109
Test name
Test status
Simulation time 222627210900 ps
CPU time 363.52 seconds
Started Apr 16 02:43:08 PM PDT 24
Finished Apr 16 02:49:12 PM PDT 24
Peak memory 200808 kb
Host smart-d204cf9e-8d81-49ef-bde6-94f718a54511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151653991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1151653991
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2296856857
Short name T210
Test name
Test status
Simulation time 84203020626 ps
CPU time 117.85 seconds
Started Apr 16 02:43:06 PM PDT 24
Finished Apr 16 02:45:05 PM PDT 24
Peak memory 200860 kb
Host smart-ccbfc5c3-33f8-475a-8f1d-cca2b010111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296856857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2296856857
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2250558567
Short name T163
Test name
Test status
Simulation time 252130645903 ps
CPU time 102.78 seconds
Started Apr 16 02:43:09 PM PDT 24
Finished Apr 16 02:44:52 PM PDT 24
Peak memory 200868 kb
Host smart-18f6f9b7-5a1a-489a-a526-8cb91d380805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250558567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2250558567
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3039558271
Short name T892
Test name
Test status
Simulation time 78567932172 ps
CPU time 158.1 seconds
Started Apr 16 02:43:09 PM PDT 24
Finished Apr 16 02:45:47 PM PDT 24
Peak memory 200936 kb
Host smart-6ac0fd3a-dc0d-4dcf-a834-2fe702c26d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039558271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3039558271
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2645724816
Short name T529
Test name
Test status
Simulation time 33319505904 ps
CPU time 80.45 seconds
Started Apr 16 02:43:09 PM PDT 24
Finished Apr 16 02:44:29 PM PDT 24
Peak memory 200856 kb
Host smart-b3aef38d-71b8-4adf-9fd5-a50a2d812aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645724816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2645724816
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.119066853
Short name T265
Test name
Test status
Simulation time 220537906009 ps
CPU time 22.6 seconds
Started Apr 16 02:43:11 PM PDT 24
Finished Apr 16 02:43:34 PM PDT 24
Peak memory 200600 kb
Host smart-845d4ae1-23f9-4c17-b1cc-79bce6848ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119066853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.119066853
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1959980361
Short name T1059
Test name
Test status
Simulation time 27165956284 ps
CPU time 24.56 seconds
Started Apr 16 02:43:11 PM PDT 24
Finished Apr 16 02:43:37 PM PDT 24
Peak memory 200920 kb
Host smart-b5ecb232-8e86-4485-9af3-3fd07ff1ecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959980361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1959980361
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.2774420162
Short name T824
Test name
Test status
Simulation time 141915980255 ps
CPU time 28.71 seconds
Started Apr 16 02:43:11 PM PDT 24
Finished Apr 16 02:43:40 PM PDT 24
Peak memory 200692 kb
Host smart-1f89bc2e-6e1e-422d-a2ac-c42c301e4741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774420162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2774420162
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.443250379
Short name T713
Test name
Test status
Simulation time 15602364 ps
CPU time 0.57 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:07 PM PDT 24
Peak memory 196192 kb
Host smart-baed8275-0c7a-4b06-ba86-4a337099385e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443250379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.443250379
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1175353685
Short name T118
Test name
Test status
Simulation time 47652516462 ps
CPU time 40.32 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 200888 kb
Host smart-52329b1b-7eeb-439f-b949-cd68aa93c287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175353685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1175353685
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1504623362
Short name T915
Test name
Test status
Simulation time 41613206502 ps
CPU time 71.68 seconds
Started Apr 16 02:39:59 PM PDT 24
Finished Apr 16 02:41:11 PM PDT 24
Peak memory 200784 kb
Host smart-c42aa48f-08f9-41a2-844f-45c704728edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504623362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1504623362
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.461877459
Short name T191
Test name
Test status
Simulation time 158453341468 ps
CPU time 54.33 seconds
Started Apr 16 02:40:00 PM PDT 24
Finished Apr 16 02:40:55 PM PDT 24
Peak memory 200808 kb
Host smart-3eabbbe0-3fa1-45fa-a0e8-87f13a155ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461877459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.461877459
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.47741200
Short name T662
Test name
Test status
Simulation time 37148516969 ps
CPU time 19.69 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:21 PM PDT 24
Peak memory 200860 kb
Host smart-cb1f3816-cf0e-4afe-9a49-9c555df51e94
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47741200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.47741200
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1926061071
Short name T1149
Test name
Test status
Simulation time 267862399919 ps
CPU time 305.88 seconds
Started Apr 16 02:40:02 PM PDT 24
Finished Apr 16 02:45:08 PM PDT 24
Peak memory 200820 kb
Host smart-c07900e4-3d55-43e7-9321-bff120984f37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926061071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1926061071
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.280129550
Short name T450
Test name
Test status
Simulation time 10772622543 ps
CPU time 17.29 seconds
Started Apr 16 02:39:58 PM PDT 24
Finished Apr 16 02:40:16 PM PDT 24
Peak memory 200752 kb
Host smart-3b045c72-1917-4b0a-a844-fe31c076e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280129550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.280129550
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3857412921
Short name T276
Test name
Test status
Simulation time 75607472024 ps
CPU time 74.2 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:41:22 PM PDT 24
Peak memory 200464 kb
Host smart-cd57895e-cd1d-4f2d-98e2-75309fd42aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857412921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3857412921
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3037255723
Short name T550
Test name
Test status
Simulation time 19993923635 ps
CPU time 70.72 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 200860 kb
Host smart-5291db80-6bc9-4017-b4e7-491dd6ac38e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037255723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3037255723
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3237595388
Short name T614
Test name
Test status
Simulation time 7066079637 ps
CPU time 15.97 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 199908 kb
Host smart-1ef539ef-5013-4b13-894b-dbd47d8b31e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237595388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3237595388
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3725702952
Short name T171
Test name
Test status
Simulation time 145577550697 ps
CPU time 22.67 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:40:25 PM PDT 24
Peak memory 200896 kb
Host smart-ea0d32ba-8b6c-490f-81e1-d0e17b5130d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725702952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3725702952
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3847699516
Short name T995
Test name
Test status
Simulation time 44249216782 ps
CPU time 65.12 seconds
Started Apr 16 02:40:01 PM PDT 24
Finished Apr 16 02:41:07 PM PDT 24
Peak memory 196908 kb
Host smart-624365eb-883c-4211-937c-570dcaff3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847699516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3847699516
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4290120005
Short name T800
Test name
Test status
Simulation time 5991377969 ps
CPU time 19.7 seconds
Started Apr 16 02:40:08 PM PDT 24
Finished Apr 16 02:40:28 PM PDT 24
Peak memory 200044 kb
Host smart-50536397-58b1-47a4-afdd-017c18793aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290120005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4290120005
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1151684641
Short name T503
Test name
Test status
Simulation time 872666235637 ps
CPU time 1574.52 seconds
Started Apr 16 02:40:06 PM PDT 24
Finished Apr 16 03:06:21 PM PDT 24
Peak memory 200836 kb
Host smart-61f50842-9dc0-40d5-b796-170bf4599328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151684641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1151684641
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1942781328
Short name T512
Test name
Test status
Simulation time 40651452408 ps
CPU time 531.95 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:48:58 PM PDT 24
Peak memory 217308 kb
Host smart-34b9abc9-21a6-482d-8d37-8c9cfe412394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942781328 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1942781328
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3711762661
Short name T294
Test name
Test status
Simulation time 1703494782 ps
CPU time 2.77 seconds
Started Apr 16 02:40:02 PM PDT 24
Finished Apr 16 02:40:05 PM PDT 24
Peak memory 199644 kb
Host smart-fb008151-92ce-43e0-bfc4-aa1c0d9cd5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711762661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3711762661
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2583123612
Short name T1012
Test name
Test status
Simulation time 54949110672 ps
CPU time 191.49 seconds
Started Apr 16 02:40:00 PM PDT 24
Finished Apr 16 02:43:12 PM PDT 24
Peak memory 200856 kb
Host smart-479f035e-8972-45c7-9c10-61ae6cdacce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583123612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2583123612
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2564683719
Short name T806
Test name
Test status
Simulation time 17368343618 ps
CPU time 19.18 seconds
Started Apr 16 02:43:13 PM PDT 24
Finished Apr 16 02:43:33 PM PDT 24
Peak memory 200796 kb
Host smart-3365ed99-5f05-4fed-9d57-83c7b958111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564683719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2564683719
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2185936060
Short name T738
Test name
Test status
Simulation time 241087916001 ps
CPU time 217.4 seconds
Started Apr 16 02:43:13 PM PDT 24
Finished Apr 16 02:46:51 PM PDT 24
Peak memory 200724 kb
Host smart-c87d7b45-0bb8-4911-81e0-c2b96afefc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185936060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2185936060
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4050005192
Short name T318
Test name
Test status
Simulation time 44846820547 ps
CPU time 39.01 seconds
Started Apr 16 02:43:10 PM PDT 24
Finished Apr 16 02:43:49 PM PDT 24
Peak memory 200924 kb
Host smart-baa75a2d-9010-4ad5-9b4d-bd5894aa827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050005192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4050005192
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2893325267
Short name T510
Test name
Test status
Simulation time 273660017698 ps
CPU time 44.88 seconds
Started Apr 16 02:43:10 PM PDT 24
Finished Apr 16 02:43:56 PM PDT 24
Peak memory 200832 kb
Host smart-a0cb13f8-d62e-415e-8e73-db48c93b3a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893325267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2893325267
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1232386583
Short name T255
Test name
Test status
Simulation time 114569890904 ps
CPU time 41.66 seconds
Started Apr 16 02:43:15 PM PDT 24
Finished Apr 16 02:43:57 PM PDT 24
Peak memory 200860 kb
Host smart-1e498c07-469b-45e8-8207-bf872a59c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232386583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1232386583
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.327571971
Short name T122
Test name
Test status
Simulation time 159806470210 ps
CPU time 51.24 seconds
Started Apr 16 02:43:16 PM PDT 24
Finished Apr 16 02:44:08 PM PDT 24
Peak memory 200840 kb
Host smart-00069310-380e-4c43-bb41-f22857ae0eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327571971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.327571971
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3362716722
Short name T201
Test name
Test status
Simulation time 24942153440 ps
CPU time 60.42 seconds
Started Apr 16 02:43:17 PM PDT 24
Finished Apr 16 02:44:18 PM PDT 24
Peak memory 200856 kb
Host smart-33f1fe01-8786-4b31-97d4-a41949d37b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362716722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3362716722
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.522930357
Short name T756
Test name
Test status
Simulation time 13288432068 ps
CPU time 25.22 seconds
Started Apr 16 02:43:16 PM PDT 24
Finished Apr 16 02:43:42 PM PDT 24
Peak memory 200912 kb
Host smart-ada0c9e8-fc3d-4197-a19d-6ef0a440b81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522930357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.522930357
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3784096369
Short name T667
Test name
Test status
Simulation time 21808582668 ps
CPU time 47.01 seconds
Started Apr 16 02:43:14 PM PDT 24
Finished Apr 16 02:44:02 PM PDT 24
Peak memory 200884 kb
Host smart-bd9eaad2-0242-444d-b5ea-87461313eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784096369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3784096369
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3629418342
Short name T709
Test name
Test status
Simulation time 18030396 ps
CPU time 0.56 seconds
Started Apr 16 02:40:08 PM PDT 24
Finished Apr 16 02:40:09 PM PDT 24
Peak memory 196208 kb
Host smart-125f5015-74c1-437a-8560-a7b29e3d09bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629418342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3629418342
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.199376912
Short name T526
Test name
Test status
Simulation time 138963416573 ps
CPU time 215.63 seconds
Started Apr 16 02:40:06 PM PDT 24
Finished Apr 16 02:43:43 PM PDT 24
Peak memory 200868 kb
Host smart-3438fdfc-8036-4493-8e7c-5c8d6a1022d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199376912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.199376912
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3176726733
Short name T389
Test name
Test status
Simulation time 62351897101 ps
CPU time 17.35 seconds
Started Apr 16 02:40:03 PM PDT 24
Finished Apr 16 02:40:21 PM PDT 24
Peak memory 200916 kb
Host smart-3b4a849a-97cf-426d-b924-d10db315bd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176726733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3176726733
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4255980268
Short name T914
Test name
Test status
Simulation time 23608973998 ps
CPU time 12.53 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 200700 kb
Host smart-6a53a084-6c91-4026-9383-de076651cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255980268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4255980268
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2572382788
Short name T437
Test name
Test status
Simulation time 63492090060 ps
CPU time 30.93 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 200032 kb
Host smart-56cf22c5-6e5a-436e-b35d-6f3b92aaf9a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572382788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2572382788
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1583438064
Short name T927
Test name
Test status
Simulation time 76758597838 ps
CPU time 269.05 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:44:34 PM PDT 24
Peak memory 201092 kb
Host smart-a64b83d6-ced8-4520-a5d5-dff98e87cba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583438064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1583438064
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2613039653
Short name T816
Test name
Test status
Simulation time 9440997267 ps
CPU time 9.29 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 200684 kb
Host smart-40d575d8-cef6-4f90-9604-55e584747817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613039653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2613039653
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.2615955905
Short name T530
Test name
Test status
Simulation time 23052765364 ps
CPU time 905.7 seconds
Started Apr 16 02:40:06 PM PDT 24
Finished Apr 16 02:55:13 PM PDT 24
Peak memory 200912 kb
Host smart-0ce2e223-c7fe-4d31-9c12-4ecdde9340e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2615955905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2615955905
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1451544510
Short name T1134
Test name
Test status
Simulation time 2655784805 ps
CPU time 5.33 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:40:14 PM PDT 24
Peak memory 199004 kb
Host smart-bd08edf5-98fb-4ca2-87eb-ea932988b29f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451544510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1451544510
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.424020394
Short name T884
Test name
Test status
Simulation time 228462148794 ps
CPU time 443.59 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:47:32 PM PDT 24
Peak memory 200836 kb
Host smart-37f6c4df-c986-436e-9629-83c649291679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424020394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.424020394
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.293670087
Short name T1004
Test name
Test status
Simulation time 2717355035 ps
CPU time 2.59 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:09 PM PDT 24
Peak memory 196856 kb
Host smart-fc9160c5-03b6-41f0-a75d-4d65213ddaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293670087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.293670087
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2766077364
Short name T295
Test name
Test status
Simulation time 889599390 ps
CPU time 3.3 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:10 PM PDT 24
Peak memory 199592 kb
Host smart-675487d4-b828-4233-9805-17d5a8a44ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766077364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2766077364
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3383387476
Short name T508
Test name
Test status
Simulation time 122132745067 ps
CPU time 204.24 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:43:30 PM PDT 24
Peak memory 200880 kb
Host smart-8d60ce1f-7174-441e-b550-4635a5a5c272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383387476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3383387476
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3052166265
Short name T73
Test name
Test status
Simulation time 417225678285 ps
CPU time 901.05 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:55:07 PM PDT 24
Peak memory 225712 kb
Host smart-cb83730f-c046-4571-b919-0972a063b595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052166265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3052166265
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2531287903
Short name T544
Test name
Test status
Simulation time 1564297023 ps
CPU time 1.74 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:08 PM PDT 24
Peak memory 199288 kb
Host smart-fafc7036-e305-49a0-816b-46021b9edc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531287903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2531287903
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2508563534
Short name T106
Test name
Test status
Simulation time 146216946456 ps
CPU time 56.54 seconds
Started Apr 16 02:40:08 PM PDT 24
Finished Apr 16 02:41:06 PM PDT 24
Peak memory 200888 kb
Host smart-f677a213-18ce-4fa9-8307-9d21386ea51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508563534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2508563534
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2785320712
Short name T1118
Test name
Test status
Simulation time 29496974646 ps
CPU time 31.57 seconds
Started Apr 16 02:43:16 PM PDT 24
Finished Apr 16 02:43:48 PM PDT 24
Peak memory 200636 kb
Host smart-aa00f634-2867-4d06-a541-a107805dfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785320712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2785320712
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3249372036
Short name T597
Test name
Test status
Simulation time 44854434005 ps
CPU time 40.13 seconds
Started Apr 16 02:43:16 PM PDT 24
Finished Apr 16 02:43:57 PM PDT 24
Peak memory 200852 kb
Host smart-c0332fd3-17b2-4a7b-9dbe-78d62786f209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249372036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3249372036
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1173435636
Short name T193
Test name
Test status
Simulation time 42086501814 ps
CPU time 40.37 seconds
Started Apr 16 02:43:19 PM PDT 24
Finished Apr 16 02:44:00 PM PDT 24
Peak memory 200820 kb
Host smart-176fb06a-175d-43ee-87d4-f6dad1d39113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173435636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1173435636
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3314466811
Short name T579
Test name
Test status
Simulation time 121286611519 ps
CPU time 348.57 seconds
Started Apr 16 02:43:21 PM PDT 24
Finished Apr 16 02:49:10 PM PDT 24
Peak memory 200856 kb
Host smart-5c6c963a-d535-4eb4-82c9-73cadc3eb71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314466811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3314466811
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2744009521
Short name T885
Test name
Test status
Simulation time 83535709596 ps
CPU time 142.97 seconds
Started Apr 16 02:43:20 PM PDT 24
Finished Apr 16 02:45:43 PM PDT 24
Peak memory 200816 kb
Host smart-47374e2c-5c55-45f2-836d-0880be70231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744009521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2744009521
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1563052898
Short name T697
Test name
Test status
Simulation time 54998891841 ps
CPU time 45.29 seconds
Started Apr 16 02:43:18 PM PDT 24
Finished Apr 16 02:44:04 PM PDT 24
Peak memory 200864 kb
Host smart-eb72e671-404a-46f3-868b-a068994ce226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563052898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1563052898
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2530003603
Short name T293
Test name
Test status
Simulation time 43715461981 ps
CPU time 38.15 seconds
Started Apr 16 02:43:20 PM PDT 24
Finished Apr 16 02:43:58 PM PDT 24
Peak memory 200840 kb
Host smart-8b963b2e-e324-4213-b611-a353f82149e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530003603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2530003603
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2939030368
Short name T904
Test name
Test status
Simulation time 25946860450 ps
CPU time 43.72 seconds
Started Apr 16 02:43:19 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200844 kb
Host smart-b4a52324-b162-4299-ac72-69b5c89e2f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939030368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2939030368
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.269028396
Short name T701
Test name
Test status
Simulation time 32169368 ps
CPU time 0.56 seconds
Started Apr 16 02:40:12 PM PDT 24
Finished Apr 16 02:40:13 PM PDT 24
Peak memory 196172 kb
Host smart-ae74366c-33c9-462c-99a7-da42dce8339b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269028396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.269028396
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4151451377
Short name T928
Test name
Test status
Simulation time 37636655478 ps
CPU time 17.14 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:23 PM PDT 24
Peak memory 200824 kb
Host smart-715de4a8-8aa8-41af-be9f-bae258dafa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151451377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4151451377
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2096295770
Short name T415
Test name
Test status
Simulation time 138823311472 ps
CPU time 209.02 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:43:34 PM PDT 24
Peak memory 200656 kb
Host smart-60aa34d0-410a-44d0-9cf1-ac3e6273678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096295770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2096295770
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.867320656
Short name T346
Test name
Test status
Simulation time 120245531094 ps
CPU time 186.04 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:43:12 PM PDT 24
Peak memory 200912 kb
Host smart-2953e034-87df-4934-aab8-7627866ed816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867320656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.867320656
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1676222721
Short name T488
Test name
Test status
Simulation time 33283135613 ps
CPU time 32.82 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:38 PM PDT 24
Peak memory 200884 kb
Host smart-0400592e-8995-475e-8bd7-929c53545c23
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676222721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1676222721
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2724219763
Short name T1041
Test name
Test status
Simulation time 93682978185 ps
CPU time 570.07 seconds
Started Apr 16 02:40:10 PM PDT 24
Finished Apr 16 02:49:41 PM PDT 24
Peak memory 200904 kb
Host smart-4f8f073b-ec3b-4e2a-adbc-f68eaa903706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724219763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2724219763
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.906286939
Short name T348
Test name
Test status
Simulation time 1489708867 ps
CPU time 1.49 seconds
Started Apr 16 02:40:10 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 197728 kb
Host smart-323f9419-98bd-4e3c-ae33-58f83df2661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906286939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.906286939
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1773602616
Short name T1137
Test name
Test status
Simulation time 71520245307 ps
CPU time 33.42 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:40:41 PM PDT 24
Peak memory 200172 kb
Host smart-3a47701c-f074-4e9f-94a7-cd0d2bc18255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773602616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1773602616
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2968843699
Short name T900
Test name
Test status
Simulation time 16367264046 ps
CPU time 223.86 seconds
Started Apr 16 02:40:08 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200840 kb
Host smart-de6ca837-70f9-4280-896f-6c1f216897cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968843699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2968843699
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3218611276
Short name T880
Test name
Test status
Simulation time 1818749997 ps
CPU time 2.6 seconds
Started Apr 16 02:40:04 PM PDT 24
Finished Apr 16 02:40:08 PM PDT 24
Peak memory 198952 kb
Host smart-d6b700a3-ff16-47ab-b100-4d927b06e749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218611276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3218611276
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3836200570
Short name T864
Test name
Test status
Simulation time 28339363750 ps
CPU time 39.86 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:54 PM PDT 24
Peak memory 200808 kb
Host smart-1276ddcb-8d67-452b-ba17-a2dc177f6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836200570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3836200570
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2234269135
Short name T64
Test name
Test status
Simulation time 740026142 ps
CPU time 1.2 seconds
Started Apr 16 02:40:09 PM PDT 24
Finished Apr 16 02:40:11 PM PDT 24
Peak memory 196532 kb
Host smart-fb08a94e-3a24-4357-9de7-914f13075a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234269135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2234269135
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1049145408
Short name T543
Test name
Test status
Simulation time 5293046471 ps
CPU time 11.21 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 200780 kb
Host smart-754735d3-89fa-440d-b550-7e9bd9e3a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049145408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1049145408
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.852765195
Short name T702
Test name
Test status
Simulation time 121407703462 ps
CPU time 144.92 seconds
Started Apr 16 02:40:12 PM PDT 24
Finished Apr 16 02:42:38 PM PDT 24
Peak memory 217380 kb
Host smart-26a05aac-feab-40c3-a8fe-7628a5bfe7ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852765195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.852765195
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.410588149
Short name T60
Test name
Test status
Simulation time 274940016708 ps
CPU time 185.09 seconds
Started Apr 16 02:40:11 PM PDT 24
Finished Apr 16 02:43:17 PM PDT 24
Peak memory 217480 kb
Host smart-0115334a-b62e-4d00-a9e4-7022d4f19ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410588149 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.410588149
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2429348857
Short name T768
Test name
Test status
Simulation time 675768010 ps
CPU time 2.49 seconds
Started Apr 16 02:40:11 PM PDT 24
Finished Apr 16 02:40:14 PM PDT 24
Peak memory 200492 kb
Host smart-e212bbfa-d3fb-4a70-a2dc-419acd0fa70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429348857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2429348857
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1327195409
Short name T949
Test name
Test status
Simulation time 111860092949 ps
CPU time 22.62 seconds
Started Apr 16 02:40:05 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 200816 kb
Host smart-9339ec8a-6e0f-4147-a928-2cb1312a3e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327195409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1327195409
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2272951616
Short name T568
Test name
Test status
Simulation time 19150127093 ps
CPU time 31.13 seconds
Started Apr 16 02:43:20 PM PDT 24
Finished Apr 16 02:43:51 PM PDT 24
Peak memory 200828 kb
Host smart-f2aa5058-ab03-491c-92c9-4d153922c1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272951616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2272951616
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3159058922
Short name T188
Test name
Test status
Simulation time 69043360390 ps
CPU time 25.12 seconds
Started Apr 16 02:43:19 PM PDT 24
Finished Apr 16 02:43:44 PM PDT 24
Peak memory 200920 kb
Host smart-ec0b6964-a649-4192-8915-8f449a640a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159058922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3159058922
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.387795684
Short name T1055
Test name
Test status
Simulation time 49645799516 ps
CPU time 132.13 seconds
Started Apr 16 02:43:18 PM PDT 24
Finished Apr 16 02:45:31 PM PDT 24
Peak memory 200912 kb
Host smart-fa9be940-f0fd-47f4-8073-c1a45daf9209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387795684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.387795684
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.526925490
Short name T1050
Test name
Test status
Simulation time 29591112825 ps
CPU time 16.47 seconds
Started Apr 16 02:43:21 PM PDT 24
Finished Apr 16 02:43:39 PM PDT 24
Peak memory 200876 kb
Host smart-163d2e5c-3a73-4c02-ae08-10eb9b35946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526925490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.526925490
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.575794510
Short name T65
Test name
Test status
Simulation time 25074101795 ps
CPU time 55.84 seconds
Started Apr 16 02:43:20 PM PDT 24
Finished Apr 16 02:44:17 PM PDT 24
Peak memory 200848 kb
Host smart-e77615d1-42cc-4b59-92c8-03bca98460d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575794510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.575794510
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.890114028
Short name T457
Test name
Test status
Simulation time 83043659773 ps
CPU time 24.84 seconds
Started Apr 16 02:43:21 PM PDT 24
Finished Apr 16 02:43:47 PM PDT 24
Peak memory 200900 kb
Host smart-bb659fe9-5b2b-4ad7-bdf6-995e4f8ffd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890114028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.890114028
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1727829944
Short name T51
Test name
Test status
Simulation time 10080057405 ps
CPU time 17.71 seconds
Started Apr 16 02:43:25 PM PDT 24
Finished Apr 16 02:43:43 PM PDT 24
Peak memory 200684 kb
Host smart-8e78f3e4-3f09-41f6-ac25-06d4f33ae569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727829944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1727829944
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.133773086
Short name T499
Test name
Test status
Simulation time 16977769687 ps
CPU time 11.59 seconds
Started Apr 16 02:43:26 PM PDT 24
Finished Apr 16 02:43:38 PM PDT 24
Peak memory 200820 kb
Host smart-96a757bf-c57a-49c0-b153-cb07c1adccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133773086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.133773086
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1744618703
Short name T649
Test name
Test status
Simulation time 98415667796 ps
CPU time 39.69 seconds
Started Apr 16 02:43:23 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200752 kb
Host smart-1010bf78-bbd8-4dcc-886a-f354c1017c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744618703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1744618703
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1324617466
Short name T1033
Test name
Test status
Simulation time 69915276403 ps
CPU time 43.12 seconds
Started Apr 16 02:43:23 PM PDT 24
Finished Apr 16 02:44:06 PM PDT 24
Peak memory 200848 kb
Host smart-feb34680-4893-4096-8ff2-4289ac280029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324617466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1324617466
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3008928891
Short name T655
Test name
Test status
Simulation time 48625513 ps
CPU time 0.59 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 196212 kb
Host smart-4b091ab9-8a6d-47f0-97d0-dfb742856461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008928891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3008928891
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.259709555
Short name T262
Test name
Test status
Simulation time 138735262590 ps
CPU time 598.26 seconds
Started Apr 16 02:40:12 PM PDT 24
Finished Apr 16 02:50:12 PM PDT 24
Peak memory 200896 kb
Host smart-6a755f2e-74eb-40f4-9e36-b052ef4946c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259709555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.259709555
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.180605427
Short name T799
Test name
Test status
Simulation time 4481443781 ps
CPU time 8.45 seconds
Started Apr 16 02:40:12 PM PDT 24
Finished Apr 16 02:40:21 PM PDT 24
Peak memory 200828 kb
Host smart-ff2a39ed-5ea9-4be9-9207-a552f474a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180605427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.180605427
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3377583104
Short name T758
Test name
Test status
Simulation time 10216667777 ps
CPU time 17.31 seconds
Started Apr 16 02:40:11 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 200796 kb
Host smart-de94783c-1bed-47fc-afc0-bddf7af5010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377583104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3377583104
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1359812647
Short name T1122
Test name
Test status
Simulation time 31323791350 ps
CPU time 53.49 seconds
Started Apr 16 02:40:08 PM PDT 24
Finished Apr 16 02:41:02 PM PDT 24
Peak memory 201096 kb
Host smart-c65de523-6f39-4e23-adb8-bbdb9d4e66fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359812647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1359812647
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1328227026
Short name T901
Test name
Test status
Simulation time 140704998267 ps
CPU time 706.46 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:52:03 PM PDT 24
Peak memory 200848 kb
Host smart-4d238fd4-7198-422e-ad58-b637c54493c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328227026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1328227026
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2130092292
Short name T460
Test name
Test status
Simulation time 794753076 ps
CPU time 1.01 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:16 PM PDT 24
Peak memory 198972 kb
Host smart-aa07fc32-47f2-490f-a428-8909b3d18af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130092292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2130092292
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.1079763808
Short name T527
Test name
Test status
Simulation time 107293878596 ps
CPU time 160.19 seconds
Started Apr 16 02:40:10 PM PDT 24
Finished Apr 16 02:42:52 PM PDT 24
Peak memory 201016 kb
Host smart-aef1de2f-febc-4fe4-90d1-09c87ec7b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079763808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1079763808
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2489877875
Short name T270
Test name
Test status
Simulation time 6409324885 ps
CPU time 94.27 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:41:51 PM PDT 24
Peak memory 200848 kb
Host smart-e5235682-5a98-4df9-b35b-a8d39571c4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489877875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2489877875
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1768415601
Short name T361
Test name
Test status
Simulation time 7389687669 ps
CPU time 58.55 seconds
Started Apr 16 02:40:07 PM PDT 24
Finished Apr 16 02:41:07 PM PDT 24
Peak memory 200036 kb
Host smart-88a8c30d-67bd-4cde-a758-e53a7cf20e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768415601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1768415601
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1211686142
Short name T636
Test name
Test status
Simulation time 19551652737 ps
CPU time 38.96 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:40:55 PM PDT 24
Peak memory 200832 kb
Host smart-2d2260e7-84e2-48c1-9ae7-1a60e783fd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211686142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1211686142
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2387573062
Short name T111
Test name
Test status
Simulation time 1349417230 ps
CPU time 2.83 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 196568 kb
Host smart-12ecbd69-55d8-4418-91a2-7c326e95d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387573062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2387573062
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3600976759
Short name T319
Test name
Test status
Simulation time 316858403 ps
CPU time 1.52 seconds
Started Apr 16 02:40:10 PM PDT 24
Finished Apr 16 02:40:12 PM PDT 24
Peak memory 199816 kb
Host smart-50a789b0-9a41-4f3c-9c5d-36bf2faf5b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600976759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3600976759
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3023085798
Short name T320
Test name
Test status
Simulation time 213381270313 ps
CPU time 338.03 seconds
Started Apr 16 02:40:17 PM PDT 24
Finished Apr 16 02:45:56 PM PDT 24
Peak memory 200904 kb
Host smart-7d64d342-0656-4c8c-a85f-ed2c3cb1e6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023085798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3023085798
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1793598176
Short name T711
Test name
Test status
Simulation time 19834503926 ps
CPU time 427.79 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:47:23 PM PDT 24
Peak memory 209088 kb
Host smart-98094cb9-97ec-417c-a2b1-0ca11992a5bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793598176 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1793598176
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1414812563
Short name T605
Test name
Test status
Simulation time 6623388861 ps
CPU time 16.7 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:32 PM PDT 24
Peak memory 200572 kb
Host smart-39a0b302-799d-41bf-8569-d853ea3174e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414812563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1414812563
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.4116287977
Short name T572
Test name
Test status
Simulation time 102036869541 ps
CPU time 89.11 seconds
Started Apr 16 02:40:09 PM PDT 24
Finished Apr 16 02:41:39 PM PDT 24
Peak memory 200820 kb
Host smart-79221c6e-af02-4d63-b660-fa70e95f1775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116287977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.4116287977
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1824101778
Short name T402
Test name
Test status
Simulation time 81866646967 ps
CPU time 31.68 seconds
Started Apr 16 02:43:25 PM PDT 24
Finished Apr 16 02:43:58 PM PDT 24
Peak memory 200908 kb
Host smart-933814ac-5c19-4341-ba42-140b78d215af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824101778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1824101778
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1830909392
Short name T126
Test name
Test status
Simulation time 65068753377 ps
CPU time 101.27 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:45:06 PM PDT 24
Peak memory 200892 kb
Host smart-36b899cd-009a-4565-bd39-39a41ad48f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830909392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1830909392
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3325423401
Short name T1174
Test name
Test status
Simulation time 84154850840 ps
CPU time 140.76 seconds
Started Apr 16 02:43:26 PM PDT 24
Finished Apr 16 02:45:47 PM PDT 24
Peak memory 200808 kb
Host smart-4cece005-df6b-403b-88b3-6089a17cc6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325423401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3325423401
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3380521176
Short name T229
Test name
Test status
Simulation time 139503662471 ps
CPU time 125.07 seconds
Started Apr 16 02:43:23 PM PDT 24
Finished Apr 16 02:45:28 PM PDT 24
Peak memory 200864 kb
Host smart-daf0a26c-8975-45df-855b-8ccbceb9f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380521176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3380521176
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1076161990
Short name T809
Test name
Test status
Simulation time 51524181827 ps
CPU time 24.89 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:43:49 PM PDT 24
Peak memory 200864 kb
Host smart-fd295c53-02ac-4a65-a478-bddb3f507517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076161990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1076161990
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3379254021
Short name T216
Test name
Test status
Simulation time 16093411773 ps
CPU time 26.12 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:43:51 PM PDT 24
Peak memory 200824 kb
Host smart-3d55fd51-d394-46da-883a-9d0f0e268e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379254021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3379254021
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1950518825
Short name T1157
Test name
Test status
Simulation time 33907072920 ps
CPU time 18.41 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:43:44 PM PDT 24
Peak memory 200884 kb
Host smart-78be44a5-cc51-42c5-b219-fad1ad0048ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950518825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1950518825
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1510350650
Short name T599
Test name
Test status
Simulation time 43029126863 ps
CPU time 15.39 seconds
Started Apr 16 02:43:24 PM PDT 24
Finished Apr 16 02:43:40 PM PDT 24
Peak memory 200892 kb
Host smart-1d80743d-0419-48b5-98e7-edb0a73c985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510350650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1510350650
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2993796397
Short name T1147
Test name
Test status
Simulation time 13026460 ps
CPU time 0.57 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:11 PM PDT 24
Peak memory 196204 kb
Host smart-bc5661c1-09d6-4f8e-a818-f31f401a7b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993796397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2993796397
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.4231283558
Short name T1148
Test name
Test status
Simulation time 72118911180 ps
CPU time 32.47 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 200784 kb
Host smart-baaa49db-546b-4680-b239-53d69d2fc8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231283558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.4231283558
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1428423730
Short name T421
Test name
Test status
Simulation time 30548628937 ps
CPU time 28.44 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:42 PM PDT 24
Peak memory 200844 kb
Host smart-0965739d-3d89-4680-97ea-ac085bd0be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428423730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1428423730
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4188026938
Short name T893
Test name
Test status
Simulation time 73773885915 ps
CPU time 175.44 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:42:06 PM PDT 24
Peak memory 199100 kb
Host smart-11a6730b-7614-4f9f-880c-f2d51b29a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188026938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4188026938
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1350155399
Short name T663
Test name
Test status
Simulation time 19407419427 ps
CPU time 11.22 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:22 PM PDT 24
Peak memory 200352 kb
Host smart-44fe52c6-19e8-4268-8745-3f1eb983b2e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350155399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1350155399
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3208647951
Short name T835
Test name
Test status
Simulation time 171511914866 ps
CPU time 373.09 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:45:23 PM PDT 24
Peak memory 200880 kb
Host smart-f456911b-42c5-4cf4-a8a2-68ee5d304704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208647951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3208647951
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.713243625
Short name T562
Test name
Test status
Simulation time 1824889103 ps
CPU time 3.89 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:20 PM PDT 24
Peak memory 199512 kb
Host smart-858e83c9-58b5-4b3c-b62c-9376f81e51bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713243625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.713243625
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.2685853510
Short name T67
Test name
Test status
Simulation time 58114902143 ps
CPU time 136.91 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 200432 kb
Host smart-62567df0-8f13-4cc0-9f0d-c36617519028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685853510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2685853510
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1334837756
Short name T425
Test name
Test status
Simulation time 6068652511 ps
CPU time 57.59 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:14 PM PDT 24
Peak memory 199948 kb
Host smart-064940d0-1f76-4e8a-be30-9e547531b5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334837756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1334837756
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.646122024
Short name T1029
Test name
Test status
Simulation time 56381062652 ps
CPU time 26.75 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:37 PM PDT 24
Peak memory 200252 kb
Host smart-fe8bd418-f200-45ff-865a-a96d8ee19d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646122024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.646122024
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.838526806
Short name T48
Test name
Test status
Simulation time 45415917818 ps
CPU time 19.78 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 196696 kb
Host smart-24422821-0bb8-4372-a8fb-cef3e09ccea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838526806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.838526806
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.4278905842
Short name T102
Test name
Test status
Simulation time 61292022 ps
CPU time 0.85 seconds
Started Apr 16 02:39:08 PM PDT 24
Finished Apr 16 02:39:10 PM PDT 24
Peak memory 218260 kb
Host smart-1e5055b1-befc-437a-acab-1b86d529f71b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278905842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4278905842
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.526019957
Short name T737
Test name
Test status
Simulation time 683807601 ps
CPU time 1.78 seconds
Started Apr 16 02:39:03 PM PDT 24
Finished Apr 16 02:39:06 PM PDT 24
Peak memory 200368 kb
Host smart-d9af45fc-f168-48c1-8e8a-0bcbf1188576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526019957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.526019957
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.4176719637
Short name T868
Test name
Test status
Simulation time 103589472306 ps
CPU time 1489.46 seconds
Started Apr 16 02:39:07 PM PDT 24
Finished Apr 16 03:03:57 PM PDT 24
Peak memory 200912 kb
Host smart-f523975b-0795-4bdd-9ee5-2ed1092fb850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176719637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4176719637
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3907144509
Short name T117
Test name
Test status
Simulation time 100998425349 ps
CPU time 421.9 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:46:12 PM PDT 24
Peak memory 216676 kb
Host smart-19be51bc-5555-4f93-8ea1-e11d2509c44a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907144509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3907144509
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2664866678
Short name T992
Test name
Test status
Simulation time 10282747818 ps
CPU time 7.55 seconds
Started Apr 16 02:39:08 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 200560 kb
Host smart-9cfb6081-d7bb-45fd-858b-a375cb55cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664866678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2664866678
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2089877930
Short name T41
Test name
Test status
Simulation time 6497737528 ps
CPU time 6.05 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 197756 kb
Host smart-c90dc948-6a3d-4891-8199-47d978cba741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089877930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2089877930
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1948685923
Short name T638
Test name
Test status
Simulation time 35528168 ps
CPU time 0.56 seconds
Started Apr 16 02:40:19 PM PDT 24
Finished Apr 16 02:40:20 PM PDT 24
Peak memory 196172 kb
Host smart-205e9104-523f-4855-88d0-63559b521d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948685923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1948685923
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3997351429
Short name T858
Test name
Test status
Simulation time 54808403720 ps
CPU time 53.18 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 200844 kb
Host smart-55dc09fe-a379-4986-acd6-d02b3a3074de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997351429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3997351429
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2470243408
Short name T166
Test name
Test status
Simulation time 225788519230 ps
CPU time 138.48 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:42:34 PM PDT 24
Peak memory 200796 kb
Host smart-de1cd398-7f5c-41df-b62e-a09c720c3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470243408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2470243408
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2725318609
Short name T147
Test name
Test status
Simulation time 20074508858 ps
CPU time 46.98 seconds
Started Apr 16 02:40:13 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200864 kb
Host smart-4370d3bb-a175-48df-b0cc-d08368bf96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725318609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2725318609
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.541205877
Short name T322
Test name
Test status
Simulation time 52270807225 ps
CPU time 22.36 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:38 PM PDT 24
Peak memory 200620 kb
Host smart-e8e25179-2e04-4a8c-81b3-956c40402c1d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541205877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.541205877
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.343652857
Short name T376
Test name
Test status
Simulation time 65524434047 ps
CPU time 77.02 seconds
Started Apr 16 02:40:17 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 200904 kb
Host smart-1716c329-41d4-409b-96d6-1e69c978dace
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343652857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.343652857
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1441742812
Short name T496
Test name
Test status
Simulation time 1588143074 ps
CPU time 4.31 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 199120 kb
Host smart-7cf83ca3-7132-4d74-a37d-f8a6202765dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441742812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1441742812
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2322224814
Short name T601
Test name
Test status
Simulation time 88697635644 ps
CPU time 152.28 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:42:49 PM PDT 24
Peak memory 201084 kb
Host smart-eeb494db-2cbc-4f5e-9370-92addc7f5608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322224814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2322224814
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2355710889
Short name T609
Test name
Test status
Simulation time 2823553103 ps
CPU time 40.62 seconds
Started Apr 16 02:40:12 PM PDT 24
Finished Apr 16 02:40:54 PM PDT 24
Peak memory 200920 kb
Host smart-ddd5cfb1-d609-439d-b5a9-b95f920bf073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355710889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2355710889
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.266478728
Short name T54
Test name
Test status
Simulation time 6697175260 ps
CPU time 49.38 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:41:05 PM PDT 24
Peak memory 200276 kb
Host smart-b9b699bc-5ee4-460e-9333-2e0f4b7372b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266478728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.266478728
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.54276375
Short name T1178
Test name
Test status
Simulation time 93186536540 ps
CPU time 151.12 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200876 kb
Host smart-46da92f9-a2d0-44b0-b041-8da161e7352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54276375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.54276375
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1055283426
Short name T474
Test name
Test status
Simulation time 1585653062 ps
CPU time 1.35 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 196476 kb
Host smart-e02ca551-a1de-4896-9df9-85ddbad88c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055283426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1055283426
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3873950361
Short name T1058
Test name
Test status
Simulation time 462547688 ps
CPU time 1.26 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 200716 kb
Host smart-35dd280c-84d8-44d9-aeeb-964277e1e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873950361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3873950361
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1188228226
Short name T810
Test name
Test status
Simulation time 59651973639 ps
CPU time 608.32 seconds
Started Apr 16 02:40:15 PM PDT 24
Finished Apr 16 02:50:24 PM PDT 24
Peak memory 217312 kb
Host smart-6c9d16a6-f5f3-4e8b-9964-4c3afd2427db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188228226 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1188228226
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2458969438
Short name T676
Test name
Test status
Simulation time 1191504946 ps
CPU time 1.27 seconds
Started Apr 16 02:40:14 PM PDT 24
Finished Apr 16 02:40:16 PM PDT 24
Peak memory 197764 kb
Host smart-326d8e14-8cee-4f88-aeac-5b9751d40a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458969438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2458969438
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4095904932
Short name T1090
Test name
Test status
Simulation time 44166308194 ps
CPU time 74.22 seconds
Started Apr 16 02:40:16 PM PDT 24
Finished Apr 16 02:41:31 PM PDT 24
Peak memory 200812 kb
Host smart-c497eac6-307e-457f-92b1-2f4cf3576b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095904932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4095904932
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2869221468
Short name T1100
Test name
Test status
Simulation time 21198469 ps
CPU time 0.56 seconds
Started Apr 16 02:40:24 PM PDT 24
Finished Apr 16 02:40:25 PM PDT 24
Peak memory 196192 kb
Host smart-ae7fc719-a601-4173-95e4-a389ea2cb1c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869221468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2869221468
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.335102645
Short name T1028
Test name
Test status
Simulation time 79213780389 ps
CPU time 124.2 seconds
Started Apr 16 02:40:18 PM PDT 24
Finished Apr 16 02:42:23 PM PDT 24
Peak memory 200644 kb
Host smart-e42e98f4-2857-436c-9654-d807c049b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335102645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.335102645
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1717843910
Short name T177
Test name
Test status
Simulation time 28221934616 ps
CPU time 25.95 seconds
Started Apr 16 02:40:20 PM PDT 24
Finished Apr 16 02:40:47 PM PDT 24
Peak memory 200844 kb
Host smart-457ff7f3-2f82-442f-9716-9ed399ee2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717843910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1717843910
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3457785150
Short name T238
Test name
Test status
Simulation time 135486558557 ps
CPU time 210.38 seconds
Started Apr 16 02:40:18 PM PDT 24
Finished Apr 16 02:43:49 PM PDT 24
Peak memory 200880 kb
Host smart-cfe521eb-0997-4631-ba75-3f4698aab9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457785150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3457785150
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4214347987
Short name T424
Test name
Test status
Simulation time 44516665185 ps
CPU time 26.68 seconds
Started Apr 16 02:40:19 PM PDT 24
Finished Apr 16 02:40:46 PM PDT 24
Peak memory 200884 kb
Host smart-14751c87-15d3-44e5-8582-5b4372b11202
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214347987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4214347987
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1512182856
Short name T281
Test name
Test status
Simulation time 74254552559 ps
CPU time 260.02 seconds
Started Apr 16 02:40:24 PM PDT 24
Finished Apr 16 02:44:44 PM PDT 24
Peak memory 200864 kb
Host smart-dd064675-0839-4aaf-8650-9d1585157fcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512182856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1512182856
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2978369271
Short name T786
Test name
Test status
Simulation time 4933139514 ps
CPU time 5.86 seconds
Started Apr 16 02:40:25 PM PDT 24
Finished Apr 16 02:40:32 PM PDT 24
Peak memory 199956 kb
Host smart-9bc50ff3-ddaa-4753-8076-776290576e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978369271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2978369271
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1778840883
Short name T721
Test name
Test status
Simulation time 101250589658 ps
CPU time 46.47 seconds
Started Apr 16 02:40:19 PM PDT 24
Finished Apr 16 02:41:06 PM PDT 24
Peak memory 201100 kb
Host smart-de71bf29-acd0-4b43-8981-e81847878c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778840883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1778840883
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1403295579
Short name T1009
Test name
Test status
Simulation time 4774893630 ps
CPU time 147.09 seconds
Started Apr 16 02:40:23 PM PDT 24
Finished Apr 16 02:42:50 PM PDT 24
Peak memory 200836 kb
Host smart-2c27c0fd-0bbf-45dc-a32a-b4797009ae9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403295579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1403295579
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1911888739
Short name T350
Test name
Test status
Simulation time 4939190316 ps
CPU time 22.79 seconds
Started Apr 16 02:40:20 PM PDT 24
Finished Apr 16 02:40:43 PM PDT 24
Peak memory 199144 kb
Host smart-006eec37-5117-4bc3-9e42-fbce5929128e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911888739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1911888739
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1083220601
Short name T1173
Test name
Test status
Simulation time 142488420286 ps
CPU time 127.9 seconds
Started Apr 16 02:40:24 PM PDT 24
Finished Apr 16 02:42:33 PM PDT 24
Peak memory 200880 kb
Host smart-ce0a2959-2ed9-441f-8e48-cf872be49911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083220601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1083220601
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2072394397
Short name T796
Test name
Test status
Simulation time 6270340336 ps
CPU time 5.2 seconds
Started Apr 16 02:40:19 PM PDT 24
Finished Apr 16 02:40:25 PM PDT 24
Peak memory 197132 kb
Host smart-be8cd051-56f6-47ca-9574-d6f516dd378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072394397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2072394397
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.803334570
Short name T438
Test name
Test status
Simulation time 484108414 ps
CPU time 1.81 seconds
Started Apr 16 02:40:22 PM PDT 24
Finished Apr 16 02:40:24 PM PDT 24
Peak memory 199232 kb
Host smart-496d88de-4ed7-4933-b4d7-fa9341f67e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803334570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.803334570
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.157285542
Short name T620
Test name
Test status
Simulation time 124162035405 ps
CPU time 84.45 seconds
Started Apr 16 02:40:27 PM PDT 24
Finished Apr 16 02:41:52 PM PDT 24
Peak memory 200844 kb
Host smart-af4ee50c-085e-46ee-882c-a9598084c950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157285542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.157285542
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3591281613
Short name T36
Test name
Test status
Simulation time 534858120136 ps
CPU time 317.16 seconds
Started Apr 16 02:40:27 PM PDT 24
Finished Apr 16 02:45:45 PM PDT 24
Peak memory 217572 kb
Host smart-26266538-06cd-47ec-a670-434f56a089fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591281613 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3591281613
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2945646501
Short name T654
Test name
Test status
Simulation time 1586889097 ps
CPU time 1.79 seconds
Started Apr 16 02:40:24 PM PDT 24
Finished Apr 16 02:40:27 PM PDT 24
Peak memory 199340 kb
Host smart-112acf84-7fc4-412c-9e4d-c5491e4dbb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945646501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2945646501
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2971121099
Short name T792
Test name
Test status
Simulation time 72338939016 ps
CPU time 46.34 seconds
Started Apr 16 02:40:21 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 200820 kb
Host smart-a14762a0-cb57-4812-b000-34aaa30031f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971121099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2971121099
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2909506879
Short name T882
Test name
Test status
Simulation time 19339424 ps
CPU time 0.64 seconds
Started Apr 16 02:40:28 PM PDT 24
Finished Apr 16 02:40:30 PM PDT 24
Peak memory 196208 kb
Host smart-a61594bf-aa07-45f2-ae3d-a8cb1e57912c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909506879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2909506879
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.791410008
Short name T485
Test name
Test status
Simulation time 186370873253 ps
CPU time 81.98 seconds
Started Apr 16 02:40:25 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 200892 kb
Host smart-8f09310a-58d1-49a5-ae44-6aa1df2a25e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791410008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.791410008
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1994842185
Short name T339
Test name
Test status
Simulation time 7247851558 ps
CPU time 4.73 seconds
Started Apr 16 02:40:25 PM PDT 24
Finished Apr 16 02:40:30 PM PDT 24
Peak memory 200556 kb
Host smart-307d1603-eb4a-4d91-89c3-eb89b65f8e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994842185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1994842185
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.127752555
Short name T178
Test name
Test status
Simulation time 117425147876 ps
CPU time 54.1 seconds
Started Apr 16 02:40:31 PM PDT 24
Finished Apr 16 02:41:26 PM PDT 24
Peak memory 200880 kb
Host smart-5aa82f6a-d162-4c59-bf68-65951d144b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127752555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.127752555
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.946922797
Short name T922
Test name
Test status
Simulation time 25716576084 ps
CPU time 51.36 seconds
Started Apr 16 02:40:31 PM PDT 24
Finished Apr 16 02:41:23 PM PDT 24
Peak memory 200872 kb
Host smart-e184da8f-8b87-4c72-bf66-592eafb71aff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946922797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.946922797
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.659095587
Short name T801
Test name
Test status
Simulation time 74999142191 ps
CPU time 392.58 seconds
Started Apr 16 02:40:25 PM PDT 24
Finished Apr 16 02:46:58 PM PDT 24
Peak memory 200840 kb
Host smart-8563fa14-53cb-430e-b01b-1a2944ae957c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659095587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.659095587
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.45398297
Short name T715
Test name
Test status
Simulation time 1217025499 ps
CPU time 2.7 seconds
Started Apr 16 02:40:26 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 198232 kb
Host smart-62ee685c-ad91-40da-b778-45bc7cf821bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45398297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.45398297
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.4082336176
Short name T836
Test name
Test status
Simulation time 410621360448 ps
CPU time 46.46 seconds
Started Apr 16 02:40:26 PM PDT 24
Finished Apr 16 02:41:13 PM PDT 24
Peak memory 201104 kb
Host smart-45136d24-9f1e-4769-a2d9-284bc19c7171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082336176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4082336176
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1221440703
Short name T382
Test name
Test status
Simulation time 8822689787 ps
CPU time 247.96 seconds
Started Apr 16 02:40:24 PM PDT 24
Finished Apr 16 02:44:33 PM PDT 24
Peak memory 200872 kb
Host smart-1c03c995-a33c-4187-abf7-7c1b39319fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221440703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1221440703
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3841854136
Short name T360
Test name
Test status
Simulation time 2234765120 ps
CPU time 12.88 seconds
Started Apr 16 02:40:25 PM PDT 24
Finished Apr 16 02:40:38 PM PDT 24
Peak memory 199392 kb
Host smart-7f94b5bd-eb48-4b15-a587-7e936a533e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841854136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3841854136
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.231515221
Short name T45
Test name
Test status
Simulation time 45116388012 ps
CPU time 18.73 seconds
Started Apr 16 02:40:29 PM PDT 24
Finished Apr 16 02:40:49 PM PDT 24
Peak memory 200820 kb
Host smart-521bf39e-086a-43df-be36-8b652ac9c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231515221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.231515221
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.110950594
Short name T894
Test name
Test status
Simulation time 43103850916 ps
CPU time 72.31 seconds
Started Apr 16 02:40:27 PM PDT 24
Finished Apr 16 02:41:40 PM PDT 24
Peak memory 196628 kb
Host smart-72c4a70d-3c82-4bdb-80cf-1188b0016d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110950594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.110950594
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3911283706
Short name T794
Test name
Test status
Simulation time 268707979 ps
CPU time 1.47 seconds
Started Apr 16 02:40:21 PM PDT 24
Finished Apr 16 02:40:23 PM PDT 24
Peak memory 199072 kb
Host smart-fb53f470-b428-4fad-8954-bc5fd8faf5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911283706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3911283706
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.595973175
Short name T641
Test name
Test status
Simulation time 521624331118 ps
CPU time 571.76 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:50:05 PM PDT 24
Peak memory 200844 kb
Host smart-4ee51503-71f4-419b-bb96-87f61b7c086d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595973175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.595973175
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.409860039
Short name T808
Test name
Test status
Simulation time 26437625582 ps
CPU time 858.7 seconds
Started Apr 16 02:40:30 PM PDT 24
Finished Apr 16 02:54:49 PM PDT 24
Peak memory 217344 kb
Host smart-a23726ce-3311-43ca-91a4-15bac7995e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409860039 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.409860039
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2953108982
Short name T558
Test name
Test status
Simulation time 688564596 ps
CPU time 3.37 seconds
Started Apr 16 02:40:31 PM PDT 24
Finished Apr 16 02:40:35 PM PDT 24
Peak memory 199856 kb
Host smart-cf6427d3-feb9-46be-a62f-f33087221e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953108982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2953108982
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2689633884
Short name T727
Test name
Test status
Simulation time 153026165747 ps
CPU time 100.84 seconds
Started Apr 16 02:40:21 PM PDT 24
Finished Apr 16 02:42:03 PM PDT 24
Peak memory 200844 kb
Host smart-25ad161b-e268-4418-bcb2-ce0a675727e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689633884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2689633884
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2040182625
Short name T783
Test name
Test status
Simulation time 17923576 ps
CPU time 0.59 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:35 PM PDT 24
Peak memory 196212 kb
Host smart-5a3810d0-a5f5-4781-9b40-7a1c836541b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040182625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2040182625
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1446496988
Short name T883
Test name
Test status
Simulation time 19138058175 ps
CPU time 37.55 seconds
Started Apr 16 02:40:30 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 200812 kb
Host smart-7c32fd84-297d-4b5e-86ac-134daf2f46a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446496988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1446496988
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.2787316100
Short name T602
Test name
Test status
Simulation time 129480076858 ps
CPU time 82.32 seconds
Started Apr 16 02:40:29 PM PDT 24
Finished Apr 16 02:41:52 PM PDT 24
Peak memory 200876 kb
Host smart-eed8c0e4-1928-43ee-8355-eb49ab037ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787316100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.2787316100
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1394975349
Short name T744
Test name
Test status
Simulation time 126098732373 ps
CPU time 200.71 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:43:55 PM PDT 24
Peak memory 200856 kb
Host smart-7d12565d-b3b3-4cb4-a1f3-58b86d5939ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394975349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1394975349
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2317569614
Short name T1083
Test name
Test status
Simulation time 272241291894 ps
CPU time 98.56 seconds
Started Apr 16 02:40:30 PM PDT 24
Finished Apr 16 02:42:09 PM PDT 24
Peak memory 200124 kb
Host smart-a4ec605b-9d30-447f-84d2-20631d7de727
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317569614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2317569614
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2896578926
Short name T1087
Test name
Test status
Simulation time 174194519978 ps
CPU time 1368.29 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 03:03:24 PM PDT 24
Peak memory 200840 kb
Host smart-053aeab8-889b-4f89-a40b-0a1a20dbc7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2896578926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2896578926
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3486552818
Short name T704
Test name
Test status
Simulation time 4567216395 ps
CPU time 3.04 seconds
Started Apr 16 02:40:30 PM PDT 24
Finished Apr 16 02:40:34 PM PDT 24
Peak memory 199680 kb
Host smart-1df813fa-b715-478f-918d-461d44203c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486552818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3486552818
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2013376849
Short name T916
Test name
Test status
Simulation time 62458413047 ps
CPU time 125.05 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:42:38 PM PDT 24
Peak memory 199812 kb
Host smart-8726cb28-704c-4c32-a7e7-d2d4033238bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013376849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2013376849
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1348949155
Short name T1172
Test name
Test status
Simulation time 19321471581 ps
CPU time 996.78 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:57:11 PM PDT 24
Peak memory 200936 kb
Host smart-fdb8d10c-cbea-4a06-933b-d5d8df4d5e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348949155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1348949155
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1468836690
Short name T839
Test name
Test status
Simulation time 4889697413 ps
CPU time 41.59 seconds
Started Apr 16 02:40:30 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 199736 kb
Host smart-79a1a1ab-8f87-481f-86a5-d9cbc7e3df50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468836690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1468836690
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3963651910
Short name T386
Test name
Test status
Simulation time 49591882707 ps
CPU time 84.22 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:41:57 PM PDT 24
Peak memory 200848 kb
Host smart-3cc5d171-01a8-4c41-b6bc-47a7b37218eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963651910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3963651910
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.152320368
Short name T974
Test name
Test status
Simulation time 3550606284 ps
CPU time 6.68 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:42 PM PDT 24
Peak memory 196952 kb
Host smart-7b0450cc-dc5e-4497-a003-75da1b9e4ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152320368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.152320368
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2907744764
Short name T9
Test name
Test status
Simulation time 670498450 ps
CPU time 1.89 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 199252 kb
Host smart-3abb700e-2aa1-4844-97b7-b2fa5e5a0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907744764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2907744764
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1308264496
Short name T506
Test name
Test status
Simulation time 578265948243 ps
CPU time 424.1 seconds
Started Apr 16 02:40:36 PM PDT 24
Finished Apr 16 02:47:41 PM PDT 24
Peak memory 200848 kb
Host smart-cdd076f8-67fc-4bc4-8c8a-e94a3a8a3756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308264496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1308264496
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1869698435
Short name T845
Test name
Test status
Simulation time 175955096698 ps
CPU time 529.58 seconds
Started Apr 16 02:40:37 PM PDT 24
Finished Apr 16 02:49:27 PM PDT 24
Peak memory 217524 kb
Host smart-4e1fcf6a-456f-44e8-b058-e0ded3dd10af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869698435 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1869698435
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2775815236
Short name T105
Test name
Test status
Simulation time 7557731853 ps
CPU time 7.79 seconds
Started Apr 16 02:40:29 PM PDT 24
Finished Apr 16 02:40:38 PM PDT 24
Peak memory 200728 kb
Host smart-3d2d52a3-83fb-44d3-87d2-96706af5069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775815236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2775815236
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2396027510
Short name T547
Test name
Test status
Simulation time 29838559439 ps
CPU time 113.91 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:42:29 PM PDT 24
Peak memory 200920 kb
Host smart-fcc03d17-8dbc-41de-aacb-650c37efba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396027510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2396027510
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3153160475
Short name T413
Test name
Test status
Simulation time 19167930 ps
CPU time 0.56 seconds
Started Apr 16 02:40:36 PM PDT 24
Finished Apr 16 02:40:38 PM PDT 24
Peak memory 196208 kb
Host smart-65bdf6f3-b4de-4a3c-addd-840bd308ff44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153160475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3153160475
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2977382180
Short name T646
Test name
Test status
Simulation time 87715610044 ps
CPU time 314.8 seconds
Started Apr 16 02:40:33 PM PDT 24
Finished Apr 16 02:45:49 PM PDT 24
Peak memory 200800 kb
Host smart-c038e4fe-b3eb-4ff0-9981-d7e2ce841c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977382180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2977382180
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2800387563
Short name T1084
Test name
Test status
Simulation time 40763138250 ps
CPU time 34.21 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:41:07 PM PDT 24
Peak memory 200628 kb
Host smart-b8548b60-1549-433b-908b-60e6ee04e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800387563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2800387563
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1786210172
Short name T1064
Test name
Test status
Simulation time 22981222089 ps
CPU time 10.87 seconds
Started Apr 16 02:40:37 PM PDT 24
Finished Apr 16 02:40:49 PM PDT 24
Peak memory 200616 kb
Host smart-2b24af7f-05b0-4c84-8629-18fe96ea7a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786210172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1786210172
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3896440523
Short name T467
Test name
Test status
Simulation time 63405128030 ps
CPU time 40.04 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:41:13 PM PDT 24
Peak memory 200776 kb
Host smart-c2f11831-ea57-41c8-a6b3-d6bb89776ff5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896440523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3896440523
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1000784874
Short name T1160
Test name
Test status
Simulation time 158679832430 ps
CPU time 1237.04 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 03:01:12 PM PDT 24
Peak memory 200924 kb
Host smart-1723eded-ea1d-4d6f-949c-32a9c684c778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000784874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1000784874
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3877625351
Short name T498
Test name
Test status
Simulation time 59142372 ps
CPU time 0.71 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:36 PM PDT 24
Peak memory 196712 kb
Host smart-905c34aa-3e5c-432a-a99c-761036426adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877625351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3877625351
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.552346714
Short name T1065
Test name
Test status
Simulation time 24930483643 ps
CPU time 39.85 seconds
Started Apr 16 02:40:37 PM PDT 24
Finished Apr 16 02:41:18 PM PDT 24
Peak memory 199220 kb
Host smart-4583ddd8-e2f4-4828-bace-e3862d8eb3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552346714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.552346714
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2012120662
Short name T722
Test name
Test status
Simulation time 22847278870 ps
CPU time 200.6 seconds
Started Apr 16 02:40:36 PM PDT 24
Finished Apr 16 02:43:57 PM PDT 24
Peak memory 200908 kb
Host smart-4bf6c966-7404-4a0c-9238-aae903789a35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012120662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2012120662
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.168883773
Short name T803
Test name
Test status
Simulation time 5936771858 ps
CPU time 28.21 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200076 kb
Host smart-b14bc10f-db45-44f6-9842-727d60bda499
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168883773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.168883773
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2021752617
Short name T180
Test name
Test status
Simulation time 211831760892 ps
CPU time 38.86 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:41:14 PM PDT 24
Peak memory 200764 kb
Host smart-aa54bd8d-4439-4cad-9688-bafe11bb6cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021752617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2021752617
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1595508532
Short name T431
Test name
Test status
Simulation time 2619762516 ps
CPU time 1.58 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 196656 kb
Host smart-d0e928c8-6627-4e28-8b42-9d9a0ffbc271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595508532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1595508532
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2050126633
Short name T595
Test name
Test status
Simulation time 734505906 ps
CPU time 3.19 seconds
Started Apr 16 02:40:35 PM PDT 24
Finished Apr 16 02:40:39 PM PDT 24
Peak memory 199132 kb
Host smart-f2fbae41-0b42-4998-b3ed-851280c8e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050126633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2050126633
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.451036805
Short name T165
Test name
Test status
Simulation time 220299142232 ps
CPU time 1096.68 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:58:51 PM PDT 24
Peak memory 217340 kb
Host smart-08390778-d53d-4d3d-8f06-a406e3d7a7a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451036805 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.451036805
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.928316967
Short name T47
Test name
Test status
Simulation time 1000880492 ps
CPU time 2.55 seconds
Started Apr 16 02:40:36 PM PDT 24
Finished Apr 16 02:40:40 PM PDT 24
Peak memory 199672 kb
Host smart-b0ba9537-5d12-417b-8ca2-c2825e3fded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928316967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.928316967
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3685556193
Short name T395
Test name
Test status
Simulation time 10067506435 ps
CPU time 4.67 seconds
Started Apr 16 02:40:32 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 200760 kb
Host smart-6b007afd-1245-4473-a509-bd737a68bd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685556193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3685556193
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2344628077
Short name T3
Test name
Test status
Simulation time 11156362 ps
CPU time 0.53 seconds
Started Apr 16 02:40:39 PM PDT 24
Finished Apr 16 02:40:41 PM PDT 24
Peak memory 195680 kb
Host smart-27fafcd0-9e9d-4e31-88b5-82e4dc6f214d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344628077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2344628077
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.151589233
Short name T890
Test name
Test status
Simulation time 141555637303 ps
CPU time 209.4 seconds
Started Apr 16 02:40:43 PM PDT 24
Finished Apr 16 02:44:13 PM PDT 24
Peak memory 200896 kb
Host smart-59479caf-0066-4026-98ae-0083293fd9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151589233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.151589233
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1380394425
Short name T596
Test name
Test status
Simulation time 74318635759 ps
CPU time 52.18 seconds
Started Apr 16 02:40:40 PM PDT 24
Finished Apr 16 02:41:33 PM PDT 24
Peak memory 200852 kb
Host smart-ae78a426-901e-461a-919d-92dde1729b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380394425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1380394425
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3764358064
Short name T765
Test name
Test status
Simulation time 124910201758 ps
CPU time 97.24 seconds
Started Apr 16 02:40:35 PM PDT 24
Finished Apr 16 02:42:13 PM PDT 24
Peak memory 201032 kb
Host smart-8e20347e-927c-426c-b51c-303f7c9acc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764358064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3764358064
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.344114275
Short name T1042
Test name
Test status
Simulation time 14166414275 ps
CPU time 24.44 seconds
Started Apr 16 02:40:38 PM PDT 24
Finished Apr 16 02:41:04 PM PDT 24
Peak memory 198588 kb
Host smart-af9edf73-6448-4486-b261-da0cf4ee52b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344114275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.344114275
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.123069140
Short name T481
Test name
Test status
Simulation time 96563347336 ps
CPU time 233.46 seconds
Started Apr 16 02:40:40 PM PDT 24
Finished Apr 16 02:44:35 PM PDT 24
Peak memory 200848 kb
Host smart-89a06230-1180-4217-9855-66eb957f62e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123069140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.123069140
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1216712423
Short name T946
Test name
Test status
Simulation time 4695381335 ps
CPU time 11 seconds
Started Apr 16 02:40:42 PM PDT 24
Finished Apr 16 02:40:54 PM PDT 24
Peak memory 199280 kb
Host smart-6d0fdc16-c1bf-4d88-bfee-85bf18dab48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216712423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1216712423
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3435696266
Short name T673
Test name
Test status
Simulation time 49303231340 ps
CPU time 66.94 seconds
Started Apr 16 02:40:40 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 209260 kb
Host smart-2cd2caaa-891d-40c4-a83d-d22b118b2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435696266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3435696266
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2331263176
Short name T430
Test name
Test status
Simulation time 10464236317 ps
CPU time 280.26 seconds
Started Apr 16 02:40:40 PM PDT 24
Finished Apr 16 02:45:21 PM PDT 24
Peak memory 200848 kb
Host smart-7cdc4925-00a6-4b44-8ba2-f22b46baf4c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331263176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2331263176
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3539806220
Short name T456
Test name
Test status
Simulation time 5364163887 ps
CPU time 3.04 seconds
Started Apr 16 02:40:38 PM PDT 24
Finished Apr 16 02:40:42 PM PDT 24
Peak memory 198936 kb
Host smart-9ebb85d5-598a-43b9-a856-a6b86ede9e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539806220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3539806220
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3754664719
Short name T999
Test name
Test status
Simulation time 24773980365 ps
CPU time 44.94 seconds
Started Apr 16 02:40:39 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 200628 kb
Host smart-1d40d3f2-b201-48ff-bfa0-2f81545739e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754664719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3754664719
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.3550895061
Short name T687
Test name
Test status
Simulation time 4169361393 ps
CPU time 3.91 seconds
Started Apr 16 02:40:37 PM PDT 24
Finished Apr 16 02:40:42 PM PDT 24
Peak memory 196892 kb
Host smart-3a2a3209-fc31-4946-ad63-f952f6428cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550895061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3550895061
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3163448909
Short name T309
Test name
Test status
Simulation time 684021506 ps
CPU time 2.32 seconds
Started Apr 16 02:40:33 PM PDT 24
Finished Apr 16 02:40:36 PM PDT 24
Peak memory 199840 kb
Host smart-d56c6738-08e6-4ae1-a790-88cbf29726d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163448909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3163448909
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2956498724
Short name T1170
Test name
Test status
Simulation time 88505607516 ps
CPU time 1070.87 seconds
Started Apr 16 02:40:40 PM PDT 24
Finished Apr 16 02:58:31 PM PDT 24
Peak memory 200844 kb
Host smart-71632f80-652c-4a48-9eb2-5dbbac01d08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956498724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2956498724
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3963354134
Short name T870
Test name
Test status
Simulation time 1495804401 ps
CPU time 1.93 seconds
Started Apr 16 02:40:36 PM PDT 24
Finished Apr 16 02:40:39 PM PDT 24
Peak memory 199896 kb
Host smart-782b460b-434b-4b61-b459-36af16426194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963354134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3963354134
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.971075653
Short name T787
Test name
Test status
Simulation time 18161628655 ps
CPU time 14.41 seconds
Started Apr 16 02:40:34 PM PDT 24
Finished Apr 16 02:40:49 PM PDT 24
Peak memory 200664 kb
Host smart-0cb474f7-8fbc-432d-bcdb-80fd519c4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971075653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.971075653
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3002646149
Short name T556
Test name
Test status
Simulation time 19835623 ps
CPU time 0.54 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:40:50 PM PDT 24
Peak memory 195216 kb
Host smart-ca1a5e39-3b10-4f6a-a78f-5e192813ed12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002646149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3002646149
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.155976588
Short name T287
Test name
Test status
Simulation time 195518556995 ps
CPU time 221.66 seconds
Started Apr 16 02:40:45 PM PDT 24
Finished Apr 16 02:44:27 PM PDT 24
Peak memory 200848 kb
Host smart-2f1421b8-5dc5-4d25-8b9c-9c1c03937214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155976588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.155976588
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1327348498
Short name T988
Test name
Test status
Simulation time 18380655960 ps
CPU time 16.12 seconds
Started Apr 16 02:40:44 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 199484 kb
Host smart-d4df6ef6-50e5-4652-b1b0-7d6c403155a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327348498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1327348498
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2500584521
Short name T772
Test name
Test status
Simulation time 52638901584 ps
CPU time 88.78 seconds
Started Apr 16 02:40:43 PM PDT 24
Finished Apr 16 02:42:13 PM PDT 24
Peak memory 200800 kb
Host smart-05ab3da2-82cb-4d7d-b437-3ef705143a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500584521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2500584521
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.750795879
Short name T1106
Test name
Test status
Simulation time 50682384836 ps
CPU time 12.52 seconds
Started Apr 16 02:40:44 PM PDT 24
Finished Apr 16 02:40:58 PM PDT 24
Peak memory 200780 kb
Host smart-4678551a-8016-4ee6-8f3b-2ee05d7e21c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750795879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.750795879
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1279167485
Short name T775
Test name
Test status
Simulation time 140935453589 ps
CPU time 1158.85 seconds
Started Apr 16 02:40:42 PM PDT 24
Finished Apr 16 03:00:02 PM PDT 24
Peak memory 200656 kb
Host smart-218196c8-458d-41b1-af5a-10ef4e527cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279167485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1279167485
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1714795928
Short name T345
Test name
Test status
Simulation time 10101035944 ps
CPU time 5.76 seconds
Started Apr 16 02:40:45 PM PDT 24
Finished Apr 16 02:40:51 PM PDT 24
Peak memory 200780 kb
Host smart-290ac694-b6df-4cc5-bf06-6c3e0dd9718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714795928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1714795928
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.232272191
Short name T477
Test name
Test status
Simulation time 39713650433 ps
CPU time 20.59 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:41:10 PM PDT 24
Peak memory 199328 kb
Host smart-4fb13130-763f-4aff-a851-3ff2b0fe0278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232272191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.232272191
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2202463480
Short name T258
Test name
Test status
Simulation time 18799316210 ps
CPU time 870.83 seconds
Started Apr 16 02:40:47 PM PDT 24
Finished Apr 16 02:55:18 PM PDT 24
Peak memory 200912 kb
Host smart-0ec76123-579d-4bd4-9e22-8a1c52445d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202463480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2202463480
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.466936568
Short name T446
Test name
Test status
Simulation time 8028388513 ps
CPU time 33.15 seconds
Started Apr 16 02:40:42 PM PDT 24
Finished Apr 16 02:41:16 PM PDT 24
Peak memory 200096 kb
Host smart-eeda5033-4f04-4148-938d-edefaa182dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466936568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.466936568
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1117649195
Short name T561
Test name
Test status
Simulation time 83422782159 ps
CPU time 39.27 seconds
Started Apr 16 02:40:43 PM PDT 24
Finished Apr 16 02:41:23 PM PDT 24
Peak memory 200832 kb
Host smart-5f74af9a-f2e8-4d25-883e-ec246f2462e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117649195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1117649195
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.135894870
Short name T343
Test name
Test status
Simulation time 537227775 ps
CPU time 1.45 seconds
Started Apr 16 02:40:43 PM PDT 24
Finished Apr 16 02:40:45 PM PDT 24
Peak memory 196236 kb
Host smart-3ff027c5-eee5-4a93-ac43-1e4875a82296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135894870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.135894870
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4153679443
Short name T1030
Test name
Test status
Simulation time 510999682 ps
CPU time 1.31 seconds
Started Apr 16 02:40:39 PM PDT 24
Finished Apr 16 02:40:42 PM PDT 24
Peak memory 200216 kb
Host smart-1b17903e-1f51-494f-bd64-fd84e17209ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153679443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4153679443
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1539863150
Short name T784
Test name
Test status
Simulation time 69890659845 ps
CPU time 35.14 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 200832 kb
Host smart-0e601f4f-5d1a-4e01-b28e-a1966f5728be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539863150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1539863150
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1103278832
Short name T628
Test name
Test status
Simulation time 587523777768 ps
CPU time 931.13 seconds
Started Apr 16 02:40:46 PM PDT 24
Finished Apr 16 02:56:18 PM PDT 24
Peak memory 230256 kb
Host smart-0bccb6c0-1170-4ced-8cbc-f6d1ab8b9f02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103278832 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1103278832
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3983513966
Short name T1133
Test name
Test status
Simulation time 7443726380 ps
CPU time 12.12 seconds
Started Apr 16 02:40:47 PM PDT 24
Finished Apr 16 02:41:00 PM PDT 24
Peak memory 200652 kb
Host smart-40967562-5515-4eee-b6e1-8488be0872bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983513966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3983513966
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1962182841
Short name T310
Test name
Test status
Simulation time 168216316536 ps
CPU time 86.59 seconds
Started Apr 16 02:40:44 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 200808 kb
Host smart-409045c3-845a-4a22-a938-db262e0e3838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962182841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1962182841
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.815432600
Short name T366
Test name
Test status
Simulation time 50494105 ps
CPU time 0.57 seconds
Started Apr 16 02:40:50 PM PDT 24
Finished Apr 16 02:40:51 PM PDT 24
Peak memory 196208 kb
Host smart-345aa3ba-1670-456d-9741-05cf131b6f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815432600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.815432600
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3088573166
Short name T140
Test name
Test status
Simulation time 155604371688 ps
CPU time 262.44 seconds
Started Apr 16 02:40:43 PM PDT 24
Finished Apr 16 02:45:06 PM PDT 24
Peak memory 200876 kb
Host smart-145c2d2f-b636-49b8-8f40-e8e44a7104aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088573166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3088573166
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1260060902
Short name T729
Test name
Test status
Simulation time 64729470702 ps
CPU time 96.12 seconds
Started Apr 16 02:40:44 PM PDT 24
Finished Apr 16 02:42:21 PM PDT 24
Peak memory 200908 kb
Host smart-be304cbb-9e8a-4a8c-b3a2-fc500d3d35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260060902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1260060902
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2582232415
Short name T453
Test name
Test status
Simulation time 77698419196 ps
CPU time 168.91 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:43:44 PM PDT 24
Peak memory 200860 kb
Host smart-b9a4c10c-3337-4a89-ad28-6dd0a724f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582232415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2582232415
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2470462407
Short name T606
Test name
Test status
Simulation time 38395800685 ps
CPU time 8.88 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:40:58 PM PDT 24
Peak memory 200888 kb
Host smart-1e53f07f-c0b3-48d9-ae65-e26eec8221b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470462407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2470462407
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2048999606
Short name T533
Test name
Test status
Simulation time 134875478597 ps
CPU time 475.66 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:48:46 PM PDT 24
Peak memory 200816 kb
Host smart-4be4e78b-3095-43b0-a288-ccf75f09dbe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048999606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2048999606
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2977376321
Short name T660
Test name
Test status
Simulation time 6293601323 ps
CPU time 27.11 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:41:17 PM PDT 24
Peak memory 200600 kb
Host smart-af38079d-3917-4a52-ae87-24d750ab2f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977376321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2977376321
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3646969230
Short name T982
Test name
Test status
Simulation time 106614959977 ps
CPU time 167.31 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:43:37 PM PDT 24
Peak memory 201080 kb
Host smart-7fd75b39-3c54-4550-bbc2-1e3d707fcf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646969230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3646969230
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1489819628
Short name T521
Test name
Test status
Simulation time 31365374857 ps
CPU time 994.37 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:57:23 PM PDT 24
Peak memory 200896 kb
Host smart-7d9822b1-83cc-4e43-9213-ed9cec26849d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489819628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1489819628
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3633339021
Short name T1129
Test name
Test status
Simulation time 1940942865 ps
CPU time 2.66 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:40:52 PM PDT 24
Peak memory 199888 kb
Host smart-df70da5c-f2fb-4ee2-ab28-ff22f8363f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633339021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3633339021
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2978643637
Short name T672
Test name
Test status
Simulation time 53455662155 ps
CPU time 22.82 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:41:16 PM PDT 24
Peak memory 200140 kb
Host smart-7c06e1f0-6d8a-4c7e-9955-c8a4a748f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978643637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2978643637
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3147905315
Short name T307
Test name
Test status
Simulation time 1826878046 ps
CPU time 2.2 seconds
Started Apr 16 02:40:50 PM PDT 24
Finished Apr 16 02:40:53 PM PDT 24
Peak memory 196572 kb
Host smart-b9fc5dde-3731-4a52-abbe-cd6155d6e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147905315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3147905315
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.755453615
Short name T947
Test name
Test status
Simulation time 624988684 ps
CPU time 1.56 seconds
Started Apr 16 02:40:44 PM PDT 24
Finished Apr 16 02:40:47 PM PDT 24
Peak memory 200624 kb
Host smart-f219ddde-46e7-4d3c-9e2b-5263a1890609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755453615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.755453615
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1863957330
Short name T22
Test name
Test status
Simulation time 14275427103 ps
CPU time 416.53 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:47:46 PM PDT 24
Peak memory 216388 kb
Host smart-2f3352cd-6122-4e72-9562-c3769dd6b631
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863957330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1863957330
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1132071921
Short name T802
Test name
Test status
Simulation time 6659097083 ps
CPU time 22.87 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 200844 kb
Host smart-0ddc96cf-fb42-42d0-be0f-8254b24c389b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132071921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1132071921
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4026675381
Short name T971
Test name
Test status
Simulation time 291569326188 ps
CPU time 37.55 seconds
Started Apr 16 02:40:45 PM PDT 24
Finished Apr 16 02:41:23 PM PDT 24
Peak memory 200820 kb
Host smart-ab5483c9-9dec-4c13-bd6f-56cb9f12255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026675381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4026675381
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.372732962
Short name T442
Test name
Test status
Simulation time 14454208 ps
CPU time 0.56 seconds
Started Apr 16 02:40:54 PM PDT 24
Finished Apr 16 02:40:55 PM PDT 24
Peak memory 196000 kb
Host smart-486ae2fc-f570-40ed-b272-a8f1022e33d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372732962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.372732962
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2240711560
Short name T798
Test name
Test status
Simulation time 140055682644 ps
CPU time 188.57 seconds
Started Apr 16 02:40:46 PM PDT 24
Finished Apr 16 02:43:55 PM PDT 24
Peak memory 200820 kb
Host smart-70d4ee18-3a17-4d79-b12c-c6f84b9d1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240711560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2240711560
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3496150584
Short name T71
Test name
Test status
Simulation time 22673243975 ps
CPU time 42.47 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:41:31 PM PDT 24
Peak memory 200852 kb
Host smart-f85cc969-b9b4-4e7c-86a0-f6f774a3f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496150584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3496150584
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.885438592
Short name T1097
Test name
Test status
Simulation time 77023816026 ps
CPU time 59.48 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:41:53 PM PDT 24
Peak memory 200768 kb
Host smart-82a3bd40-d130-4ba7-acec-e05af6192bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885438592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.885438592
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1900597919
Short name T321
Test name
Test status
Simulation time 320966081488 ps
CPU time 79.18 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:42:14 PM PDT 24
Peak memory 198080 kb
Host smart-78dc3bff-631e-444e-967e-bc3c70f35604
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900597919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1900597919
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2403183118
Short name T967
Test name
Test status
Simulation time 99338419766 ps
CPU time 217.75 seconds
Started Apr 16 02:40:50 PM PDT 24
Finished Apr 16 02:44:28 PM PDT 24
Peak memory 200848 kb
Host smart-d6fed05c-7609-4f1e-ae97-fc3321600ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403183118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2403183118
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1974227441
Short name T1054
Test name
Test status
Simulation time 1356186927 ps
CPU time 2.73 seconds
Started Apr 16 02:40:50 PM PDT 24
Finished Apr 16 02:40:53 PM PDT 24
Peak memory 196904 kb
Host smart-1f5cc6c7-4379-4771-bd7d-993d9f91adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974227441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1974227441
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3375400074
Short name T651
Test name
Test status
Simulation time 94560793897 ps
CPU time 162.91 seconds
Started Apr 16 02:40:51 PM PDT 24
Finished Apr 16 02:43:35 PM PDT 24
Peak memory 201116 kb
Host smart-7ab74432-4f2a-40e5-84ca-99e11c8a40a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375400074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3375400074
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3086601632
Short name T257
Test name
Test status
Simulation time 8009908213 ps
CPU time 414.43 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:47:49 PM PDT 24
Peak memory 200916 kb
Host smart-cf5b538d-3f88-4ff3-b533-a65f2112439f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086601632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3086601632
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.815126345
Short name T913
Test name
Test status
Simulation time 1383295292 ps
CPU time 1.76 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:40:55 PM PDT 24
Peak memory 197100 kb
Host smart-7c0e3ba7-0473-47e7-b4fe-3c4663579fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815126345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.815126345
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1150753456
Short name T577
Test name
Test status
Simulation time 17574500334 ps
CPU time 30.14 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:25 PM PDT 24
Peak memory 200292 kb
Host smart-d8799e67-9809-447d-9061-fa2ee694e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150753456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1150753456
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.419847602
Short name T930
Test name
Test status
Simulation time 505607176 ps
CPU time 1.09 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:40:56 PM PDT 24
Peak memory 196220 kb
Host smart-5e454a28-6601-4653-860a-4373e690468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419847602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.419847602
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3761524215
Short name T1091
Test name
Test status
Simulation time 10548147450 ps
CPU time 18.74 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:41:09 PM PDT 24
Peak memory 200808 kb
Host smart-208bd121-b8ff-4076-a9f0-ae17e134c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761524215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3761524215
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3000439647
Short name T732
Test name
Test status
Simulation time 297357444926 ps
CPU time 100.77 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:42:35 PM PDT 24
Peak memory 200916 kb
Host smart-b196eccf-d172-4ac7-9940-ba7ce597927c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000439647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3000439647
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1035481584
Short name T936
Test name
Test status
Simulation time 12920606967 ps
CPU time 121.53 seconds
Started Apr 16 02:40:48 PM PDT 24
Finished Apr 16 02:42:51 PM PDT 24
Peak memory 209364 kb
Host smart-b84e7813-273e-43a7-abb1-3551d8ff64ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035481584 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1035481584
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.4034543011
Short name T804
Test name
Test status
Simulation time 6905207614 ps
CPU time 11.19 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200456 kb
Host smart-5c5cf4f2-598f-469f-ba78-162febd5e2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034543011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.4034543011
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.4038487569
Short name T528
Test name
Test status
Simulation time 45167222354 ps
CPU time 86.03 seconds
Started Apr 16 02:40:49 PM PDT 24
Finished Apr 16 02:42:16 PM PDT 24
Peak memory 200848 kb
Host smart-a2ef4302-b4b8-4dce-9cda-fa6d53c16e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038487569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.4038487569
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3098781428
Short name T448
Test name
Test status
Simulation time 64479848 ps
CPU time 0.53 seconds
Started Apr 16 02:40:51 PM PDT 24
Finished Apr 16 02:40:53 PM PDT 24
Peak memory 196228 kb
Host smart-95702d87-ed1d-49bb-a892-fdc8ef39ddf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098781428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3098781428
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1821949967
Short name T860
Test name
Test status
Simulation time 124216628038 ps
CPU time 79.76 seconds
Started Apr 16 02:40:55 PM PDT 24
Finished Apr 16 02:42:16 PM PDT 24
Peak memory 200840 kb
Host smart-852f8596-75f5-4164-bc71-8edc50d0c0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821949967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1821949967
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.660612227
Short name T33
Test name
Test status
Simulation time 21519374385 ps
CPU time 9.95 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:41:03 PM PDT 24
Peak memory 200788 kb
Host smart-7cc82069-2d46-4f40-8e10-d38a54e13914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660612227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.660612227
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.853441774
Short name T412
Test name
Test status
Simulation time 6163123939 ps
CPU time 5.93 seconds
Started Apr 16 02:40:51 PM PDT 24
Finished Apr 16 02:40:58 PM PDT 24
Peak memory 197448 kb
Host smart-bce9da42-df3e-4926-8a5e-e3285b4bbdc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853441774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.853441774
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2830360712
Short name T8
Test name
Test status
Simulation time 220776567299 ps
CPU time 177.92 seconds
Started Apr 16 02:40:51 PM PDT 24
Finished Apr 16 02:43:50 PM PDT 24
Peak memory 200824 kb
Host smart-ac2074fd-bec0-43ff-bba4-d62666bb9f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830360712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2830360712
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2925275387
Short name T724
Test name
Test status
Simulation time 5176334715 ps
CPU time 9.94 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:04 PM PDT 24
Peak memory 199476 kb
Host smart-da2c7540-04da-47b7-80ab-1d2861e6e257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925275387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2925275387
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3067042098
Short name T532
Test name
Test status
Simulation time 105318528327 ps
CPU time 52.82 seconds
Started Apr 16 02:40:55 PM PDT 24
Finished Apr 16 02:41:49 PM PDT 24
Peak memory 200544 kb
Host smart-326af81f-d608-4eb5-81f2-a1d1b3e52dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067042098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3067042098
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1573857749
Short name T110
Test name
Test status
Simulation time 9544835760 ps
CPU time 141.62 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:43:14 PM PDT 24
Peak memory 200896 kb
Host smart-ce757741-59bf-42bd-a2e7-2856492b368a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573857749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1573857749
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.600458388
Short name T817
Test name
Test status
Simulation time 4669964075 ps
CPU time 23.32 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:18 PM PDT 24
Peak memory 200620 kb
Host smart-3ad3394f-834c-410a-850b-779c35c27cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600458388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.600458388
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.224574365
Short name T472
Test name
Test status
Simulation time 36364504717 ps
CPU time 55.43 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:50 PM PDT 24
Peak memory 200904 kb
Host smart-8b23d4f6-4d92-49fa-af2f-4b2e4ed8ffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224574365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.224574365
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2082676325
Short name T918
Test name
Test status
Simulation time 2984102949 ps
CPU time 5.8 seconds
Started Apr 16 02:40:55 PM PDT 24
Finished Apr 16 02:41:02 PM PDT 24
Peak memory 196736 kb
Host smart-aaeb3ea3-10d6-4404-9818-16425e388841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082676325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2082676325
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.282716019
Short name T580
Test name
Test status
Simulation time 479149793 ps
CPU time 1.11 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:40:54 PM PDT 24
Peak memory 199224 kb
Host smart-5a7aad98-f3b4-469d-abdc-429df8c56338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282716019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.282716019
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2913723419
Short name T443
Test name
Test status
Simulation time 158002644571 ps
CPU time 374.32 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:47:09 PM PDT 24
Peak memory 200876 kb
Host smart-aeb22bf7-f067-49ca-bdb0-673a11b51959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913723419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2913723419
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.266735045
Short name T298
Test name
Test status
Simulation time 3701855391 ps
CPU time 2.47 seconds
Started Apr 16 02:40:54 PM PDT 24
Finished Apr 16 02:40:58 PM PDT 24
Peak memory 200448 kb
Host smart-16213cfe-2647-43ca-8344-09529a3aee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266735045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.266735045
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1984770006
Short name T1031
Test name
Test status
Simulation time 158943498211 ps
CPU time 89.66 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:42:23 PM PDT 24
Peak memory 200812 kb
Host smart-81c2fe9c-8d7d-43bf-ad56-9b6f46052aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984770006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1984770006
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1478674623
Short name T975
Test name
Test status
Simulation time 34363890 ps
CPU time 0.55 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 196208 kb
Host smart-1a67bbfa-e082-4903-89d4-6ebfdd3d3b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478674623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1478674623
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.154825141
Short name T119
Test name
Test status
Simulation time 51735271096 ps
CPU time 49.66 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:40:00 PM PDT 24
Peak memory 198964 kb
Host smart-9e92deff-10b7-4fa2-82fd-24e980e09c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154825141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.154825141
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4042151084
Short name T1066
Test name
Test status
Simulation time 120070866652 ps
CPU time 103.82 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 200844 kb
Host smart-e02aa67b-73cf-4247-9589-b48c74bc6f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042151084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4042151084
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.735539018
Short name T1082
Test name
Test status
Simulation time 83071294547 ps
CPU time 35.36 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:49 PM PDT 24
Peak memory 200860 kb
Host smart-192bd449-b860-4903-b480-443c2c37a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735539018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.735539018
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2288687336
Short name T856
Test name
Test status
Simulation time 70802712624 ps
CPU time 37.87 seconds
Started Apr 16 02:39:06 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 200860 kb
Host smart-fd6e3215-151f-4dee-b19c-91e0b153479e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288687336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2288687336
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.85659143
Short name T353
Test name
Test status
Simulation time 162755321292 ps
CPU time 352.75 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:45:11 PM PDT 24
Peak memory 200844 kb
Host smart-a94a4b5d-c61d-4d13-909f-1cf9890102b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85659143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.85659143
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4037341011
Short name T598
Test name
Test status
Simulation time 2916487684 ps
CPU time 1.6 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:12 PM PDT 24
Peak memory 199320 kb
Host smart-5e9c1ac2-674e-447c-9aa0-251438ab2bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037341011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4037341011
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.2661453937
Short name T349
Test name
Test status
Simulation time 18581514939 ps
CPU time 15.01 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 200876 kb
Host smart-6dab6178-5d3b-47a4-aa10-8f1c3c91864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661453937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2661453937
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1399093878
Short name T962
Test name
Test status
Simulation time 13747676121 ps
CPU time 374.91 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:45:28 PM PDT 24
Peak memory 201096 kb
Host smart-b2f4a385-1703-4720-b3e5-eeca4959f574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399093878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1399093878
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2794927637
Short name T1110
Test name
Test status
Simulation time 1289522463 ps
CPU time 1.96 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:13 PM PDT 24
Peak memory 197648 kb
Host smart-0714f1f8-60f6-422a-b720-02b879103f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2794927637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2794927637
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3863385330
Short name T857
Test name
Test status
Simulation time 128931756946 ps
CPU time 13.26 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 200556 kb
Host smart-6c59019a-2f16-4964-9795-22f588dfeceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863385330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3863385330
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2989682126
Short name T290
Test name
Test status
Simulation time 41979297399 ps
CPU time 42.39 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:58 PM PDT 24
Peak memory 196716 kb
Host smart-854b9eae-1346-492a-b4b0-92562b866425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989682126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2989682126
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2176373373
Short name T103
Test name
Test status
Simulation time 124193566 ps
CPU time 0.76 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 218880 kb
Host smart-4777489d-909f-48e1-abc7-0e50ade74950
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176373373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2176373373
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.88837317
Short name T559
Test name
Test status
Simulation time 535961163 ps
CPU time 1.43 seconds
Started Apr 16 02:39:07 PM PDT 24
Finished Apr 16 02:39:09 PM PDT 24
Peak memory 200768 kb
Host smart-b13c7759-34bc-44c5-af75-5d17fbceadcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88837317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.88837317
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2564824855
Short name T932
Test name
Test status
Simulation time 150715091810 ps
CPU time 130.21 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 200876 kb
Host smart-22fa764e-2700-44bd-92a0-4cd137f10ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564824855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2564824855
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2613665664
Short name T494
Test name
Test status
Simulation time 116884689896 ps
CPU time 1028.5 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:56:19 PM PDT 24
Peak memory 225764 kb
Host smart-6ee2d4c6-143c-43d1-a37d-94fd6b0deefd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613665664 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2613665664
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2704785114
Short name T755
Test name
Test status
Simulation time 364693643 ps
CPU time 1.42 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:17 PM PDT 24
Peak memory 199208 kb
Host smart-79dac173-0249-4f5c-b2d7-bc8dbb4050e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704785114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2704785114
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3142917082
Short name T978
Test name
Test status
Simulation time 53408849902 ps
CPU time 134.17 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 200172 kb
Host smart-af00e6c2-9c49-4592-bda0-cf584f7d6f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142917082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3142917082
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1770512416
Short name T725
Test name
Test status
Simulation time 31368497 ps
CPU time 0.55 seconds
Started Apr 16 02:40:54 PM PDT 24
Finished Apr 16 02:40:56 PM PDT 24
Peak memory 196176 kb
Host smart-5f18b89f-951f-4432-ab10-4510d99d8122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770512416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1770512416
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3636252014
Short name T612
Test name
Test status
Simulation time 67134093167 ps
CPU time 58.22 seconds
Started Apr 16 02:40:52 PM PDT 24
Finished Apr 16 02:41:51 PM PDT 24
Peak memory 200888 kb
Host smart-4f635abc-486c-45ba-8a50-05973b470339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636252014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3636252014
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2456631708
Short name T996
Test name
Test status
Simulation time 139382621153 ps
CPU time 67.29 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:42:02 PM PDT 24
Peak memory 200748 kb
Host smart-a343fa56-0568-4146-9447-30d0533180e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456631708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2456631708
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.927943597
Short name T1180
Test name
Test status
Simulation time 28333891761 ps
CPU time 26.41 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:21 PM PDT 24
Peak memory 200904 kb
Host smart-64b17104-f33f-4596-a912-21b752a400e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927943597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.927943597
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.620761466
Short name T665
Test name
Test status
Simulation time 24423619252 ps
CPU time 40.32 seconds
Started Apr 16 02:40:53 PM PDT 24
Finished Apr 16 02:41:35 PM PDT 24
Peak memory 198036 kb
Host smart-3743f887-2c8b-4fec-82e2-2c713074c928
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620761466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.620761466
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3886413709
Short name T377
Test name
Test status
Simulation time 139284768532 ps
CPU time 1416.42 seconds
Started Apr 16 02:40:59 PM PDT 24
Finished Apr 16 03:04:36 PM PDT 24
Peak memory 200916 kb
Host smart-4b19a804-5974-4848-baab-e5a5092ef32e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886413709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3886413709
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1026383817
Short name T121
Test name
Test status
Simulation time 150093276 ps
CPU time 0.66 seconds
Started Apr 16 02:40:59 PM PDT 24
Finished Apr 16 02:41:00 PM PDT 24
Peak memory 196736 kb
Host smart-f86295d2-d586-46b0-b8a2-0206b2fc48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026383817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1026383817
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2786014452
Short name T539
Test name
Test status
Simulation time 85205044259 ps
CPU time 127.71 seconds
Started Apr 16 02:40:59 PM PDT 24
Finished Apr 16 02:43:08 PM PDT 24
Peak memory 200872 kb
Host smart-7dbaf3c5-34ef-4cdd-a805-b2aa9fd109ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786014452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2786014452
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.2592227792
Short name T495
Test name
Test status
Simulation time 19781424233 ps
CPU time 1031.97 seconds
Started Apr 16 02:40:56 PM PDT 24
Finished Apr 16 02:58:09 PM PDT 24
Peak memory 200856 kb
Host smart-fed80ed5-c96c-4b24-b9f5-fbb15a3cea74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592227792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2592227792
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1328146458
Short name T815
Test name
Test status
Simulation time 2697407217 ps
CPU time 9.71 seconds
Started Apr 16 02:40:54 PM PDT 24
Finished Apr 16 02:41:05 PM PDT 24
Peak memory 199792 kb
Host smart-6229cf8f-a085-42b1-87c2-b648c9c6e45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328146458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1328146458
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2890411397
Short name T1008
Test name
Test status
Simulation time 146639946597 ps
CPU time 39.71 seconds
Started Apr 16 02:40:58 PM PDT 24
Finished Apr 16 02:41:38 PM PDT 24
Peak memory 200892 kb
Host smart-fa2f3640-b4f2-4410-86b2-e405cbe410ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890411397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2890411397
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.4071699180
Short name T681
Test name
Test status
Simulation time 2875523903 ps
CPU time 3.02 seconds
Started Apr 16 02:40:57 PM PDT 24
Finished Apr 16 02:41:00 PM PDT 24
Peak memory 196592 kb
Host smart-12262c08-eeca-4f25-b1a0-4fe6b5281015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071699180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.4071699180
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1896322647
Short name T1120
Test name
Test status
Simulation time 10531303203 ps
CPU time 19.79 seconds
Started Apr 16 02:40:51 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 200796 kb
Host smart-224e5aaf-1ce9-4dda-b444-20120a3a3918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896322647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1896322647
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2428918212
Short name T753
Test name
Test status
Simulation time 40477460779 ps
CPU time 26.17 seconds
Started Apr 16 02:40:58 PM PDT 24
Finished Apr 16 02:41:25 PM PDT 24
Peak memory 200884 kb
Host smart-9a9d51e4-7ca7-43f8-afac-633ecf49bf36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428918212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2428918212
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.960813273
Short name T487
Test name
Test status
Simulation time 125654403700 ps
CPU time 341.87 seconds
Started Apr 16 02:40:56 PM PDT 24
Finished Apr 16 02:46:38 PM PDT 24
Peak memory 217344 kb
Host smart-253a58c7-16bc-4873-ba1a-1f9fabf2b74b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960813273 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.960813273
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.541629516
Short name T1130
Test name
Test status
Simulation time 549608085 ps
CPU time 2.22 seconds
Started Apr 16 02:40:58 PM PDT 24
Finished Apr 16 02:41:01 PM PDT 24
Peak memory 199840 kb
Host smart-ad74543b-3991-4322-9eba-a14fb3cec89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541629516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.541629516
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3146147089
Short name T1014
Test name
Test status
Simulation time 122857550898 ps
CPU time 94.8 seconds
Started Apr 16 02:40:55 PM PDT 24
Finished Apr 16 02:42:30 PM PDT 24
Peak memory 200804 kb
Host smart-0196caa4-d46a-475a-ad62-a0c4fc9b93f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146147089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3146147089
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2310326532
Short name T1112
Test name
Test status
Simulation time 31279349 ps
CPU time 0.55 seconds
Started Apr 16 02:41:02 PM PDT 24
Finished Apr 16 02:41:03 PM PDT 24
Peak memory 196156 kb
Host smart-9f649c0c-9046-4929-9655-56215ee9f474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310326532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2310326532
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2051150214
Short name T668
Test name
Test status
Simulation time 75136612345 ps
CPU time 31.81 seconds
Started Apr 16 02:40:56 PM PDT 24
Finished Apr 16 02:41:28 PM PDT 24
Peak memory 200896 kb
Host smart-5a8c38fc-1298-4b8b-9bdf-3f97c4766bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051150214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2051150214
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1529924473
Short name T256
Test name
Test status
Simulation time 64445972535 ps
CPU time 110.72 seconds
Started Apr 16 02:40:56 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200852 kb
Host smart-8b96a3a0-3a04-458b-8ea4-df6b2d5de6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529924473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1529924473
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4072034235
Short name T66
Test name
Test status
Simulation time 21766158123 ps
CPU time 53.48 seconds
Started Apr 16 02:41:00 PM PDT 24
Finished Apr 16 02:41:55 PM PDT 24
Peak memory 200824 kb
Host smart-8099faf8-8170-4c1f-aa7c-6009f890a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072034235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4072034235
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2403427761
Short name T463
Test name
Test status
Simulation time 8699774057 ps
CPU time 4.75 seconds
Started Apr 16 02:41:03 PM PDT 24
Finished Apr 16 02:41:09 PM PDT 24
Peak memory 197932 kb
Host smart-9227eb52-9861-4504-8b9e-5b0710d12937
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403427761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2403427761
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2134315407
Short name T384
Test name
Test status
Simulation time 80912970912 ps
CPU time 264.02 seconds
Started Apr 16 02:41:02 PM PDT 24
Finished Apr 16 02:45:27 PM PDT 24
Peak memory 200808 kb
Host smart-b3770151-8170-4769-bab7-d9b8bed7153a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134315407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2134315407
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.623710604
Short name T21
Test name
Test status
Simulation time 6533416613 ps
CPU time 6.96 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:41:13 PM PDT 24
Peak memory 199396 kb
Host smart-c87913a1-67ce-4a1b-ba0f-a56aa73162ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623710604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.623710604
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1212470513
Short name T677
Test name
Test status
Simulation time 20094528032 ps
CPU time 8.26 seconds
Started Apr 16 02:41:03 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 195812 kb
Host smart-b0f6033b-f3b0-41ab-97a4-73dec7678283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212470513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1212470513
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3445161993
Short name T726
Test name
Test status
Simulation time 10216866090 ps
CPU time 285.79 seconds
Started Apr 16 02:41:03 PM PDT 24
Finished Apr 16 02:45:50 PM PDT 24
Peak memory 200920 kb
Host smart-ce7f6119-2a93-4f23-b60b-24869081543c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445161993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3445161993
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3398945211
Short name T747
Test name
Test status
Simulation time 1692163239 ps
CPU time 3.4 seconds
Started Apr 16 02:41:02 PM PDT 24
Finished Apr 16 02:41:07 PM PDT 24
Peak memory 198656 kb
Host smart-02325a3b-f51f-4f78-9647-c7c7e1fe12ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398945211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3398945211
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.78803859
Short name T557
Test name
Test status
Simulation time 188659212792 ps
CPU time 118.39 seconds
Started Apr 16 02:41:07 PM PDT 24
Finished Apr 16 02:43:07 PM PDT 24
Peak memory 200808 kb
Host smart-5a060daf-46f1-499a-8db3-5259399fe851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78803859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.78803859
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2017358205
Short name T834
Test name
Test status
Simulation time 40688041100 ps
CPU time 4.53 seconds
Started Apr 16 02:41:03 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 196644 kb
Host smart-7f31db70-354e-4c3c-b413-20197659163c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017358205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2017358205
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2674830970
Short name T378
Test name
Test status
Simulation time 758756698 ps
CPU time 1.2 seconds
Started Apr 16 02:40:59 PM PDT 24
Finished Apr 16 02:41:00 PM PDT 24
Peak memory 200372 kb
Host smart-17fc8864-05c6-4137-a5a9-f4bda557c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674830970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2674830970
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.440541087
Short name T973
Test name
Test status
Simulation time 333473720440 ps
CPU time 1280.68 seconds
Started Apr 16 02:41:04 PM PDT 24
Finished Apr 16 03:02:26 PM PDT 24
Peak memory 200848 kb
Host smart-12d5092c-ae1d-4e38-a200-69d06b61eae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440541087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.440541087
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3584228045
Short name T1144
Test name
Test status
Simulation time 44737038226 ps
CPU time 586.1 seconds
Started Apr 16 02:41:00 PM PDT 24
Finished Apr 16 02:50:47 PM PDT 24
Peak memory 217528 kb
Host smart-58142233-e1c4-43cf-8fa7-6f372d1440e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584228045 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3584228045
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3787824887
Short name T621
Test name
Test status
Simulation time 524734982 ps
CPU time 1.9 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 199380 kb
Host smart-cb9714b2-ad1c-4892-8c96-69733328ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787824887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3787824887
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2135527376
Short name T821
Test name
Test status
Simulation time 110526219926 ps
CPU time 109.73 seconds
Started Apr 16 02:40:57 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200812 kb
Host smart-c417ac4c-4ceb-4b62-bc7f-dcd9c9592fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135527376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2135527376
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3066375356
Short name T352
Test name
Test status
Simulation time 25185448 ps
CPU time 0.57 seconds
Started Apr 16 02:41:08 PM PDT 24
Finished Apr 16 02:41:10 PM PDT 24
Peak memory 196176 kb
Host smart-21a99efe-4061-4eea-9edc-fe66378196ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066375356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3066375356
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1006364756
Short name T540
Test name
Test status
Simulation time 19592832187 ps
CPU time 8.21 seconds
Started Apr 16 02:41:02 PM PDT 24
Finished Apr 16 02:41:10 PM PDT 24
Peak memory 200388 kb
Host smart-586bc86f-3d45-403d-9168-786cfa7cb9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006364756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1006364756
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.821269456
Short name T172
Test name
Test status
Simulation time 119874988021 ps
CPU time 48.98 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:41:54 PM PDT 24
Peak memory 200464 kb
Host smart-9a40714a-3f3f-4321-a707-ace27970313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821269456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.821269456
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.762988720
Short name T1095
Test name
Test status
Simulation time 89510814293 ps
CPU time 128.57 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:43:14 PM PDT 24
Peak memory 200872 kb
Host smart-a4d973f0-23cb-4e22-ac1a-6e77b8648912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762988720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.762988720
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.584973631
Short name T423
Test name
Test status
Simulation time 45638342415 ps
CPU time 77.26 seconds
Started Apr 16 02:41:08 PM PDT 24
Finished Apr 16 02:42:26 PM PDT 24
Peak memory 200764 kb
Host smart-994cefba-82ff-4f97-a937-6f81ad4ab089
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584973631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.584973631
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3757739037
Short name T470
Test name
Test status
Simulation time 57921586616 ps
CPU time 352.41 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:46:58 PM PDT 24
Peak memory 200904 kb
Host smart-15babffc-4eb7-4513-85df-b87ea41d9caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757739037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3757739037
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2902502462
Short name T357
Test name
Test status
Simulation time 5402639692 ps
CPU time 4 seconds
Started Apr 16 02:41:07 PM PDT 24
Finished Apr 16 02:41:11 PM PDT 24
Peak memory 200248 kb
Host smart-e384e6b0-ed86-4739-8a7d-c0be17398e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902502462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2902502462
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2036054961
Short name T328
Test name
Test status
Simulation time 105368850517 ps
CPU time 80.86 seconds
Started Apr 16 02:41:07 PM PDT 24
Finished Apr 16 02:42:30 PM PDT 24
Peak memory 201092 kb
Host smart-caf34f34-6ce6-4524-9b63-5a56601e4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036054961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2036054961
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.314797775
Short name T513
Test name
Test status
Simulation time 16510642921 ps
CPU time 205.94 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:44:32 PM PDT 24
Peak memory 200892 kb
Host smart-377b17fe-cbb2-42e7-994a-a2b73300c324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314797775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.314797775
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.468351552
Short name T850
Test name
Test status
Simulation time 2519751529 ps
CPU time 18.13 seconds
Started Apr 16 02:41:07 PM PDT 24
Finished Apr 16 02:41:25 PM PDT 24
Peak memory 199340 kb
Host smart-c67e87f9-343a-4fdb-bff9-cdd3c9a650d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468351552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.468351552
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1406314451
Short name T699
Test name
Test status
Simulation time 142373347545 ps
CPU time 373.27 seconds
Started Apr 16 02:41:06 PM PDT 24
Finished Apr 16 02:47:20 PM PDT 24
Peak memory 200816 kb
Host smart-ea64e023-da3e-4624-af10-d28b58998b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406314451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1406314451
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1949349022
Short name T1111
Test name
Test status
Simulation time 4789175688 ps
CPU time 2.67 seconds
Started Apr 16 02:41:06 PM PDT 24
Finished Apr 16 02:41:10 PM PDT 24
Peak memory 196912 kb
Host smart-2927a885-c3ab-4e0b-958b-fd03dbb4baf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949349022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1949349022
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3710840925
Short name T417
Test name
Test status
Simulation time 6161129039 ps
CPU time 15.41 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:41:22 PM PDT 24
Peak memory 200848 kb
Host smart-309e1a2b-6722-4f3a-ab82-23676f708092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710840925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3710840925
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.4068014334
Short name T656
Test name
Test status
Simulation time 10732906294 ps
CPU time 58.93 seconds
Started Apr 16 02:41:10 PM PDT 24
Finished Apr 16 02:42:09 PM PDT 24
Peak memory 217376 kb
Host smart-499957c7-256b-4946-a6f7-2d7edceb6526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068014334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.4068014334
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2604191566
Short name T1113
Test name
Test status
Simulation time 6009873299 ps
CPU time 17.5 seconds
Started Apr 16 02:41:04 PM PDT 24
Finished Apr 16 02:41:23 PM PDT 24
Peak memory 200536 kb
Host smart-677bf631-4717-4a4e-92b7-7be618b53971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604191566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2604191566
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2515758913
Short name T452
Test name
Test status
Simulation time 5639721172 ps
CPU time 9.26 seconds
Started Apr 16 02:41:02 PM PDT 24
Finished Apr 16 02:41:12 PM PDT 24
Peak memory 200016 kb
Host smart-9de17a4a-341e-463f-bb0a-44acd8ebaaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515758913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2515758913
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3371231753
Short name T409
Test name
Test status
Simulation time 15458299 ps
CPU time 0.55 seconds
Started Apr 16 02:41:14 PM PDT 24
Finished Apr 16 02:41:15 PM PDT 24
Peak memory 196240 kb
Host smart-7062d278-4bb1-41be-9d44-c54da8d5c339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371231753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3371231753
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2037020163
Short name T1158
Test name
Test status
Simulation time 177606810137 ps
CPU time 160.72 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200924 kb
Host smart-7910bfd1-9a94-4108-92fe-29f9e9c203a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037020163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2037020163
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1520570368
Short name T542
Test name
Test status
Simulation time 72626328521 ps
CPU time 52.78 seconds
Started Apr 16 02:41:08 PM PDT 24
Finished Apr 16 02:42:02 PM PDT 24
Peak memory 200768 kb
Host smart-4e6412c9-a578-4610-b301-567b249e5ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520570368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1520570368
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3095227704
Short name T196
Test name
Test status
Simulation time 45360621643 ps
CPU time 72.7 seconds
Started Apr 16 02:41:10 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 200924 kb
Host smart-3822017c-6867-4f14-9985-1a7e60f7ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095227704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3095227704
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4014429697
Short name T867
Test name
Test status
Simulation time 7660173457 ps
CPU time 12.01 seconds
Started Apr 16 02:41:10 PM PDT 24
Finished Apr 16 02:41:23 PM PDT 24
Peak memory 197636 kb
Host smart-d7d39e15-df13-49fa-84dd-3f81177caef6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014429697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4014429697
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.652751922
Short name T1142
Test name
Test status
Simulation time 129543371954 ps
CPU time 644.88 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:51:58 PM PDT 24
Peak memory 200852 kb
Host smart-9bab5add-b838-40c4-8f79-0bb122e93cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652751922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.652751922
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4103609063
Short name T720
Test name
Test status
Simulation time 3904082510 ps
CPU time 2.4 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:41:16 PM PDT 24
Peak memory 198164 kb
Host smart-dcedca1a-5a7f-4f98-b4a2-0a2525d82320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103609063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4103609063
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1908125001
Short name T379
Test name
Test status
Simulation time 83735337150 ps
CPU time 143.38 seconds
Started Apr 16 02:41:11 PM PDT 24
Finished Apr 16 02:43:36 PM PDT 24
Peak memory 200824 kb
Host smart-9d910e83-b9f6-4c9d-a5ae-ed061347bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908125001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1908125001
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1637317185
Short name T422
Test name
Test status
Simulation time 24472572120 ps
CPU time 283.32 seconds
Started Apr 16 02:41:09 PM PDT 24
Finished Apr 16 02:45:53 PM PDT 24
Peak memory 200852 kb
Host smart-4aec0c38-7fca-4f4f-a8e2-0ce81bdad397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1637317185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1637317185
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1559638895
Short name T749
Test name
Test status
Simulation time 5115357026 ps
CPU time 50.94 seconds
Started Apr 16 02:41:11 PM PDT 24
Finished Apr 16 02:42:02 PM PDT 24
Peak memory 199216 kb
Host smart-c5b062bc-2eeb-45dc-9146-24798db74255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559638895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1559638895
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2603111565
Short name T980
Test name
Test status
Simulation time 47765494888 ps
CPU time 74.59 seconds
Started Apr 16 02:41:13 PM PDT 24
Finished Apr 16 02:42:28 PM PDT 24
Peak memory 200728 kb
Host smart-581bf12f-21a7-4d7a-8881-f552e12ff23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603111565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2603111565
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1079609749
Short name T740
Test name
Test status
Simulation time 1664236642 ps
CPU time 1.32 seconds
Started Apr 16 02:41:13 PM PDT 24
Finished Apr 16 02:41:15 PM PDT 24
Peak memory 196476 kb
Host smart-a60c15d0-408e-4c2b-9808-84217b60b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079609749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1079609749
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2144526258
Short name T462
Test name
Test status
Simulation time 246128538 ps
CPU time 1.63 seconds
Started Apr 16 02:41:08 PM PDT 24
Finished Apr 16 02:41:11 PM PDT 24
Peak memory 199368 kb
Host smart-5ff533d1-2ec8-483c-820a-158ddd08775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144526258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2144526258
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1739192518
Short name T1167
Test name
Test status
Simulation time 444065693771 ps
CPU time 148.35 seconds
Started Apr 16 02:41:11 PM PDT 24
Finished Apr 16 02:43:41 PM PDT 24
Peak memory 200908 kb
Host smart-34e40042-529c-44a4-9b77-79ab581c13e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739192518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1739192518
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.905936833
Short name T805
Test name
Test status
Simulation time 16082318111 ps
CPU time 135.14 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:43:28 PM PDT 24
Peak memory 216464 kb
Host smart-a8bb9da6-5e71-47dc-a280-5bea0daca581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905936833 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.905936833
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1501597633
Short name T970
Test name
Test status
Simulation time 6728156280 ps
CPU time 15.84 seconds
Started Apr 16 02:41:11 PM PDT 24
Finished Apr 16 02:41:27 PM PDT 24
Peak memory 200788 kb
Host smart-6c84604d-30ce-4a3b-939d-2cbd75a53297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501597633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1501597633
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.797290190
Short name T373
Test name
Test status
Simulation time 88289157703 ps
CPU time 146.47 seconds
Started Apr 16 02:41:05 PM PDT 24
Finished Apr 16 02:43:33 PM PDT 24
Peak memory 200908 kb
Host smart-6cb86521-8635-4a2a-a389-1d56b36a3483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797290190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.797290190
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.248597669
Short name T593
Test name
Test status
Simulation time 11904312 ps
CPU time 0.54 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:41:16 PM PDT 24
Peak memory 195632 kb
Host smart-23c34610-2748-4893-b374-ed6dd71645ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248597669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.248597669
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2097656496
Short name T902
Test name
Test status
Simulation time 58605731683 ps
CPU time 31.85 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 200856 kb
Host smart-1eac76c6-1da0-4417-9066-f62a767e9894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097656496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2097656496
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.165226406
Short name T505
Test name
Test status
Simulation time 83519193642 ps
CPU time 68.6 seconds
Started Apr 16 02:41:11 PM PDT 24
Finished Apr 16 02:42:20 PM PDT 24
Peak memory 200844 kb
Host smart-c3a0475f-dc97-43a5-bf06-ed99f903511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165226406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.165226406
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1253791100
Short name T554
Test name
Test status
Simulation time 98029228133 ps
CPU time 152.13 seconds
Started Apr 16 02:41:13 PM PDT 24
Finished Apr 16 02:43:46 PM PDT 24
Peak memory 200872 kb
Host smart-771dccb4-0d06-4862-9aef-0cfb647804d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253791100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1253791100
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2181731155
Short name T878
Test name
Test status
Simulation time 47770353315 ps
CPU time 33.81 seconds
Started Apr 16 02:41:14 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 198072 kb
Host smart-ae466a42-a7d3-4b82-ae20-d50500218be5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181731155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2181731155
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2044861604
Short name T1016
Test name
Test status
Simulation time 54129833392 ps
CPU time 73.9 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:42:30 PM PDT 24
Peak memory 200884 kb
Host smart-b9d90447-d678-4caa-b032-56fd33e73ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044861604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2044861604
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2141890409
Short name T983
Test name
Test status
Simulation time 6878639459 ps
CPU time 12.32 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:41:28 PM PDT 24
Peak memory 199592 kb
Host smart-06a080b3-eef7-4d2c-ba8d-2ce1b57a66c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141890409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2141890409
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3458611984
Short name T272
Test name
Test status
Simulation time 70926195878 ps
CPU time 119.45 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:43:13 PM PDT 24
Peak memory 209216 kb
Host smart-6b2f65c2-abaf-444f-a323-dc7dc4c9410c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458611984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3458611984
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2192001902
Short name T332
Test name
Test status
Simulation time 13798398580 ps
CPU time 71.36 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:42:27 PM PDT 24
Peak memory 200928 kb
Host smart-c58d879c-0ddf-4d10-9e9d-851d4f7178cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192001902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2192001902
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4042690304
Short name T683
Test name
Test status
Simulation time 7689619651 ps
CPU time 18.22 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 200012 kb
Host smart-08ec17ab-b166-4743-bd3a-b7efe42d0f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4042690304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4042690304
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1675073723
Short name T957
Test name
Test status
Simulation time 146078410251 ps
CPU time 211.76 seconds
Started Apr 16 02:41:17 PM PDT 24
Finished Apr 16 02:44:50 PM PDT 24
Peak memory 200880 kb
Host smart-975d010f-fb50-47d5-b4ac-696869b63380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675073723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1675073723
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.741306501
Short name T714
Test name
Test status
Simulation time 41358364348 ps
CPU time 28.24 seconds
Started Apr 16 02:41:15 PM PDT 24
Finished Apr 16 02:41:45 PM PDT 24
Peak memory 197188 kb
Host smart-bcce31d4-16d3-4aad-8a64-0a7f0b306833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741306501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.741306501
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3649983393
Short name T407
Test name
Test status
Simulation time 285312325 ps
CPU time 2.09 seconds
Started Apr 16 02:41:12 PM PDT 24
Finished Apr 16 02:41:15 PM PDT 24
Peak memory 199148 kb
Host smart-71bece8c-6454-403f-967b-f6ada743c01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649983393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3649983393
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2684170786
Short name T169
Test name
Test status
Simulation time 105733056752 ps
CPU time 53.01 seconds
Started Apr 16 02:41:17 PM PDT 24
Finished Apr 16 02:42:11 PM PDT 24
Peak memory 200824 kb
Host smart-6f0ea885-c51f-42b2-8873-9f2f4bd34525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684170786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2684170786
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4052697935
Short name T1069
Test name
Test status
Simulation time 1059900772 ps
CPU time 3.4 seconds
Started Apr 16 02:41:13 PM PDT 24
Finished Apr 16 02:41:17 PM PDT 24
Peak memory 199664 kb
Host smart-0dc2536f-d53e-4160-b8df-650c2e0e3e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052697935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4052697935
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3016450651
Short name T504
Test name
Test status
Simulation time 71617251190 ps
CPU time 63.82 seconds
Started Apr 16 02:41:10 PM PDT 24
Finished Apr 16 02:42:15 PM PDT 24
Peak memory 200924 kb
Host smart-a6062b04-12bb-4d91-a139-b24143f20b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016450651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3016450651
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2092916775
Short name T27
Test name
Test status
Simulation time 10856215 ps
CPU time 0.54 seconds
Started Apr 16 02:41:18 PM PDT 24
Finished Apr 16 02:41:20 PM PDT 24
Peak memory 196236 kb
Host smart-5be9d464-063e-4603-9411-1fe4eeb2bcfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092916775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2092916775
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3243946141
Short name T984
Test name
Test status
Simulation time 78126975296 ps
CPU time 29.51 seconds
Started Apr 16 02:41:21 PM PDT 24
Finished Apr 16 02:41:51 PM PDT 24
Peak memory 200928 kb
Host smart-337950e5-986f-4b3e-ae56-10eab190d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243946141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3243946141
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3984982168
Short name T538
Test name
Test status
Simulation time 29780600871 ps
CPU time 14.08 seconds
Started Apr 16 02:41:18 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 200824 kb
Host smart-80ebbb23-a4bb-4802-8c72-9859d68567a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984982168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3984982168
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2423359164
Short name T135
Test name
Test status
Simulation time 55031037371 ps
CPU time 25.18 seconds
Started Apr 16 02:41:17 PM PDT 24
Finished Apr 16 02:41:43 PM PDT 24
Peak memory 200760 kb
Host smart-b2d77d77-e9cd-4733-80c7-387f6c8f6405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423359164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2423359164
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1390818790
Short name T754
Test name
Test status
Simulation time 59192844719 ps
CPU time 17.54 seconds
Started Apr 16 02:41:19 PM PDT 24
Finished Apr 16 02:41:37 PM PDT 24
Peak memory 200664 kb
Host smart-f1d3562f-780c-4f80-946a-34ca8bd9d132
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390818790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1390818790
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1446681250
Short name T483
Test name
Test status
Simulation time 64701757835 ps
CPU time 495.69 seconds
Started Apr 16 02:41:17 PM PDT 24
Finished Apr 16 02:49:34 PM PDT 24
Peak memory 200872 kb
Host smart-df8803ed-fabd-45ed-b3db-b3640c83b32c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446681250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1446681250
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1195967090
Short name T1102
Test name
Test status
Simulation time 5318335058 ps
CPU time 3.11 seconds
Started Apr 16 02:41:20 PM PDT 24
Finished Apr 16 02:41:24 PM PDT 24
Peak memory 198920 kb
Host smart-78b8b09c-713a-431e-adef-5303b63e8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195967090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1195967090
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.348996546
Short name T486
Test name
Test status
Simulation time 57890446527 ps
CPU time 52.38 seconds
Started Apr 16 02:41:19 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 201044 kb
Host smart-b0e77e52-cb79-4de1-9f03-117df71581a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348996546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.348996546
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3078154328
Short name T640
Test name
Test status
Simulation time 18378786042 ps
CPU time 412.34 seconds
Started Apr 16 02:41:19 PM PDT 24
Finished Apr 16 02:48:12 PM PDT 24
Peak memory 200888 kb
Host smart-3daf96d5-15bb-4ee3-a656-748cda0cee91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078154328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3078154328
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4089936873
Short name T966
Test name
Test status
Simulation time 4763221027 ps
CPU time 11.51 seconds
Started Apr 16 02:41:17 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 199544 kb
Host smart-9a68b1db-f16b-4bc9-9e0f-bed213efaa83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089936873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4089936873
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2416451979
Short name T10
Test name
Test status
Simulation time 24210501588 ps
CPU time 39.75 seconds
Started Apr 16 02:41:21 PM PDT 24
Finished Apr 16 02:42:01 PM PDT 24
Peak memory 200820 kb
Host smart-69827b72-f32c-4ae5-b34d-4be076bf41ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416451979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2416451979
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3780854179
Short name T564
Test name
Test status
Simulation time 3380287382 ps
CPU time 1.11 seconds
Started Apr 16 02:41:19 PM PDT 24
Finished Apr 16 02:41:21 PM PDT 24
Peak memory 196756 kb
Host smart-b41712b8-a785-4a1d-b1e7-29057613492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780854179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3780854179
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1817064908
Short name T616
Test name
Test status
Simulation time 5897215040 ps
CPU time 20.54 seconds
Started Apr 16 02:41:16 PM PDT 24
Finished Apr 16 02:41:37 PM PDT 24
Peak memory 200024 kb
Host smart-1a36a770-1367-4dac-8a33-974d71997134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817064908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1817064908
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.289810059
Short name T1107
Test name
Test status
Simulation time 34133524749 ps
CPU time 66.23 seconds
Started Apr 16 02:41:20 PM PDT 24
Finished Apr 16 02:42:27 PM PDT 24
Peak memory 200924 kb
Host smart-95e57201-1ff2-462c-b3f6-c2e43b3b73e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289810059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.289810059
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4123646178
Short name T592
Test name
Test status
Simulation time 78770116190 ps
CPU time 628.02 seconds
Started Apr 16 02:41:22 PM PDT 24
Finished Apr 16 02:51:51 PM PDT 24
Peak memory 227516 kb
Host smart-defa8176-8d95-48ed-b030-69dd58d9f7d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123646178 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4123646178
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.797598492
Short name T886
Test name
Test status
Simulation time 1177104155 ps
CPU time 2.6 seconds
Started Apr 16 02:41:22 PM PDT 24
Finished Apr 16 02:41:25 PM PDT 24
Peak memory 200124 kb
Host smart-e29640fc-5a77-481b-bf1b-83591437c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797598492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.797598492
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1338554580
Short name T354
Test name
Test status
Simulation time 48178937443 ps
CPU time 48.29 seconds
Started Apr 16 02:41:20 PM PDT 24
Finished Apr 16 02:42:09 PM PDT 24
Peak memory 200240 kb
Host smart-fd663ea1-c952-4ba5-9fac-94093c85c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338554580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1338554580
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2917770269
Short name T991
Test name
Test status
Simulation time 25241161 ps
CPU time 0.55 seconds
Started Apr 16 02:41:29 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 195208 kb
Host smart-915ec5d0-d650-4492-9a4c-9aaa9226b5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917770269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2917770269
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4217817412
Short name T380
Test name
Test status
Simulation time 57392755977 ps
CPU time 43.48 seconds
Started Apr 16 02:41:26 PM PDT 24
Finished Apr 16 02:42:10 PM PDT 24
Peak memory 200800 kb
Host smart-a334b148-02c9-46e3-a2b6-7691c53118ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217817412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4217817412
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3213066308
Short name T50
Test name
Test status
Simulation time 30500089455 ps
CPU time 25.68 seconds
Started Apr 16 02:41:25 PM PDT 24
Finished Apr 16 02:41:51 PM PDT 24
Peak memory 199656 kb
Host smart-3142603b-f1a3-4c05-abdd-b54e5aca784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213066308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3213066308
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.1222564448
Short name T1086
Test name
Test status
Simulation time 12801294898 ps
CPU time 11.04 seconds
Started Apr 16 02:41:22 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 197512 kb
Host smart-08c16df7-331f-49e5-9b7e-dc068ca62960
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222564448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1222564448
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.986571335
Short name T368
Test name
Test status
Simulation time 166997512219 ps
CPU time 447.07 seconds
Started Apr 16 02:41:31 PM PDT 24
Finished Apr 16 02:48:59 PM PDT 24
Peak memory 200916 kb
Host smart-bc6c43c5-ea3e-4e2c-a5dd-d14261a9f76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=986571335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.986571335
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3840803235
Short name T899
Test name
Test status
Simulation time 2938525773 ps
CPU time 5.57 seconds
Started Apr 16 02:41:35 PM PDT 24
Finished Apr 16 02:41:42 PM PDT 24
Peak memory 198652 kb
Host smart-5177a350-0ddd-428e-97a9-47ebe08575f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840803235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3840803235
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1858742647
Short name T759
Test name
Test status
Simulation time 120505552856 ps
CPU time 97.87 seconds
Started Apr 16 02:41:22 PM PDT 24
Finished Apr 16 02:43:01 PM PDT 24
Peak memory 209224 kb
Host smart-bb18ff9e-8d20-4c27-9b22-45c076bfda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858742647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1858742647
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1720454898
Short name T686
Test name
Test status
Simulation time 12500813199 ps
CPU time 96.91 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:43:14 PM PDT 24
Peak memory 200824 kb
Host smart-1920f29f-ee4a-4516-8220-0c0d1f794859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720454898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1720454898
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.572344487
Short name T897
Test name
Test status
Simulation time 5253411868 ps
CPU time 23.89 seconds
Started Apr 16 02:41:23 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 199076 kb
Host smart-80eb54f4-8d45-407a-ac00-123d073ec632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572344487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.572344487
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.460472904
Short name T292
Test name
Test status
Simulation time 341015080484 ps
CPU time 158.43 seconds
Started Apr 16 02:41:24 PM PDT 24
Finished Apr 16 02:44:03 PM PDT 24
Peak memory 200840 kb
Host smart-9d5c1230-2e64-4667-bbf5-872207bf9e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460472904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.460472904
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3743662713
Short name T288
Test name
Test status
Simulation time 5376390940 ps
CPU time 10.24 seconds
Started Apr 16 02:41:23 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 196928 kb
Host smart-99aabc94-3ca7-4fb7-ab50-2cf72bbc64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743662713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3743662713
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.723458222
Short name T439
Test name
Test status
Simulation time 651744631 ps
CPU time 2.76 seconds
Started Apr 16 02:41:24 PM PDT 24
Finished Apr 16 02:41:28 PM PDT 24
Peak memory 198652 kb
Host smart-3b6a4c07-beff-4e83-9753-89af8609692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723458222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.723458222
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.907965303
Short name T329
Test name
Test status
Simulation time 212446107509 ps
CPU time 723.51 seconds
Started Apr 16 02:41:27 PM PDT 24
Finished Apr 16 02:53:32 PM PDT 24
Peak memory 217328 kb
Host smart-b63e0143-c8e2-45a8-a672-bc209154f957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907965303 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.907965303
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1896285645
Short name T502
Test name
Test status
Simulation time 1234870758 ps
CPU time 1.61 seconds
Started Apr 16 02:41:26 PM PDT 24
Finished Apr 16 02:41:28 PM PDT 24
Peak memory 199320 kb
Host smart-2bfb1426-1f10-4456-ac64-0b2d9cf7e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896285645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1896285645
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2422131820
Short name T778
Test name
Test status
Simulation time 16114524014 ps
CPU time 21.13 seconds
Started Apr 16 02:41:22 PM PDT 24
Finished Apr 16 02:41:44 PM PDT 24
Peak memory 200908 kb
Host smart-c9394b5e-4c25-4f54-9476-e6bcd122ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422131820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2422131820
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.4051676403
Short name T807
Test name
Test status
Simulation time 22922745 ps
CPU time 0.55 seconds
Started Apr 16 02:41:34 PM PDT 24
Finished Apr 16 02:41:35 PM PDT 24
Peak memory 196236 kb
Host smart-03aaa382-6997-4ee8-a1d9-5310a45d54d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051676403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4051676403
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4125011293
Short name T953
Test name
Test status
Simulation time 41218392871 ps
CPU time 73.28 seconds
Started Apr 16 02:41:28 PM PDT 24
Finished Apr 16 02:42:42 PM PDT 24
Peak memory 200888 kb
Host smart-db35564e-8a32-4ea4-80c8-898a9ea98b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125011293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4125011293
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4002513908
Short name T618
Test name
Test status
Simulation time 217745141213 ps
CPU time 166.21 seconds
Started Apr 16 02:41:27 PM PDT 24
Finished Apr 16 02:44:14 PM PDT 24
Peak memory 200760 kb
Host smart-bcd70940-3f86-459d-9aab-2412c944721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002513908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4002513908
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.614674744
Short name T873
Test name
Test status
Simulation time 64536433058 ps
CPU time 56.33 seconds
Started Apr 16 02:41:27 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 200912 kb
Host smart-0d0099ae-f7ab-4270-a118-0f8c9d19bb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614674744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.614674744
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1523854316
Short name T969
Test name
Test status
Simulation time 50937305448 ps
CPU time 43.99 seconds
Started Apr 16 02:41:28 PM PDT 24
Finished Apr 16 02:42:12 PM PDT 24
Peak memory 199784 kb
Host smart-0df98f27-682e-4fdf-b6a5-ae28945a2bd0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523854316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1523854316
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1447718430
Short name T617
Test name
Test status
Simulation time 93850046031 ps
CPU time 894.97 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:56:32 PM PDT 24
Peak memory 200820 kb
Host smart-71102293-2b88-4bb5-bc45-e06886f69d03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1447718430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1447718430
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2668308309
Short name T718
Test name
Test status
Simulation time 5346029364 ps
CPU time 6.36 seconds
Started Apr 16 02:41:35 PM PDT 24
Finished Apr 16 02:41:42 PM PDT 24
Peak memory 199420 kb
Host smart-e65338ca-8f97-4e04-9b17-9a20a884b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668308309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2668308309
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3986120191
Short name T282
Test name
Test status
Simulation time 130577902615 ps
CPU time 55.37 seconds
Started Apr 16 02:41:26 PM PDT 24
Finished Apr 16 02:42:22 PM PDT 24
Peak memory 200772 kb
Host smart-860acfb8-6a4d-41e8-841c-861cc8570f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986120191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3986120191
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3402006478
Short name T719
Test name
Test status
Simulation time 23160193596 ps
CPU time 294.23 seconds
Started Apr 16 02:41:29 PM PDT 24
Finished Apr 16 02:46:24 PM PDT 24
Peak memory 200828 kb
Host smart-01e059bd-019f-42d3-84d4-5ac912c74d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402006478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3402006478
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.719413267
Short name T520
Test name
Test status
Simulation time 1497034106 ps
CPU time 1.98 seconds
Started Apr 16 02:41:30 PM PDT 24
Finished Apr 16 02:41:33 PM PDT 24
Peak memory 197644 kb
Host smart-005fe56b-f764-4f8a-b856-c4562a697455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719413267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.719413267
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3620861829
Short name T552
Test name
Test status
Simulation time 98173242175 ps
CPU time 54.05 seconds
Started Apr 16 02:41:28 PM PDT 24
Finished Apr 16 02:42:23 PM PDT 24
Peak memory 200788 kb
Host smart-b8dc6d64-8fef-4737-8376-4e1b59095a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620861829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3620861829
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.494598433
Short name T814
Test name
Test status
Simulation time 2987175132 ps
CPU time 4.76 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:41:42 PM PDT 24
Peak memory 196708 kb
Host smart-03634e53-9fd8-46e3-9683-649ee1b1593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494598433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.494598433
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1358963816
Short name T392
Test name
Test status
Simulation time 287112731 ps
CPU time 2 seconds
Started Apr 16 02:41:28 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 199512 kb
Host smart-4e1c3ef2-2ad0-4e32-ac18-319d1ad90b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358963816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1358963816
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1881026734
Short name T444
Test name
Test status
Simulation time 210201126312 ps
CPU time 569.4 seconds
Started Apr 16 02:41:38 PM PDT 24
Finished Apr 16 02:51:08 PM PDT 24
Peak memory 200816 kb
Host smart-68745215-9d26-4c87-a0b3-1b002f8eed5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881026734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1881026734
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3551571294
Short name T175
Test name
Test status
Simulation time 14653884141 ps
CPU time 136.07 seconds
Started Apr 16 02:41:31 PM PDT 24
Finished Apr 16 02:43:47 PM PDT 24
Peak memory 217080 kb
Host smart-28e33600-ca8a-4b5c-9899-92f25314f098
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551571294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3551571294
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2085191983
Short name T1023
Test name
Test status
Simulation time 528271042 ps
CPU time 2.14 seconds
Started Apr 16 02:41:27 PM PDT 24
Finished Apr 16 02:41:30 PM PDT 24
Peak memory 199820 kb
Host smart-af42c9e3-606c-47e6-a528-7a6d18e29ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085191983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2085191983
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3979855226
Short name T1101
Test name
Test status
Simulation time 72434432950 ps
CPU time 31.33 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:42:08 PM PDT 24
Peak memory 200844 kb
Host smart-ffbafcf0-b79e-4a01-b409-2fd2cb171292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979855226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3979855226
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.108017939
Short name T388
Test name
Test status
Simulation time 12591729 ps
CPU time 0.56 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:41:34 PM PDT 24
Peak memory 196224 kb
Host smart-eecdb963-6de9-4ecd-81f7-6db38fc53576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108017939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.108017939
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2096344370
Short name T401
Test name
Test status
Simulation time 63742988302 ps
CPU time 23.28 seconds
Started Apr 16 02:41:32 PM PDT 24
Finished Apr 16 02:41:56 PM PDT 24
Peak memory 200700 kb
Host smart-8f36f44c-2c80-46d7-8fcd-73f94a960c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096344370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2096344370
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.475829674
Short name T125
Test name
Test status
Simulation time 19937606419 ps
CPU time 9.68 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:41:44 PM PDT 24
Peak memory 200860 kb
Host smart-937ed7fd-75f4-4b0f-b325-6afb6d84df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475829674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.475829674
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.451403516
Short name T576
Test name
Test status
Simulation time 164530284376 ps
CPU time 67.62 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:42:42 PM PDT 24
Peak memory 200884 kb
Host smart-e497a962-64c3-4162-ab61-10edd57a33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451403516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.451403516
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3338118743
Short name T735
Test name
Test status
Simulation time 60697066102 ps
CPU time 26.55 seconds
Started Apr 16 02:41:34 PM PDT 24
Finished Apr 16 02:42:02 PM PDT 24
Peak memory 200856 kb
Host smart-15addf4b-9e62-4971-bc08-96bae1a07b3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338118743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3338118743
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.477986069
Short name T108
Test name
Test status
Simulation time 56196082615 ps
CPU time 531.44 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:50:26 PM PDT 24
Peak memory 200664 kb
Host smart-bab7c149-c18d-45fd-a995-317610a83627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477986069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.477986069
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1732148825
Short name T938
Test name
Test status
Simulation time 4701762732 ps
CPU time 15.29 seconds
Started Apr 16 02:41:32 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 200804 kb
Host smart-726f9259-e8bc-47dd-a4ef-617f65feec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732148825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1732148825
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1554818282
Short name T484
Test name
Test status
Simulation time 32320740853 ps
CPU time 16.26 seconds
Started Apr 16 02:41:41 PM PDT 24
Finished Apr 16 02:41:58 PM PDT 24
Peak memory 201048 kb
Host smart-ec0e9a7a-af3b-4383-8b58-0ccd4ddf9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554818282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1554818282
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3073972823
Short name T767
Test name
Test status
Simulation time 23622399483 ps
CPU time 304.7 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:46:39 PM PDT 24
Peak memory 200800 kb
Host smart-eae63f1f-6c4a-40b7-9e6c-e0d02ed7435e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3073972823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3073972823
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3802309321
Short name T26
Test name
Test status
Simulation time 3338773194 ps
CPU time 27.14 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:42:01 PM PDT 24
Peak memory 199796 kb
Host smart-141724c3-822c-4960-a5c4-11dc3f93d8e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802309321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3802309321
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1112948831
Short name T387
Test name
Test status
Simulation time 130206962249 ps
CPU time 94.34 seconds
Started Apr 16 02:41:33 PM PDT 24
Finished Apr 16 02:43:08 PM PDT 24
Peak memory 200520 kb
Host smart-eed953c0-c3e0-4328-b2b7-1ee0168e5f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112948831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1112948831
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.281981985
Short name T344
Test name
Test status
Simulation time 6497730214 ps
CPU time 4.63 seconds
Started Apr 16 02:41:31 PM PDT 24
Finished Apr 16 02:41:36 PM PDT 24
Peak memory 196928 kb
Host smart-c8fc5e74-1151-402a-839a-d77891eae8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281981985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.281981985
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.662751021
Short name T1039
Test name
Test status
Simulation time 905988055 ps
CPU time 2.75 seconds
Started Apr 16 02:41:40 PM PDT 24
Finished Apr 16 02:41:43 PM PDT 24
Peak memory 200744 kb
Host smart-51a48e3f-861f-4bc7-a60d-c15dc7472d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662751021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.662751021
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3694460869
Short name T764
Test name
Test status
Simulation time 201165494656 ps
CPU time 602.06 seconds
Started Apr 16 02:41:34 PM PDT 24
Finished Apr 16 02:51:37 PM PDT 24
Peak memory 200912 kb
Host smart-d805993b-d6ba-4fe6-adc6-e28ca0d2a34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694460869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3694460869
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.4067235818
Short name T57
Test name
Test status
Simulation time 509665419520 ps
CPU time 1349.5 seconds
Started Apr 16 02:41:34 PM PDT 24
Finished Apr 16 03:04:04 PM PDT 24
Peak memory 217280 kb
Host smart-42d2cc9f-ccd4-48e5-a801-9bd395ed6fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067235818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.4067235818
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1615261244
Short name T291
Test name
Test status
Simulation time 1426559220 ps
CPU time 4.51 seconds
Started Apr 16 02:41:32 PM PDT 24
Finished Apr 16 02:41:37 PM PDT 24
Peak memory 199864 kb
Host smart-aa6a9a6e-e377-4a21-815a-920b0d1cd4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615261244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1615261244
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.1149741856
Short name T728
Test name
Test status
Simulation time 48244895615 ps
CPU time 14.45 seconds
Started Apr 16 02:41:35 PM PDT 24
Finished Apr 16 02:41:50 PM PDT 24
Peak memory 199392 kb
Host smart-c54e96f1-5110-4feb-9fb2-8f69222be392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149741856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1149741856
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.37458744
Short name T569
Test name
Test status
Simulation time 13223315 ps
CPU time 0.54 seconds
Started Apr 16 02:41:39 PM PDT 24
Finished Apr 16 02:41:40 PM PDT 24
Peak memory 195592 kb
Host smart-1d94318b-01df-4ef6-896b-914c1f6601a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37458744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.37458744
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1822136189
Short name T888
Test name
Test status
Simulation time 18324602305 ps
CPU time 29.37 seconds
Started Apr 16 02:41:39 PM PDT 24
Finished Apr 16 02:42:09 PM PDT 24
Peak memory 200800 kb
Host smart-c79e0fe6-64ae-4749-a9a1-97851a6b7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822136189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1822136189
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3968182897
Short name T1078
Test name
Test status
Simulation time 31678976006 ps
CPU time 25.34 seconds
Started Apr 16 02:41:43 PM PDT 24
Finished Apr 16 02:42:09 PM PDT 24
Peak memory 200912 kb
Host smart-b2d4326d-d22f-43b9-8a09-4ce231cb4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968182897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3968182897
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.701631084
Short name T1124
Test name
Test status
Simulation time 129099491937 ps
CPU time 19.64 seconds
Started Apr 16 02:41:43 PM PDT 24
Finished Apr 16 02:42:03 PM PDT 24
Peak memory 200812 kb
Host smart-c0f3f994-85f2-44ec-a957-994b1c582d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701631084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.701631084
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3469265546
Short name T127
Test name
Test status
Simulation time 158452393278 ps
CPU time 276.69 seconds
Started Apr 16 02:41:38 PM PDT 24
Finished Apr 16 02:46:15 PM PDT 24
Peak memory 198952 kb
Host smart-5edb002d-9c1e-4547-9e20-30b76891feb7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469265546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3469265546
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3206176879
Short name T1001
Test name
Test status
Simulation time 326632692822 ps
CPU time 288.33 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:46:31 PM PDT 24
Peak memory 200908 kb
Host smart-904fd5e3-e816-485e-99a4-51e9484613a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206176879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3206176879
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1596460368
Short name T887
Test name
Test status
Simulation time 5456630088 ps
CPU time 10.72 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:41:54 PM PDT 24
Peak memory 199156 kb
Host smart-f21064ad-9e27-4841-bd2c-0bd735616196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596460368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1596460368
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1422564143
Short name T1053
Test name
Test status
Simulation time 50275954931 ps
CPU time 90.38 seconds
Started Apr 16 02:41:36 PM PDT 24
Finished Apr 16 02:43:07 PM PDT 24
Peak memory 199768 kb
Host smart-44929a8a-99db-4abb-bdec-ec800d905024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422564143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1422564143
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2031688299
Short name T993
Test name
Test status
Simulation time 16222078527 ps
CPU time 120.08 seconds
Started Apr 16 02:41:44 PM PDT 24
Finished Apr 16 02:43:45 PM PDT 24
Peak memory 200856 kb
Host smart-abff6fd6-e27f-436d-bc5f-bf640f564acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031688299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2031688299
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.959801977
Short name T574
Test name
Test status
Simulation time 3160731813 ps
CPU time 13.56 seconds
Started Apr 16 02:41:44 PM PDT 24
Finished Apr 16 02:41:58 PM PDT 24
Peak memory 199184 kb
Host smart-100398c6-d382-4b47-b502-2e7419fde39b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=959801977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.959801977
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3488099811
Short name T832
Test name
Test status
Simulation time 121471446261 ps
CPU time 213.82 seconds
Started Apr 16 02:41:44 PM PDT 24
Finished Apr 16 02:45:18 PM PDT 24
Peak memory 200544 kb
Host smart-fc1eeaaa-e1ce-443b-99d4-d1a2a2eac2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488099811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3488099811
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2188860643
Short name T314
Test name
Test status
Simulation time 6006965698 ps
CPU time 11.05 seconds
Started Apr 16 02:41:35 PM PDT 24
Finished Apr 16 02:41:47 PM PDT 24
Peak memory 196904 kb
Host smart-1946e1de-4b5f-440f-a40c-f49c06b32efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188860643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2188860643
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2913841440
Short name T335
Test name
Test status
Simulation time 310384380 ps
CPU time 1.13 seconds
Started Apr 16 02:41:34 PM PDT 24
Finished Apr 16 02:41:36 PM PDT 24
Peak memory 199184 kb
Host smart-32659009-0dd7-4dd2-86ab-86e45b9cdc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913841440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2913841440
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.878737673
Short name T826
Test name
Test status
Simulation time 461367947150 ps
CPU time 620.74 seconds
Started Apr 16 02:41:39 PM PDT 24
Finished Apr 16 02:52:00 PM PDT 24
Peak memory 217420 kb
Host smart-366cf366-d8aa-45f6-b8b4-4d0291972706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878737673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.878737673
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.889331037
Short name T317
Test name
Test status
Simulation time 17802368405 ps
CPU time 311.2 seconds
Started Apr 16 02:41:39 PM PDT 24
Finished Apr 16 02:46:51 PM PDT 24
Peak memory 209360 kb
Host smart-00e9aefc-fb14-465a-a01a-1e85e3e68bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889331037 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.889331037
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2327592378
Short name T342
Test name
Test status
Simulation time 1378473872 ps
CPU time 5.19 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:41:48 PM PDT 24
Peak memory 200708 kb
Host smart-45fb7ad2-5b2a-4499-913a-609db56e2139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327592378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2327592378
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1684190077
Short name T955
Test name
Test status
Simulation time 35286341106 ps
CPU time 16.22 seconds
Started Apr 16 02:41:32 PM PDT 24
Finished Apr 16 02:41:49 PM PDT 24
Peak memory 200904 kb
Host smart-62994d07-d28e-4b78-b41f-43784cd32237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684190077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1684190077
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3475765745
Short name T907
Test name
Test status
Simulation time 43334170 ps
CPU time 0.56 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:14 PM PDT 24
Peak memory 196156 kb
Host smart-5f838341-06d3-49ac-82c4-846423d40399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475765745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3475765745
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1482280223
Short name T555
Test name
Test status
Simulation time 40122137868 ps
CPU time 38.39 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:39:50 PM PDT 24
Peak memory 200888 kb
Host smart-8a034b4a-9d93-4ffb-9dde-630217274eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482280223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1482280223
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.984633822
Short name T771
Test name
Test status
Simulation time 9179287173 ps
CPU time 16.34 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 200480 kb
Host smart-cf77d6cf-7055-465c-8bc8-9c0be3c29cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984633822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.984633822
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1208191939
Short name T212
Test name
Test status
Simulation time 72848917456 ps
CPU time 24.68 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:42 PM PDT 24
Peak memory 200828 kb
Host smart-75406e2b-797c-4735-9012-5a8e38aba746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208191939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1208191939
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3999668319
Short name T622
Test name
Test status
Simulation time 25789658374 ps
CPU time 6.66 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 200772 kb
Host smart-ae35379b-6cd6-49cb-b332-5f8818162921
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999668319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3999668319
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1959001260
Short name T338
Test name
Test status
Simulation time 75883127873 ps
CPU time 168.89 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:42:06 PM PDT 24
Peak memory 200920 kb
Host smart-7425a3f5-4721-4345-834c-6d4632c3e145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959001260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1959001260
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4157289709
Short name T874
Test name
Test status
Simulation time 6703399242 ps
CPU time 19.66 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:33 PM PDT 24
Peak memory 200824 kb
Host smart-e400546d-8f10-44b8-90a6-8fbe20702675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157289709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4157289709
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.1589015473
Short name T781
Test name
Test status
Simulation time 52344312058 ps
CPU time 23.18 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:41 PM PDT 24
Peak memory 199716 kb
Host smart-3c15ec06-400a-4e41-983a-6a29a56df4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589015473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1589015473
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.4098187450
Short name T708
Test name
Test status
Simulation time 3612187443 ps
CPU time 209.55 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:42:40 PM PDT 24
Peak memory 200912 kb
Host smart-05c0289d-64f6-4157-9fb6-c20ff647d633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098187450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4098187450
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1963329242
Short name T1017
Test name
Test status
Simulation time 1299371308 ps
CPU time 1.06 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:17 PM PDT 24
Peak memory 196568 kb
Host smart-f3f09e22-8c5d-4790-ae7a-4c03169d2e1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963329242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1963329242
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.4245001907
Short name T535
Test name
Test status
Simulation time 44653645258 ps
CPU time 86.17 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:40:37 PM PDT 24
Peak memory 200832 kb
Host smart-bb092fa9-14db-4a4c-a18f-96c53998c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245001907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.4245001907
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1166251366
Short name T385
Test name
Test status
Simulation time 3906567225 ps
CPU time 1.76 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:39:14 PM PDT 24
Peak memory 196912 kb
Host smart-68288227-002a-40af-9635-8720df30cb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166251366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1166251366
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1370440461
Short name T46
Test name
Test status
Simulation time 784570023 ps
CPU time 1.19 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:17 PM PDT 24
Peak memory 199696 kb
Host smart-e0932680-551b-4a3e-9780-644a766415fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370440461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1370440461
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3856952101
Short name T761
Test name
Test status
Simulation time 110888897538 ps
CPU time 449.2 seconds
Started Apr 16 02:39:08 PM PDT 24
Finished Apr 16 02:46:39 PM PDT 24
Peak memory 209280 kb
Host smart-9d042323-eda3-4ec3-b7ed-38b2d6bf2491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856952101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3856952101
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.23645221
Short name T624
Test name
Test status
Simulation time 26890587284 ps
CPU time 725.82 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:51:18 PM PDT 24
Peak memory 216944 kb
Host smart-2520324b-b02e-4b6e-b0a3-773a512906be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645221 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.23645221
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2168536258
Short name T1021
Test name
Test status
Simulation time 9464523530 ps
CPU time 10.37 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:20 PM PDT 24
Peak memory 200840 kb
Host smart-e65d83b9-09c0-45d1-a272-8b6d5034e7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168536258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2168536258
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2776599110
Short name T675
Test name
Test status
Simulation time 62994850307 ps
CPU time 306.93 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:44:18 PM PDT 24
Peak memory 200860 kb
Host smart-fb851e07-27e1-41ef-815f-0d96d5565cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776599110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2776599110
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1961211551
Short name T6
Test name
Test status
Simulation time 103638744319 ps
CPU time 41.55 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 200920 kb
Host smart-7eab2673-283c-40f2-b19f-207ba9f4c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961211551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1961211551
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3418685657
Short name T1128
Test name
Test status
Simulation time 73784097220 ps
CPU time 1093.55 seconds
Started Apr 16 02:41:38 PM PDT 24
Finished Apr 16 02:59:52 PM PDT 24
Peak memory 233860 kb
Host smart-8e2faed9-6c28-4aa4-9bbd-7a8dc1e5d4e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418685657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3418685657
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2327216684
Short name T63
Test name
Test status
Simulation time 15950594836 ps
CPU time 104.81 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:43:30 PM PDT 24
Peak memory 217324 kb
Host smart-2e12f0da-c609-48c1-899e-2f541675111b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327216684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2327216684
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1982893261
Short name T695
Test name
Test status
Simulation time 111015422846 ps
CPU time 168.64 seconds
Started Apr 16 02:41:43 PM PDT 24
Finished Apr 16 02:44:32 PM PDT 24
Peak memory 200804 kb
Host smart-d152a2bd-cf58-4ed4-9040-c801b3dac6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982893261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1982893261
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1692778251
Short name T1057
Test name
Test status
Simulation time 34257820810 ps
CPU time 407.74 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:48:33 PM PDT 24
Peak memory 217540 kb
Host smart-5c181173-10bb-4821-b0e4-caeb662e5cc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692778251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1692778251
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1514056823
Short name T1068
Test name
Test status
Simulation time 88930258155 ps
CPU time 22.5 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:42:08 PM PDT 24
Peak memory 200856 kb
Host smart-d0ac06ec-9055-405a-b04f-be172901e003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514056823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1514056823
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2651649157
Short name T18
Test name
Test status
Simulation time 42313367219 ps
CPU time 372.61 seconds
Started Apr 16 02:41:41 PM PDT 24
Finished Apr 16 02:47:55 PM PDT 24
Peak memory 216784 kb
Host smart-c9659035-a1e6-44a7-a2c3-c1f28934cf74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651649157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2651649157
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.569283271
Short name T185
Test name
Test status
Simulation time 98470267356 ps
CPU time 215.79 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:45:21 PM PDT 24
Peak memory 200864 kb
Host smart-ebc487e3-40dd-402a-8596-cbf852aefa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569283271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.569283271
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.904370511
Short name T315
Test name
Test status
Simulation time 35174235153 ps
CPU time 405.42 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:48:31 PM PDT 24
Peak memory 217508 kb
Host smart-302f2bc0-a584-4b8e-873c-8b7888841b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904370511 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.904370511
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2646146080
Short name T197
Test name
Test status
Simulation time 104539026485 ps
CPU time 39.64 seconds
Started Apr 16 02:41:44 PM PDT 24
Finished Apr 16 02:42:24 PM PDT 24
Peak memory 200848 kb
Host smart-a671fcc0-5356-425c-bfe2-64e236c0aedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646146080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2646146080
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2706731876
Short name T841
Test name
Test status
Simulation time 50297483413 ps
CPU time 860.11 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:56:07 PM PDT 24
Peak memory 217500 kb
Host smart-0c8bc868-50f2-4378-ae61-928a49f22a57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706731876 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2706731876
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.724909538
Short name T571
Test name
Test status
Simulation time 8098448501 ps
CPU time 11.99 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:41:59 PM PDT 24
Peak memory 200492 kb
Host smart-a04d37dc-2ef8-4b6c-a3dd-5670ee71294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724909538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.724909538
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2372946733
Short name T1079
Test name
Test status
Simulation time 160796609120 ps
CPU time 222.25 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:45:28 PM PDT 24
Peak memory 217260 kb
Host smart-0e109b23-310a-4297-aa0a-623c9877fb06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372946733 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2372946733
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.434310203
Short name T1150
Test name
Test status
Simulation time 19611531371 ps
CPU time 9.62 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:41:56 PM PDT 24
Peak memory 200728 kb
Host smart-fc1b0f94-1ac1-4981-8093-a29432e11896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434310203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.434310203
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.824273906
Short name T316
Test name
Test status
Simulation time 12142034486 ps
CPU time 148.5 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:44:14 PM PDT 24
Peak memory 217516 kb
Host smart-cfffe375-3766-4281-b592-1bbc2007f28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824273906 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.824273906
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1557794588
Short name T1151
Test name
Test status
Simulation time 111096199286 ps
CPU time 440.39 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:49:03 PM PDT 24
Peak memory 200832 kb
Host smart-f3752eda-65df-475c-8735-5692dc7793c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557794588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1557794588
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4021430682
Short name T223
Test name
Test status
Simulation time 89539452839 ps
CPU time 997.28 seconds
Started Apr 16 02:41:44 PM PDT 24
Finished Apr 16 02:58:22 PM PDT 24
Peak memory 217392 kb
Host smart-4e1cc6b1-c861-43a0-8d1f-a38a1ed0ad5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021430682 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4021430682
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3324497
Short name T1143
Test name
Test status
Simulation time 96434897668 ps
CPU time 84.99 seconds
Started Apr 16 02:41:42 PM PDT 24
Finished Apr 16 02:43:08 PM PDT 24
Peak memory 200896 kb
Host smart-175d34d7-560f-48e5-8a64-5044d4f4ec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3324497
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3851188606
Short name T972
Test name
Test status
Simulation time 1230399760114 ps
CPU time 1002.21 seconds
Started Apr 16 02:41:41 PM PDT 24
Finished Apr 16 02:58:24 PM PDT 24
Peak memory 225660 kb
Host smart-e9dc8813-b36c-42aa-ac3a-6bc49dba4195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851188606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3851188606
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.874243961
Short name T28
Test name
Test status
Simulation time 11416084 ps
CPU time 0.57 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:15 PM PDT 24
Peak memory 196044 kb
Host smart-1a77d1c6-dec9-487d-a3f9-4d7c853bd1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874243961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.874243961
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1868176792
Short name T733
Test name
Test status
Simulation time 50514013125 ps
CPU time 29.3 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:43 PM PDT 24
Peak memory 200800 kb
Host smart-07d3585c-15e5-4d28-931a-0e4b35631e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868176792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1868176792
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2588389249
Short name T146
Test name
Test status
Simulation time 24513064731 ps
CPU time 10.46 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:39:22 PM PDT 24
Peak memory 200828 kb
Host smart-58eeaa5b-13df-42a7-a855-cadeccf16556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588389249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2588389249
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2436622776
Short name T919
Test name
Test status
Simulation time 73498647618 ps
CPU time 145.33 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:41:38 PM PDT 24
Peak memory 200832 kb
Host smart-84089ea2-bc42-4fc1-818e-a552bde143c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436622776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2436622776
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3785940389
Short name T44
Test name
Test status
Simulation time 184025072459 ps
CPU time 530.99 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:48:07 PM PDT 24
Peak memory 200828 kb
Host smart-4b9d9cea-09ca-43e7-87e1-6fc491348624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785940389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3785940389
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2507738283
Short name T1089
Test name
Test status
Simulation time 10191046275 ps
CPU time 23.08 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:39:36 PM PDT 24
Peak memory 200724 kb
Host smart-4c3bfc4d-60d1-4658-8aab-af1faca733f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507738283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2507738283
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3587497450
Short name T347
Test name
Test status
Simulation time 54808129841 ps
CPU time 56.09 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:40:10 PM PDT 24
Peak memory 200056 kb
Host smart-9680768d-b634-42db-9085-57a67719da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587497450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3587497450
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.79453812
Short name T408
Test name
Test status
Simulation time 8536689287 ps
CPU time 524.59 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:48:00 PM PDT 24
Peak memory 200804 kb
Host smart-a0681a6d-ab72-4487-b6a2-07f5ba92dc51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79453812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.79453812
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2733481267
Short name T776
Test name
Test status
Simulation time 6677527828 ps
CPU time 66.85 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:40:19 PM PDT 24
Peak memory 199212 kb
Host smart-94ba9532-64b6-41d0-9332-f26ae202d391
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733481267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2733481267
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1240433877
Short name T369
Test name
Test status
Simulation time 20456556518 ps
CPU time 5.97 seconds
Started Apr 16 02:39:09 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 197892 kb
Host smart-4427428c-03ea-4480-b61c-5d1ac06f6232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240433877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1240433877
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.367230881
Short name T537
Test name
Test status
Simulation time 3385949160 ps
CPU time 1.9 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:18 PM PDT 24
Peak memory 197228 kb
Host smart-aecbc128-52d0-4ee9-bc54-902e14df8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367230881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.367230881
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3848846002
Short name T924
Test name
Test status
Simulation time 6005796798 ps
CPU time 21.57 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:39:34 PM PDT 24
Peak memory 200660 kb
Host smart-3dca0226-ebfc-4200-aed0-5390f6767579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848846002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3848846002
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.4193788241
Short name T666
Test name
Test status
Simulation time 113176139927 ps
CPU time 170.78 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:42:06 PM PDT 24
Peak memory 200880 kb
Host smart-7566e5ff-6c9a-434b-ba02-a90f30b07f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193788241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4193788241
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.563108492
Short name T848
Test name
Test status
Simulation time 12598473137 ps
CPU time 128.26 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:41:19 PM PDT 24
Peak memory 216500 kb
Host smart-ffcf942e-ae61-4084-88dc-25fb19eeea2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563108492 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.563108492
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.602919569
Short name T367
Test name
Test status
Simulation time 1214707960 ps
CPU time 3.76 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:24 PM PDT 24
Peak memory 199128 kb
Host smart-381e8eca-e737-403a-b614-6e6b61ad6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602919569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.602919569
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1605520782
Short name T896
Test name
Test status
Simulation time 6235386356 ps
CPU time 8.47 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 200460 kb
Host smart-8032979a-3607-477a-8a05-e0b4f61cb743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605520782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1605520782
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2062755142
Short name T985
Test name
Test status
Simulation time 13498790266 ps
CPU time 23.4 seconds
Started Apr 16 02:41:49 PM PDT 24
Finished Apr 16 02:42:13 PM PDT 24
Peak memory 200592 kb
Host smart-dee478a0-9cf5-41de-bf7b-0822452f891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062755142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2062755142
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1128328754
Short name T549
Test name
Test status
Simulation time 100873042912 ps
CPU time 849.4 seconds
Started Apr 16 02:41:47 PM PDT 24
Finished Apr 16 02:55:57 PM PDT 24
Peak memory 217524 kb
Host smart-3632fc4c-7996-4076-b698-2a3b16182852
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128328754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1128328754
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2251523790
Short name T921
Test name
Test status
Simulation time 172063735859 ps
CPU time 194.02 seconds
Started Apr 16 02:41:48 PM PDT 24
Finished Apr 16 02:45:03 PM PDT 24
Peak memory 200776 kb
Host smart-49c5afed-688b-421f-89d2-0a70ca58af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251523790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2251523790
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.104736394
Short name T1036
Test name
Test status
Simulation time 131935280585 ps
CPU time 205.93 seconds
Started Apr 16 02:41:47 PM PDT 24
Finished Apr 16 02:45:13 PM PDT 24
Peak memory 200804 kb
Host smart-62780d2d-8a14-4e1b-9c7e-7d05b57e840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104736394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.104736394
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2714819241
Short name T795
Test name
Test status
Simulation time 61811070049 ps
CPU time 196.44 seconds
Started Apr 16 02:41:45 PM PDT 24
Finished Apr 16 02:45:03 PM PDT 24
Peak memory 217468 kb
Host smart-dcd46f65-496f-4240-b2f9-9304ad35f610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714819241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2714819241
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2598495673
Short name T1000
Test name
Test status
Simulation time 57829081100 ps
CPU time 21.37 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:42:08 PM PDT 24
Peak memory 200500 kb
Host smart-c1cc63e1-0c72-48ba-8296-5a453d2da915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598495673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2598495673
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3165476924
Short name T130
Test name
Test status
Simulation time 50344577178 ps
CPU time 663.78 seconds
Started Apr 16 02:41:49 PM PDT 24
Finished Apr 16 02:52:53 PM PDT 24
Peak memory 217300 kb
Host smart-0f6ba005-9a5d-4bf3-bba6-78c119bc234e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165476924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3165476924
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2021803990
Short name T645
Test name
Test status
Simulation time 37971887230 ps
CPU time 63.29 seconds
Started Apr 16 02:41:47 PM PDT 24
Finished Apr 16 02:42:51 PM PDT 24
Peak memory 200740 kb
Host smart-cb6dc88d-f13d-4d59-ad2f-8460780eee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021803990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2021803990
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1288647006
Short name T1081
Test name
Test status
Simulation time 128455001468 ps
CPU time 994.25 seconds
Started Apr 16 02:41:48 PM PDT 24
Finished Apr 16 02:58:23 PM PDT 24
Peak memory 226104 kb
Host smart-7e61f455-426a-4d2e-b4d2-71e943cf5d6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288647006 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1288647006
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.4051787123
Short name T871
Test name
Test status
Simulation time 33226702898 ps
CPU time 611.15 seconds
Started Apr 16 02:41:48 PM PDT 24
Finished Apr 16 02:52:00 PM PDT 24
Peak memory 217256 kb
Host smart-279ba9ab-fa6a-4f65-ac0e-2ecfd87d1ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051787123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.4051787123
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1363993091
Short name T203
Test name
Test status
Simulation time 20968759717 ps
CPU time 18.52 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:42:06 PM PDT 24
Peak memory 200860 kb
Host smart-6a043a86-f96a-4f2e-a49d-2a5565ea8b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363993091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1363993091
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.744653550
Short name T934
Test name
Test status
Simulation time 53426852015 ps
CPU time 552.08 seconds
Started Apr 16 02:41:48 PM PDT 24
Finished Apr 16 02:51:01 PM PDT 24
Peak memory 217516 kb
Host smart-002481cb-3504-470c-a827-387bc80990f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744653550 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.744653550
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.782606491
Short name T976
Test name
Test status
Simulation time 275633677312 ps
CPU time 223.72 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:45:30 PM PDT 24
Peak memory 200904 kb
Host smart-e018c1e9-57e1-4f93-836a-35f5fa4f072a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782606491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.782606491
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1475014057
Short name T1125
Test name
Test status
Simulation time 252830114182 ps
CPU time 1283.77 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 03:03:11 PM PDT 24
Peak memory 228020 kb
Host smart-58413d1c-65de-4417-949e-6f673a661155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475014057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1475014057
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1433094623
Short name T1005
Test name
Test status
Simulation time 221033949700 ps
CPU time 55.09 seconds
Started Apr 16 02:41:47 PM PDT 24
Finished Apr 16 02:42:42 PM PDT 24
Peak memory 200812 kb
Host smart-f001291f-ccd6-4e13-a0a7-8e861257d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433094623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1433094623
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2068285603
Short name T546
Test name
Test status
Simulation time 172471819699 ps
CPU time 653.86 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:52:41 PM PDT 24
Peak memory 217348 kb
Host smart-c742a68f-945b-40b2-ac52-d55c418e844f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068285603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2068285603
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2016251298
Short name T1094
Test name
Test status
Simulation time 14284589984 ps
CPU time 24.21 seconds
Started Apr 16 02:41:46 PM PDT 24
Finished Apr 16 02:42:11 PM PDT 24
Peak memory 200660 kb
Host smart-37f60adc-fc4a-40c2-8afb-19b3b33d8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016251298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2016251298
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.374033293
Short name T812
Test name
Test status
Simulation time 142161182825 ps
CPU time 831.67 seconds
Started Apr 16 02:41:48 PM PDT 24
Finished Apr 16 02:55:41 PM PDT 24
Peak memory 225756 kb
Host smart-c3d280ea-00ab-4e4d-a549-79440ed7a74c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374033293 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.374033293
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2163020432
Short name T1169
Test name
Test status
Simulation time 64108832 ps
CPU time 0.55 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 195164 kb
Host smart-4df0b86a-1bd2-4674-bfd1-6805c83615a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163020432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2163020432
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2073574007
Short name T607
Test name
Test status
Simulation time 36359183884 ps
CPU time 53.88 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:11 PM PDT 24
Peak memory 200904 kb
Host smart-30026339-d5e8-4d52-9e27-5b6f32d59701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073574007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2073574007
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2151404937
Short name T301
Test name
Test status
Simulation time 37759546357 ps
CPU time 14 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:28 PM PDT 24
Peak memory 200576 kb
Host smart-a9f00809-fe3a-41d6-9384-a5c2563e775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151404937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2151404937
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4195548475
Short name T963
Test name
Test status
Simulation time 7214082811 ps
CPU time 16.74 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:30 PM PDT 24
Peak memory 201100 kb
Host smart-87b66c92-95f1-41c3-abaa-9106173b28ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195548475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4195548475
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3212258146
Short name T1119
Test name
Test status
Simulation time 24881552314 ps
CPU time 10.71 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:26 PM PDT 24
Peak memory 198948 kb
Host smart-5865709b-64e4-4a62-9162-f56ba89a8f18
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212258146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3212258146
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.358415905
Short name T777
Test name
Test status
Simulation time 72160506319 ps
CPU time 129.83 seconds
Started Apr 16 02:39:23 PM PDT 24
Finished Apr 16 02:41:35 PM PDT 24
Peak memory 200744 kb
Host smart-583ed317-5eaf-48a3-b8a1-c3a0555eaa4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=358415905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.358415905
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2030622572
Short name T545
Test name
Test status
Simulation time 7011843306 ps
CPU time 8.51 seconds
Started Apr 16 02:39:11 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 199840 kb
Host smart-6fbbdada-ac01-42c8-bbe7-ca9196fb452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030622572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2030622572
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4278747774
Short name T876
Test name
Test status
Simulation time 29876511052 ps
CPU time 52.6 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:10 PM PDT 24
Peak memory 201068 kb
Host smart-48fed807-5f81-4db2-8fef-d5f2e5335cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278747774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4278747774
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2114783394
Short name T1038
Test name
Test status
Simulation time 12847793852 ps
CPU time 241.95 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:43:16 PM PDT 24
Peak memory 201096 kb
Host smart-6cfc61d4-f64a-4ac7-8b3e-4ab93312692e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114783394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2114783394
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.287483600
Short name T334
Test name
Test status
Simulation time 6004196574 ps
CPU time 15.78 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 200088 kb
Host smart-570df666-dfee-40b4-8c8c-64f79521d5b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287483600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.287483600
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1852517216
Short name T866
Test name
Test status
Simulation time 25793606541 ps
CPU time 48.82 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:40:03 PM PDT 24
Peak memory 200872 kb
Host smart-75cbb301-f4e9-4cce-9f49-69aee15fe5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852517216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1852517216
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1677035592
Short name T741
Test name
Test status
Simulation time 38611935838 ps
CPU time 13.33 seconds
Started Apr 16 02:39:12 PM PDT 24
Finished Apr 16 02:39:27 PM PDT 24
Peak memory 196624 kb
Host smart-c9a9124a-9cf3-43e2-aaec-74d5025eded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677035592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1677035592
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.493378841
Short name T581
Test name
Test status
Simulation time 333814828 ps
CPU time 1.05 seconds
Started Apr 16 02:39:13 PM PDT 24
Finished Apr 16 02:39:16 PM PDT 24
Peak memory 199360 kb
Host smart-f8ebb51f-6343-42b4-8c64-5950aa241978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493378841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.493378841
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2306905071
Short name T1096
Test name
Test status
Simulation time 81087909441 ps
CPU time 110.02 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:41:08 PM PDT 24
Peak memory 200832 kb
Host smart-a4002d9b-43a1-4f02-b7dd-1feec09d7e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306905071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2306905071
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2876641903
Short name T56
Test name
Test status
Simulation time 355003185107 ps
CPU time 585.25 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:49:03 PM PDT 24
Peak memory 225752 kb
Host smart-fef9f871-aa7d-4432-9805-665c234f3ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876641903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2876641903
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3888571570
Short name T881
Test name
Test status
Simulation time 11501701265 ps
CPU time 2.28 seconds
Started Apr 16 02:39:10 PM PDT 24
Finished Apr 16 02:39:14 PM PDT 24
Peak memory 200128 kb
Host smart-0d8e5955-137b-47f1-b2cc-f436fd715b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888571570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3888571570
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.188829478
Short name T851
Test name
Test status
Simulation time 327170127152 ps
CPU time 59.53 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:17 PM PDT 24
Peak memory 200824 kb
Host smart-898f5ac5-58ab-44c1-9613-2a6d0cd378c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188829478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.188829478
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3644070072
Short name T206
Test name
Test status
Simulation time 12665732436 ps
CPU time 20.3 seconds
Started Apr 16 02:41:49 PM PDT 24
Finished Apr 16 02:42:10 PM PDT 24
Peak memory 200788 kb
Host smart-465611e3-1766-43d0-a684-62ba25628f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644070072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3644070072
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4089187063
Short name T567
Test name
Test status
Simulation time 40667315120 ps
CPU time 411.17 seconds
Started Apr 16 02:41:50 PM PDT 24
Finished Apr 16 02:48:42 PM PDT 24
Peak memory 217532 kb
Host smart-0c72d9b6-4a32-4e11-806a-22ea86259582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089187063 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4089187063
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2416310783
Short name T1152
Test name
Test status
Simulation time 29261923766 ps
CPU time 61.28 seconds
Started Apr 16 02:41:51 PM PDT 24
Finished Apr 16 02:42:52 PM PDT 24
Peak memory 200920 kb
Host smart-3b8e040f-5da1-46f9-8efa-1c2245bc1564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416310783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2416310783
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3510234159
Short name T519
Test name
Test status
Simulation time 67793564870 ps
CPU time 448.98 seconds
Started Apr 16 02:41:50 PM PDT 24
Finished Apr 16 02:49:20 PM PDT 24
Peak memory 226552 kb
Host smart-9a9471d1-f97a-42f2-a361-d315fee4afad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510234159 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3510234159
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.777254903
Short name T774
Test name
Test status
Simulation time 130198630147 ps
CPU time 175.51 seconds
Started Apr 16 02:41:50 PM PDT 24
Finished Apr 16 02:44:46 PM PDT 24
Peak memory 200816 kb
Host smart-65d10930-ba3f-48f6-96d9-37266b5d0273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777254903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.777254903
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3590147857
Short name T299
Test name
Test status
Simulation time 18780556992 ps
CPU time 202.2 seconds
Started Apr 16 02:41:52 PM PDT 24
Finished Apr 16 02:45:14 PM PDT 24
Peak memory 217584 kb
Host smart-4e19cd00-57dd-468c-bea6-a56cb5d624fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590147857 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3590147857
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.896130655
Short name T475
Test name
Test status
Simulation time 11933161196 ps
CPU time 26.6 seconds
Started Apr 16 02:41:51 PM PDT 24
Finished Apr 16 02:42:18 PM PDT 24
Peak memory 200816 kb
Host smart-2e13e7c8-446c-447b-b003-7a235ec08e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896130655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.896130655
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3512292835
Short name T59
Test name
Test status
Simulation time 81887656565 ps
CPU time 910.68 seconds
Started Apr 16 02:41:53 PM PDT 24
Finished Apr 16 02:57:05 PM PDT 24
Peak memory 216680 kb
Host smart-6f3ba09f-bfeb-4cdd-aedf-e16829eb6f0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512292835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3512292835
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1194833361
Short name T207
Test name
Test status
Simulation time 21496585872 ps
CPU time 41.29 seconds
Started Apr 16 02:41:52 PM PDT 24
Finished Apr 16 02:42:34 PM PDT 24
Peak memory 200884 kb
Host smart-7c29dd7c-f86a-4f54-aa6e-490e97437ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194833361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1194833361
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.360018730
Short name T234
Test name
Test status
Simulation time 258315285821 ps
CPU time 1281.99 seconds
Started Apr 16 02:41:52 PM PDT 24
Finished Apr 16 03:03:15 PM PDT 24
Peak memory 233688 kb
Host smart-40872c87-ad8f-4c44-b3b2-4201c59b0de1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360018730 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.360018730
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3223114751
Short name T381
Test name
Test status
Simulation time 40101487080 ps
CPU time 67.57 seconds
Started Apr 16 02:41:56 PM PDT 24
Finished Apr 16 02:43:04 PM PDT 24
Peak memory 200876 kb
Host smart-f7afe5ce-decc-4678-a015-92613726314a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223114751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3223114751
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2539262799
Short name T1043
Test name
Test status
Simulation time 344664097715 ps
CPU time 572.48 seconds
Started Apr 16 02:41:55 PM PDT 24
Finished Apr 16 02:51:28 PM PDT 24
Peak memory 225772 kb
Host smart-3ea1c424-bd78-4255-9a07-f8d3f6e03442
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539262799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2539262799
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3597714494
Short name T829
Test name
Test status
Simulation time 27851403252 ps
CPU time 347.29 seconds
Started Apr 16 02:41:56 PM PDT 24
Finished Apr 16 02:47:44 PM PDT 24
Peak memory 217296 kb
Host smart-4d2b87a1-fe9a-4427-a246-2d1b0891a42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597714494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3597714494
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2128696382
Short name T145
Test name
Test status
Simulation time 23390009084 ps
CPU time 38.06 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:42:39 PM PDT 24
Peak memory 200628 kb
Host smart-b71f9519-0138-4179-bf5f-971fecc683fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128696382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2128696382
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2824498781
Short name T390
Test name
Test status
Simulation time 70214947896 ps
CPU time 1100.53 seconds
Started Apr 16 02:41:55 PM PDT 24
Finished Apr 16 03:00:16 PM PDT 24
Peak memory 225752 kb
Host smart-f4b96c54-f74a-4745-91b4-619e282ab8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824498781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2824498781
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.910878666
Short name T507
Test name
Test status
Simulation time 64303752602 ps
CPU time 99.93 seconds
Started Apr 16 02:41:56 PM PDT 24
Finished Apr 16 02:43:37 PM PDT 24
Peak memory 200848 kb
Host smart-924d0e15-7516-4209-b19c-3d9636bd03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910878666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.910878666
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1843794499
Short name T113
Test name
Test status
Simulation time 15012998863 ps
CPU time 136.18 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:44:17 PM PDT 24
Peak memory 210500 kb
Host smart-942e57b2-0edb-4882-af8c-e9535ef65c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843794499 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1843794499
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2940916345
Short name T524
Test name
Test status
Simulation time 21685902772 ps
CPU time 34.08 seconds
Started Apr 16 02:41:56 PM PDT 24
Finished Apr 16 02:42:30 PM PDT 24
Peak memory 200824 kb
Host smart-4dae2769-2b9b-41a9-aae4-3d774edb47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940916345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2940916345
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.117356258
Short name T1105
Test name
Test status
Simulation time 12507794266 ps
CPU time 122.55 seconds
Started Apr 16 02:41:55 PM PDT 24
Finished Apr 16 02:43:59 PM PDT 24
Peak memory 210436 kb
Host smart-38e17212-5e40-4ca8-a3ce-f2ff0fbe786d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117356258 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.117356258
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3560027343
Short name T853
Test name
Test status
Simulation time 39218676 ps
CPU time 0.57 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 196220 kb
Host smart-5678557a-0409-4efa-a21b-283c440aef0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560027343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3560027343
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2989615426
Short name T297
Test name
Test status
Simulation time 12828083239 ps
CPU time 23.17 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 200868 kb
Host smart-0e6a358d-6207-405d-a2ea-31f15dbc5326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989615426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2989615426
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2712195893
Short name T476
Test name
Test status
Simulation time 29513406526 ps
CPU time 63.72 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:40:20 PM PDT 24
Peak memory 200620 kb
Host smart-2c8b55bc-5ef0-4a64-a7e5-dbca3f391418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712195893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2712195893
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.4137671163
Short name T770
Test name
Test status
Simulation time 144505799197 ps
CPU time 266.25 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:43:44 PM PDT 24
Peak memory 200860 kb
Host smart-03f05066-7c3a-4eb0-8f0b-da29e9fb5398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137671163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4137671163
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.1971489538
Short name T451
Test name
Test status
Simulation time 228673039107 ps
CPU time 214.84 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:42:51 PM PDT 24
Peak memory 200752 kb
Host smart-ffa24419-ac19-499c-bd50-d17b8335504f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971489538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1971489538
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.4043626477
Short name T434
Test name
Test status
Simulation time 8448304057 ps
CPU time 23.36 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:45 PM PDT 24
Peak memory 200512 kb
Host smart-c4a3d90b-fc92-409c-836f-146b3c3d8180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043626477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4043626477
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2000284994
Short name T751
Test name
Test status
Simulation time 58294830568 ps
CPU time 35.55 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:39:57 PM PDT 24
Peak memory 199752 kb
Host smart-42085794-1975-4a6f-9c2a-a9657112b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000284994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2000284994
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2670567754
Short name T931
Test name
Test status
Simulation time 30304357550 ps
CPU time 133.49 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:41:33 PM PDT 24
Peak memory 200840 kb
Host smart-5d469908-0488-4ccf-a2c2-f796cab953d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2670567754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2670567754
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2827950216
Short name T20
Test name
Test status
Simulation time 6078012060 ps
CPU time 19.22 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:39 PM PDT 24
Peak memory 199904 kb
Host smart-e243e174-39d3-4624-bf83-06cddc542a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827950216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2827950216
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.404474400
Short name T698
Test name
Test status
Simulation time 88783443636 ps
CPU time 21.53 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:40 PM PDT 24
Peak memory 200856 kb
Host smart-cd9201ab-ff6a-4859-a42d-628481235152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404474400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.404474400
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3553650757
Short name T987
Test name
Test status
Simulation time 5761671000 ps
CPU time 2.55 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:22 PM PDT 24
Peak memory 196940 kb
Host smart-4a5704c9-fe2a-4391-885e-765b7783ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553650757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3553650757
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.283841917
Short name T703
Test name
Test status
Simulation time 738676580 ps
CPU time 2.62 seconds
Started Apr 16 02:39:15 PM PDT 24
Finished Apr 16 02:39:20 PM PDT 24
Peak memory 199520 kb
Host smart-cca70bcf-2ea5-4801-b7ce-65521d0ba22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283841917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.283841917
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3395015843
Short name T811
Test name
Test status
Simulation time 550751386127 ps
CPU time 718.29 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:51:14 PM PDT 24
Peak memory 200768 kb
Host smart-4e9b8b68-bbe2-4311-a79d-64591304fb06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395015843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3395015843
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.70055185
Short name T1074
Test name
Test status
Simulation time 38131845967 ps
CPU time 300.82 seconds
Started Apr 16 02:39:16 PM PDT 24
Finished Apr 16 02:44:19 PM PDT 24
Peak memory 217372 kb
Host smart-097f6b36-a87e-4556-9893-b494bed62204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70055185 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.70055185
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.562267260
Short name T959
Test name
Test status
Simulation time 2567378459 ps
CPU time 1.87 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 199468 kb
Host smart-e340548d-d1ea-45db-81a5-ef015e884edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562267260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.562267260
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3492159018
Short name T363
Test name
Test status
Simulation time 38891622103 ps
CPU time 15.78 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:39:36 PM PDT 24
Peak memory 197968 kb
Host smart-eb05ff41-d2eb-4752-9d04-c53c3644a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492159018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3492159018
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2156942877
Short name T1154
Test name
Test status
Simulation time 141564894273 ps
CPU time 115.2 seconds
Started Apr 16 02:41:53 PM PDT 24
Finished Apr 16 02:43:49 PM PDT 24
Peak memory 200732 kb
Host smart-b5f66e7f-4b33-4b85-8f86-817ceb8d3a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156942877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2156942877
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.989623696
Short name T997
Test name
Test status
Simulation time 31778066165 ps
CPU time 161.13 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:44:39 PM PDT 24
Peak memory 209132 kb
Host smart-e7ca7e9d-0fd8-444c-a352-cd68bd50aaba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989623696 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.989623696
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1138520869
Short name T1104
Test name
Test status
Simulation time 57354223635 ps
CPU time 81.74 seconds
Started Apr 16 02:41:58 PM PDT 24
Finished Apr 16 02:43:20 PM PDT 24
Peak memory 200896 kb
Host smart-7591d5c6-3d4f-4827-8fd3-8b9b947b2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138520869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1138520869
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.737941754
Short name T746
Test name
Test status
Simulation time 53379969941 ps
CPU time 764.18 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:54:42 PM PDT 24
Peak memory 229784 kb
Host smart-e8999229-b609-4084-9c37-b71ec295ddd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737941754 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.737941754
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2610763500
Short name T573
Test name
Test status
Simulation time 26244207865 ps
CPU time 18.45 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:42:16 PM PDT 24
Peak memory 200908 kb
Host smart-41cb7b0b-fc9a-432a-aef6-02f5725a9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610763500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2610763500
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1497186149
Short name T859
Test name
Test status
Simulation time 78321368863 ps
CPU time 125.45 seconds
Started Apr 16 02:41:56 PM PDT 24
Finished Apr 16 02:44:02 PM PDT 24
Peak memory 200888 kb
Host smart-c2ffd5f4-2dac-40ff-9802-cc7d6d636ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497186149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1497186149
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2118855176
Short name T943
Test name
Test status
Simulation time 212498079037 ps
CPU time 113.42 seconds
Started Apr 16 02:41:57 PM PDT 24
Finished Apr 16 02:43:52 PM PDT 24
Peak memory 217460 kb
Host smart-7059238b-bde4-4129-819b-bd92d0fb3568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118855176 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2118855176
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3234158882
Short name T247
Test name
Test status
Simulation time 238054179074 ps
CPU time 51.24 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:42:52 PM PDT 24
Peak memory 200796 kb
Host smart-ad04705d-f6c4-4449-a6eb-682d53f07ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234158882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3234158882
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2890619315
Short name T209
Test name
Test status
Simulation time 204687965027 ps
CPU time 1026.06 seconds
Started Apr 16 02:41:59 PM PDT 24
Finished Apr 16 02:59:06 PM PDT 24
Peak memory 227456 kb
Host smart-fcca9e49-b547-4463-a397-7bb785c72e7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890619315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2890619315
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1292649205
Short name T331
Test name
Test status
Simulation time 122391299597 ps
CPU time 196.55 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:45:18 PM PDT 24
Peak memory 200904 kb
Host smart-79d04464-018d-4e94-9c20-2781884af50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292649205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1292649205
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3843929466
Short name T62
Test name
Test status
Simulation time 73669873073 ps
CPU time 785.59 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:55:06 PM PDT 24
Peak memory 217348 kb
Host smart-54fb6f0d-9e35-4755-94cb-50ffa5f46f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843929466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3843929466
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.291653753
Short name T1046
Test name
Test status
Simulation time 98399122794 ps
CPU time 46.47 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:42:47 PM PDT 24
Peak memory 200880 kb
Host smart-2253fc44-6093-44ec-beee-8c482460ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291653753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.291653753
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2267360661
Short name T114
Test name
Test status
Simulation time 28006351687 ps
CPU time 314.17 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:47:16 PM PDT 24
Peak memory 217536 kb
Host smart-8526b9c4-d632-4a93-9e11-989ab2291a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267360661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2267360661
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3435037117
Short name T623
Test name
Test status
Simulation time 72333709009 ps
CPU time 7.05 seconds
Started Apr 16 02:42:02 PM PDT 24
Finished Apr 16 02:42:10 PM PDT 24
Peak memory 199668 kb
Host smart-38cf807c-6be7-46de-8a41-a5cf89dd480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435037117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3435037117
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.659617146
Short name T15
Test name
Test status
Simulation time 35909234540 ps
CPU time 248.28 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:46:10 PM PDT 24
Peak memory 217340 kb
Host smart-cc21635a-d283-4494-881b-e3d5c83ca9ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659617146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.659617146
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.97401610
Short name T723
Test name
Test status
Simulation time 242153172473 ps
CPU time 90.75 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:43:32 PM PDT 24
Peak memory 200804 kb
Host smart-0a4f3001-0b7b-4272-9250-24935970957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97401610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.97401610
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.7013409
Short name T979
Test name
Test status
Simulation time 77562930501 ps
CPU time 672 seconds
Started Apr 16 02:42:00 PM PDT 24
Finished Apr 16 02:53:13 PM PDT 24
Peak memory 217556 kb
Host smart-c4b24d41-dd82-4877-910d-b5993461c17c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7013409 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.7013409
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.4200012590
Short name T1027
Test name
Test status
Simulation time 70527610046 ps
CPU time 55.98 seconds
Started Apr 16 02:42:01 PM PDT 24
Finished Apr 16 02:42:58 PM PDT 24
Peak memory 200952 kb
Host smart-453d568f-c917-4db7-a0c4-8ef445c6ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200012590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4200012590
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2922870972
Short name T190
Test name
Test status
Simulation time 282513887027 ps
CPU time 1149.89 seconds
Started Apr 16 02:42:02 PM PDT 24
Finished Apr 16 03:01:13 PM PDT 24
Peak memory 233820 kb
Host smart-e3a1fb14-69fa-4b07-8516-08b50901a850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922870972 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2922870972
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.420720490
Short name T750
Test name
Test status
Simulation time 145586093 ps
CPU time 0.57 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:25 PM PDT 24
Peak memory 196216 kb
Host smart-b4579e24-9128-46c8-b921-78607379ea81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420720490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.420720490
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3707708476
Short name T440
Test name
Test status
Simulation time 141078654885 ps
CPU time 47.49 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:40:07 PM PDT 24
Peak memory 200888 kb
Host smart-78b5ef10-9859-4d8d-a106-f0348a87af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707708476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3707708476
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1557445398
Short name T691
Test name
Test status
Simulation time 174635056085 ps
CPU time 70.01 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:40:29 PM PDT 24
Peak memory 200900 kb
Host smart-b85670b7-1eee-44db-bced-0bf025f4fcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557445398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1557445398
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2962653727
Short name T611
Test name
Test status
Simulation time 15774056629 ps
CPU time 30.15 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:50 PM PDT 24
Peak memory 200824 kb
Host smart-0f9b7b03-4a4d-44c6-b20b-b63af601b323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962653727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2962653727
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2431099647
Short name T1092
Test name
Test status
Simulation time 63704289616 ps
CPU time 111.9 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:41:11 PM PDT 24
Peak memory 200864 kb
Host smart-91356ec0-0fa1-414d-99db-82eb10606917
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431099647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2431099647
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1074064943
Short name T1007
Test name
Test status
Simulation time 45934198444 ps
CPU time 369.09 seconds
Started Apr 16 02:39:18 PM PDT 24
Finished Apr 16 02:45:29 PM PDT 24
Peak memory 200936 kb
Host smart-fc5c5785-9e1b-47ed-b7ec-2748433202fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074064943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1074064943
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1842867094
Short name T1060
Test name
Test status
Simulation time 7428263813 ps
CPU time 8.12 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:39:31 PM PDT 24
Peak memory 199332 kb
Host smart-b8c48804-4ba7-47a9-a1cb-91be1d1235c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842867094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1842867094
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1322596086
Short name T619
Test name
Test status
Simulation time 31980156439 ps
CPU time 61.72 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:40:23 PM PDT 24
Peak memory 209276 kb
Host smart-0f4da887-9311-4d54-a7be-a961db5b5476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322596086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1322596086
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.4235279948
Short name T341
Test name
Test status
Simulation time 10789918646 ps
CPU time 169.91 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:42:14 PM PDT 24
Peak memory 200876 kb
Host smart-0a5feed8-9516-471e-a029-f3a27640cc10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235279948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4235279948
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3356986033
Short name T16
Test name
Test status
Simulation time 6315663418 ps
CPU time 56.46 seconds
Started Apr 16 02:39:19 PM PDT 24
Finished Apr 16 02:40:18 PM PDT 24
Peak memory 198708 kb
Host smart-9b233928-af81-4af0-ae1d-532eaabcdde8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356986033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3356986033
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3366933981
Short name T583
Test name
Test status
Simulation time 19161219830 ps
CPU time 31.39 seconds
Started Apr 16 02:39:22 PM PDT 24
Finished Apr 16 02:39:56 PM PDT 24
Peak memory 200688 kb
Host smart-a3c75e25-a16b-40f2-af92-a4944d2a17f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366933981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3366933981
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1791900005
Short name T626
Test name
Test status
Simulation time 6289159259 ps
CPU time 5.85 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:39:29 PM PDT 24
Peak memory 196964 kb
Host smart-9e02c366-48ad-4ba3-8747-6413e134c765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791900005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1791900005
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4129278353
Short name T252
Test name
Test status
Simulation time 6082126035 ps
CPU time 6.73 seconds
Started Apr 16 02:39:14 PM PDT 24
Finished Apr 16 02:39:22 PM PDT 24
Peak memory 200816 kb
Host smart-95daa2bf-a8b1-45ad-965d-c93358b3af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129278353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4129278353
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4189832016
Short name T731
Test name
Test status
Simulation time 359922061403 ps
CPU time 406.65 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:46:06 PM PDT 24
Peak memory 200896 kb
Host smart-30e52e1d-c0ea-40c4-be6e-07f231607590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189832016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4189832016
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3679692355
Short name T61
Test name
Test status
Simulation time 123481212729 ps
CPU time 714.79 seconds
Started Apr 16 02:39:20 PM PDT 24
Finished Apr 16 02:51:17 PM PDT 24
Peak memory 216824 kb
Host smart-0ef4c2e2-d32e-4980-b5b6-4328802124c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679692355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3679692355
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4243171099
Short name T1177
Test name
Test status
Simulation time 3743291948 ps
CPU time 1.73 seconds
Started Apr 16 02:39:17 PM PDT 24
Finished Apr 16 02:39:21 PM PDT 24
Peak memory 199960 kb
Host smart-e194356a-f941-4ae2-bb9e-77528063f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243171099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4243171099
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1696432161
Short name T5
Test name
Test status
Simulation time 22557121998 ps
CPU time 46.8 seconds
Started Apr 16 02:39:21 PM PDT 24
Finished Apr 16 02:40:10 PM PDT 24
Peak memory 200836 kb
Host smart-9210ab41-665a-4ed3-ade8-f2ac1cd016ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696432161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1696432161
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1151774388
Short name T240
Test name
Test status
Simulation time 67915907706 ps
CPU time 62.7 seconds
Started Apr 16 02:42:03 PM PDT 24
Finished Apr 16 02:43:06 PM PDT 24
Peak memory 200832 kb
Host smart-659b3ede-1659-4bfd-a1b5-13d00e8b1092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151774388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1151774388
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2904504597
Short name T1161
Test name
Test status
Simulation time 73831897218 ps
CPU time 54.94 seconds
Started Apr 16 02:41:59 PM PDT 24
Finished Apr 16 02:42:54 PM PDT 24
Peak memory 200844 kb
Host smart-5455ba74-d99e-435f-8538-c6a345dc254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904504597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2904504597
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.967921277
Short name T58
Test name
Test status
Simulation time 148041405033 ps
CPU time 578.7 seconds
Started Apr 16 02:42:06 PM PDT 24
Finished Apr 16 02:51:45 PM PDT 24
Peak memory 229468 kb
Host smart-92f0bf8d-7888-41a9-a0da-5c36b824628d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967921277 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.967921277
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4023234950
Short name T1136
Test name
Test status
Simulation time 155294824668 ps
CPU time 163.56 seconds
Started Apr 16 02:42:07 PM PDT 24
Finished Apr 16 02:44:51 PM PDT 24
Peak memory 200944 kb
Host smart-3f762b68-1421-4b39-a6ed-5511c3d47e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023234950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4023234950
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3507999863
Short name T1166
Test name
Test status
Simulation time 85531338652 ps
CPU time 546.73 seconds
Started Apr 16 02:42:04 PM PDT 24
Finished Apr 16 02:51:11 PM PDT 24
Peak memory 220564 kb
Host smart-d37ecd46-c097-483a-abfa-dd9e3d0c133f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507999863 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3507999863
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2089037693
Short name T120
Test name
Test status
Simulation time 58800543254 ps
CPU time 44.18 seconds
Started Apr 16 02:42:06 PM PDT 24
Finished Apr 16 02:42:51 PM PDT 24
Peak memory 200860 kb
Host smart-007be0f6-789b-49f0-9239-a2993e260208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089037693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2089037693
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3888469125
Short name T763
Test name
Test status
Simulation time 237048180273 ps
CPU time 105.43 seconds
Started Apr 16 02:42:07 PM PDT 24
Finished Apr 16 02:43:53 PM PDT 24
Peak memory 200852 kb
Host smart-df578938-8b73-4711-8608-34b9c0c4d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888469125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3888469125
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2232681001
Short name T1099
Test name
Test status
Simulation time 52347866916 ps
CPU time 550.39 seconds
Started Apr 16 02:42:06 PM PDT 24
Finished Apr 16 02:51:17 PM PDT 24
Peak memory 217540 kb
Host smart-0010ed16-1dc3-4045-9bbe-0481a050a9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232681001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2232681001
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1469686066
Short name T748
Test name
Test status
Simulation time 172619227277 ps
CPU time 160.9 seconds
Started Apr 16 02:42:04 PM PDT 24
Finished Apr 16 02:44:46 PM PDT 24
Peak memory 200888 kb
Host smart-c8e2027d-5027-48b7-88e4-9609c2f84339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469686066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1469686066
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2577046934
Short name T149
Test name
Test status
Simulation time 111091115835 ps
CPU time 2055.53 seconds
Started Apr 16 02:42:06 PM PDT 24
Finished Apr 16 03:16:22 PM PDT 24
Peak memory 217264 kb
Host smart-da0f5666-956f-4e8f-8bc9-0a621b89a357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577046934 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2577046934
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3123324783
Short name T263
Test name
Test status
Simulation time 348429760153 ps
CPU time 52.1 seconds
Started Apr 16 02:42:04 PM PDT 24
Finished Apr 16 02:42:57 PM PDT 24
Peak memory 200868 kb
Host smart-12287538-d1ea-4ec9-ac4f-433cc550ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123324783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3123324783
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3138508780
Short name T518
Test name
Test status
Simulation time 192229586400 ps
CPU time 336.93 seconds
Started Apr 16 02:42:05 PM PDT 24
Finished Apr 16 02:47:42 PM PDT 24
Peak memory 216144 kb
Host smart-ae143c7e-8d1a-45a2-8975-4fb181120c4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138508780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3138508780
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1595331624
Short name T872
Test name
Test status
Simulation time 18111087050 ps
CPU time 38.84 seconds
Started Apr 16 02:42:05 PM PDT 24
Finished Apr 16 02:42:44 PM PDT 24
Peak memory 200916 kb
Host smart-0576313c-ba48-47cd-8019-1d0f50e5511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595331624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1595331624
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2611464466
Short name T739
Test name
Test status
Simulation time 276046472809 ps
CPU time 707 seconds
Started Apr 16 02:42:08 PM PDT 24
Finished Apr 16 02:53:56 PM PDT 24
Peak memory 225772 kb
Host smart-6236281b-d175-4009-a215-93236025c1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611464466 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2611464466
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3657190153
Short name T575
Test name
Test status
Simulation time 116773538107 ps
CPU time 160.36 seconds
Started Apr 16 02:42:03 PM PDT 24
Finished Apr 16 02:44:44 PM PDT 24
Peak memory 200872 kb
Host smart-8fd48223-a469-49ec-b32a-569e20804a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657190153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3657190153
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2390155041
Short name T648
Test name
Test status
Simulation time 15778776373 ps
CPU time 134.84 seconds
Started Apr 16 02:42:08 PM PDT 24
Finished Apr 16 02:44:23 PM PDT 24
Peak memory 216868 kb
Host smart-f6cc03d8-ab1c-46c2-96fc-626fbb7ce871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390155041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2390155041
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.984139471
Short name T838
Test name
Test status
Simulation time 111039396874 ps
CPU time 204.72 seconds
Started Apr 16 02:42:05 PM PDT 24
Finished Apr 16 02:45:31 PM PDT 24
Peak memory 200816 kb
Host smart-c851e8ba-db0d-4c36-87c6-2959054e5841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984139471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.984139471
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1501973279
Short name T242
Test name
Test status
Simulation time 45184142550 ps
CPU time 274.81 seconds
Started Apr 16 02:42:08 PM PDT 24
Finished Apr 16 02:46:43 PM PDT 24
Peak memory 217500 kb
Host smart-1abe6fff-8997-4770-9c9a-22ac70694da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501973279 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1501973279
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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