Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	117277	1			T1	49		T2	2		T3	27
all_values[1]	117277	1			T1	49		T2	2		T3	27
all_values[2]	117277	1			T1	49		T2	2		T3	27
all_values[3]	117277	1			T1	49		T2	2		T3	27
all_values[4]	117277	1			T1	49		T2	2		T3	27
all_values[5]	117277	1			T1	49		T2	2		T3	27
all_values[6]	117277	1			T1	49		T2	2		T3	27
all_values[7]	117277	1			T1	49		T2	2		T3	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

465796

1

T1

195

T2

16

T3

158

auto[1]

472420

1

T1

197

T3

58

T4

142

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879162

1

T1

345

T2

13

T3

185

auto[1]

59054

1

T1

47

T2

3

T3

31

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34847	1			T1	8		T5	15		T6	1
all_values[0]	auto[0]	auto[1]	23303	1			T1	22		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	35893	1			T1	11		T4	3		T5	12
all_values[0]	auto[1]	auto[1]	23234	1			T1	8		T3	25		T4	17
all_values[1]	auto[0]	auto[0]	56521	1			T1	23		T2	2		T3	26
all_values[1]	auto[0]	auto[1]	1769	1			T1	1		T6	3		T8	1
all_values[1]	auto[1]	auto[0]	57136	1			T1	25		T3	1		T4	41
all_values[1]	auto[1]	auto[1]	1851	1			T11	18		T12	10		T37	2
all_values[2]	auto[0]	auto[0]	53629	1			T1	19		T2	1		T3	23
all_values[2]	auto[0]	auto[1]	2854	1			T1	6		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	58102	1			T1	14		T5	37		T6	13
all_values[2]	auto[1]	auto[1]	2692	1			T1	10		T3	1		T5	10
all_values[3]	auto[0]	auto[0]	56442	1			T1	33		T2	2		T3	26
all_values[3]	auto[0]	auto[1]	364	1			T12	1		T106	4		T53	2
all_values[3]	auto[1]	auto[0]	60104	1			T1	16		T3	1		T5	35
all_values[3]	auto[1]	auto[1]	367	1			T5	2		T11	1		T12	1
all_values[4]	auto[0]	auto[0]	59968	1			T1	20		T2	2		T4	21
all_values[4]	auto[0]	auto[1]	540	1			T13	13		T12	6		T106	1
all_values[4]	auto[1]	auto[0]	56213	1			T1	29		T3	27		T4	13
all_values[4]	auto[1]	auto[1]	556	1			T4	7		T30	6		T72	1
all_values[5]	auto[0]	auto[0]	61418	1			T1	17		T2	2		T3	27
all_values[5]	auto[0]	auto[1]	197	1			T16	1		T29	6		T72	3
all_values[5]	auto[1]	auto[0]	55490	1			T1	32		T4	20		T5	6
all_values[5]	auto[1]	auto[1]	172	1			T72	3		T111	4		T112	3
all_values[6]	auto[0]	auto[0]	56043	1			T1	23		T2	2		T3	26
all_values[6]	auto[0]	auto[1]	209	1			T16	2		T29	1		T73	1
all_values[6]	auto[1]	auto[0]	60845	1			T1	26		T3	1		T4	41
all_values[6]	auto[1]	auto[1]	180	1			T16	1		T29	1		T72	1
all_values[7]	auto[0]	auto[0]	57328	1			T1	23		T2	2		T3	25
all_values[7]	auto[0]	auto[1]	364	1			T13	14		T122	2		T73	2
all_values[7]	auto[1]	auto[0]	59183	1			T1	26		T3	2		T5	37
all_values[7]	auto[1]	auto[1]	402	1			T13	1		T12	4		T14	1