Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2360	1			T1	5		T2	1		T3	1
auto[BaudRate115200]	2057	1			T1	6		T5	18		T6	3
auto[BaudRate230400]	1935	1			T1	9		T4	1		T5	7
auto[BaudRate128Kbps]	2079	1			T1	5		T3	1		T5	17
auto[BaudRate256Kbps]	2233	1			T1	4		T3	3		T5	12
auto[BaudRate1Mbps]	1985	1			T1	4		T3	4		T6	1
auto[BaudRate1p5Mbps]	1416	1			T2	1		T6	3		T8	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1428	1			T11	22		T32	9		T116	9
freqs[25]	1155	1			T31	2		T35	7		T14	10
freqs[48]	617	1			T6	19		T17	15		T51	2
freqs[50]	450	1			T318	42		T319	54		T320	8
freqs[100]	1409	1			T37	8		T16	59		T132	6

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	225	1			T11	5		T32	1		T116	1
auto[BaudRate9600]	freqs[25]	203	1			T35	2		T14	3		T253	2
auto[BaudRate9600]	freqs[48]	118	1			T6	2		T17	15		T118	3
auto[BaudRate9600]	freqs[50]	71	1			T318	6		T319	3		T320	8
auto[BaudRate9600]	freqs[100]	211	1			T16	7		T132	1		T276	1
auto[BaudRate115200]	freqs[24]	196	1			T11	1		T32	2		T116	4
auto[BaudRate115200]	freqs[25]	182	1			T14	1		T253	1		T117	1
auto[BaudRate115200]	freqs[48]	69	1			T6	3		T51	1		T29	15
auto[BaudRate115200]	freqs[50]	92	1			T318	15		T319	12		T137	2
auto[BaudRate115200]	freqs[100]	204	1			T16	12		T132	2		T113	1
auto[BaudRate230400]	freqs[24]	209	1			T32	2		T116	1		T19	10
auto[BaudRate230400]	freqs[25]	156	1			T35	1		T14	1		T253	1
auto[BaudRate230400]	freqs[48]	70	1			T6	2		T29	13		T145	2
auto[BaudRate230400]	freqs[50]	43	1			T318	3		T319	3		T137	3
auto[BaudRate230400]	freqs[100]	154	1			T16	4		T132	1		T113	3
auto[BaudRate128Kbps]	freqs[24]	207	1			T11	1		T32	1		T116	1
auto[BaudRate128Kbps]	freqs[25]	162	1			T35	1		T14	1		T253	2
auto[BaudRate128Kbps]	freqs[48]	93	1			T6	4		T104	2		T118	1
auto[BaudRate128Kbps]	freqs[50]	57	1			T318	9		T319	6		T137	1
auto[BaudRate128Kbps]	freqs[100]	199	1			T16	7		T113	2		T281	2
auto[BaudRate256Kbps]	freqs[24]	225	1			T11	5		T32	1		T116	1
auto[BaudRate256Kbps]	freqs[25]	179	1			T31	1		T35	1		T253	1
auto[BaudRate256Kbps]	freqs[48]	87	1			T6	4		T104	1		T118	1
auto[BaudRate256Kbps]	freqs[50]	65	1			T318	6		T319	15		T137	1
auto[BaudRate256Kbps]	freqs[100]	188	1			T37	1		T16	6		T321	3
auto[BaudRate1Mbps]	freqs[24]	254	1			T11	5		T32	1		T116	1
auto[BaudRate1Mbps]	freqs[25]	174	1			T35	2		T14	3		T55	2
auto[BaudRate1Mbps]	freqs[48]	98	1			T6	1		T51	1		T104	3
auto[BaudRate1Mbps]	freqs[50]	60	1			T319	6		T137	1		T138	3
auto[BaudRate1Mbps]	freqs[100]	237	1			T37	2		T16	10		T132	1
auto[BaudRate1p5Mbps]	freqs[25]	99	1			T31	1		T14	1		T254	1
auto[BaudRate1p5Mbps]	freqs[48]	82	1			T6	3		T118	1		T29	13
auto[BaudRate1p5Mbps]	freqs[50]	62	1			T318	3		T319	9		T138	2
auto[BaudRate1p5Mbps]	freqs[100]	216	1			T37	5		T16	13		T132	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded