Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	32978146	1			T1	445		T3	31		T4	390
all_levels[1]	209007	1			T1	42		T3	7		T5	1987
all_levels[2]	2510	1			T1	9		T3	3		T6	9
all_levels[3]	1098	1			T1	6		T3	7		T5	1
all_levels[4]	804	1			T1	4		T3	11		T5	1
all_levels[5]	533	1			T1	3		T5	2		T6	2
all_levels[6]	421	1			T1	1		T6	2		T8	1
all_levels[7]	369	1			T1	3		T3	1		T9	1
all_levels[8]	316	1			T1	3		T3	1		T14	1
all_levels[9]	238	1			T1	3		T9	1		T13	1
all_levels[10]	217	1			T1	1		T9	1		T13	1
all_levels[11]	186	1			T3	2		T9	4		T13	1
all_levels[12]	148	1			T3	1		T113	2		T114	1
all_levels[13]	142	1			T115	1		T16	1		T53	1
all_levels[14]	136	1			T9	1		T11	1		T116	1
all_levels[15]	139	1			T9	1		T11	1		T113	2
all_levels[16]	146	1			T3	1		T10	1		T11	1
all_levels[17]	97	1			T8	1		T13	1		T35	1
all_levels[18]	72	1			T9	1		T113	4		T117	1
all_levels[19]	91	1			T10	1		T16	1		T53	1
all_levels[20]	70	1			T1	1		T10	1		T32	1
all_levels[21]	69	1			T35	1		T53	1		T58	1
all_levels[22]	58	1			T35	1		T116	1		T26	1
all_levels[23]	62	1			T9	1		T32	1		T116	1
all_levels[24]	70	1			T32	2		T35	1		T116	1
all_levels[25]	67	1			T3	1		T9	2		T32	1
all_levels[26]	67	1			T9	1		T35	1		T14	1
all_levels[27]	47	1			T1	1		T116	1		T118	1
all_levels[28]	54	1			T35	1		T117	1		T119	1
all_levels[29]	34	1			T116	1		T120	2		T121	1
all_levels[30]	42	1			T18	1		T122	1		T123	1
all_levels[31]	31	1			T26	1		T124	1		T111	1
all_levels[32]	34	1			T125	1		T126	1		T127	1
all_levels[33]	32	1			T128	1		T121	1		T111	1
all_levels[34]	29	1			T18	1		T53	1		T124	1
all_levels[35]	23	1			T10	1		T114	1		T128	1
all_levels[36]	31	1			T129	1		T120	1		T130	1
all_levels[37]	23	1			T53	1		T121	1		T131	1
all_levels[38]	19	1			T132	1		T133	1		T134	1
all_levels[39]	22	1			T121	1		T135	1		T136	1
all_levels[40]	33	1			T1	1		T32	1		T132	1
all_levels[41]	16	1			T117	1		T137	1		T138	1
all_levels[42]	16	1			T113	1		T139	1		T140	1
all_levels[43]	22	1			T141	3		T142	1		T143	2
all_levels[44]	11	1			T138	1		T142	1		T144	1
all_levels[45]	16	1			T34	3		T128	1		T138	1
all_levels[46]	20	1			T1	1		T145	1		T111	2
all_levels[47]	10	1			T146	1		T147	1		T148	1
all_levels[48]	22	1			T149	1		T150	1		T99	1
all_levels[49]	11	1			T151	1		T152	1		T153	1
all_levels[50]	17	1			T154	1		T117	1		T137	2
all_levels[51]	21	1			T115	2		T111	1		T146	1
all_levels[52]	15	1			T121	2		T146	2		T148	1
all_levels[53]	13	1			T111	1		T155	1		T156	1
all_levels[54]	7	1			T157	1		T120	1		T158	1
all_levels[55]	9	1			T144	1		T99	1		T159	1
all_levels[56]	7	1			T120	1		T98	1		T160	1
all_levels[57]	10	1			T161	2		T136	1		T162	1
all_levels[58]	5	1			T11	1		T123	1		T112	1
all_levels[59]	14	1			T126	1		T163	1		T142	1
all_levels[60]	7	1			T163	1		T111	1		T149	2
all_levels[61]	5	1			T164	1		T99	1		T165	1
all_levels[62]	9	1			T166	1		T167	1		T168	1
all_levels[63]	6	1			T11	1		T107	1		T111	1
all_levels[64]	115	1			T5	1		T11	1		T14	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33191167

1

T1

524

T3

58

T4

370

auto[1]

4970

1

T3

8

T4

20

T5

11

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	32973645	1			T1	445		T3	24		T4	370
all_levels[0]	auto[1]	4501	1			T3	7		T4	20		T5	11
all_levels[1]	auto[0]	208925	1			T1	42		T3	7		T5	1987
all_levels[1]	auto[1]	82	1			T169	1		T170	2		T171	1
all_levels[2]	auto[0]	2494	1			T1	9		T3	3		T6	9
all_levels[2]	auto[1]	16	1			T172	1		T173	1		T140	1
all_levels[3]	auto[0]	1079	1			T1	6		T3	7		T5	1
all_levels[3]	auto[1]	19	1			T145	1		T174	1		T97	2
all_levels[4]	auto[0]	768	1			T1	4		T3	11		T5	1
all_levels[4]	auto[1]	36	1			T113	1		T175	1		T137	1
all_levels[5]	auto[0]	524	1			T1	3		T5	2		T6	2
all_levels[5]	auto[1]	9	1			T40	1		T176	1		T177	1
all_levels[6]	auto[0]	414	1			T1	1		T6	2		T8	1
all_levels[6]	auto[1]	7	1			T178	1		T160	1		T179	1
all_levels[7]	auto[0]	351	1			T1	3		T3	1		T9	1
all_levels[7]	auto[1]	18	1			T180	1		T181	4		T182	1
all_levels[8]	auto[0]	306	1			T1	3		T3	1		T14	1
all_levels[8]	auto[1]	10	1			T176	1		T183	3		T184	1
all_levels[9]	auto[0]	219	1			T1	3		T9	1		T13	1
all_levels[9]	auto[1]	19	1			T104	2		T141	1		T142	3
all_levels[10]	auto[0]	197	1			T1	1		T9	1		T13	1
all_levels[10]	auto[1]	20	1			T125	1		T155	2		T149	1
all_levels[11]	auto[0]	175	1			T3	1		T9	2		T13	1
all_levels[11]	auto[1]	11	1			T3	1		T9	2		T150	2
all_levels[12]	auto[0]	135	1			T3	1		T113	2		T114	1
all_levels[12]	auto[1]	13	1			T180	1		T97	1		T185	2
all_levels[13]	auto[0]	135	1			T115	1		T16	1		T53	1
all_levels[13]	auto[1]	7	1			T186	2		T187	3		T188	1
all_levels[14]	auto[0]	124	1			T9	1		T11	1		T116	1
all_levels[14]	auto[1]	12	1			T54	1		T189	1		T190	1
all_levels[15]	auto[0]	128	1			T9	1		T11	1		T113	2
all_levels[15]	auto[1]	11	1			T191	2		T171	1		T192	1
all_levels[16]	auto[0]	134	1			T3	1		T10	1		T11	1
all_levels[16]	auto[1]	12	1			T193	1		T194	2		T195	2
all_levels[17]	auto[0]	91	1			T8	1		T13	1		T35	1
all_levels[17]	auto[1]	6	1			T142	1		T155	2		T196	1
all_levels[18]	auto[0]	68	1			T9	1		T113	4		T117	1
all_levels[18]	auto[1]	4	1			T197	1		T198	2		T199	1
all_levels[19]	auto[0]	76	1			T10	1		T16	1		T53	1
all_levels[19]	auto[1]	15	1			T114	2		T120	2		T200	4
all_levels[20]	auto[0]	67	1			T1	1		T10	1		T32	1
all_levels[20]	auto[1]	3	1			T201	2		T202	1		-	-
all_levels[21]	auto[0]	67	1			T35	1		T53	1		T58	1
all_levels[21]	auto[1]	2	1			T195	1		T203	1		-	-
all_levels[22]	auto[0]	54	1			T35	1		T116	1		T26	1
all_levels[22]	auto[1]	4	1			T134	1		T204	1		T205	1
all_levels[23]	auto[0]	60	1			T9	1		T32	1		T116	1
all_levels[23]	auto[1]	2	1			T145	1		T206	1		-	-
all_levels[24]	auto[0]	63	1			T32	1		T35	1		T116	1
all_levels[24]	auto[1]	7	1			T32	1		T207	3		T208	1
all_levels[25]	auto[0]	60	1			T3	1		T9	1		T32	1
all_levels[25]	auto[1]	7	1			T9	1		T191	2		T119	2
all_levels[26]	auto[0]	63	1			T9	1		T35	1		T14	1
all_levels[26]	auto[1]	4	1			T209	1		T174	1		T210	1
all_levels[27]	auto[0]	47	1			T1	1		T116	1		T118	1
all_levels[28]	auto[0]	48	1			T35	1		T117	1		T119	1
all_levels[28]	auto[1]	6	1			T211	1		T212	1		T213	3
all_levels[29]	auto[0]	31	1			T116	1		T120	2		T121	1
all_levels[29]	auto[1]	3	1			T214	1		T215	2		-	-
all_levels[30]	auto[0]	36	1			T18	1		T122	1		T123	1
all_levels[30]	auto[1]	6	1			T111	3		T216	3		-	-
all_levels[31]	auto[0]	28	1			T26	1		T124	1		T111	1
all_levels[31]	auto[1]	3	1			T217	1		T218	1		T219	1
all_levels[32]	auto[0]	29	1			T125	1		T126	1		T127	1
all_levels[32]	auto[1]	5	1			T220	1		T221	1		T222	3
all_levels[33]	auto[0]	26	1			T128	1		T121	1		T111	1
all_levels[33]	auto[1]	6	1			T176	1		T223	1		T159	1
all_levels[34]	auto[0]	23	1			T18	1		T53	1		T124	1
all_levels[34]	auto[1]	6	1			T163	2		T181	2		T224	2
all_levels[35]	auto[0]	23	1			T10	1		T114	1		T128	1
all_levels[36]	auto[0]	30	1			T129	1		T120	1		T130	1
all_levels[36]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[37]	auto[0]	21	1			T53	1		T121	1		T131	1
all_levels[37]	auto[1]	2	1			T226	2		-	-		-	-
all_levels[38]	auto[0]	16	1			T132	1		T133	1		T134	1
all_levels[38]	auto[1]	3	1			T42	1		T159	2		-	-
all_levels[39]	auto[0]	19	1			T121	1		T135	1		T136	1
all_levels[39]	auto[1]	3	1			T210	1		T227	2		-	-
all_levels[40]	auto[0]	21	1			T1	1		T32	1		T132	1
all_levels[40]	auto[1]	12	1			T218	2		T228	1		T229	4
all_levels[41]	auto[0]	14	1			T117	1		T137	1		T138	1
all_levels[41]	auto[1]	2	1			T230	2		-	-		-	-
all_levels[42]	auto[0]	13	1			T113	1		T139	1		T140	1
all_levels[42]	auto[1]	3	1			T231	1		T232	1		T233	1
all_levels[43]	auto[0]	17	1			T141	1		T142	1		T143	1
all_levels[43]	auto[1]	5	1			T141	2		T143	1		T234	2
all_levels[44]	auto[0]	10	1			T138	1		T142	1		T144	1
all_levels[44]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[45]	auto[0]	12	1			T34	1		T128	1		T138	1
all_levels[45]	auto[1]	4	1			T34	2		T236	1		T149	1
all_levels[46]	auto[0]	19	1			T1	1		T145	1		T111	2
all_levels[46]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[47]	auto[0]	10	1			T146	1		T147	1		T148	1
all_levels[48]	auto[0]	16	1			T149	1		T150	1		T99	1
all_levels[48]	auto[1]	6	1			T238	3		T208	2		T239	1
all_levels[49]	auto[0]	11	1			T151	1		T152	1		T153	1
all_levels[50]	auto[0]	15	1			T154	1		T117	1		T137	1
all_levels[50]	auto[1]	2	1			T137	1		T240	1		-	-
all_levels[51]	auto[0]	19	1			T115	2		T111	1		T146	1
all_levels[51]	auto[1]	2	1			T181	1		T241	1		-	-
all_levels[52]	auto[0]	12	1			T121	2		T146	1		T148	1
all_levels[52]	auto[1]	3	1			T146	1		T242	2		-	-
all_levels[53]	auto[0]	12	1			T111	1		T155	1		T156	1
all_levels[53]	auto[1]	1	1			T243	1		-	-		-	-
all_levels[54]	auto[0]	6	1			T157	1		T120	1		T158	1
all_levels[54]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[55]	auto[0]	9	1			T144	1		T99	1		T159	1
all_levels[56]	auto[0]	7	1			T120	1		T98	1		T160	1
all_levels[57]	auto[0]	7	1			T161	1		T136	1		T162	1
all_levels[57]	auto[1]	3	1			T161	1		T245	2		-	-
all_levels[58]	auto[0]	5	1			T11	1		T123	1		T112	1
all_levels[59]	auto[0]	12	1			T126	1		T163	1		T142	1
all_levels[59]	auto[1]	2	1			T217	1		T246	1		-	-
all_levels[60]	auto[0]	6	1			T163	1		T111	1		T149	1
all_levels[60]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T164	1		T99	1		T165	1
all_levels[62]	auto[0]	8	1			T166	1		T167	1		T168	1
all_levels[62]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[63]	auto[0]	6	1			T11	1		T107	1		T111	1
all_levels[64]	auto[0]	96	1			T5	1		T11	1		T14	1
all_levels[64]	auto[1]	19	1			T139	1		T154	1		T248	5