Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	117277	1			T1	49		T2	2		T3	27
all_pins[1]	117277	1			T1	49		T2	2		T3	27
all_pins[2]	117277	1			T1	49		T2	2		T3	27
all_pins[3]	117277	1			T1	49		T2	2		T3	27
all_pins[4]	117277	1			T1	49		T2	2		T3	27
all_pins[5]	117277	1			T1	49		T2	2		T3	27
all_pins[6]	117277	1			T1	49		T2	2		T3	27
all_pins[7]	117277	1			T1	49		T2	2		T3	27

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	907901	1			T1	371		T2	16		T3	189
values[0x1]	30315	1			T1	21		T3	27		T4	26
transitions[0x0=>0x1]	29076	1			T1	21		T3	27		T4	25
transitions[0x1=>0x0]	28613	1			T1	20		T3	27		T4	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	93958	1			T1	41		T2	2		T3	2
all_pins[0]	values[0x1]	23319	1			T1	8		T3	25		T4	18
all_pins[0]	transitions[0x0=>0x1]	22696	1			T1	8		T3	25		T4	18
all_pins[0]	transitions[0x1=>0x0]	1221	1			T11	4		T12	4		T37	2
all_pins[1]	values[0x0]	115433	1			T1	49		T2	2		T3	27
all_pins[1]	values[0x1]	1844	1			T11	18		T12	10		T37	2
all_pins[1]	transitions[0x0=>0x1]	1714	1			T11	17		T12	10		T37	2
all_pins[1]	transitions[0x1=>0x0]	2636	1			T1	10		T3	1		T5	10
all_pins[2]	values[0x0]	114511	1			T1	39		T2	2		T3	26
all_pins[2]	values[0x1]	2766	1			T1	10		T3	1		T5	10
all_pins[2]	transitions[0x0=>0x1]	2694	1			T1	10		T3	1		T5	10
all_pins[2]	transitions[0x1=>0x0]	295	1			T5	2		T12	1		T29	1
all_pins[3]	values[0x0]	116910	1			T1	49		T2	2		T3	27
all_pins[3]	values[0x1]	367	1			T5	2		T11	1		T12	1
all_pins[3]	transitions[0x0=>0x1]	321	1			T5	2		T11	1		T12	1
all_pins[3]	transitions[0x1=>0x0]	510	1			T4	7		T30	6		T72	1
all_pins[4]	values[0x0]	116721	1			T1	49		T2	2		T3	27
all_pins[4]	values[0x1]	556	1			T4	7		T30	6		T72	1
all_pins[4]	transitions[0x0=>0x1]	469	1			T4	6		T30	6		T73	1
all_pins[4]	transitions[0x1=>0x0]	148	1			T13	3		T28	1		T249	1
all_pins[5]	values[0x0]	117042	1			T1	49		T2	2		T3	27
all_pins[5]	values[0x1]	235	1			T4	1		T13	3		T28	1
all_pins[5]	transitions[0x0=>0x1]	192	1			T4	1		T13	3		T28	1
all_pins[5]	transitions[0x1=>0x0]	783	1			T1	3		T3	1		T9	6
all_pins[6]	values[0x0]	116451	1			T1	46		T2	2		T3	26
all_pins[6]	values[0x1]	826	1			T1	3		T3	1		T9	6
all_pins[6]	transitions[0x0=>0x1]	767	1			T1	3		T3	1		T9	6
all_pins[6]	transitions[0x1=>0x0]	343	1			T13	1		T12	4		T14	1
all_pins[7]	values[0x0]	116875	1			T1	49		T2	2		T3	27
all_pins[7]	values[0x1]	402	1			T13	1		T12	4		T14	1
all_pins[7]	transitions[0x0=>0x1]	223	1			T13	1		T117	1		T28	1
all_pins[7]	transitions[0x1=>0x0]	22677	1			T1	7		T3	25		T4	18