Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7903263	1			T1	171		T3	53		T5	4913
all_levels[1]	1722122	1			T1	23		T3	3		T5	71
all_levels[2]	506224	1			T1	12		T5	45		T6	10
all_levels[3]	250942	1			T1	13		T3	3		T5	10
all_levels[4]	294398	1			T1	106		T5	7		T6	12
all_levels[5]	613660	1			T1	24		T3	1		T5	72
all_levels[6]	366853	1			T1	11		T3	2		T5	107
all_levels[7]	250997	1			T1	9		T5	97		T6	16
all_levels[8]	362149	1			T1	17		T5	65		T6	15
all_levels[9]	236611	1			T1	17		T5	60		T6	8
all_levels[10]	307114	1			T1	6		T3	1		T5	64
all_levels[11]	784009	1			T1	11		T5	60		T6	27
all_levels[12]	288350	1			T1	3		T5	45		T6	11
all_levels[13]	249388	1			T1	6		T5	24		T6	10
all_levels[14]	219355	1			T1	5		T5	18		T6	42
all_levels[15]	263751	1			T1	4		T4	17		T5	68
all_levels[16]	324664	1			T1	3		T4	369		T5	106
all_levels[17]	200283	1			T1	6		T5	104		T6	4
all_levels[18]	350889	1			T1	12		T5	112		T6	67
all_levels[19]	253327	1			T1	6		T5	102		T8	2
all_levels[20]	234325	1			T1	23		T5	97		T8	4
all_levels[21]	310438	1			T5	64		T11	35		T13	1
all_levels[22]	220749	1			T1	10		T5	64		T9	2
all_levels[23]	385346	1			T1	4		T5	66		T11	27
all_levels[24]	318067	1			T1	1		T5	66		T11	20
all_levels[25]	221185	1			T1	2		T5	44		T11	27
all_levels[26]	373058	1			T1	14		T5	56		T11	29
all_levels[27]	331108	1			T5	100		T11	30		T14	1
all_levels[28]	218420	1			T5	71		T11	19		T14	2
all_levels[29]	172682	1			T5	71		T11	29		T14	1
all_levels[30]	494792	1			T5	62		T11	22		T13	1
all_levels[31]	491028	1			T1	1		T5	402		T11	926
all_levels[32]	13676090	1			T1	4		T5	11958		T10	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33191167

1

T1

524

T3

58

T4

370

auto[1]

4470

1

T3

5

T4

16

T8

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7901114	1			T1	171		T3	48		T5	4913
all_levels[0]	auto[1]	2149	1			T3	5		T8	2		T9	5
all_levels[1]	auto[0]	1721694	1			T1	23		T3	3		T5	71
all_levels[1]	auto[1]	428	1			T8	1		T253	1		T16	1
all_levels[2]	auto[0]	506190	1			T1	12		T5	45		T6	10
all_levels[2]	auto[1]	34	1			T169	1		T141	1		T172	1
all_levels[3]	auto[0]	250711	1			T1	13		T3	3		T5	10
all_levels[3]	auto[1]	231	1			T54	4		T28	19		T29	2
all_levels[4]	auto[0]	294354	1			T1	106		T5	7		T6	12
all_levels[4]	auto[1]	44	1			T53	1		T120	3		T236	1
all_levels[5]	auto[0]	613642	1			T1	24		T3	1		T5	72
all_levels[5]	auto[1]	18	1			T264	1		T258	1		T111	2
all_levels[6]	auto[0]	366832	1			T1	11		T3	2		T5	107
all_levels[6]	auto[1]	21	1			T8	2		T32	1		T56	1
all_levels[7]	auto[0]	250839	1			T1	9		T5	97		T6	16
all_levels[7]	auto[1]	158	1			T28	3		T249	1		T137	1
all_levels[8]	auto[0]	362108	1			T1	17		T5	65		T6	15
all_levels[8]	auto[1]	41	1			T253	3		T129	2		T274	2
all_levels[9]	auto[0]	236585	1			T1	17		T5	60		T6	8
all_levels[9]	auto[1]	26	1			T323	1		T324	2		T210	2
all_levels[10]	auto[0]	307093	1			T1	6		T3	1		T5	64
all_levels[10]	auto[1]	21	1			T32	1		T119	1		T217	2
all_levels[11]	auto[0]	783983	1			T1	11		T5	60		T6	27
all_levels[11]	auto[1]	26	1			T9	1		T279	1		T129	2
all_levels[12]	auto[0]	288304	1			T1	3		T5	45		T6	11
all_levels[12]	auto[1]	46	1			T36	1		T33	1		T34	3
all_levels[13]	auto[0]	249349	1			T1	6		T5	24		T6	10
all_levels[13]	auto[1]	39	1			T113	2		T251	1		T207	1
all_levels[14]	auto[0]	219330	1			T1	5		T5	18		T6	42
all_levels[14]	auto[1]	25	1			T170	1		T123	1		T142	1
all_levels[15]	auto[0]	263522	1			T1	4		T4	1		T5	68
all_levels[15]	auto[1]	229	1			T4	16		T12	16		T16	1
all_levels[16]	auto[0]	324640	1			T1	3		T4	369		T5	106
all_levels[16]	auto[1]	24	1			T32	1		T73	1		T123	1
all_levels[17]	auto[0]	200249	1			T1	6		T5	104		T6	4
all_levels[17]	auto[1]	34	1			T115	1		T125	1		T255	1
all_levels[18]	auto[0]	350872	1			T1	12		T5	112		T6	67
all_levels[18]	auto[1]	17	1			T254	1		T120	2		T119	2
all_levels[19]	auto[0]	253306	1			T1	6		T5	102		T8	2
all_levels[19]	auto[1]	21	1			T289	1		T128	3		T145	1
all_levels[20]	auto[0]	234285	1			T1	23		T5	97		T8	4
all_levels[20]	auto[1]	40	1			T139	1		T126	1		T183	2
all_levels[21]	auto[0]	310408	1			T5	64		T11	35		T13	1
all_levels[21]	auto[1]	30	1			T54	2		T134	2		T173	1
all_levels[22]	auto[0]	220724	1			T1	10		T5	64		T9	2
all_levels[22]	auto[1]	25	1			T264	2		T155	3		T325	1
all_levels[23]	auto[0]	385320	1			T1	4		T5	66		T11	27
all_levels[23]	auto[1]	26	1			T326	1		T142	3		T298	1
all_levels[24]	auto[0]	318040	1			T1	1		T5	66		T11	20
all_levels[24]	auto[1]	27	1			T145	1		T97	2		T195	4
all_levels[25]	auto[0]	221162	1			T1	2		T5	44		T11	27
all_levels[25]	auto[1]	23	1			T32	1		T128	1		T111	1
all_levels[26]	auto[0]	373035	1			T1	14		T5	56		T11	29
all_levels[26]	auto[1]	23	1			T32	2		T125	1		T124	1
all_levels[27]	auto[0]	331100	1			T5	100		T11	30		T14	1
all_levels[27]	auto[1]	8	1			T149	1		T237	1		T327	1
all_levels[28]	auto[0]	218406	1			T5	71		T11	19		T14	2
all_levels[28]	auto[1]	14	1			T192	1		T328	1		T329	2
all_levels[29]	auto[0]	172661	1			T5	71		T11	29		T14	1
all_levels[29]	auto[1]	21	1			T113	1		T97	1		T149	1
all_levels[30]	auto[0]	494776	1			T5	62		T11	22		T13	1
all_levels[30]	auto[1]	16	1			T196	1		T330	5		T103	1
all_levels[31]	auto[0]	491009	1			T1	1		T5	402		T11	926
all_levels[31]	auto[1]	19	1			T120	2		T150	1		T177	3
all_levels[32]	auto[0]	13675524	1			T1	4		T5	11958		T10	4
all_levels[32]	auto[1]	566	1			T10	1		T32	1		T253	2